Perovskite / crystalline silicon tandem cell and preparation method therefor

Abstract

The present application belongs to the field of perovskite / crystalline silicon tandem cells. Disclosed are a perovskite / crystalline silicon tandem cell and a preparation method therefor. The perovskite / crystalline silicon tandem cell comprises a bottom cell and a top cell, wherein the bottom cell uses a crystalline silicon wafer as a substrate, an interface passivation layer, a first doped silicon layer, a first transparent conductive oxide film layer and a metal conductive film layer are sequentially provided on the back surface of the bottom cell, and an interface passivation layer, a second doped silicon layer and an intermediate composite layer are sequentially provided on the front surface of the bottom cell; the top cell uses a perovskite light-absorbing layer as a light-absorbing layer, a first carrier transport layer is provided on the back surface, and a second carrier transport layer, a second transparent conductive oxide film layer and a metal grid line electrode are sequentially provided on the front surface; and an amorphous germanium layer is provided between the second doped silicon layer and the intermediate composite layer, thereby enhancing the tunneling conductivity between the second doped silicon layer and the intermediate composite layer, reducing the interfacial contact resistance, and improving the FF and conversion efficiency of the cell.

Description

Perovskite / crystalline silicon tandem cell and preparation method thereof

[0001] The present disclosure is based on and claims priority to Chinese Patent Application No. 202411163137.9 filed on August 22, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of perovskite / crystalline silicon tandem, in particular, to a perovskite / crystalline silicon tandem cell and a preparation method thereof. BACKGROUND

[0003] The highest laboratory conversion efficiency of single-crystalline silicon cells has reached 27.09%, close to the theoretical limit of 29.4%, and the future efficiency improvement space is small. In order to break through the efficiency ceiling, perovskite / crystalline silicon tandem cells have become one of the new directions of photovoltaic technology revolution. The perovskite / crystalline silicon tandem cell formed by stacking crystalline silicon cells and perovskite cells has a theoretical conversion efficiency of 43%, and the highest laboratory conversion efficiency has reached 33.9%. The perovskite / crystalline silicon tandem cell has a significantly higher theoretical efficiency and laboratory efficiency than the single-crystalline silicon cell.

[0004] The tandem cell needs to use an intermediate series layer to exchange carriers between the top and bottom cells, so its photoelectric performance will directly affect the photoelectric conversion efficiency of the tandem cell.

[0005] The intermediate series layer usually uses a transparent conductive oxide film layer or an n / p type silicon-based tunneling junction. Using an n / p type silicon-based tunneling junction as an intermediate series layer, due to the process conditions, the n / p type silicon-based tunneling junction has a high tunneling barrier, which makes the carrier tunneling probability low, the density of defect states at the interface low, and the carrier exchange rate low, resulting in an increase in the recombination loss of photo-generated carriers, thereby causing high electrical loss at the tunneling junction in the solar cell. Using a TCO composite junction as an intermediate series layer, there is a Schottky barrier between the TCO film layer and the doped silicon layer, and the barrier height is greatly affected by the effective doping concentration and the bandgap of the doped silicon layer, which easily leads to a too high interface contact resistance, causing an increase in the series resistance of the cell and a decrease in the fill factor. In addition, too high a barrier height will result in a too large thickness of the depletion layer in the doped silicon layer, affecting the open-circuit voltage of the cell, and ultimately leading to a decrease in the conversion efficiency of the cell.

[0006] In view of this, the present applicant has carried out in-depth research on this demand, and thus the present case has been produced.

[0007] SUMMARY

[0008] In view of the problems existing in the prior art that the transparent conductive oxide film layer or n / p type silicon-based tunneling recombination junction is used as the intermediate series layer of the perovskite / crystalline silicon tandem cell, the application provides a perovskite / crystalline silicon tandem cell, which comprises a bottom cell and a top cell,

[0009] The bottom cell takes a crystalline silicon wafer as a substrate, and the back surface of the bottom cell is sequentially provided with an interface passivation layer, a first doped silicon layer, a first transparent conductive oxide film layer and a metal conductive film layer, and the front surface of the bottom cell is sequentially provided with an interface passivation layer, a second doped silicon layer and an intermediate recombination layer.

[0010] The top cell takes a perovskite light-absorbing layer as a light-absorbing layer, and the back surface of the top cell is provided with a first carrier transport layer, and the front surface of the top cell is sequentially provided with a second carrier transport layer, a second transparent conductive oxide film layer and a metal grid electrode; and an amorphous germanium layer is arranged between the second doped silicon layer and the intermediate recombination layer.

[0011] Preferably, the amorphous germanium layer is amorphous, nanocrystalline or microcrystalline and is not doped, p-type doped or n-type doped.

[0012] Preferably, the amorphous germanium layer comprises at least one of hydrogenated amorphous germanium, hydrogenated amorphous germanium silicon or hydrogenated amorphous germanium carbon thin film, and the thickness of the amorphous germanium layer is 0.5-5.0 nm.

[0013] Preferably, the crystalline silicon wafer can be a Czochralski single crystal silicon wafer, a cast ingot single crystal silicon wafer or a polycrystalline silicon wafer, can be N-type doped or P-type doped, has a resistivity of 0.1-10.0 Ωcm and a thickness of 50-500 um.

[0014] Preferably, the intermediate recombination layer is one of a transparent conductive oxide layer, n-type doped silicon or p-type doped silicon, and the thickness of the intermediate recombination layer is 10-30 nm.

[0015] Preferably, the first doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polycrystalline silicon film layer, and is n-type doped or p-type doped, and the doping concentration is 10 17 -10 20 cm -3 ;

[0016] The second doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polycrystalline silicon film layer, and is n-type doped or p-type doped, and the doping concentration is 10 17 -10 20 cm -3 , and the second doped silicon layer and the first doped silicon layer are opposite in conductive type;

[0017] The low-temperature amorphous silicon film layer is formed at a temperature of 100-300℃, and the high-temperature polycrystalline silicon film layer is formed at a temperature of 600-1000℃.

[0018] Preferably, the low-temperature amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, uc-Si:H, uc-SiOx:H, uc-SiCx:H, and has a thickness of 5-20 nm.

[0019] The high-temperature polysilicon film layer includes at least one of poly-Si, poly-SiOx, poly-SiNx, poly-SiCx, and has a thickness of 5-50 nm.

[0020] Preferably, the first transparent conductive oxide film layer includes at least one of doped indium oxide, tin oxide, and zinc oxide-based thin film, and has a thickness of 60-150 nm.

[0021] The second transparent conductive oxide film layer includes at least one of doped indium oxide, tin oxide, and zinc oxide-based thin film, and has a thickness of 60-150 nm.

[0022] The metal conductive film layer includes at least one of Ag, Al, Ni, Cu, and Fe, and has a thickness of 100-1000 nm.

[0023] Preferably, the interface passivation layer includes at least one of an intrinsic amorphous silicon film layer or a tunneling dielectric film layer.

[0024] The intrinsic amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, and a-SiCx:H, and has a thickness of 4-8 nm; the tunneling dielectric film layer includes at least one of SiOx, SiNx, and SiCx, and has a thickness of 1-3 nm.

[0025] Preferably, the perovskite light-absorbing layer has a general formula of ABX3, where A is a monovalent cation, including but not limited to any one of lithium, sodium, potassium, cesium, amine group, or amidine group; B is a divalent cation, including but not limited to any one of lead and tin; X is a monovalent anion, including but not limited to any one of iodine, bromine, and chlorine; the perovskite light-absorbing layer has a thickness of 500-1500 nm.

[0026] Preferably, the first carrier transport layer includes a first inorganic carrier transport layer and a first organic carrier transport layer stacked together; the first carrier transport layer is a hole transport layer or an electron transport layer; the first carrier transport layer has the same conductivity type as the first doped silicon layer.

[0027] The second carrier transport layer includes a second inorganic carrier transport layer and a second organic carrier transport layer stacked together; the second carrier transport layer is a hole transport layer or an electron transport layer; the second carrier transport layer has a conductivity type opposite to that of the first carrier transport layer and the same as that of the second doped silicon layer.

[0028] Preferably, the first inorganic carrier transport layer comprises an inorganic hole transport layer or an inorganic electron transport layer; the second inorganic carrier transport layer comprises an inorganic hole transport layer or an inorganic electron transport layer, and the first inorganic carrier transport layer and the second inorganic carrier transport layer are opposite in conductive type;

[0029] The inorganic hole transport layer comprises at least one of NiOx, V2O5, MoOx, WOx, Cu2O, and has a thickness of 0.5-50.0 nm; the inorganic electron transport layer preferably comprises at least one of SnO2, TiO2, ZnO, Nb2O5, ZrO2, TiSnOx, SnZnOx, LiF, and MgFx, and has a thickness of 0.5-50.0 nm;

[0030] The first organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, the second organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, and the first organic carrier transport layer and the second organic carrier transport layer are opposite in conductive type;

[0031] The organic hole transport layer preferably comprises at least one of 2PACz, Me-4PACz, MeO-2PACz, PTAA, P3HT, Poly-TPD, PEDOT:PSS, Spiro-OMeTAD, m-MTDATA, Spiro-TTB, F4-TCNQ, F6-TCNNQ, and TAPC, and has a thickness of 0.5-50.0 nm;

[0032] The organic electron transport layer preferably comprises at least one of fullerene C60, fullerene C70, and fullerene derivative PCBM, and has a thickness of 0.5-50.0 nm.

[0033] Preferably, the metal gate line electrode is at least one of Ag, Al, Ni, Cu, and Fe, has a gate line thickness of 0.1-20.0 um, and has a pitch of 0.5-5.0 mm.

[0034] The application also provides a preparation method of the above perovskite / crystalline silicon stacked cell, which is simple in process and easy to implement, and specifically comprises the following steps:

[0035] S1, etching and cleaning the surface of the crystalline silicon wafer;

[0036] S2, sequentially arranging a first interface passivation layer and a first doped silicon layer on the back surface of the crystalline silicon wafer; and sequentially arranging a second interface passivation layer, a second doped silicon layer, an amorphous germanium layer, and an intermediate composite layer on the front surface of the crystalline silicon wafer;

[0037] S3, arranging a first transparent conductive oxide film layer and a metal conductive film layer on the surface of the first doped silicon layer on the back surface; and arranging a first carrier transport layer on the surface of the first doped silicon layer on the front surface.

[0038] S4, depositing a perovskite light-absorbing layer on the surface of the first carrier transport layer;

[0039] S5, depositing a second carrier transport layer on the surface of the perovskite light-absorbing layer;

[0040] S6, depositing a second transparent conductive oxide film layer on the surface of the second carrier transport layer;

[0041] S7, disposing a metal grid line electrode on the surface of the second transparent conductive oxide film layer.

[0042] The beneficial effects of the technical scheme of the present application are as follows: a layer of ultra-thin amorphous germanium is arranged between the second doped silicon layer and the intermediate composite layer, which enhances the tunneling conduction capability between the second doped silicon layer and the intermediate composite layer, reduces the interface contact resistance, and improves the FF and conversion efficiency of the battery. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical scheme of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0044] Fig. 1 is a schematic diagram of the layer structure of a perovskite / crystalline silicon stacked battery in the present application;

[0045] Fig. 2 is a preparation process flow chart of a perovskite / crystalline silicon stacked battery in the present application;

[0046] Fig. 3 is a schematic diagram of the layer structure of a perovskite / crystalline silicon stacked battery in Example 1 of the present application;

[0047] Fig. 4 is a schematic diagram of the layer structure of a perovskite / crystalline silicon stacked battery in Example 2 of the present application;

[0048] Fig. 5 is a schematic diagram of the layer structure of a perovskite / crystalline silicon stacked battery in Comparative Example 1 of the present application.

[0049] In the drawings: 1, bottom cell; 11, crystalline silicon wafer; 12, interface passivation layer; 13, first doped silicon layer; 14, first transparent conductive oxide film layer; 15, metal conductive film layer; 16, second doped silicon layer; 17, intermediate composite layer; 2, top cell; 21, perovskite light-absorbing layer; 22, first carrier transport layer; 23, second carrier transport layer; 24, second transparent conductive oxide film layer; 25, metal grid line electrode. DETAILED DESCRIPTION

[0050] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0051] As shown in FIG. 1, a perovskite / crystalline silicon tandem cell includes a bottom cell 1 and a top cell 2,

[0052] The bottom cell 1 takes a crystalline silicon wafer 11 as a substrate, and the back surface is sequentially provided with an interface passivation layer 12, a first doped silicon layer 13, a first transparent conductive oxide film layer 14 and a metal conductive film layer 15, and the front surface is sequentially provided with the interface passivation layer 12, a second doped silicon layer 16 and an intermediate composite layer 17;

[0053] The top cell 2 takes a perovskite light-absorbing layer 21 as a light-absorbing layer, and the back surface is provided with a first carrier transport layer 22, and the front surface is sequentially provided with a second carrier transport layer 23, a second transparent conductive oxide film layer 24 and a metal grid electrode 25; an amorphous germanium layer 3 is arranged between the second doped silicon layer 16 and the intermediate composite layer 17.

[0054] As a preferred embodiment, the amorphous germanium layer 3 is amorphous, nanocrystalline or microcrystalline without doping, p-type doping or n-type doping.

[0055] As a preferred embodiment, the amorphous germanium layer 3 includes at least one of hydrogenated amorphous germanium, hydrogenated amorphous germanium silicon or hydrogenated amorphous germanium carbon thin film, and the thickness is 0.5-5.0 nm.

[0056] As a preferred embodiment, the crystalline silicon wafer 11 can be a Czochralski monocrystalline silicon wafer, a cast ingot monocrystalline silicon wafer or a polycrystalline silicon wafer, can be N-type doped or P-type doped, has a resistivity of 0.1-10.0 Ωcm and a thickness of 50-500 um.

[0057] As a preferred embodiment, the intermediate composite layer 18 is one of a transparent conductive oxide layer, n-type doped silicon or p-type doped silicon, and the thickness is 10-30 nm.

[0058] As a preferred embodiment, the first doped silicon layer 13 is a low-temperature amorphous silicon film layer or a high-temperature polycrystalline silicon film layer, and is n-type doped or p-type doped, with a doping concentration of 10 17 -10 20 cm -3;

[0059] The second doped silicon layer 17 is a low-temperature amorphous silicon film layer or a high-temperature polysilicon film layer, and is n-type doped or p-type doped, with a doping concentration of 10 17 -10 20 cm -3 , and the second doped silicon layer is opposite in conductive type to the first doped silicon layer.

[0060] The low-temperature amorphous silicon film layer is formed at a temperature of 100-300℃, and the high-temperature polysilicon film layer is formed at a temperature of 600-1000℃.

[0061] As a preferred embodiment, the low-temperature amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, uc-Si:H, uc-SiOx:H, uc-SiCx:H, with a thickness of 5-20nm.

[0062] The high-temperature polysilicon film layer includes at least one of poly-Si, poly-SiOx, poly-SiNx, poly-SiCx, with a thickness of 5-50nm.

[0063] As a preferred embodiment, the first transparent conductive oxide film layer 14 includes at least one of doped indium oxide, tin oxide, zinc oxide-based thin film, with a thickness of 60-150nm.

[0064] The second transparent conductive oxide film layer 24 includes at least one of doped indium oxide, tin oxide, zinc oxide-based thin film, with a thickness of 60-150nm.

[0065] The metal conductive film layer 15 includes at least one of Ag, Al, Ni, Cu, Fe, with a thickness of 100-1000nm.

[0066] As a preferred embodiment, the interface passivation layer 16 includes at least one of an intrinsic amorphous silicon film layer or a tunneling dielectric film layer.

[0067] The intrinsic amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, with a thickness of 4-8nm; and the tunneling dielectric film layer includes at least one of SiOx, SiNx, SiCx, with a thickness of 1-3nm.

[0068] As a preferred embodiment, the perovskite light-absorbing layer 21 has a general formula of ABX3, where A is a monovalent cation, including but not limited to any one of lithium, sodium, potassium, cesium, amine group or amidine group; B is a divalent cation, including but not limited to any one of lead or tin; X is a monovalent anion, including but not limited to any one of iodine, bromine or chlorine; and the perovskite light-absorbing layer has a thickness of 500-1500nm.

[0069] As a preferred embodiment, the first carrier transport layer 22 comprises a first inorganic carrier transport layer and a first organic carrier transport layer stacked together; the first carrier transport layer is a hole transport layer or an electron transport layer; the first carrier transport layer has the same conductivity type as the first doped silicon layer;

[0070] The second carrier transport layer 23 comprises a second inorganic carrier transport layer and a second organic carrier transport layer stacked together; the second carrier transport layer is a hole transport layer or an electron transport layer; the second carrier transport layer has the opposite conductivity type as the first carrier transport layer and the same conductivity type as the second doped silicon layer.

[0071] As a preferred embodiment, the first inorganic carrier transport layer comprises an inorganic hole transport layer or an inorganic electron transport layer; the second inorganic carrier transport layer comprises an inorganic hole transport layer or an inorganic electron transport layer, and the first inorganic carrier transport layer has the opposite conductivity type as the second inorganic carrier transport layer;

[0072] The inorganic hole transport layer comprises at least one of NiOx, V2O5, MoOx, WOx, Cu2O, and has a thickness of 0.5-50.0 nm; the inorganic electron transport layer preferably comprises at least one of SnO2, TiO2, ZnO, Nb2O5, ZrO2, TiSnOx, SnZnOx, LiF, MgFx, and has a thickness of 0.5-50.0 nm;

[0073] The first organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer; the second organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, and the first organic carrier transport layer has the opposite conductivity type as the second organic carrier transport layer;

[0074] The organic hole transport layer preferably comprises at least one of 2PACz, Me-4PACz, MeO-2PACz, PTAA, P3HT, Poly-TPD, PEDOT:PSS, Spiro-OMeTAD, m-MTDATA, Spiro-TTB, F4-TCNQ, F6-TCNNQ, TAPC, and has a thickness of 0.5-50.0 nm;

[0075] The organic electron transport layer preferably comprises at least one of fullerene C60, fullerene C70, fullerene derivative PCBM, and has a thickness of 0.5-50.0 nm.

[0076] As a preferred embodiment, the metal gate line electrode 25 is at least one of Ag, Al, Ni, Cu, and Fe, has a gate line thickness of 0.1-20.0 um, and a pitch of 0.5-5.0 mm.

[0077] As shown in Figure 2, the present embodiment also provides a preparation method of the above perovskite / crystalline silicon stacked cell, which is simple in process and easy to implement, and specifically includes the following steps:

[0078] S1, etching and cleaning the surface of the crystalline silicon wafer;

[0079] S2, sequentially arranging a first interface passivation layer and a first doped silicon layer on the back surface of the crystalline silicon wafer; and sequentially arranging a second interface passivation layer, a second doped silicon layer, an amorphous germanium layer and an intermediate composite layer on the front surface of the crystalline silicon wafer;

[0080] S3, arranging a first transparent conductive oxide film layer and a metal conductive film layer on the surface of the first doped silicon layer on the back surface; and arranging a first carrier transport layer on the surface of the first doped silicon layer on the front surface;

[0081] S4, depositing a perovskite light-absorbing layer on the surface of the first carrier transport layer;

[0082] S5, depositing a second carrier transport layer on the surface of the perovskite light-absorbing layer;

[0083] S6, depositing a second transparent conductive oxide film layer on the surface of the second carrier transport layer;

[0084] S7, arranging a metal grid electrode on the surface of the second transparent conductive oxide film layer.

[0085] The beneficial effects of the perovskite / crystalline silicon stacked cell and the preparation process thereof in the present embodiment will be further commented on through several groups of examples.

[0086] Example 1:

[0087] As shown in Figure 3, the perovskite / crystalline silicon stacked cell in the present embodiment includes, from back to front, an Ag conductive film layer, an ITO layer, a p-a-Si:H layer, an i-a-Si:H layer, an n-CZ Si layer, an i-a-Si:H layer, an n-a-Si:H layer, an a-GeCx:H layer, a p-uc-SiOx:H layer, a NiOx layer, a 2PACz layer, a PVK layer, a LiF layer, a C60 layer, a SnO2 layer, an IZO layer and an Ag grid line.

[0088] The preparation method of the perovskite / crystalline silicon stacked cell in the present embodiment includes the following steps:

[0089] S1, using a wet process to clean the surface of an N-type silicon wafer; using acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and forming a surface pyramid texture on the surface of the single crystal silicon wafer to increase the absorption of sunlight and reduce reflection; the single crystal silicon wafer is a phosphorus-doped N-type single crystal silicon wafer with a resistivity of 1 Ωcm and a thickness of 150 um.

[0090] S2, i / p type amorphous silicon layer is deposited on the back surface of the silicon wafer and i / n type amorphous silicon layer is deposited on the front surface of the silicon wafer by PECVD; the thickness of the i layer on the back surface is 4-8 nm, the thickness of the p layer is 5-10 nm, the boron doping concentration is 0.5%; the thickness of the i layer on the front surface is 4-8 nm, the thickness of the n layer is 5-10 nm, the phosphorus doping concentration is 1%; the deposition temperature is 200℃.

[0091] S3, n type doped amorphous germanium layer with a thickness of 0.5-1 nm is deposited on the surface of the n type amorphous silicon layer on the front surface by PECVD process, the reaction gas is PH3, GeH4 and H2, the flow ratio of PH3 and GeH4 is 0.01, the flow ratio of H2 and GeH4 is 5, the power density of the PECVD equipment is 15 mW / cm2, the pressure is 50 Pa, and the substrate temperature is 200℃; then p type doped microcrystalline silicon oxide layer p-uc-SiOx:H is deposited on the surface of the amorphous germanium layer, the deposition temperature is 180℃, the thickness is 15 nm, SiH4, CO2, H2 and B2H6 are used as the reaction gas, the CO2 / SiH4 gas flow ratio is 0.5, the H2 / SiH4 flow ratio is 200:1, and the B2H6 / SiH4 gas flow ratio is 0.5%. 2

[0092] S4, ITO / Ag is deposited on the surface of the p type amorphous silicon layer on the back surface by PVD, the ITO target material is 90wt% In2O3+10wt% SnO, the sputtering atmosphere is 0.2% O2 / Ar, the thickness of ITO is 100 nm, the Ag target material is pure 99.99wt%, and the thickness of Ag is 500 nm; then NiOx is deposited on the surface of the p type doped microcrystalline silicon oxide layer on the front surface by RF sputtering process, the target material is NiO target material with a purity of 99.99%, the sputtering atmosphere is pure Ar, and the thickness is 20 nm.

[0093] S5, 2PACz and PVK layers are deposited on the surface of NiOx by spin coating and drying. First, 1 mg / mL 2PACz ethanol solution is used for spin coating at a speed of 4000 rpm for 30 s, and then dried at 100℃ for 10 min; DMF and DMSO mixed solution (volume ratio 4:1) perovskite precursor solution of component of 1.7 mol / L CsFA 0.05 FA 0.8 MA 0.15 Pb(I 0.755 Br 0.255 )3 is used for spin coating at a speed of 3500 rpm for 40 s, and then dried at 100℃ / N2 for 30 min, and the obtained perovskite band gap is 1.69 eV.

[0094] ​S6, LiF / C60 is deposited on the surface of PVK layer by evaporation. 1nm LiF is evaporated on the surface of PVK, and 18nm C60 is evaporated on the surface of LiF.

[0095] S7, SnO2 is deposited on the surface of C60 by ALD process. TDMASn and H2O are used as reaction gas, N2 is used as carrier gas, the deposition temperature is 80℃, and the thickness of SnO2 is 20nm.

[0096] S8, IZO is deposited on the surface of SnO2 by PVD process. The composition of IZO target material is 90wt% In2O3+10wt% ZnO, the sputtering atmosphere is 0.2% O2 / Ar, the thickness of IZO is 100nm, the purity of Ag target material is 99.99wt%, and the thickness of Ag is 500nm.

[0097] S9, low-temperature Ag paste gate line electrode is formed on the surface of IZO by printing and curing. The width of gate line is 30um, the pitch is 2mm, the curing temperature is 120℃, and the curing time is 10min.

[0098] Example 2:

[0099] As shown in FIG. 4, the perovskite / crystalline silicon stacked cell in this embodiment includes, from back to front, Ag conductive film layer, ITO layer, p-poly-Si layer, SiO2 layer, n-CZ Si layer, SiO2 layer, n-poly-Si layer, a-GeCx:H layer, p-uc-SiOx:H layer, NiOx layer, 2PACz layer, PVK layer, LiF layer, C60 layer, SnO2 layer, IZO layer, and Ag gate line.

[0100] The preparation method of the perovskite / crystalline silicon stacked cell in this embodiment includes the following steps:

[0101] S1, the surface of N-type silicon wafer is prepared and cleaned by wet process. Acid and alkali chemicals are used to eliminate organic contamination and metal impurities on the surface of silicon wafer, form surface pyramid texture on the surface of monocrystalline silicon wafer, increase the absorption of sunlight and reduce reflection; the monocrystalline silicon wafer is phosphorus-doped N-type monocrystalline silicon wafer with resistivity of 1Ωcm and thickness of 150um.

[0102] S2, depositing ultra-thin SiO2 film layer and p-type amorphous silicon film layer on the back surface of the silicon wafer by PECVD; depositing ultra-thin SiO2 film layer and n-type amorphous silicon film layer on the front surface of the silicon wafer. The ultra-thin SiO2 film layer is formed by plasma discharge oxidation with N2O as the reaction gas, the deposition temperature is 250°C, and the thickness is 2nm; the n-type amorphous silicon film layer is deposited at a temperature of 250°C and a thickness of 20nm, with SiH4, H2 and PH3 as the reaction gases, and the PH3 / SiH4 gas flow ratio being 1.5%; the p-type amorphous silicon film layer is deposited at a temperature of 250°C and a thickness of 20nm, with SiH4, H2 and B2H6 as the reaction gases, and the B2H6 / SiH4 gas flow ratio being 1%.

[0103] S3, activating the p-type and n-type amorphous silicon film layers by high-temperature annealing in a furnace tube, the annealing temperature being 850°C, the time being 30min, and the annealing atmosphere being N2; after the annealing treatment, the p-type and n-type amorphous silicon film layers are converted into p-type and n-type polycrystalline silicon film layers, the doping concentration being 1E20-1E21cm -3 .

[0104] S4, removing the parasitic oxide layer on the surface of the p-type and n-type polycrystalline silicon film layers after the annealing by using HF solution, the HF concentration being 1wt%, the temperature being 20-30°C, and the time being 1-3min.

[0105] S5, depositing n-type doped amorphous germanium carbon layer with a thickness of 0.5-1.0nm on the front n-type polycrystalline silicon film layer by PECVD process, the reaction gases being PH3, GeH4, CH4 and H2, the flow ratio of PH3 and GeH4 being 0.01, the flow ratio of CH4 / GeH4 being 4, and the flow ratio of H2 and GeH4 being 5, the power density of the PECVD equipment being 75mW / cm 2 , the pressure being 50Pa, and the substrate temperature being 180°C; then depositing p-type doped microcrystalline silicon oxide layer p-uc-SiOx:H on the surface of the amorphous germanium carbon layer, the deposition temperature being 180°C, the thickness being 15nm, and the reaction gases being SiH4, CO2, H2 and B2H6, the CO2 / SiH4 gas flow ratio being 0.5, the H2 / SiH4 flow ratio being 200:1, and the B2H6 / SiH4 gas flow ratio being 0.5%.

[0106] S6, depositing ITO / Ag on the surface of the back p-amorphous silicon layer by PVD, the ITO target material being 90wt% In2O3+10wt% SnO, the sputtering atmosphere being 0.2% O2 / Ar, the ITO thickness being 100nm, the Ag target material being pure with a purity of 99.99wt%, and the Ag thickness being 500nm; depositing NiOx on the surface of the front p-type doped microcrystalline silicon oxide layer, the sputtering target material being pure NiO with a purity of 99.99%, the sputtering atmosphere being pure Ar, and the thickness being 20nm;

[0107] S7, 2PACz and PVK layers are deposited on the surface of NiOx by spin coating + drying. First, 1 mg / mL 2PACz ethanol solution is spin coated at a speed of 4000 rpm for 30 s, and then dried at 100°C for 10 min; a DMF and DMSO mixed solution (volume ratio 4:1) of 1.7 mol / L Cs 0.05 FA 0.8 MA 0.15 Pb(I 0.755 Br 0.255 )3 perovskite precursor solution, speed 3500 rpm, time 40 s, then dried at 100°C / N2for 30 min, and the obtained perovskite band gap is 1.69 eV.

[0108] S8, LiF / C60 is deposited on the surface of the PVK layer by evaporation. 1 nm of LiF is evaporated on the surface of PVK, and 18 nm of C60 is evaporated on the surface of LiF.

[0109] S9, SnO2is deposited on the surface of C60 by ALD process. TDMASn and H2O are used as reaction gas, N2is used as carrier gas, the deposition temperature is 80°C, and the thickness of SnO2deposited is 20 nm.

[0110] S10, IZO is deposited on the surface of SnO2by PVD process. The composition of IZO target material is 90wt% In2O3+10wt% ZnO, the sputtering atmosphere is 0.2% O2 / Ar, the thickness of IZO is 100 nm, the purity of Ag target material is 99.99wt%, and the thickness of Ag is 500 nm.

[0111] S11, low-temperature Ag paste gate line electrode is formed on the surface of IZO by printing + curing. The width of the gate line is 30 um, the pitch is 2 mm, the curing temperature is 120°C, and the curing time is 10 min.

[0112] Comparative Example 1:

[0113] As shown in FIG. 5, the perovskite / crystalline silicon stacked cell in the present comparative example includes, from back to front, an Ag conductive film layer, an ITO layer, a p-a-Si:H layer, an i-a-Si:H layer, an n-CZ Si layer, an i-a-Si:H layer, an n-a-Si:H layer, a p-uc-SiOx:H layer, a NiOx layer, a 2PACz layer, a PVK layer, a LiF layer, a C60 layer, a SnO2layer, an IZO layer, and an Ag gate line.

[0114] The preparation method of the perovskite / crystalline silicon stacked cell in the present comparative example includes the following steps:

[0115] S1, using wet process, the surface of N-type silicon wafer is etched and cleaned. Using acid and alkali chemicals, the organic contamination and metal impurities on the surface of the silicon wafer are eliminated, the surface pyramid texture is formed on the surface of the monocrystalline silicon wafer, the absorption of sunlight is increased and the reflection is reduced; the monocrystalline silicon wafer is a phosphorus-doped N-type monocrystalline silicon wafer with a resistivity of 1Ωcm and a thickness of 150um.

[0116] S2, using PECVD method, i / p type amorphous silicon layer is deposited on the back surface of the silicon wafer, and i / n type amorphous silicon layer is deposited on the front surface of the silicon wafer. The thickness of the back i layer is 4-8nm, the thickness of the p layer is 5-10nm, the boron doping concentration is 0.5%; the thickness of the front i layer is 4-8nmn, the thickness of the n layer is 5-10nm, the phosphorus doping concentration is 1%; the deposition temperature is 200℃.

[0117] S3, using PECVD process, p-type doped microcrystalline silicon oxide layer p-uc-SiOx:H is deposited on the surface of the front n-type polysilicon film layer, the deposition temperature is 180℃, the thickness is 15nm, SiH4, CO2, H2 and B2H6 are used as reaction gas, the CO2 / SiH4 gas flow ratio is 0.5, the H2 / SiH4 flow ratio is 200:1, and the B2H6 / SiH4 gas flow ratio is 0.5%.

[0118] S4, using PVD method, ITO / Ag is deposited on the surface of the back p amorphous silicon layer, the ITO target material is 90wt% In2O3+10wt% SnO, the sputtering atmosphere is 0.2% O2 / Ar, the ITO thickness is 100nm, the Ag target material is pure 99.99wt%, and the Ag thickness is 500nm; NiOx is deposited on the front p-type doped microcrystalline silicon oxide layer, the NiOx adopts RF sputtering process, the purity of the NiOx target material is 99.99%, the sputtering atmosphere is pure Ar, and the thickness of the NiOx is 20nm.

[0119] S5, using spin coating + drying method, 2PACz and PVK layers are deposited on the surface of the NiOx. First, 1mg / mL 2PACz ethanol solution is used for spin coating at a speed of 4000r / min for 30s, and then dried at 100℃ for 10min; 1.7mol / L Cs 0.05 FA 0.8 MA 0.15 Pb(I 0.755 Br 0.255 )3 DMF and DMSO mixed solution (volume ratio 4:1) perovskite precursor solution, speed 3500rpm, time 40s, then dried at 100℃ / N2 for 30min, the obtained perovskite band gap is 1.69eV.

[0120] S6, LiF / C60 is deposited on the surface of PVK layer by evaporation. 1 nm LiF is evaporated on the surface of PVK, and 20 nm C60 is evaporated on the surface of LiF.

[0121] S7, SnO2 is deposited on the surface of C60 by ALD process. TDMASn and H2O are used as reaction gas, N2 is used as carrier gas, the deposition temperature is 80°C, and the thickness of SnO2 is 20 nm.

[0122] S8, IZO is deposited on the surface of SnO2 by PVD process. The composition of IZO target material is 90wt% In2O3+10wt% ZnO, the sputtering atmosphere is 0.2% O2 / Ar, the thickness of IZO is 100 nm; the purity of Ag target material is 99.99wt%, the sputtering atmosphere is pure Ar, and the thickness of Ag is 500 nm.

[0123] S9, low-temperature Ag paste gate line electrode is formed on the surface of IZO by printing and curing. The width of gate line is 30 um, the pitch is 2 mm, the curing temperature is 120°C, and the curing time is 10 min.

[0124] The batteries obtained in the above two groups of examples and one group of comparative examples are subjected to performance test, IV tester is used to determine the parameters of the solar cell sheet, and the results are shown in Table 1.

[0125] Table 1 shows the performance test results of the batteries in the examples.

[0126] As shown in Table 1, in the perovskite / silicon tandem battery of Comparative Example 1, the n / p type silicon-based tunnel junction is used as the intermediate series layer, and the tunneling barrier of the n / p type silicon-based tunnel junction is relatively high due to the limitation of process conditions, which makes the carrier tunneling probability low, the density of defect states at the interface low, and the carrier exchange rate low, resulting in an increase in the recombination loss of photo-generated carriers, thereby causing high electrical loss at the tunnel junction in the solar cell, and low FF and efficiency of the tandem battery.

[0127] In Example 1, an ultra-thin amorphous germanium layer a-Ge:H is arranged between the bottom battery n-a-Si:H and the intermediate composite layer p-uc-SiOx:H, which enhances the tunneling conductivity between n-a-Si:H and p-uc-SiOx:H, reduces the interface tunneling barrier, and improves the FF and conversion efficiency of the battery.

[0128] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A perovskite / crystalline silicon tandem cell, characterized by, The bottom cell and the top cell are included, The bottom cell takes a crystalline silicon wafer as a substrate, and a back surface of the crystalline silicon wafer is sequentially provided with an interface passivation layer, a first doped silicon layer, a first transparent conductive oxide film layer and a metal conductive film layer, and a front surface of the crystalline silicon wafer is sequentially provided with an interface passivation layer, a second doped silicon layer and an intermediate composite layer; The top cell takes a perovskite light-absorbing layer as a light-absorbing layer, and a back surface of the top cell is provided with a first carrier transport layer, and a front surface of the top cell is sequentially provided with a second carrier transport layer, a second transparent conductive oxide film layer and a metal grid electrode; and an amorphous germanium layer is arranged between the second doped silicon layer and the intermediate composite layer.

2. The perovskite / crystalline silicon tandem cell of claim 1, wherein The amorphous germanium layer is undoped, p-type doped or n-type doped amorphous, nanocrystalline or microcrystalline.

3. The perovskite / crystalline silicon tandem cell of claim 1, wherein The amorphous germanium layer includes at least one of hydrogenated amorphous germanium, hydrogenated amorphous germanium silicon or hydrogenated amorphous germanium carbon thin film, and a thickness of the amorphous germanium layer is 0.5-5.0 nm.

4. The perovskite / crystalline silicon tandem cell of claim 1, wherein, The intermediate composite layer is one of a transparent conductive oxide layer, n-type doped silicon or p-type doped silicon, and a thickness of the intermediate composite layer is 10-30 nm.

5. The perovskite / crystalline silicon tandem cell of claim 1, wherein, The first doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polysilicon film layer, and is n-type doped or p-type doped, with a doping concentration of 10 17 -10 20 cm -3 ; The second doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polysilicon film layer, and is n-type doped or p-type doped, with a doping concentration of 10 17 -10 20 cm -3 , and the second doped silicon layer is opposite to the first doped silicon layer in the conductive type. The low-temperature amorphous silicon film layer is formed at a temperature of 100-300 ℃, and the high-temperature polysilicon film layer is formed at a temperature of 600-1000 ℃.

6. The perovskite / crystalline silicon tandem cell of claim 5, wherein, The low-temperature amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, uc-Si:H, uc-SiOx:H and uc-SiCx:H, and a thickness of the low-temperature amorphous silicon film layer is 5-20 nm; The high-temperature polysilicon film layer includes at least one of poly-Si, poly-SiOx, poly-SiNx and poly-SiCx, and a thickness of the high-temperature polysilicon film layer is 5-50 nm.

7. The perovskite / crystalline silicon stacked cell according to claim 1, wherein the interface passivation layer includes at least one of an intrinsic amorphous silicon film layer or a tunneling dielectric film layer; The intrinsic amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H and a-SiCx:H, and a thickness of the intrinsic amorphous silicon film layer is 4-8 nm; and the tunneling dielectric film layer includes at least one of SiOx, SiNx and SiCx, and a thickness of the tunneling dielectric film layer is 1-3 nm.

8. The perovskite / crystalline silicon stacked cell according to claim 1, wherein the first carrier transport layer includes a first inorganic carrier transport layer and a first organic carrier transport layer which are stacked; the first carrier transport layer is a hole transport layer or an electron transport layer; and the first carrier transport layer and the first doped silicon layer are of the same conductive type; The second carrier transport layer includes a second inorganic carrier transport layer and a second organic carrier transport layer which are stacked; the second carrier transport layer is a hole transport layer or an electron transport layer; the second carrier transport layer and the first carrier transport layer are of opposite conductive types, and the second carrier transport layer and the second doped silicon layer are of the same conductive type.

9. The perovskite / crystalline silicon stacked cell according to claim 8, wherein the first inorganic carrier transport layer includes an inorganic hole transport layer or an inorganic electron transport layer; the second inorganic carrier transport layer includes an inorganic hole transport layer or an inorganic electron transport layer; and the first inorganic carrier transport layer and the second inorganic carrier transport layer are of opposite conductive types. ​ ​ ​ The inorganic hole transport layer comprises at least one of NiOx, V2O5, MoOx, WOx, Cu2O, and has a thickness of 0.5-50.0 nm; the inorganic electron transport layer preferably comprises at least one of SnO2, TiO2, ZnO, Nb2O5, ZrO2, TiSnOx, SnZnOx, LiF, MgFx, and has a thickness of 0.5-50.0 nm; The first organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, the second organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, and the first organic carrier transport layer and the second organic carrier transport layer are opposite in conductive type; The organic hole transport layer preferably comprises at least one of 2PACz, Me-4PACz, MeO-2PACz, PTAA, P3HT, Poly-TPD, PEDOT:PSS, Spiro-OMeTAD, m-MTDATA, Spiro-TTB, F4-TCNQ, F6-TCNNQ, and TAPC, and has a thickness of 0.5-50.0 nm; The organic electron transport layer preferably comprises at least one of fullerene C60, fullerene C70, and fullerene derivative PCBM, and has a thickness of 0.5-50.0 nm.

10. A method of manufacturing the perovskite / crystalline silicon tandem cell of claim 1, wherein, The method comprises the following steps: S1, etching and cleaning the surface of a crystalline silicon wafer; S2, sequentially arranging a first interface passivation layer and a first doped silicon layer on the back surface of the crystalline silicon wafer, and sequentially arranging a second interface passivation layer, a second doped silicon layer, an amorphous germanium layer, and an intermediate composite layer on the front surface of the crystalline silicon wafer; S3, arranging a first transparent conductive oxide film layer and a metal conductive film layer on the surface of the first doped silicon layer on the back surface, and arranging a first carrier transport layer on the surface of the first doped silicon layer on the front surface; S4, depositing a perovskite light-absorbing layer on the surface of the first carrier transport layer; S5, depositing a second carrier transport layer on the surface of the perovskite light-absorbing layer; S6, depositing a second transparent conductive oxide film layer on the surface of the second carrier transport layer; S7, arranging a metal grid electrode on the surface of the second transparent conductive oxide film layer.

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