Semiconductor packaging structure and preparation method therefor

Abstract

The present application relates to a semiconductor packaging structure and a preparation method therefor. The semiconductor packaging structure comprises: a DRAM wafer, the DRAM wafer comprising a plurality of DRAM chips and a plurality of first through-silicon vias penetrating the DRAM wafer; a BEOL layer, which is located on one side of the DRAM wafer; a DTC layer, which is located on the side surface of the BEOL layer facing away from the DRAM wafer, the DTC layer comprising a plurality of DTC chips, and each DTC chip being provided with a plurality of second through-silicon vias; and a processor layer, which is located on the side surface of the DTC layer facing away from the BEOL layer, the processor layer comprising a plurality of processor chips, wherein the DRAM wafer and the DTC layer are connected together by means of hybrid bonding, and the DTC layer and the processor layer are connected together by means of hybrid bonding. The semiconductor packaging structure provided in the present application can improve the integration density of a system, improve the stability and strength of an SoW packaging structure, reduce the transmission distance and transmission power consumption for stored data, mitigate crosstalk and return loss by means of a DTC, and reduce power network impedance, thereby further improving the signal integrity of a DRAM and the overall power integrity of the system.

Description

Semiconductor package structure and preparation method thereof

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411156445.9, filed on August 21, 2024, and entitled "Semiconductor package structure and preparation method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor package structure, in particular to a semiconductor package structure and a preparation method thereof. BACKGROUND

[0004] System on Wafer (SoW) packaging technology is a kind of advanced packaging technology. The core advantage of SoW packaging technology lies in its ability to achieve high integration and modularization. By integrating multiple functional modules on a single wafer, SoW packaging can reduce the interconnection distance between chips, reduce signal transmission delay, and improve data transmission rate. In addition, SoW packaging can also reduce power consumption and improve energy efficiency by sharing power and signal lines.

[0005] However, SoW packaging technology also has some technical defects, the most critical of which is the integration of memory. Since SoW packaging technology usually focuses on the integration of logic chips, the integration of memory chips is relatively complex. Memory chips usually require a large area to store data, and they also have higher requirements for signal integrity and power consumption. The current memory integration scheme in SOW packaging technology is to connect a dynamic random access memory (DRAM) with a PCIe interface storage card to a processor (xPU). This approach has two problems: 1) the transmission path from DRAM to xPU is long; 2) DRAM data transmission needs to go through protocol conversion. This scheme not only adds extra load power consumption, but also leads to poor signal integrity and power integrity, and occupies a lot of area vertically, resulting in poor overall stability and strength of the package structure.

[0006] Therefore, a solution is needed that can integrate DRAM and xPU chips directly together, reduce the transmission path from DRAM to xPU, reduce transmission power consumption, improve signal integrity and power integrity, and improve the overall stability and strength of the package structure. SUMMARY

[0007] Therefore, the application provides a semiconductor packaging structure and a preparation method thereof to solve the problems of long transmission path from DRAM to xPU, high transmission power consumption, poor signal integrity and power integrity, and poor overall stability and strength of the packaging structure due to the protocol conversion of DRAM data transmission in the existing SOW packaging technology.

[0008] The application provides a semiconductor packaging structure, comprising:

[0009] a DRAM wafer, wherein the DRAM wafer comprises a plurality of DRAM chips and a plurality of first through silicon vias penetrating through the DRAM wafer;

[0010] a BEOL layer located on one side of the DRAM wafer;

[0011] a DTC layer located on a surface of the BEOL layer away from the DRAM wafer, wherein the DTC layer comprises a plurality of DTC chips, and each DTC chip comprises a plurality of second through silicon vias;

[0012] a processor layer located on a surface of the DTC layer away from the BEOL layer, wherein the processor layer comprises a plurality of processor chips;

[0013] the DRAM wafer and the DTC layer are connected together by hybrid bonding, and the DTC layer and the processor layer are connected together by hybrid bonding.

[0014] Optionally, the processor chip comprises a plurality of interconnection pins.

[0015] The interconnection pins are connected to the BEOL layer through the second through silicon vias, and then connected to the DRAM chip.

[0016] Optionally, the DRAM chip further comprises a plurality of solder balls and PADs.

[0017] The solder balls are located on a surface of the DRAM wafer away from the DTC layer, and the solder balls are connected to the first through silicon vias.

[0018] The PADs are connected to the second through silicon vias.

[0019] The interconnection pins are connected to the BEOL layer through the second through silicon vias, and then connected to the solder balls through the PADs and the second through silicon vias.

[0020] Optionally, there is a first gap between any two adjacent DTC chips.

[0021] The DTC layer is a DTC wafer or a plurality of DTC chips, and the DTC wafer comprises a plurality of DTC chips.

[0022] When the DTC layer is a DTC wafer, the first gap is filled with silicon; when the DTC layer is a plurality of DTC chips, the first gap is filled with air.

[0023] Optionally, there is a second gap between any two adjacent processor chips.

[0024] The processor layer is a processor wafer or a plurality of processor chips; the processor wafer includes a plurality of processor chips.

[0025] When the processor layer is a processor wafer, the second gap is filled with silicon; when the processor layer is a plurality of processor chips, the filling material of the second gap is plastic package material, heat-conducting material or air.

[0026] The application also provides a preparation method of a semiconductor packaging structure, characterized by comprising the following steps:

[0027] A DRAM wafer is provided; the DRAM wafer includes a plurality of DRAM chips and a plurality of first through-silicon vias penetrating through the DRAM wafer.

[0028] A BEOL layer is formed on one side of the DRAM wafer.

[0029] A DTC layer is arranged on the surface of the side of the BEOL layer away from the DRAM wafer, and the DRAM wafer and the DTC layer are connected together by hybrid bonding; the DTC layer includes a plurality of DTC chips; the DTC chips are provided with a plurality of second through-silicon vias.

[0030] A processor layer is arranged on the surface of the side of the DTC layer away from the BEOL layer, and the DTC layer and the processor layer are connected together by hybrid bonding; the processor layer includes a plurality of processor chips.

[0031] Optionally, the DRAM chips further include a plurality of solder balls and pads; the solder balls are connected with the first through-silicon vias.

[0032] In the step of connecting the DRAM wafer and the DTC layer together by hybrid bonding,

[0033] A BEOL layer is formed on the surface of the side of the DRAM wafer away from the solder balls, and the metal layer in the BEOL layer is connected with the pads of the DRAM chips, so that the pads correspond to the second through-silicon vias through the BEOL layer.

[0034] The pads and the second through-silicon vias are connected together by hybrid bonding.

[0035] Optionally, the processor chips include a plurality of interconnection pins.

[0036] the step of connecting the DTC layer and the processor layer together through hybrid bonding,

[0037] the interconnection pins are connected to the second through silicon vias one by one and through hybrid bonding, so that the interconnection pins are connected to the BEOL layer through the second through silicon vias, and then connected to the DRAM chip.

[0038] Optionally, the step of providing the DRAM wafer further comprises:

[0039] providing a wafer, and forming the first through silicon vias and the recess in the wafer;

[0040] fixing the DRAM chip in the recess;

[0041] reconfiguring the DRAM chip to form the DRAM wafer;

[0042] Alternatively:

[0043] providing an initial DRAM wafer, the DRAM wafer comprising a plurality of DRAM chips and initial through silicon vias penetrating the DRAM chips;

[0044] forming the first through silicon vias on the initial DRAM wafer to obtain the DRAM wafer; wherein part of the first through silicon vias are connected to the initial through silicon vias.

[0045] Optionally, the DTC layer is a DTC wafer or a plurality of DTC chips; the DTC wafer comprises a plurality of DTC chips;

[0046] the processor layer is a processor wafer or a plurality of processor chips; the processor wafer comprises a plurality of processor chips.

[0047] The technical solution of the present application has the following advantages:

[0048] The semiconductor packaging structure provided by the application realizes the integration of memory chips through the SoW packaging technology. Firstly, the DRAM wafer and the xPU chip are directly integrated together through the SoW packaging technology, which greatly shortens the signal transmission path length from the DRAM wafer to the xPU chip, reduces the transmission power consumption, and improves the signal integrity. Secondly, the DRAM wafer can be used as an additional bottom support for the xPU chip without occupying the wafer area in the packaging structure, which realizes a great interconnection density and integration degree, reduces the wafer warping in the packaging structure, improves the wafer strength, and further improves the stability and strength of the packaging structure. Finally, by arranging the embedded deep trench capacitor (DTC) between the DRAM wafer and the xPU chip, and by interconnecting the xPU chip and the DTC through hybrid bonding and interconnecting the DTC and the DRAM wafer through hybrid bonding, the power supply for the xPU chip and the DRAM wafer can be optimized, the power supply ripple can be reduced, the overall system stability can be improved, and the signal transmission interference can be further reduced, and the signal integrity can be improved. Therefore, the semiconductor packaging structure provided by the application deeply integrates the DRAM, the DTC, the TSV and the xPU, which can improve the system integration density, improve the stability and strength of the SoW packaging structure, reduce the transmission distance and transmission power consumption of the storage data, improve the crosstalk and return loss through the DTC, reduce the power supply network impedance, and further improve the signal integrity of the DRAM and the overall power integrity of the system.

[0049] The semiconductor packaging structure provided by the application realizes the integration of memory chips through the SoW packaging technology. Firstly, the DRAM wafer and the xPU chip are directly integrated together through the SoW packaging technology, which greatly shortens the signal transmission path length from the DRAM wafer to the xPU chip, reduces the transmission power consumption, and improves the signal integrity. Secondly, the DRAM wafer can be used as an additional bottom support for the xPU chip without occupying the wafer area in the packaging structure, which realizes a great interconnection density and integration degree, reduces the wafer warping in the packaging structure, improves the wafer strength, and further improves the stability and strength of the packaging structure. Finally, by arranging the embedded deep trench capacitor (DTC) between the DRAM wafer and the xPU chip, and by interconnecting the xPU chip and the DTC through hybrid bonding and interconnecting the DTC and the DRAM wafer through hybrid bonding, the power supply for the xPU chip and the DRAM wafer can be optimized, the power supply ripple can be reduced, the overall system stability can be improved, and the signal transmission interference can be further reduced, and the signal integrity can be improved. Therefore, the semiconductor packaging structure provided by the application deeply integrates the DRAM, the DTC, the TSV and the xPU, which can improve the system integration density, improve the stability and strength of the SoW packaging structure, reduce the transmission distance and transmission power consumption of the storage data, improve the crosstalk and return loss through the DTC, reduce the power supply network impedance, and further improve the signal integrity of the DRAM and the overall power integrity of the system. Therefore, the semiconductor packaging structure provided by the application deeply integrates the DRAM, the DTC, the TSV and the xPU, which can improve the system integration density, improve the stability and strength of the SoW packaging structure, reduce the transmission distance and transmission power consumption of the storage data, improve the crosstalk and return loss through the DTC, reduce the power supply network impedance, and further improve the signal integrity of the DRAM and the overall power integrity of the system. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed to be used in the description of the specific embodiments or prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0051] Fig. 1 is a structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present application;

[0052] Fig. 2 is a flowchart of a method for manufacturing a semiconductor packaging structure according to an embodiment of the present application;

[0053] Figs. 3-6 are structural schematic diagrams of various flows of a method for manufacturing a semiconductor packaging structure according to an embodiment of the present application.

[0054] Legend: 1-DRAM wafer; 2-BEOL layer; 3-DTC layer; 4-processor layer; 11-DRAM chip; 12-first through-silicon via; 13-solder ball; 31-DTC chip; 32-second through-silicon via; 41-processor chip; 42-interconnection pin. DETAILED DESCRIPTION

[0055] To solve the problems of long transmission path from DRAM to xPU in the existing SOW packaging technology, DRAM data transmission needs to go through protocol conversion, resulting in high transmission power consumption, poor signal integrity and power integrity, and occupying a large area in the vertical direction, leading to poor overall stability and strength of the packaging structure, the present application provides a semiconductor packaging structure, comprising: a DRAM wafer; the DRAM wafer comprises a plurality of DRAM chips and a plurality of first through-silicon vias penetrating the DRAM wafer; a BEOL layer located on one side of the DRAM wafer; a DTC layer located on the surface of the side of the BEOL layer away from the DRAM wafer, the DTC layer comprising a plurality of DTC chips; the DTC chip has a plurality of second through-silicon vias; a processor layer located on the surface of the side of the DTC layer away from the BEOL layer; the processor layer comprises a plurality of processor chips; the DRAM wafer and the DTC layer are connected together by hybrid bonding; the DTC layer and the processor layer are connected together by hybrid bonding.

[0056] The application further provides a preparation method of the semiconductor packaging structure, comprising the following steps: providing a DRAM wafer; the DRAM wafer comprises a plurality of DRAM chips and a plurality of first through silicon vias penetrating through the DRAM wafer; forming a BEOL layer on one side of the DRAM wafer; disposing a DTC layer on the surface of the side of the BEOL layer away from the DRAM wafer, and connecting the DRAM wafer and the DTC layer together through hybrid bonding; the DTC layer comprises a plurality of DTC chips; the DTC chips are provided with a plurality of second through silicon vias; disposing a processor layer on the surface of the side of the DTC layer away from the BEOL layer, and connecting the DTC layer and the processor layer together through hybrid bonding; the processor layer comprises a plurality of processor chips.

[0057] The technical solutions of the application will be described clearly and completely in the following with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application. In the description of the application, it should be noted that the terms “first”, “second”, “third” are only used for description purpose, and cannot be understood as indicating or implying relative importance.

[0058] Embodiment 1

[0059] Referring to FIG. 1, the embodiment provides a semiconductor packaging structure, comprising:

[0060] a DRAM wafer 1; the DRAM wafer comprises a plurality of DRAM chips 11 and a plurality of first through silicon vias 12 penetrating through the DRAM wafer 1;

[0061] a BEOL layer 2 located on one side of the DRAM wafer 1;

[0062] a DTC layer 3 located on the surface of the side of the BEOL layer 2 away from the DRAM wafer 1; the DTC layer 3 comprises a plurality of DTC chips 31; the DTC chips are provided with a plurality of second through silicon vias 32;

[0063] a processor layer 4 located on the surface of the side of the DTC layer 3 away from the BEOL layer 2; the processor layer 4 comprises a plurality of processor chips 41;

[0064] the DRAM wafer 1 and the DTC layer 3 are connected together through hybrid bonding; the DTC layer 3 and the processor layer 4 are connected together through hybrid bonding.

[0065] In specific implementation, the DRAM chips 11 can be distributed on the wafer, or can be arranged in a targeted manner directly below the processor chips 41 without covering the wafer.

[0066] In some embodiments, the first TSVs 12 are located between adjacent DRAM chips 11, and no first TSVs are located within the DRAM chips 11; in other embodiments, some of the first TSVs 12 pass through the DRAM chips 11.

[0067] The semiconductor package structure provided by the embodiment realizes the integration of memory chips through the SoW packaging technology. First, the DRAM wafer and the xPU chip are directly integrated together through the SoW packaging technology, which greatly shortens the signal transmission path length of the DRAM wafer to the xPU chip, reduces the transmission power consumption, and improves the signal integrity. Second, the embodiment does not need to occupy the area of the wafer in the packaging structure, realizes a great interconnection density and integration, and the DRAM wafer can also serve as an additional bottom support for the xPU chip, reduces the wafer warpage in the packaging structure, improves the wafer strength, and further improves the stability and strength of the packaging structure. Finally, by arranging the DTC between the DRAM wafer and the xPU chip, and by interconnecting the xPU chip and the DTC through hybrid bonding and interconnecting the DTC and the DRAM wafer through hybrid bonding, the power supply can be cooperatively optimized, the power supply ripple can be reduced, the overall system stability can be improved, and the DTC can further reduce the interference of signal transmission and improve the signal integrity. Therefore, the semiconductor package structure provided by the embodiment deeply integrates the DRAM, the DTC, the TSV, and the xPU, can improve the system integration density, improve the stability and strength of the SoW packaging structure, reduce the transmission distance and transmission power consumption of the storage data, improve the crosstalk and return loss through the DTC, reduce the power supply network impedance, and further improve the signal integrity of the DRAM and the overall power integrity of the system.

[0068] Optionally, in the embodiment, the processor chip 41 includes a plurality of interconnection pins 42.

[0069] The interconnection pins 42 are connected to the BEOL layer 2 through the second TSVs 32, and then connected to the DRAM chips 11.

[0070] In specific implementation, the BEOL layer 2 can also realize the interconnection between the processor chips 41 through the interconnection pins 42 and the second TSVs 32.

[0071] Optionally, in the embodiment, the DRAM chip further includes a plurality of solder balls 13 and PADs;

[0072] The solder balls 13 are located on the side surface of the DRAM wafer 1 facing away from the DTC layer 3; the solder balls 13 are connected to the first TSVs 12.

[0073] The PAD is connected with the second through silicon via 32;

[0074] The interconnection pin 42 is connected to the BEOL layer 2 through the second through silicon via 32, and then connected with the solder ball 13 through the PAD and the second through silicon via 32.

[0075] In particular implementation, the second through silicon via 32 is used to lead out the interconnection pin 42 of the xPU chip, facilitating interconnection with the DRAM wafer 1; the PAD is used to connect the first through silicon via 12 and the second through silicon via 32, and realize hybrid bonding of the DTC layer 3 and the DRAM wafer 1 in combination with the BEOL layer 2; the first through silicon via 12 is used to lead out the signal of the interconnection pin 42 to the side of the DRAM wafer 1 opposite to the processor layer 4; and the solder ball 13 is used to expand functions, and realize back vertical power supply through a voltage regulation module (VRM).

[0076] In some embodiments, the solder ball 13 does not need to be arranged on all the first through silicon vias 12, and can be arranged according to actual needs.

[0077] Optionally, in this embodiment, there is a first gap between any two adjacent DTC chips 31.

[0078] The DTC layer 3 is a DTC wafer or a plurality of DTC chips 31; and the DTC wafer includes a plurality of DTC chips 31.

[0079] When the DTC layer 3 is a DTC wafer, the first gap is silicon filling; and when the DTC layer 3 is a plurality of DTC chips 31, the first gap is air filling.

[0080] Optionally, in this embodiment, there is a second gap between any two adjacent processor chips 41.

[0081] The processor layer 4 is a processor wafer or a plurality of processor chips 41; and the processor wafer includes a plurality of processor chips.

[0082] When the processor layer 4 is a processor wafer, the second gap is silicon filling; and when the processor layer 4 is a plurality of processor chips 41, the filling material of the second gap is plastic sealing material, heat-conducting material or air.

[0083] Embodiment 2

[0084] Referring to FIG. 2, the application further provides a preparation method of a semiconductor packaging structure, which is used to prepare the semiconductor packaging structure of the above embodiment 1. The method includes the following steps:

[0085] S201, providing a DRAM wafer; the DRAM wafer includes a plurality of DRAM chips; and the DRAM chip is provided with a plurality of first through silicon vias, as shown in FIG. 3.

[0086] S202, forming a BEOL layer on one side of the DRAM wafer, as shown in FIG. 4.

[0087] S203, disposing a DTC layer on the surface of the side of the BEOL layer away from the DRAM wafer, and connecting the DRAM wafer and the DTC layer together through hybrid bonding; the DTC layer comprises a plurality of DTC chips; the DTC chips are provided with a plurality of second through silicon vias, as shown in FIG. 5.

[0088] S204, disposing a processor layer on the surface of the side of the DTC layer away from the BEOL layer, and connecting the DTC layer and the processor layer together through hybrid bonding; the processor layer comprises a plurality of processor chips, as shown in FIG. 6.

[0089] The semiconductor packaging structure preparation method provided by the embodiment can prepare the semiconductor packaging structure provided by the embodiment. The semiconductor packaging structure provided by the embodiment realizes the integration of memory chips through SoW packaging technology. First, the DRAM wafer and the xPU chip are directly integrated together through SoW packaging technology in the embodiment, which greatly shortens the signal transmission path length from the DRAM wafer to the xPU chip, reduces the transmission power consumption, and improves the signal integrity. Second, the embodiment does not need to occupy the wafer area in the packaging structure, realizes great interconnection density and integration, and the DRAM wafer can also serve as an additional bottom support for the xPU chip, reduces the wafer warpage in the packaging structure, improves the wafer strength, and further improves the stability and strength of the packaging structure. Finally, by disposing the DTC between the DRAM wafer and the xPU chip, and interconnecting the xPU chip and the DTC through hybrid bonding, and interconnecting the DTC and the DRAM wafer through hybrid bonding, the power supply can be optimized cooperatively, the power supply ripple can be reduced, the overall system stability can be improved, and the DTC can further reduce the interference of signal transmission and improve the signal integrity. Therefore, the semiconductor packaging structure preparation method provided by the embodiment introduces BEOL technology, through silicon via technology, wafer reconstruction technology, hybrid bonding technology, etc., realizes high-density interconnection of DRAM, DTC and xPU, and forms a high-integration and high-interconnection-density semiconductor packaging structure.

[0090] Optionally, in some embodiments, the DRAM chip further comprises a plurality of solder balls and PADs; the solder balls are connected with the first through silicon vias;

[0091] In the step of connecting the DRAM wafer and the DTC layer together through hybrid bonding,

[0092] forming a BEOL layer on the side of the DRAM wafer opposite to the side of the solder balls, and connecting the PADs of the DRAM chips to the metal layers in the BEOL layer, so that the PADs of the DRAM chips are repositioned through the BEOL layer, and the repositioned PADs correspond to the second through silicon vias through the BEOL layer;

[0093] mixing and bonding the PADs and the second through silicon vias together.

[0094] In particular implementation, first, the PADs of the DRAM chips are repositioned through the metal layers in the BEOL layer (the actual positions of the PADs do not change), so that the repositioned PADs correspond to the second through silicon vias through the BEOL layer, and then the DRAM wafer and the DTC layer are integrated together through the mixing and bonding process.

[0095] Optionally, in some embodiments, the processor chip includes a plurality of interconnection pins;

[0096] In the step of mixing and bonding the DTC layer and the processor layer together,

[0097] corresponding to the second through silicon vias one by one and mixing and bonding together, so that the interconnection pins are connected to the BEOL layer through the second through silicon vias, and then connected to the DRAM chips.

[0098] In particular implementation, the BEOL layer can also realize the interconnection between the processor chips through the interconnection pins and the second through silicon vias.

[0099] Optionally, in some embodiments, the step of providing the DRAM wafer further includes:

[0100] providing a wafer, and forming the first through silicon vias and grooves in the wafer;

[0101] fixing the DRAM chips in the grooves;

[0102] reconstructing the DRAM chips to form the DRAM wafer;

[0103] or:

[0104] providing an initial DRAM wafer, the DRAM wafer including a plurality of DRAM chips and initial through silicon vias penetrating through the DRAM chips;

[0105] forming the first through silicon vias on the initial DRAM wafer to obtain the DRAM wafer; and

[0106] In practice, there are multiple ways to form the DRAM wafer:

[0107] In one example, first, a first through silicon via and a recess are formed on a wafer; second, a DRAM chip in a single form (or a DRAM module, which can be formed by 3D stacking of DRAM chips, and it should be noted that the height of the module should be controlled to ensure that the wafer reconstruction can be completed) is provided; and finally, the DRAM chip or DRAM module is fixed in the recess to complete the DRAM wafer reconstruction, forming a DRAM wafer with a first through silicon via structure, wherein the first through silicon via 12 is located between adjacent DRAM chips, and there is no first through silicon via in the DRAM chip. The warpage of the DRAM wafer needs to be controlled during the process.

[0108] In another example, first, an initial DRAM wafer obtained by Fab flow is provided, which includes a plurality of DRAM chips and an initial through silicon via penetrating the DRAM chips; then, a Via-Last process is used to form the first through silicon via on the initial DRAM wafer, obtaining a DRAM wafer with a first through silicon via structure; and part of the first through silicon via is connected with the initial through silicon via.

[0109] In other examples, a DRAM wafer with a first through silicon via structure obtained by a Fab flow process can be directly used.

[0110] Optionally, in some embodiments, the DTC layer is a DTC wafer or a plurality of DTC chips; the DTC wafer includes a plurality of DTC chips.

[0111] The processor layer is a processor wafer or a plurality of processor chips; the processor wafer includes a plurality of processor chips.

[0112] In practice, the integration of the DRAM wafer and the DTC layer can be Wafer-to-Wafer (W2W) integration of the DTC wafer in a hybrid bonding form or Die-to-Wafer (D2W) integration of a single DTC chip with the DRAM wafer.

[0113] In practice, the integration of the DTC layer and the xPU layer can be W2W integration of the entire xPU wafer in a hybrid bonding form or D2W integration of a single xPU chip with the DTC layer.

[0114] Optionally, in some embodiments, when the DTC layer is a DTC wafer, before the step of disposing the DTC layer on the side surface of the BEOL layer facing away from the DRAM wafer, the method further comprises: preparing a DTC wafer with a second through-silicon via structure, and the preparation can be performed in two ways: the first way is to selectively arrange the DTC and the second through-silicon via array at intervals, so that the DTC interface and the second through-silicon via can correspond to each interconnection pin of the xPU, achieving the purpose of leading out the signals of the xPU, that is, obtaining a DTC wafer with a TSV structure; the second way is to perform front and back RDL operations on the DTC wafer separately or together, similar to the process flow of a through-silicon via adapter, to realize double-sided wiring of the front surface (the surface connected to the xPU) and the back surface (the surface connected to the DRAM wafer).

[0115] Obviously, the above embodiments are only examples for the purpose of clarity, and are not intended to limit the embodiments. Based on the above description, those skilled in the art can make other different forms of changes or modifications. Here, it is not necessary and impossible to enumerate all the embodiments. The obvious changes or modifications derived therefrom are still within the scope of protection of the present application.

Claims

1. A semiconductor package structure, comprising: Comprising: a DRAM wafer; the DRAM wafer comprising a plurality of DRAM chips and a plurality of first through-silicon vias (TSVs) penetrating through the DRAM wafer; a BEOL layer on one side of the DRAM wafer; a DTC layer on a side surface of the BEOL layer facing away from the DRAM wafer, the DTC layer comprising a plurality of DTC chips, the DTC chips being provided with a plurality of second TSVs; a processor layer on a side surface of the DTC layer facing away from the BEOL layer, the processor layer comprising a plurality of processor chips; the DRAM wafer and the DTC layer being connected together by hybrid bonding, and the DTC layer and the processor layer being connected together by hybrid bonding.

2. The semiconductor package structure of claim 1, wherein: the processor chips comprise a plurality of interconnection pins; the interconnection pins are connected to the BEOL layer through the second TSVs, and then connected to the DRAM chips.

3. The semiconductor package structure of claim 2, wherein: the DRAM chips further comprise a plurality of solder balls and pads (PADs); the solder balls are on a side surface of the DRAM wafer facing away from the DTC layer, and the solder balls are connected to the first TSVs; the PADs are connected to the second TSVs; the interconnection pins are connected to the BEOL layer through the second TSVs, and then connected to the solder balls through the PADs and the first TSVs.

4. The semiconductor package structure of claim 1, wherein: a first gap exists between any two adjacent DTC chips; the DTC layer is a DTC wafer or a plurality of DTC chips, and the DTC wafer comprises a plurality of DTC chips; when the DTC layer is a DTC wafer, the first gap is filled with silicon, and when the DTC layer is a plurality of DTC chips, the first gap is filled with air.

5. The semiconductor package structure of claim 1, wherein: a second gap exists between any two adjacent processor chips; the processor layer is a processor wafer or a plurality of processor chips, and the processor wafer comprises a plurality of processor chips; when the processor layer is a processor wafer, the second gap is filled with silicon, and when the processor layer is a plurality of processor chips, the second gap is filled with molding compound, thermally conductive material, or air.

6. A method of fabricating a semiconductor package structure, comprising: Comprising the following steps: providing a DRAM wafer; the DRAM wafer comprising a plurality of DRAM chips and a plurality of first TSVs penetrating through the DRAM wafer; forming a BEOL layer on one side of the DRAM wafer; providing a DTC layer on a side surface of the BEOL layer facing away from the DRAM wafer, and connecting the DRAM wafer and the DTC layer together by hybrid bonding, the DTC layer comprising a plurality of DTC chips, and the DTC chips being provided with a plurality of second TSVs; providing a processor layer on a side surface of the DTC layer facing away from the BEOL layer, and connecting the DTC layer and the processor layer together by hybrid bonding, the processor layer comprising a plurality of processor chips.

7. The method of claim 6, wherein: the DRAM chips further comprise a plurality of solder balls and pads; and the solder balls are connected to the first TSVs; in the step of connecting the DRAM wafer and the DTC layer together by hybrid bonding, a BEOL layer is formed on a surface of the DRAM wafer opposite to the solder balls, and a metal layer in the BEOL layer is connected to the pads of the DRAM chips, so that the pads are connected to the second TSVs through the BEOL layer; the pads and the second TSVs are connected together by hybrid bonding.

8. The method of claim 7, wherein: the processor chips comprise a plurality of interconnection pins; in the step of connecting the DTC layer and the processor layer together by hybrid bonding, the interconnection pins are connected to the second TSVs one by one by hybrid bonding, so that the interconnection pins are connected to the BEOL layer through the second TSVs, and then connected to the DRAM chips.

9. The method of claim 8, wherein: before the step of providing the DRAM wafer, the method further comprises: providing a wafer, and forming the first TSVs and grooves in the wafer; fixing the DRAM chips in the grooves; reconfiguring the DRAM chips to form the DRAM wafer; or providing an initial DRAM wafer, and the initial DRAM wafer comprises a plurality of DRAM chips and initial TSVs penetrating through the DRAM chips; forming the first TSVs on the initial DRAM wafer to obtain the DRAM wafer; and part of the first TSVs are connected to the initial TSVs.

10. The method of claim 6, wherein: the DTC layer is a DTC wafer or a plurality of DTC chips, and the DTC wafer comprises a plurality of DTC chips; the processor layer is a processor wafer or a plurality of processor chips, and the processor wafer comprises a plurality of processor chips.

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