Method for producing a technical semiconductor substrate, and technical semiconductor substrate

Abstract

The invention relates to a method (100) for producing a technical semiconductor substrate, comprising the steps of providing (110) a powder mixture comprising a semiconductor powder having a first coefficient of thermal expansion and an additive having a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion, producing (120) a polycrystalline semiconductor substrate from the powder mixture by means of sintering, wherein the polycrystalline semiconductor substrate has a third coefficient of thermal expansion which is greater than the first coefficient of thermal expansion, and applying (130) a monocrystalline semiconductor layer to the polycrystalline semiconductor substrate by means of bonding.

Description

[0001] R. 414940

[0002] - 1 -

[0003] Description

[0004] Method for producing a technical semiconductor substrate and technical semiconductor substrate

[0005] The invention relates to a method for producing a technical semiconductor substrate, a technical semiconductor substrate and a vertical power semiconductor device with a technical semiconductor substrate.

[0006] State of the art

[0007] Engineered semiconductor substrates can be specifically manufactured to optimize the properties of semiconductor substrates for use in power devices. These substrates are created, for example, by bonding a thin monocrystalline layer to a polycrystalline substrate. Subsequently, further semiconductor layers are epitaxially deposited onto the engineered semiconductor substrate. If the semiconductor materials of the monocrystalline layer and the polycrystalline substrate differ, it becomes problematic to epitaxially deposit thick layers onto the monocrystalline layer, as this can lead to stresses within the monocrystalline layer, potentially resulting in wafer bow. This complicates substrate processing and can even lead to wafer breakage.

[0008] The purpose of the invention is to overcome this disadvantage.

[0009] Disclosure of the invention

[0010] The inventive method for producing a technical semiconductor substrate comprises providing a powder mixture comprising a semiconductor powder with a first coefficient of thermal expansion and an R. 414940

[0011] - 2 -

[0012] The additive has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion. Furthermore, the process comprises producing a polycrystalline semiconductor substrate from the powder mixture by sintering, wherein the polycrystalline semiconductor substrate has a third coefficient of thermal expansion that is greater than the first coefficient of thermal expansion, and depositing a monocrystalline semiconductor layer onto the polycrystalline semiconductor substrate by bonding.

[0013] The advantage here is that the coefficient of thermal expansion of the polycrystalline substrate can be adapted to the coefficient of thermal expansion of the monocrystalline layer.

[0014] In a further training course, the powder mixture contains up to 10% additive.

[0015] An advantage here is that the lattice mismatch between the polycrystalline semiconductor substrate and the monocrystalline semiconductor layer is less than 5%.

[0016] In another embodiment, the additive contains BN, TiN, AIN or Y2O3.

[0017] The advantage here is that the coefficient of thermal expansion of the polycrystalline semiconductor substrate can be increased by up to 20%.

[0018] In a further training course, the monocrystalline semiconductor layer includes GaN.

[0019] The advantage here is that thick GaN epitaxy layers can be produced on the technical semiconductor substrate.

[0020] In another embodiment, the semiconductor powder contains SiC.

[0021] The advantage here is that the electrical and thermal conductivity of SiC are not significantly affected by the additive.

[0022] The technical semiconductor substrate comprises a polycrystalline semiconductor substrate and a monocrystalline semiconductor layer, which is applied to the polycrystalline substrate. R. 414940

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[0024] The semiconductor substrate is arranged according to the invention, the polycrystalline semiconductor substrate has an additive.

[0025] The advantage here is that thick epitaxial layers can be created on the technical semiconductor substrate.

[0026] In a further training course, the additive comprises a volume fraction of up to 10% of the polycrystalline semiconductor substrate.

[0027] In another embodiment, the additive contains BN, TiN, AIN or Y2O3.

[0028] In a further training course, the polycrystalline semiconductor substrate SiC and the monocrystalline semiconductor layer GaN are included.

[0029] The advantage here is that the thermal expansion coefficients of the two materials have a small difference, so that the remaining delta can be easily compensated.

[0030] The vertical power semiconductor device according to the invention comprises a technical semiconductor substrate according to the invention.

[0031] Further advantages arise from the following description of exemplary embodiments or the dependent patent claims.

[0032] Brief description of the drawings

[0033] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. These show:

[0034] Figure 1 shows a method for producing a technical semiconductor substrate,

[0035] Figure 2 shows a technical semiconductor substrate, and

[0036] Figure 3 shows a power semiconductor device with a technical semiconductor substrate. R. 414940

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[0038] Figure 1 shows a process 100 for producing a technical semiconductor substrate. The process 100 starts with a step 110 in which a powder mixture of semiconductor powder with a first coefficient of thermal expansion and an additive with a second coefficient of thermal expansion are provided. The second coefficient of thermal expansion differs in magnitude from the first coefficient of thermal expansion. The second coefficient of thermal expansion can be larger or smaller than the first coefficient of thermal expansion. The proportion of the additive in the powder mixture is up to 10%. In a subsequent step 120, a polycrystalline semiconductor substrate is produced from the powder mixture by sintering. The polycrystalline semiconductor substrate has a third coefficient of thermal expansion. The magnitude of the third coefficient of thermal expansion lies between the first and second coefficients of thermal expansion.In a subsequent step 130, a monocrystalline semiconductor layer is deposited onto the polycrystalline semiconductor layer using bonding. For this purpose, a predetermined breaking point is created in a monocrystalline donor wafer, for example, by hydrogen ion implantation. The predetermined breaking point is typically located up to 1 pm below the surface of the donor wafer that has been exposed to hydrogen ion implantation. After bonding the monocrystalline donor wafer to the polycrystalline semiconductor substrate, the predetermined breaking point is activated, leaving a monocrystalline semiconductor layer on the polycrystalline semiconductor substrate. The surface of the monocrystalline semiconductor layer can then optionally be polished to provide a smoother surface for epitaxial fabrication, a so-called epi-ready surface.

[0039] In a preferred embodiment, the semiconductor powder comprises SiC. The additive includes, for example, BN, TiN, AIN, or Y2O3. In these cases, the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion, which in turn makes the third coefficient of thermal expansion also greater than the first coefficient of thermal expansion. In other words, the addition of additive R. 414940

[0040] - 5 - causes an increase in the thermal coefficient of the polycrystalline semiconductor substrate. The monocrystalline semiconductor layer comprises GaN.

[0041] Alternatively, the monocrystalline semiconductor layer comprises gallium oxide or AIN.

[0042] In another embodiment, the semiconductor powder is SiC and the monocrystalline semiconductor layer is GaN. Adding the additive BN to the semiconductor powder at a volume fraction of 10% of the powder mixture increases the coefficient of thermal expansion of the polycrystalline semiconductor substrate by almost 20% compared to the coefficient of thermal expansion of a pure polycrystalline semiconductor substrate made of SiC. This reduces the mismatch in the coefficient of thermal expansion between the polycrystalline semiconductor substrate with the additive and the coefficient of thermal expansion of the monocrystalline semiconductor layer from 25% to 5%.

[0043] If other additives are used, care must be taken to ensure that a material with a higher coefficient of thermal expansion than SiC is used. Furthermore, care must be taken to ensure that the positive properties of polycrystalline SiC, particularly its electrical and thermal conductivity, are not significantly reduced. Therefore, the volume fraction of the additives must be limited. In the case of BN, TiN, and AIN, this is typically to concentrations up to 10%, and for yttrium oxide to a maximum of 5%.

[0044] Using process 100, technical semiconductor substrates are produced on which thick epitaxial layers up to 20 pm can be created.

[0045] Figure 2 shows a technical semiconductor substrate 200 comprising a polycrystalline semiconductor substrate 201 and a monocrystalline semiconductor layer 202 arranged on the polycrystalline semiconductor substrate 201. The polycrystalline semiconductor substrate 201 includes an additive. The additive comprises a volume fraction of up to 10% of the polycrystalline semiconductor substrate 201.

[0046] In a preferred embodiment, the polycrystalline semiconductor substrate comprises SiC and the monocrystalline semiconductor layer comprises GaN. The additive comprises, for example, BN, TiN, AIN, or Y₂O₃. R. 414940

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[0048] Figure 3 shows a power semiconductor device 300 with a technical semiconductor substrate as shown in Figure 2. The power semiconductor device 300 comprises a drain electrode 309 on which the polycrystalline semiconductor substrate 201 is arranged. The monocrystalline semiconductor layer 202 is arranged on the polycrystalline semiconductor substrate 201. In a preferred embodiment, the polycrystalline semiconductor substrate 201 comprises SiC and an additive, and the monocrystalline semiconductor layer 202 comprises GaN. The additive comprises BN, TiN, AlN, or Y₂O₃ with a volume concentration of up to 10%. An epitaxial layer 301, preferably comprising GaN, is arranged on the monocrystalline semiconductor layer 202. The power semiconductor device 300 shown here is a trench MOSFET. The transistor head of the trench MOSFET is arranged on the epitaxial layer 301.The transistor head comprises p-doped shielding regions 302, a p-doped channel region 303, an n-doped source region 304, a gate electrode 305, a gate dielectric 306, an insulating layer 307 and a source metallization 308.

[0049] The invention is used, for example, in GaN power transistors exhibiting a high reverse voltage, particularly MOSFETs used in the electric drive systems of electric or hybrid vehicles, for example in DC / DC converters and inverters, as well as in vehicle chargers. The power transistors can also be used in inverters for household appliances such as washing machines.

Claims

R. 414940 - 7 - Claims 1. Method (100) for producing a technical semiconductor substrate comprising the steps: • Providing (110) a powder mixture comprising a semiconductor powder having a first coefficient of thermal expansion and an additive having a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion, • Producing (120) a polycrystalline semiconductor substrate from the powder mixture by sintering, wherein the polycrystalline semiconductor substrate has a third coefficient of thermal expansion which is greater than the first coefficient of thermal expansion, and • Application (130) of a monocrystalline semiconductor layer onto the polycrystalline semiconductor substrate using Bondens.

2. Method (100) according to claim 1 , characterized in that the powder mixture comprises up to 10% additive.

3. Method (100) according to one of claims 1 or 2, characterized in that the additive comprises BN, TiN, AIN or Y2O3.

4. Method (100) according to one of the preceding claims, characterized in that the monocrystalline semiconductor layer comprises GaN.

5. Method (100) according to one of the preceding claims, characterized in that the semiconductor powder comprises SiC.

6. Technical semiconductor substrate (200) comprising a polycrystalline semiconductor substrate (201) and a monocrystalline semiconductor layer (202) deposited on the polycrystalline R. 414940 - 8 - semiconductor substrate (201) is arranged, characterized in that the polycrystalline semiconductor substrate (201) has an additive.

7. Technical semiconductor substrate (200) according to claim 6, characterized in that the additive comprises a volume fraction of up to 10% of the polycrystalline semiconductor substrate included.

8. Technical semiconductor substrate (200) according to claim 6 or 7, characterized in that the additive comprises BN, TiN, AIN or Y2O3.

9. Technical semiconductor substrate (200) according to any one of claims 6 to 8, characterized in that the polycrystalline semiconductor substrate comprises SiC and the monocrystalline semiconductor layer comprises GaN.

10. Vertical power semiconductor device with a technical semiconductor substrate (200) according to any one of claims 6 to 9.

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