Arithmetic processing device and control method

Abstract

CPU packages (10, 20) are configured such that one of CPU cores (1, 2, 3, 4) can locally access a volatile storage unit (6) of the host package (10) and remotely access a volatile storage unit (16) of the other CPU package (20). The present invention also comprises: a monitoring unit (22a) that monitors the access volume of either or both of the frequency of access and the amount of data read from and written to the volatile storage unit (16) of the other CPU package (20); and a frequency changing unit (23a) that changes the operating frequency of an uncore unit (15) included in the monitored CPU package (20) on the basis of the access volume.

Description

Processing device and control method

[0001] The present invention relates to a processing device and a control method, and more particularly to a control method for power-saving control of a processing device including a plurality of CPU packages each including a multi-core CPU (Central Processing Unit) and a volatile storage unit controlled by the multi-core CPU.

[0002] In order to reduce the power consumption of physical servers used to provide web and network services, virtual machine placement methods using virtualization technology have been proposed (Non-Patent Documents 1 and 2). For example, Non-Patent Document 1 describes a technology using NUMA (Non-Uniform Memory Access). This technology selects a CPU core within the same NUMA node and assigns it to a virtual machine. This reduces the occurrence of remote memory access and prevents performance degradation.

[0003] Podzimek, Andrej, et al. "Analyzing the impact of cpu pinning and partial cpu loads on performance and energy efficiency." 2015 15th IEEE / ACM International Symposium on Cluster, Cloud and Grid Computing. IEEE, 2015. (https: / / ieeexplore.ieee.org / document / 7152466)Zhan, Xin, et al. "Carb: A c-state power management arbiter for latency-critical workloads."IEEE Computer Architecture Letters 16.1 (2016): 6-9. (https: / / ieeexplore.ieee.org / document / 7425206)

[0004] Some CPUs used in typical datacenter servers have built-in interfaces, such as a memory controller and a bus that connects to external components (other NUMA nodes, I / O devices, etc.), in the uncore section. The data transfer processing speed within this memory controller, interface, and CPU package depends on the operating frequency of the uncore section. Meanwhile, physical servers equipped with multiple CPU sockets achieve power savings by lowering the uncore frequency and power supply voltage of unused CPU packages (nodes). In this case, if a remote access occurs from the package (local node) running an application to another CPU package (remote node), the access speed to the memory of the other CPU package decreases, resulting in degradation of application performance.

[0005] The present invention has been made in view of the above background, and an object of the present invention is to provide an appropriate access speed for accessing the storage unit of another CPU package.

[0006] In order to solve the above-mentioned problems, the present invention provides an arithmetic processing device having a plurality of CPU packages each having a CPU with a plurality of CPU cores and an uncore unit, and a memory unit controlled by the CPU, wherein the CPU packages are configured so that each CPU core can access the memory unit of its own package as well as the memory units of the other CPU packages, and the device is characterized by comprising a monitoring unit that monitors the amount of access to the memory units of the other CPU packages, either the amount of data accessed or the access frequency, or both, and a frequency change unit that changes the operating frequency of the uncore unit included in the monitored CPU package based on the amount of access.

[0007] According to the present invention, the access speed for accessing the storage unit of another CPU package can be made appropriate.

[0008] FIG. 1 is a configuration diagram (1) of a processing device according to a first embodiment of the present invention; FIG. 2 is a configuration diagram (2) of a processing device according to a first embodiment of the present invention; FIG. 1 is an explanatory diagram (1) explaining a usage state of a processing device according to a first embodiment of the present invention; FIG. 2 is an explanatory diagram (2) explaining a usage state of a processing device according to a first embodiment of the present invention; FIG. 3 is a flowchart explaining the operation of a processing device according to a first embodiment of the present invention; FIG. 4 is a configuration diagram of a processing device according to a second embodiment of the present invention; and FIG. 5 is a configuration diagram explaining the function of a CPU core of a processing device according to a second embodiment of the present invention.

[0009] <<Overview of the Processing Device>> The following describes a processing device according to one embodiment of the present invention. As shown in FIGS. 1A and 1B , the processing device 100 includes multiple CPU packages 10 and 20. The CPU package 10 includes a CPU 7 having multiple CPU cores 1, 2, 3, and 4 and an uncore unit 5, and a storage unit (e.g., a volatile storage unit 6, an L3 cache 5a, and a non-volatile storage unit (not shown)) controlled by the CPU 7. The CPU package 20 includes a CPU 17 having multiple CPU cores 11, 12, 13, and 14 and an uncore unit 15, and a storage unit (e.g., a volatile storage unit 16, an L3 cache 15a, and a non-volatile storage unit (not shown)) controlled by the CPU 17. In this arithmetic processing device 100, the CPU packages 10 and 20 are configured so that each CPU core (e.g., CPU cores 1, 2, 3, and 4) can access (locally access) the storage unit (volatile storage unit 6) of its own package (e.g., CPU package 10) and can access (remotely access) the storage unit (volatile storage unit 16) of the other CPU package 20. Furthermore, the arithmetic processing device 100 includes a monitoring unit 22a that monitors the amount of data accessed (read / write) to the storage unit (volatile storage unit 16) of the other CPU package 20 and / or the access frequency, and a frequency changing unit 23a that changes the operating frequency of the uncore unit 15 included in the monitored CPU package 20 based on the access amount. For example, when the access amount (access frequency) is low, the operating frequency of the uncore unit 15 is lowered to save power. Conversely, when the access amount (access frequency) is high, the operating frequency is increased. This increases the amount of data locally accessed from the storage unit (volatile storage unit 6) via the uncore unit 15, thereby suppressing performance degradation of the application during power-saving operation.

[0010] First Embodiment <Hardware Configuration> Figures 1A and 1B are configuration diagrams of a processing device 100 according to a first embodiment of the present invention. However, in Figure 1B, the physical server 90 is omitted, and the controller 30 is depicted as being disposed in the center. The processing device 100 includes multiple (two) CPU packages 10, 20, a controller 30 that controls the CPU packages 10, 20, and a communication unit 40. Here, the number of CPU packages is multiple and is not limited to two. Furthermore, the multiple CPU packages 10, 20 and the communication unit 40 constitute a physical server 90 (Figure 1A).

[0011] The CPU packages 10 and 20 include CPUs 7 and 17 and volatile storage units 6 and 16. The CPU 7 includes multiple (e.g., four) CPU cores 1, 2, 3, and 4 and an uncore unit 5. Similarly, the CPU 17 includes multiple (e.g., four) CPU cores 11, 12, 13, and 14 and an uncore unit 15.

[0012] The CPU cores 1, 2, 3, 4, 11, 12, 13, and 14 are hardware that executes arithmetic operations such as numerical calculations and logical calculations. The controller 30 appropriately allocates virtual machines that execute application programs to the CPU cores 1, 2, 3, 4, 11, 12, 13, and 14. The CPU cores 1, 2, 3, 4, 11, 12, 13, and 14 implement predetermined functions by executing application programs. The CPU cores 1, 2, 3, 4, 11, 12, 13, and 14 can also operate in a power-saving manner by lowering the clock frequency or voltage.

[0013] The uncore units 5 and 15 are defined as portions (uncores) of the CPU packages 10 and 20 that are not CPU cores. The uncore units 5 and 15 include, for example, an L3 cache 5a or 15a, a memory bus MB, and an I / O port (not shown) for use when the CPU cores 1, 2, 3, 4, 11, 12, 13, and 14 access the volatile storage units 6 and 16. The uncore units 5 and 15 can adjust their operating frequencies independently of the clock frequencies of the CPU cores 1, 2, 3, 4, 11, 12, 13, and 14. The CPUs 7 and 17 include an L1 cache and an L2 cache (not shown).

[0014] The volatile storage units 6 and 16 are, for example, dynamic random access memories (DRAMs) with a storage capacity of 16 Gbytes. Here, the volatile storage units 6 and 16 have the same storage capacity, but they do not have to have the same storage capacity. The communication unit 40 is an interface for connecting to a network.

[0015] The controller 30 is configured with other CPUs and functions as a control unit that controls the CPU packages 10 and 20 (FIG. 2B) of the physical server 90 (FIG. 1A). The controller 30 includes a resource controller 21a, a monitoring unit 22a, and a frequency change unit 23a. The resource controller 21a configures virtual machines and allocates applications to resources such as CPU cores 1, 2, 3, 4, 11, 12, 13, and 14 via application allocation signals A1 and A2. The monitoring unit 22a monitors the amount of access (data volume and access frequency) from one of the CPU packages 10 and 20 to the L3 caches 5a and 15a and volatile memories 6 and 16 of the other CPU package via monitoring signals W1 and W2. The monitoring unit 22a monitors the amount of access using, for example, a performance monitoring counter (PMC) included in the CPU packages 10 and 20. This PMC indicates the number of load instructions issued to obtain data from the memory or cache of a remote node after an L3 cache miss in the local node.

[0016] One of the CPU cores 1, 2, 3, and 4 and the CPU cores 11, 12, 13, and 14 (for example, CPU cores 1, 2, 3, and 4) can not only access (locally access) one of the volatile storage units 6 and 16 (volatile storage unit 6), but also access (remotely access) the other (volatile storage unit 16) via a remote access signal RA. Specifically, when an application program is being executed on the CPU cores 1, 2, 3, and 4 of the CPU package 10, the CPU cores 1, 2, 3, and 4 can not only locally access the volatile storage unit 6 via the L3 cache 5a, but also remotely access the volatile storage unit 16 via the CPU package 20. In other words, the CPU cores 1, 2, 3, and 4 share data in the volatile storage units 6 and 16 via the L3 cache 5a.

[0017] At this time, the monitoring unit 22a monitors the amount of remote access by the CPU cores 1, 2, 3, and 4 to the L3 cache 15a and the volatile storage unit 16. Conversely, when an application is being executed by the CPU cores 11, 12, 13, and 14 of the CPU package 20, the monitoring unit 22a monitors the amount of remote access by the CPU cores 11, 12, 13, and 14 to the L3 cache 5a and the volatile storage unit 6. At this time, the CPU cores 1, 2, 3, and 4 and the CPU cores 11, 12, 13, and 14 share data in the volatile storage units 6 and 16.

[0018] When an application is being executed on the CPU cores 1, 2, 3, and 4 and the amount of access (access frequency) monitored by the monitoring unit 22a is less than a predetermined setting value, the frequency change unit 23a uses the frequency control signal F2 to lower the operating frequency of the uncore unit 15. As a result, when the clock frequencies of the CPU cores 11, 12, 13, and 14 are low and in power-saving mode, the entire CPU package 20, including the uncore unit 15, is maintained in power-saving mode. Conversely, when the amount of access (access frequency) monitored by the monitoring unit 22a is greater than a predetermined setting value, the operating frequency of the uncore unit 15 is increased. This speeds up the access response when the uncore unit 15 remotely accesses the uncore unit 15, increasing the amount of data. Therefore, even when the CPU cores 11, 12, 13, and 14 are in power-saving mode, the amount of data increases. This suppresses performance degradation of applications during power-saving operation. When an application is being executed by the CPU cores 11, 12, 13, and 14, the frequency change unit 23a increases or decreases the clock frequency of the uncore unit 5 using the frequency control signal F1.

[0019] 2 and 3 are explanatory diagrams illustrating an example of a usage state of the processing device according to the first embodiment of the present invention. The processing system 1000 (FIG. 2) includes a processing device 100 as a server and a load balancer 200, and receives traffic from a network via the load balancer 200. The load balancer 200 distributes the traffic received from the network with other servers to reduce the load.

[0020] 2 shows a state in which application 1a is executed by a single CPU core 1, while FIG. 3 shows a state in which applications 1a and 2a are executed by multiple CPU cores 1 and 2. In other words, the resource controller 21a controls the CPU package 10 (CPU cores 1, 2, 3, and 4) to allocate virtual machines that execute applications. As a result, the virtual machine that executes application 1a is allocated to CPU core 1, and the virtual machine that executes application 2a (FIG. 3) is allocated to CPU core 2. In other words, applications 1a and 2a are executed by the CPU package 10.

[0021] Application 1a has strict performance requirements, such as a web application that must return an ACK or other response within a specified time. Application 2a (FIG. 3) is an in-memory database or deep learning application that uses a large amount of memory. Note that CPU cores 1, 2, 3, and 4 share data in volatile storage unit 6.

[0022] In Figures 2 and 3, no applications are allocated to the CPU cores 11, 12, 13, and 14 of the CPU package 20, and the CPU package 20 is set to power-saving mode (idle state). In Figure 2, even though the performance requirements of application 1a are strict, there is sufficient resource capacity, such as in the volatile storage unit 6, so application 1a functions normally. However, in the state of Figure 3 where application 2a is added, there is no sufficient resource capacity, and memory contention occurs in the volatile storage unit 6. As a result, the virtual machines executing applications 1a and 2a remotely access the L3 cache 15a and the volatile storage unit 16. Then, the monitoring unit 22a detects an increase in the amount of access to the volatile storage unit 16, and the frequency change unit 23a increases the operating frequency of the uncore unit 15. As a result, the volatile storage unit 16 operates at high speed even when the CPU cores 11, 12, 13, and 14 are in power-saving mode. Then, when the processing of the application 2a that had been constraining the operation of the volatile storage unit 6 is completed and the virtual machine is removed, the frequency change unit 23a gradually reduces the drive frequency of the uncore unit 15. This returns to the state shown in FIG.

[0023] <<Operation Description>> FIG. 4 is a flowchart illustrating the operation of the arithmetic processing device according to the first embodiment of the present invention. This flow is initiated by power-on or reset, and steps S2 to S11 are periodically repeated (e.g., every one second). First, the controller 30 activates the monitoring unit 22a (step S1). After processing step S1, the monitoring unit 22a causes the CPU core 1 executing the application 1a (FIGS. 2 and 3) to acquire data via the communication unit 40 (FIG. 1) (step S2). As a result, the monitoring unit 22a periodically acquires the amount of remote access (data volume and access frequency) to the volatile storage unit 16 (FIG. 1). After processing step S2, the monitoring unit 22a calculates a moving average value (moving average value Xt) over a certain period of time in the past (step S3). That is, the monitoring unit 22a calculates the moving average value Xt of the amount of access. After processing step S3, the monitoring unit 22a compares the latest moving average value Xt with the past maximum value Xmax and minimum value Xmin (step S4). After the process of step S4, the monitoring unit 22a updates the latest moving average value Xt and the past maximum value Xmax and minimum value Xmin to the latest information (step S5).

[0024] After processing step S5, the monitoring unit 22a determines whether the current uncore frequency is the minimum value (step S6). Here, the uncore frequency refers to the operating frequency of the uncore unit 15 other than the CPU package 10 on which the application 1a (FIGS. 2 and 3) executes. If the current uncore frequency is the minimum value (Yes in step S6), the monitoring unit 22a determines whether the conditional expression "Xt > Xmin + (Xmax + Xmin) × 0.5" is satisfied (step S7). If the conditional expression is satisfied (Yes in step S7), the frequency changing unit 23a sets the uncore frequency to the maximum value (step S8).

[0025] That is, if the moving average value Xt of the traffic volume is greater than the first set value (Xmin+(Xmax+Xmin)×0.5), the uncore frequency is set to the maximum value.

[0026] On the other hand, if the current uncore frequency is not the minimum value (No in step S6), the monitoring unit 22a determines whether or not the conditional expression "Xt<Xmax-(Xmax+Xmin)×0.5" is satisfied (step S9). If the conditional expression is satisfied (Yes in step S9), the frequency changing unit 23a gradually reduces the uncore frequency of the uncore unit 15 (FIG. 1) to the minimum value (step S10). For example, the frequency changing unit 23a reduces the uncore frequency by 100 MHz every 5 seconds to the minimum value.

[0027] That is, if the moving average value Xt of the traffic volume is less than the second set value (Xmax-(Xmax+Xmin)×0.5), the uncore frequency is gradually reduced to the minimum value.

[0028] After the processing of steps S8 and S10, or when the determination of steps S7 and S9 is No, the controller 30 determines whether or not monitoring can be ended (step S11). "Monitoring can be ended" means, for example, when remote access is no longer performed due to the end of execution of the application 1a. When it is determined that monitoring can be ended (Yes in step S11), the controller 30 ends the processing. On the other hand, when it is determined that monitoring cannot be ended (No in step S11), the controller 30 repeats the processing from step S2 onwards.

[0029] Through these processes, the frequency changer 23a changes (controls) the operating frequency of the uncore unit 15 so that the traffic volume falls within (converges to) a predetermined range (an intermediate range between the past maximum value Xmax and the past minimum value Xmin). Specifically, the frequency changer 23a changes (controls) the operating frequency of the uncore unit 15 so that the moving average value Xt of the traffic volume falls within a predetermined range (an intermediate range between the past maximum value Xmax and the past minimum value Xmin). This reduces the frequency of sudden changes in the operating frequency.

[0030] As described above, according to the arithmetic processing device 100 of this embodiment, the CPU cores 1, 2, 3, and 4 that execute one or more applications locally access the volatile storage unit 6. In this state, the CPU package 20 that does not execute an application can reduce the clock frequency and voltage and enter a power-saving mode. At this time, the uncore frequency of the uncore unit 15 is maintained at a low value (minimum value).

[0031] The CPU cores 1, 2, 3, and 4 execute multiple applications, and when the load becomes heavy and resources become insufficient, they remotely access the volatile storage unit 16 via the L3 cache 5a. The monitor 22a monitors the access volume (data volume and access frequency) of the remotely accessed L3 cache 15a and the volatile storage unit 16. When the access volume is high, the frequency changer 23a increases the uncore frequency of the uncore unit 15. This allows the CPU cores 11, 12, 13, and 14 to be in a power-saving mode, while the CPU cores 1, 2, 3, and 4 can remotely access the volatile storage unit 16 at high speed. On the other hand, when the access volume is low, the frequency changer 23a decreases the uncore frequency of the uncore unit 15. The frequency changer 23a maintains the uncore frequency at a minimum value or decreases it to a minimum value. This maintains the power-saving mode of the entire CPU package 20.

[0032] Second Embodiment The resource controller 21 a, the monitoring unit 22 a, and the frequency change unit 23 a in the first embodiment are functions realized by the controller 30 disposed outside the CPU packages 10 and 20. In this embodiment, the resource controller 21 b, the monitoring unit 22 b, and the frequency change unit 23 b ( FIG. 6 ) are realized by a CPU core included in one of the CPU packages 10 and 20.

[0033] 5 is a configuration diagram of a processing device according to a second embodiment of the present invention. Similar to the processing device 100 (FIG. 1) of the first embodiment, the processing device 101 includes a plurality of CPU packages 10 and 20 and a communication unit 40. However, the processing device 101 differs from the processing device 100 in that it does not include the controller 30.

[0034] 6 is a block diagram illustrating the functions of a CPU core of a processing unit according to a second embodiment of the present invention. The CPU core 11 executes a control program to implement the functions of a resource controller 21b, a monitoring unit 22b, and a frequency changer 23b. The functions of the resource controller 21b, the monitoring unit 22b, and the frequency changer 23b are similar to the functions of the resource controller 21a, the monitoring unit 22a, and the frequency changer 2ab in the first embodiment.

[0035] According to the arithmetic processing device 101 of this embodiment, unlike the arithmetic processing device 100 of the first embodiment, the control program is always executed by the CPU 17. Therefore, the CPU package 20 is executed at an appropriate clock frequency and power supply voltage.

[0036] <<Modifications>> (1) In the above embodiments, the volatile storage units 6 and 16 are used, but non-volatile storage units (such as ROMs (Read On Memory) and HDDs (Hard Disk Drives)) may also be used. In this case, the volatile storage units 6 and 16, the non-volatile storage units, and the L3 caches 5a and 15a are collectively referred to as storage units. (2) When lowering the uncore frequency, the uncore frequency may be increased in response to a sudden increase in monitoring data. (3) The maximum value Xmax and minimum value Xmin of the access volume may be initialized for a certain period of time, or in response to the termination of a running application, the addition of a new application, changes in the load fluctuation trend, etc., and a flow may be added to update the values ​​to values ​​appropriate for the latest server status. According to this, the threshold value (for example, the right-hand side of the conditional expression in step S7 (Xmin + (Xmax + Xmin) × 0.5) or the right-hand side of the conditional expression in step S9 (Xmax - (Xmax + Xmin) × 0.5)) when setting the uncore frequency to the maximum value (step S8) or when lowering it to the minimum value (step S10) is automatically set. An initialization request may also be received from the resource controller 21a or the like. Specific examples of the resource controller 21a include switches that manage virtual machines such as Kubernetes (registered trademark) and OpenStack (registered trademark). (4) When time-series data is collected and accumulated in a storage unit or the like for a long period of time, a statistical or machine learning method may be used to predict the future increase / decrease trend of the monitoring data, and a control decision may be made based on this future prediction. (5) When the monitoring unit 22a can acquire data related to application performance other than metrics related to remote access, the threshold value may be set by combining these values.

[0037] <Effects> The effects of the arithmetic processing device 100 will be described below.

[0038] (1) While an application program is being executed, the CPU cores 1, 2, 3, and 4 of one of the CPU packages 10 change the operating frequency of the uncore unit 15 included in the monitored CPU package 20 based on the amount of data accessed (remotely accessed) and / or the access frequency of a storage unit (e.g., a volatile storage unit 16, an L3 cache 5a, or a nonvolatile storage unit (not shown)) of another CPU package 20. This allows for high-speed remote access to the storage unit (volatile storage unit 16). This reduces performance degradation of applications that occurs during power-saving operation, which reduces the clock frequencies of the CPU cores 11, 12, 13, and 14 and the uncore unit 15. It also enables the uncore unit 15 to be power-saving. In other words, this achieves both performance degradation suppression of applications residing on the local node and power saving on the remote node.

[0039] (2) The frequency changer 23a changes (controls) the operating frequency of the uncore unit so that the traffic volume (for example, the moving average value of the traffic volume) falls within a predetermined range (the intermediate range between the past maximum value Xmax and minimum value Xmin). This reduces the frequency of sudden changes in the operating frequency. (3) The monitors 22a, 22b and the frequency changers 23a, 23b are functional units realized by a controller 30 disposed outside the CPU package or by the CPU cores 1, 2, 3, 4, 11, 12, 13, and 14 included in any of the CPU packages 10, 20.

[0040] 1, 2, 3, 4, 11, 12, 13, 14 CPU core 1a, 2a Application 5, 15 Uncore unit 5a, 15a L3 cache 6, 16 Volatile storage unit (DRAM, storage unit) 7, 17 CPU 10, 20 CPU package 21a, 21b Resource controller 22a, 22b Monitoring unit 23a, 23b Frequency change unit 30 Controller 40 Communication unit 100, 101 Processing unit 200 Load balancer 1000, 1001 Processing system A1, A2 Application allocation signal F1, F2 Frequency control signal W1, W2 Monitoring signal RA Remote access signal MB Memory bus

Claims

1. A processing device comprising a plurality of CPU packages each comprising a CPU having a plurality of CPU cores and an uncore unit, and a memory unit controlled by the CPU, wherein the CPU packages are configured so that each CPU core can access the memory unit of its own package as well as the memory units of the other CPU packages, and the processing device is characterized by comprising: a monitoring unit that monitors the amount of access to the memory units of the other CPU packages, either the amount of data accessed or the access frequency, or both; and a frequency change unit that changes the operating frequency of the uncore unit included in the monitored CPU package based on the amount of access.

2. The arithmetic processing unit according to claim 1, wherein said frequency changer changes said operating frequency so as to keep said traffic volume within a predetermined range.

3. The arithmetic processing device according to claim 1 or 2, characterized in that the monitoring unit and the frequency change unit are functional units realized by a controller arranged outside the CPU package or a CPU core included in one of the CPU packages.

4. A control method executed by a processing device having multiple CPU packages each including a CPU having multiple CPU cores and an uncore unit, and a memory unit controlled by the CPU, wherein the CPU packages are configured so that each CPU core can access the memory unit of its own package as well as the memory units of the other CPU packages, and the processing device executes a monitoring step of monitoring the amount of access to the memory units of the other CPU packages, either the amount of data accessed or the access frequency, or both, and a frequency change step of changing the operating frequency of the uncore unit included in the monitored CPU package based on the amount of access.

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