Control signal generation circuit, electric power conversion device, and vehicle

Abstract

A control signal generation circuit 5 according to one embodiment comprises: an insulated gate driver that is configured to output a control pulse signal corresponding to a common input pulse signal to first and second switching elements; a delay signal generation unit that is configured to generate at least one delay pulse signal using the control pulse signal; and a logic synthesis unit that is configured to generate first and second control pulse signals by performing different logic synthesis on two signal sets among a plurality of signal sets that are defined by the at least one delay pulse signal and the control pulse signal, wherein the first control pulse signal is different from the control pulse signal, and the second control pulse signal is different from the control pulse signal and the first control pulse signal.

Description

Control signal generating circuit, power conversion device, and vehicle

[0001] The present invention relates to a control signal generating circuit, a power conversion device, and a vehicle.

[0002] Patent Document 1 discloses a technology using a parallel circuit of a first switching element that is a Si-IGBT and a second switching element that is a SiC-MOSFET in a switch section that constitutes an inverter (see Patent Document 1). The first switching element and the second switching element are driven by a first switching control signal (gate drive signal) and a second switching control signal (gate drive signal) that are different from each other. In order to generate the different first switching control signal (gate drive signal) and second switching control signal (gate drive signal), an inverter control device equipped with a microcomputer needs to generate and output different switching control source signals for the first switching control signal and the second switching control signal.

[0003] Patent No. 6468363

[0004] [Summary] An object according to one aspect of the present disclosure is to provide a technique capable of generating, from a single input pulse signal, a first control pulse signal and a second control pulse signal for controlling two switching elements having different characteristics.

[0005] A control signal generation circuit according to the present disclosure includes: an isolation circuit having an input end and an output end that are insulated from each other; an isolation circuit configured to output from the output end a control pulse signal corresponding to an input pulse signal that is input to the input end and is common to a first switching element and a second switching element, the first switching element and the second switching element having different transition times between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state; a delay signal generation unit configured to generate at least one delay pulse signal using the control pulse signal; and a logic synthesis unit configured to generate a first control pulse signal for the first switching element and a second control pulse signal for the second switching element by performing different logic synthesis on two signal sets out of a plurality of signal sets defined by the at least one delay pulse signal and the control pulse signal, wherein the first control pulse signal is different from the control pulse signal, and the second control pulse signal is different from the control pulse signal and the first control pulse signal.

[0006] FIG. 1 is a schematic diagram of a system configuration of a power conversion device to which a control signal generating circuit according to a first embodiment is applied. FIG. 2 is a circuit diagram for explaining a schematic configuration of an example of a switch unit and a control signal generating circuit. FIG. 3 is a time chart of various signals in the first embodiment. FIG. 4 is a circuit diagram of a control signal generating circuit according to a second embodiment. FIG. 5 is a time chart of various signals in the second embodiment. FIG. 6 is a circuit diagram of a control signal generating circuit according to a third embodiment. FIG. 7 is a time chart of various signals in the third embodiment. FIG. 8 is a circuit diagram for explaining a fourth embodiment. FIG. 9 is a circuit diagram for explaining a fifth embodiment. FIG. 10 is a circuit diagram for explaining a sixth embodiment. FIG. 11 is a diagram for explaining a modification of the sixth embodiment. FIG. 12 is a circuit diagram for explaining a seventh embodiment. FIG. 13 is a diagram showing an example configuration of a vehicle equipped with a power conversion device. FIG. 14 is a schematic diagram of an example of a switch unit. FIG. 15 is a schematic diagram of another example of a switch unit.

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The following description of the preferred embodiments of the present disclosure will be given with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and redundant description will be omitted.

[0008] First Embodiment Fig. 1 is a schematic diagram of a system configuration of a power conversion device to which a control signal generation circuit according to a first embodiment is applied. The power conversion device 1 is a device that converts power between direct current and alternating current. The power conversion device 1 is mounted on a vehicle such as a hybrid vehicle or an electric vehicle. The alternating current may be single-phase or multi-phase. Unless otherwise specified below, a configuration will be described in which the power conversion device 1 is mounted on the vehicle and the alternating current is three-phase.

[0009] 1, the power conversion device 1 is disposed between a motor (rotating electric machine) 2 driven by AC and a DC power supply unit 3. The power conversion device 1 is configured to convert DC power from the DC power supply unit 3 into AC power to drive the motor 2. The power conversion device 1 is configured to convert AC power generated in the motor 2 into DC power for regeneration.

[0010] The DC power supply unit 3 includes a high-voltage DC power supply. An example of the rated voltage of the DC power supply unit 3 is 300 V or more and 900 V or less. The DC power supply unit 3 may be configured to be capable of storing electricity. Examples of the DC power supply unit 3 include a secondary battery and an electric double layer capacitor. Examples of the secondary battery include a nickel-metal hydride secondary battery and a lithium-ion secondary battery. The DC power supply unit 3 may be a battery that combines a secondary battery and an electric double layer capacitor. The DC power supply unit 3 may be an all-solid-state battery. The DC power supply unit 3 may include a DC / DC converter.

[0011] The motor 2 functions as a driving power source for a vehicle such as a hybrid vehicle, an electric vehicle, etc. The motor 2 functions as an electric motor and also as a generator.

[0012] The power conversion device 1 includes an inverter circuit 4 and a plurality of control signal generation circuits 5 .

[0013] The inverter circuit 4 has a leg 41u, a leg 41v, and a leg 41w. The leg 41u is a U-phase leg, the leg 41v is a V-phase leg, and the leg 41w is a W-phase leg. The three legs 41u, 41v, and 41w are connected in parallel between a high-potential line 6a electrically connected to the positive electrode of the DC power supply unit 3 and a low-potential line 6b electrically connected to the negative electrode of the DC power supply unit 3.

[0014] Each of the leg 41u, the leg 41v, and the leg 41w has an upper arm switch unit 20 and a lower arm switch unit 20. Therefore, the inverter circuit 4 shown in Fig. 1 has six switch units 20. The two switch units 20 included in each of the leg 41u, the leg 41v, and the leg 41w are configured to be switchable between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state.

[0015] The two switch sections 20 included in each of the legs 41u, 41v, and 41w are connected in series between the high potential line 6a and the low potential line 6b.

[0016] A node (connection point) 42u between the switch unit 20 of the upper arm and the switch unit 20 of the lower arm of the leg 41u is an AC input / output point, and is electrically connected to a U-phase electrode of the motor 2. A node (connection point) 42v between the switch unit 20 of the upper arm and the switch unit 20 of the lower arm of the leg 41v is an AC input / output point, and is electrically connected to a V-phase electrode of the motor 2. A node (connection point) 42w between the switch unit 20 of the upper arm and the switch unit 20 of the lower arm of the leg 41w is an AC input / output point, and is electrically connected to a W-phase electrode of the motor 2.

[0017] The power conversion device 1 may include a capacitor 43 for smoothing the DC voltage supplied from the DC power supply unit 3 to the inverter circuit 4. The capacitor 43 is connected in parallel to the legs 41u, 41v, and 41w between the high potential line 6a and the low potential line 6b.

[0018] The plurality of control signal generating circuits 5 are provided corresponding to the two switch units 20 included in each of the legs 41u, 41v, and 41w. Therefore, in the configuration shown in FIG. 1 , the power conversion device 1 has six control signal generating circuits 5. The six control signal generating circuits 5 drive the switch units 20 based on input pulse signals corresponding to the respective control signal generating circuits 5 from an external control device 7. An example of the external control device 7 is an ECU (Electronic Control Unit) installed in an automobile.

[0019] In the power conversion device 1, the six switch units 20 have the same configuration, and the six control signal generation circuits 5 also have the same configuration. Therefore, the switch units 20 and the control signal generation circuits 5 will be described using one set of switch unit 20 and control signal generation circuit 5 as an example.

[0020] FIG. 2 is a circuit diagram for explaining a schematic configuration of an example of the switch section 20 and the control signal generating circuit 5. As shown in FIG.

[0021] [Switch Section] The switch section 20 has a first switching element 21 and a second switching element 22. The first switching element 21 and the second switching element 22 are connected in parallel between a node 20a and a node 20b of the switch section 20.

[0022] When the switch section 20 constitutes the upper arm, the node 20a of the switch section 20 of the upper arm is electrically connected to the high potential line 6a, and the node 20b of the switch section 20 of the upper arm is electrically connected to the node 20a of the switch section 20 of the lower arm.

[0023] When the switch section 20 constitutes the lower arm, the node 20a of the switch section 20 of the lower arm is electrically connected to the node 20b of the switch section 20 of the upper arm, and the node 20b of the switch section 20 of the lower arm is electrically connected to the low potential line 6b.

[0024] Each of the first switching element 21 and the second switching element 22 is a semiconductor switching element that can be switched between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state.

[0025] Examples of semiconductor switching elements used for the first switching element 21 and the second switching element 22 include bipolar transistors and unipolar transistors. An example of a bipolar transistor is an insulated gate bipolar transistor (IGBT). An example of a unipolar transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor switching elements may be power semiconductors. Examples of semiconductor materials for the semiconductor switching elements include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).

[0026] Each of the first switching element 21 and the second switching element 22 may be a semiconductor switching element obtained by combining transistor types and semiconductor materials, for example, the first switching element 21 and the second switching element 22 may be a Si-based IGBT, a Si-based MOSFET, a SiC-based IGBT, or a SiC-based MOSFET.

[0027] The first switching element 21 and the second switching element 22 that configure the switch unit 20 are combined to have different characteristics. In one embodiment, the first switching element 21 and the second switching element 22 have different transition times between the on state and the off state.

[0028] In the following description, unless otherwise specified, the first switching element 21 is a Si-based IGBT (hereinafter referred to as an "Si-IGBT"), and the second switching element 22 is a SiC-based MOSFET (hereinafter referred to as an "SiC-MOSFET"). In this case, the second switching element 22 is a switching element whose transition time between the on state and the off state is shorter than that of the first switching element 21. In other words, the second switching element 22 is a switching element capable of faster switching than the first switching element 21.

[0029] The first switching element 21 may be a bare chip of a Si-IGBT or an element in which the bare chip is housed in a package, and the second switching element 22 may be a bare chip of a SiC-MOSFET or an element in which the bare chip is housed in a package.

[0030] The first switching element 21 has a first main terminal, a second main terminal, and a control terminal. If the first switching element 21 is a Si-IGBT, the first main terminal, the second main terminal, and the control terminal correspond to a collector, an emitter, and a gate. The second switching element 22 has a first main terminal, a second main terminal, and a control terminal. If the second switching element 22 is a SiC-MOSFET, the first main terminal, the second main terminal, and the control terminal correspond to a drain, a source, and a gate.

[0031] As described above, unless otherwise specified, the case will be described in which the first switching element 21 is a Si-IGBT and the second switching element 22 is a SiC-MOSFET, and therefore the first main terminal, second main terminal and control terminal of the first switching element 21 will be referred to as the collector, emitter and gate, and the first main terminal, second main terminal and control terminal of the second switching element 22 will be referred to as the drain, source and gate.

[0032] The collector of the first switching element 21 and the drain of the second switching element 22 are electrically connected to a node 20a. The emitter of the first switching element 21 and the source of the second switching element 22 are electrically connected to a node 20b. Therefore, the potential of the node 20b is the potential of the emitter of the first switching element 21 and the source of the second switching element 22.

[0033] The gate of the first switching element 21 and the gate of the second switching element 22 are electrically connected to the control signal generating circuit 5 .

[0034] The switch unit 20 may include a freewheeling diode 23. The freewheeling diode 23 is connected in anti-parallel to the second switching element 22. Specifically, the cathode of the freewheeling diode 23 is electrically connected to the drain (or node 20a) of the second switching element 22. The anode of the freewheeling diode 23 is electrically connected to the source (or node 20b) of the second switching element 22. A parasitic diode in a SiC-MOSFET may be used as the freewheeling diode 23.

[0035] [Control Signal Generation Circuit] The control signal generation circuit 5 is a circuit that outputs a first gate signal (first drive pulse signal) for driving the first switching element 21 and a second gate signal (second drive pulse signal) for driving the second switching element 22, based on a common input pulse signal for the first switching element 21 and the second switching element 22. In Fig. 2, the external control device 7 that generates and outputs the input pulse signal is schematically illustrated as a pulse signal source.

[0036] The control signal generating circuit 5 according to this embodiment has an input terminal 5a to which an input pulse signal is input, a first output terminal 5b that outputs a first gate signal, and a second output terminal 5c that outputs a second gate signal. The input terminal 5a is electrically connected to the external control device 7. The first output terminal 5b is electrically connected to the gate of the first switching element 21. The second output terminal 5c is electrically connected to the gate of the second switching element 22.

[0037] The control signal generating circuit 5 of this embodiment has a first high potential input terminal 5d, a first reference potential input terminal 5e, a second high potential input terminal (second input terminal) 5f, and a second reference potential input terminal (first input terminal) 5g.

[0038] The first high potential input terminal 5d is electrically connected to the external power supply 61. A first high potential is input to the first high potential input terminal 5d from the external power supply 61. In the control signal generating circuit 5, a wiring that is electrically connected to the first high potential input terminal 5d and provides the first high potential is referred to as a first high potential line 56a.

[0039] The first reference potential input terminal 5e is electrically connected to an external reference potential wiring 63 (or a reference potential source) that provides the first reference potential. In the control signal generating circuit 5, the wiring that is electrically connected to the first reference potential input terminal 5e and that provides the first reference potential is referred to as a first reference potential line 56b.

[0040] An example of the voltage provided by the potential difference between the first high potential and the first reference potential (hereinafter, sometimes referred to as the "first predetermined voltage") is 5V.

[0041] The second high potential input terminal 5f is electrically connected to the external power supply 62. A second high potential is input to the second high potential input terminal 5f from the external power supply 62. The second high potential is a potential higher than the first high potential. In the control signal generation circuit 5, the wiring that is electrically connected to the second high potential input terminal 5f and provides the second high potential is referred to as a second high potential line 57a.

[0042] The second reference potential input terminal 5g is a terminal to which the second reference potential is input. In the embodiment shown in FIG. 2, the second reference potential input terminal 5g is electrically connected to the node 20b, and therefore the second reference potential is the potential of the node 20b. As described above, the potential of the node 20b is the potential of the emitter of the first switching element 21 and the source of the second switching element 22. In the control signal generating circuit 5, the wiring that is electrically connected to the second reference potential input terminal 5g and provides the second reference potential is referred to as the second reference potential line 57b.

[0043] An example of the voltage provided by the potential difference between the second high potential and the second reference potential (hereinafter, sometimes referred to as the "second predetermined voltage") is 18V.

[0044] The control signal generating circuit 5 may include a step-down circuit 55. The step-down circuit 55 has a function of converting the second high potential (first voltage potential) into a lower third high potential (second voltage potential). In the embodiment shown in FIG. 2, the step-down circuit 55 is electrically connected to the second high potential line 57a. As a result, the step-down circuit 55 is electrically connected to the second high potential input terminal 5f. An example of the step-down circuit 55 is a step-down regulator.

[0045] The control signal generating circuit 5 includes an insulated gate driver 51 and a signal generating unit 52 .

[0046] <Insulated Gate Driver> The isolated gate driver 51 outputs a control pulse signal from an output terminal (output terminal) 51b in response to an input pulse signal input from an input terminal (input end) 51a. The isolated gate driver 51 is configured to be able to transmit a signal from the input terminal 51a to the output terminal 51b while the input terminal 51a and the output terminal 51b are insulated from each other. Therefore, the isolated gate driver 51 has an isolation circuit configured to be able to transmit a signal. The isolation circuit may be a circuit using a photocoupler, a magnetic coupler using a transformer, or a capacitive coupler using a capacitor. The isolated gate driver 51 may be an integrated circuit (IC). The isolated gate driver 51 may be, for example, an IC known as a GDIC.

[0047] The isolated gate driver 51 may include a signal level conversion circuit (e.g., an amplifier) ​​that converts the signal level of a signal input to the input terminal 51 a and outputs the converted signal. The isolated gate driver 51 may also include protection circuits such as a low voltage protection circuit and an overvoltage protection circuit. Unless otherwise specified below, the isolated gate driver 51 is an isolated circuit that outputs a signal input to the input terminal 51 a from the output terminal 51 b as a signal in substantially the same state without converting the signal level.

[0048] The insulated gate driver 51 is electrically connected between a first high potential line 56 a and a first reference potential line 56 b, and is driven by a first predetermined voltage which is the potential difference between the first high potential and the first reference potential. An example of the drive voltage of the insulated gate driver 51 is 5 V.

[0049] In the insulated gate driver 51, the input terminal 51a side and the output terminal 51b side are insulated. Therefore, the control signal generation circuit 5 is also insulated between the input side and the output side. Therefore, the control signal generation circuit 5 has an input side (hereinafter referred to as the "primary side") and an output side (hereinafter referred to as the "secondary side") that are insulated by the insulated gate driver 51.

[0050] The signal generating unit 52 is electrically connected to the output terminal 51b of the insulated gate driver 51, and is a circuit configured to generate a first control pulse signal for the first switching element 21 and a second control pulse signal for the second switching element 22 using the control pulse signal from the output terminal 51b. The first control pulse signal and the second control pulse signal are different signals generated from a common control pulse signal. The signal generating unit 52 has a delay signal generating unit 10 and a logic synthesis unit 16.

[0051] The delay signal generating section 10 generates a delay pulse signal that is delayed relative to the control pulse signal. The delay signal generating section 10 has a delay circuit 11 that generates the delay pulse signal.

[0052] The delay circuit 11 is configured to be able to set a resistance value for delaying the rising edge of the control pulse signal and a resistance value for delaying the falling edge of the control pulse signal. The delay circuit 11 has a parallel circuit (resistance unit) 12 in which a first series circuit 13 and a second series circuit 14 are connected in parallel, and a capacitor 15.

[0053] The parallel circuit 12 has a node (first terminal) 12a and a node (second terminal) 12b. The node 12a is electrically connected to the output terminal 51b. A control pulse signal is input to the node 12a. The node 12b is electrically connected to the logic synthesis unit 16.

[0054] The first series circuit 13 is configured by connecting a first diode 131 and a first resistor 132 in series. The anode of the first diode 131 is connected to the node 12a. The first resistor 132 is connected between the cathode of the first diode 131 and the node 12b. An example of the forward voltage of the first diode 131 is 0.5 V or more and 1.0 V or less. An example of the resistance value of the first resistor 132 is 10 Ω or more and 10 kΩ or less.

[0055] The second series circuit 14 is configured by connecting a second diode 141 and a second resistor 142 in series. The anode of the second diode 141 is connected to the node 12b. The second resistor 142 is connected between the cathode of the second diode 141 and the node 12a. Examples of the forward voltage of the second diode 141 are the same as those of the first diode 131. The second diode 141 may be the same as or different from the first diode 131. Examples of the resistance value of the second resistor 142 are the same as those of the first resistor 132. The second resistor 142 may be the same as or different from the first resistor 132.

[0056] The capacitor 15 is connected between the node 12b and the first reference potential line 56b. The capacitance of the capacitor 15 is, for example, 10 pF or more and 10 nF or less.

[0057] In the delay circuit 11, the first series circuit 13 functions as a signal path that delays the rising edge of the control pulse signal from the output terminal 51b, and a delay circuit that delays the rising edge of the control pulse signal is configured by the first series circuit 13 (specifically, the first resistor 132) and the capacitor 15. The delay time for the rising edge is determined by the resistance value of the first resistor 132 and the capacitance of the capacitor 15.

[0058] In the delay circuit 11, the second series circuit 14 functions as a signal path that delays the falling edge of the control pulse signal, and the second series circuit 14 and the capacitor 15 form a delay circuit that delays the falling edge of the control pulse signal. The delay time for the falling edge is determined by the resistance value of the second resistor 142 and the capacitance of the capacitor 15.

[0059] The logic synthesis unit 16 includes an AND circuit 161 for generating the first control pulse signal and an OR circuit 162 for generating the second control pulse signal. The logic synthesis unit 16 may be driven by a third voltage stepped down by the step-down circuit 55.

[0060] The AND circuit 161 is electrically connected to the insulated gate driver 51 and the delay signal generator 10. A signal set of a control pulse signal and a first delay pulse signal is input to the AND circuit 161. The AND circuit 161 is a logical product circuit that outputs a first control pulse signal by performing a logical product of the input control pulse signal and the first delay pulse signal. The AND circuit 161 may be electrically connected between the step-down circuit 55 and the second reference potential line 57b. In this case, the AND circuit 161 is driven by a third voltage that is obtained by stepping down the second voltage by the step-down circuit 55. An example of the drive voltage of the AND circuit 161 is 5V.

[0061] The OR circuit 162 is electrically connected to the insulated gate driver 51 and the delay signal generator 10. A signal set of a control pulse signal and a first delay pulse signal is input to the OR circuit 162. The OR circuit 162 is a logical OR circuit that outputs a second control pulse signal by performing a logical OR on the input control pulse signal and the second delay pulse signal. The OR circuit 162 may be electrically connected between the step-down circuit 55 and the second reference potential line 57b. In this case, the OR circuit 162 is driven by a third voltage that is obtained by stepping down the second voltage by the step-down circuit 55. An example of the drive voltage of the OR circuit 162 is 5V.

[0062] The first control pulse signal and the second control pulse signal generated by the signal generating unit 52 using the control pulse signal output from the insulated gate driver 51 are signals for driving the first switching element 21 and the second switching element 22. Therefore, in one embodiment, the first control pulse signal and the second control pulse signal may be output from the first output terminal 5b and the second output terminal 5c as the first gate signal and the second gate signal.

[0063] 2, the control signal generating circuit 5 may have a first push-pull circuit 53a and a second push-pull circuit 53b in a stage subsequent to the logic synthesis unit 16. Unless otherwise specified, the following description will be given of an embodiment in which the control signal generating circuit 5 includes the first push-pull circuit 53a and the second push-pull circuit 53b.

[0064] The first push-pull circuit 53a is electrically connected to the AND circuit 161. The high-potential end 531a of the first push-pull circuit 53a is electrically connected to the second high-potential line 57a. Therefore, the high-potential end 531a of the first push-pull circuit 53a is electrically connected to the second high-potential input terminal 5f. The low-potential end 532a of the first push-pull circuit 53a is electrically connected to the second reference potential line 57b. Therefore, the low-potential end 532a of the first push-pull circuit 53a is electrically connected to the second reference potential input terminal 5g. Therefore, the first push-pull circuit 53a is driven by a second predetermined voltage. The first push-pull circuit 53a has a first transistor Tr1 and a second transistor Tr2 connected in series between the second high-potential line 57a and the second reference potential line 57b. The first push-pull circuit 53a is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series.

[0065] In this embodiment, the first transistor Tr1 is an npn transistor, and the second transistor Tr2 is a pnp transistor. The collector of the first transistor Tr1 is connected to the second high potential line 57a. Therefore, the collector of the first transistor Tr1 is the high potential end 531a. The emitter of the first transistor Tr1 is connected to the emitter of the second transistor Tr2. The collector of the second transistor Tr2 is connected to the second reference potential line 57b. Therefore, the collector of the second transistor Tr2 is the low potential end 532a. The gates of the first transistor Tr1 and the second transistor Tr2 are electrically connected to the AND circuit 161, and the first control pulse signal output from the AND circuit 161 is input thereto.

[0066] In the first push-pull circuit 53a configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the first control pulse signal from the AND circuit 161. As a result, a first gate signal is obtained by amplifying the first control pulse signal. Since the first output terminal 5b is electrically connected to the gate of the first switching element 21, the first gate signal is input to the gate of the first switching element 21.

[0067] A node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 in the first push-pull circuit 53a may be electrically connected to the first output terminal 5b via a first gate resistor 54a. That is, the first gate resistor 54a may be disposed on a signal path between the node between the series-connected first transistor Tr1 and second transistor Tr2 and the first output terminal 5b. An example of the resistance value of the first gate resistor 54a is 1 Ω or more and 100 Ω or less. In this case, the first gate signal is input to the first output terminal 5b via the first gate resistor 54a.

[0068] The second push-pull circuit 53b is electrically connected to the OR circuit 162. The high-potential end 531b of the second push-pull circuit 53b is electrically connected to the second high-potential line 57a, and the low-potential end 532b of the second push-pull circuit 53b is electrically connected to the second reference potential line 57b. Therefore, the second push-pull circuit 53b is driven by a second predetermined voltage. The second push-pull circuit 53b has a first transistor Tr1 and a second transistor Tr2 connected in series between the second high-potential line 57a and the second reference potential line 57b. The second push-pull circuit 53b is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series.

[0069] In this embodiment, the first transistor Tr1 and the second transistor Tr2 included in the second push-pull circuit 53b are the same as those in the first push-pull circuit 53a. That is, the first transistor Tr1 is an npn transistor, and the second transistor Tr2 is a pnp transistor. The collector of the first transistor Tr1 is connected to the second high-potential line 57a. Therefore, the collector of the first transistor Tr1 is the high-potential end 531b. The emitter of the first transistor Tr1 is connected to the emitter of the second transistor Tr2. The collector of the second transistor Tr2 is connected to the second reference potential line 57b. Therefore, the collector of the second transistor Tr2 is the low-potential end 532b. The gates of the first transistor Tr1 and the second transistor Tr2 are electrically connected to the OR circuit 162, and the second control pulse signal output from the OR circuit 162 is input thereto.

[0070] In the second push-pull circuit 53b, a node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 is electrically connected to the second output terminal 5c. That is, a second gate resistor 54b is disposed on the signal path between the node between the first transistor Tr1 and the second transistor Tr2 connected in series and the second output terminal 5c.

[0071] In the second push-pull circuit 53b configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the second control pulse signal from the OR circuit 162. As a result, a second gate signal is obtained by amplifying the second control pulse signal. The second gate signal is input to the second output terminal 5c. Since the second output terminal 5c is electrically connected to the gate of the second switching element 22, the second gate signal is input to the gate of the second switching element 22.

[0072] A node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 of the second push-pull circuit 53b may be electrically connected to the second output terminal 5c via a second gate resistor 54b. That is, the second gate resistor 54b may be disposed on a signal path between the node between the series-connected first transistor Tr1 and second transistor Tr2 and the second output terminal 5c. The resistance value of the second gate resistor 54b may be the same as that of the first gate resistor 54a. The resistance value of the second gate resistor 54b may be the same as or different from that of the first gate resistor 54a. In this case, the second gate signal is input to the second output terminal 5c via the second gate resistor 54b.

[0073] 3 is a time chart of various signals in the first embodiment. In FIG. 3, the input pulse signal, the control pulse signal, the delay pulse signal, the first control pulse signal, the second control pulse signal, and the current of the main circuit (hereinafter referred to as "main circuit current") are respectively represented as the input pulse signal S0, the control pulse signal S1, the delay pulse signal S2, the first control pulse signal S3, the second control pulse signal S4, and the main circuit current I Ｍ In this embodiment, the control pulse signal S1 is the same as the input pulse signal S0, so in FIG. 3, the input pulse signal S0 and the control pulse signal S1 are shown together. The main circuit current I Ｍ is the current flowing through the switch unit 20. Specifically, the main circuit current I Ｍ is the current flowing between node 20a and node 20b.

[0074] In FIG. 3, the AND circuit 161 and the OR circuit 162 have threshold voltages (threshold signal levels) for regarding an input signal as High and Low, respectively. ＩＨ and V ＩＬ In the AND circuit 161 and the OR circuit 162, when the input signal is V ＩＨ Once it exceeds V ＩＬ is considered to be in a High state unless the input signal falls below V ＩＬ Once it falls below V ＩＨIt is considered to be in a low state unless it exceeds V. ＩＨ An example of V is 3V, ＩＬ An example is 2V.

[0075] An example of the operation of the control signal generating circuit 5 and the switch section 20 will be described with reference to FIGS.

[0076] When an input pulse signal S0 is input to an insulated gate driver 51 included in the control signal generation circuit 5, the insulated gate driver 51 outputs a control pulse signal S1 based on the input pulse signal S0. In this embodiment, the control pulse signal S1 is the same signal as the input pulse signal S0. As shown in FIG. 3 , the input pulse signal S0 and the control pulse signal S1 have pulses that rise at time t1 and fall at time t3. When the control pulse signal S1 is input to the delay signal generation unit 10, the delay signal generation unit 10 generates a delay pulse signal S2.

[0077] The delay signal generating unit 10 includes a parallel circuit 12 and a capacitor 15. The parallel circuit 12 includes a first series circuit 13 that contributes to delaying the rising edge and a second series circuit 14 that contributes to delaying the falling edge. Therefore, as shown in FIG. 3 , the delay pulse signal S2 rises at time t2, which is a delay time td1 after time t1, and falls at time t4, which is a delay time td2 after time t3.

[0078] "Rising after a delay time from a certain time (referred to as "time α")" means that the signal level gradually increases from time α and exceeds a certain threshold level after the delay time. "Falling after a delay time from a certain time (referred to as "time β")" means that the signal level gradually decreases from time β and falls below a certain threshold level after the delay time.

[0079] In the example shown in FIG. 3, the threshold level that determines the delay time of the rising edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the OR circuit 162 as High. ＩＨ The threshold level that determines the delay time of the falling edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the OR circuit 162 as Low. ＩＬ is.

[0080] The delayed pulse signal S2 generated by the delayed signal generating unit 10 is input to the logic synthesis unit 16. The logic synthesis unit 16 has an AND circuit 161 and an OR circuit 162. The AND circuit 161 performs a logical AND on the signal set of the control pulse signal S1 and the delayed pulse signal S2 to generate a first control pulse signal S3. The OR circuit 162 performs a logical OR on the signal set of the control pulse signal S1 and the delayed pulse signal S2 to generate a second control pulse signal S4.

[0081] In the example shown in FIG. 3, the signal level (voltage) of the control pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time t3, the threshold voltage V ＩＬ Therefore, the control pulse signal S1 input to the AND circuit 161 and the OR circuit 162 is in a High state from time t1 to time t3, and thereafter, the control pulse signal S1 again falls below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0082] The signal level (voltage) of the delayed pulse signal S2 is equal to or exceeds the threshold voltage V ＩＨ At time t4, the threshold voltage V ＩＬ Therefore, the delayed pulse signal S2 input to the AND circuit 161 and the OR circuit 162 is in a High state from time t2 to time t4, and thereafter, the delayed pulse signal S2 again falls below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0083] The first control pulse signal S3 is generated by the logical AND of the control pulse signal S1 and the delayed pulse signal S2. Due to the relationship between the high and low states of the control pulse signal S1 and the delayed pulse signal S2 in the AND circuit 161, the first control pulse signal S3 is a pulse signal that rises at time t2 and falls at time t3.

[0084] The second control pulse signal S4 is generated by the logical OR of the control pulse signal S1 and the delayed pulse signal S2. Due to the relationship between the high and low states of the control pulse signal S1 and the delayed pulse signal S2 in the OR circuit 162, the second control pulse signal S4 is a pulse signal that rises at time t1 and falls at time t4.

[0085] In this way, the control signal generating circuit 5 can generate the first control pulse signal S3 and the second control pulse signal S4 with different delay states based on one input pulse signal S0 (control pulse signal S1).

[0086] 2, the first control pulse signal S3 is input to the first push-pull circuit 53a and output as a first gate signal. The first gate signal is input to the first output terminal 5b. The first output terminal 5b is electrically connected to the gate of the first switching element 21, so that the first switching element 21 is driven by the first gate signal.

[0087] The first gate signal is a pulse signal obtained by amplifying the first control pulse signal, and therefore has the same waveform as the first control pulse signal.

[0088] In the control signal generating circuit 5, the second control pulse signal S4 is input to the second push-pull circuit 53b and output as a second gate signal. The second gate signal is input to the second output terminal 5c. Since the second output terminal 5c is electrically connected to the gate of the second switching element 22, the second switching element 22 is driven by the second gate signal.

[0089] The second gate signal is a pulse signal obtained by amplifying the second control pulse signal S4, and therefore has the same waveform as the second control pulse signal S4.

[0090] The first switching element 21 is driven by a first gate signal having a waveform similar to that of the first control pulse signal S3, so it is turned on at time t2 and turned off at time t3. The second switching element 22 is driven by a second gate signal having a waveform similar to that of the second control pulse signal S4, so it is turned on at time t1 and turned off at time t4.

[0091] The timing at which the first switching element 21 and the second switching element 22 turn on is adjusted by the delay time td1. When the resistance of the first resistor 132 is R1 [Ω] and the capacitance of the capacitor 15 is C [F], the delay time td1 [s] is expressed as the product of the resistance R1 [Ω] and the capacitance C [F]. Therefore, by adjusting the resistance R1 and the capacitance C, it is possible to adjust the timing at which the first switching element 21 and the second switching element 22 turn on.

[0092] The timing at which the first switching element 21 and the second switching element 22 turn off is adjusted by the delay time td2. When the resistance value of the second resistor 142 is R2 [Ω], the delay time td2 [s] is expressed as the product of the resistance value R2 [Ω] and the capacitance C [F]. Therefore, by adjusting the resistance value R2 and the capacitance C, it is possible to adjust the timing at which the first switching element 21 and the second switching element 22 turn off.

[0093] The switch unit 20 is configured by connecting a first switching element 21 and a second switching element 22 in parallel. Therefore, when either the first switching element 21 or the second switching element 22 is in the ON state, the node 20a and the node 20b are in a conductive state. That is, when either the first switching element 21 or the second switching element 22 is in the ON state, the switch unit 20 is in an ON state. On the other hand, when both the first switching element 21 and the second switching element 22 are in the OFF state, the node 20a and the node 20b are in a non-conductive state. That is, when both the first switching element 21 and the second switching element 22 are in the OFF state, the switch unit 20 is in an OFF state. Therefore, the switch unit 20 is in an ON state from time t1 to time t4, and as shown in FIG. 3 , the main circuit current I Ｍ is playing.

[0094] As can be seen from the time chart of various signals shown in Fig. 3, the second switching element 22, which is a SiC-MOSFET, performs the turn-on and turn-off functions of the switch unit 20 by driving the switch unit 20 using the control signal generating circuit 5 having the signal generating unit 52. Since the transition time between the on state and the off state of a SiC-MOSFET is shorter than that of a Si-IGBT, the transition time for turn-on and turn-off can also be shortened in the switch unit 20. In other words, the switch unit 20 can achieve high-speed switching similar to that of a SiC-MOSFET.

[0095] As can be seen from the time chart of various signals shown in Figure 3, when the switch unit 20 is driven by the control signal generation circuit 5 having the signal generation unit 52, the first switching element 21, which is a Si-IGBT, is also in the ON state from time t2 to time t3. Si-IGBTs have smaller conduction losses at high currents than SiC-MOSFETs and are more resistant to overcurrents. Therefore, when the switch unit 20 is turned on and more current begins to flow, the current flows mainly through the first switching element 21, improving the switch unit 20's resistance to overcurrents.

[0096] The switch unit 20 of the power conversion device 1 is configured by connecting a first switching element 21 and a second switching element 22 having different characteristics in parallel. Therefore, the configuration of the control signal generation circuit 5 allows the first switching element 21 and the second switching element 22 to be driven so as to effectively utilize the respective characteristics of the first switching element 21 and the second switching element 22. This makes it possible to realize a switch unit 20 with superior characteristics compared to a case where the switch unit 20 is configured with only one of the first switching element 21 and the second switching element 22. As a result, the characteristics of the power conversion device 1 including the switch unit 20 are also improved.

[0097] When the switch unit 20 has first and second switching elements 21 and 22 with different characteristics, it is possible to generate different first and second gate signals for the first and second switching elements 21 and 22 based on different input pulse signals. In this case, a drive circuit that generates the first gate signal based on the input pulse signal corresponding to the first switching element 21 and a drive circuit that generates the second gate signal based on the input pulse signal corresponding to the second switching element 22 are required. In other words, two drive circuits are required for one switch unit 20. As a result, when the power conversion device 1 has six switch units 20 as shown in FIG. 1 , the number of drive circuits included in the power conversion device 1 is 12. When different first and second gate signals are generated for the first and second switching elements 21 and 22 based on different input pulse signals, the external control device 7 is configured to generate different input pulse signals for the switch unit 20 including the first and second switching elements 21 and 22. Therefore, for example, an existing external control device 7 cannot be used when the switch section 20 is configured with either the first switching element 21 or the second switching element 22.

[0098] In contrast to this, the control signal generating circuit 5 can generate the first control pulse signal and the second control pulse signal for the first switching element 21 and the second switching element 22 from a common input pulse signal.

[0099] Specifically, when an input pulse signal is input to the control signal generation circuit 5, the input pulse signal is input to the insulated gate driver 51. The insulated gate driver 51 outputs a control pulse signal that corresponds to the input pulse signal and is common to the first switching element 21 and the second switching element 22. The control pulse signal output from the insulated gate driver 51 is input to the signal generation unit 52. The signal generation unit 52 generates a first control pulse signal corresponding to the first switching element 21 and a second control pulse signal corresponding to the second switching element 22 from the input control pulse signal.

[0100] In this way, the control signal generating circuit 5 can generate a first control pulse signal and a second control pulse signal for driving the first switching element 21 and the second switching element 22 from an input pulse signal common to the first switching element 21 and the second switching element 22.

[0101] Therefore, only one control signal generating circuit 5 is required for each switch unit 20. As a result, as shown in FIG. 1 , if the power conversion device 1 has six switch units 20, the power conversion device 1 has six control signal generating circuits 5. Therefore, in a configuration of the control signal generating circuit 5 including the signal generating unit 52, the number of control signal generating circuits 5 included in the power conversion device 1 can be reduced compared to a case where different input pulse signals are used for the first switching element 21 and the second switching element 22. Since the number of control signal generating circuits 5 is thus reduced, the manufacturing cost of the power conversion device 1 can be reduced.

[0102] Since the control signal generation circuit 5 includes an insulated gate driver 51, the primary side and secondary side of the control signal generation circuit 5 are insulated from each other. This makes it possible to prevent noise, overvoltage, and the like from the switch unit 20 from being transmitted to the external control device 7. Since the control signal generation circuit 5 includes an insulated gate driver 51, signals can be transmitted between circuits having different reference potentials in a system including the control signal generation circuit 5, thereby improving the degree of freedom in system design.

[0103] In the control signal generation circuit 5, it is also possible to arrange an insulated gate driver (or an isolation circuit) after the signal generation unit 52 (specifically, after the logic synthesis unit 16). However, since the signal generation unit 52 outputs the first control pulse signal and the second control pulse signal, it is necessary to provide an insulated gate driver for each of the first control pulse signal and the second control pulse signal.

[0104] In contrast, in the control signal generation circuit 5, the insulated gate driver 51 is arranged upstream of the signal generation unit 52 (specifically, upstream of the delay circuit 11). In this case, the control signal generation circuit 5 has only one insulated gate driver 51. That is, in the control signal generation circuit 5, the number of insulated gate drivers required is reduced compared to when the insulated gate driver is arranged downstream of the signal generation unit 52 (specifically, downstream of the logic synthesis unit 16). This reduces the manufacturing cost of the control signal generation circuit 5 and simplifies the configuration of the control signal generation circuit 5.

[0105] Because the control signal generating circuit 5 generates the first control pulse signal and the second control pulse signal for the first switching element 21 and the second switching element 22 from a common input pulse signal, it is possible to use an existing external control device 7. Therefore, the switch unit 20 can be easily applied to an existing external control device 7 and a device equipped with the external control device 7 (e.g., a hybrid vehicle, an electric vehicle, etc.). For example, when the switch unit 20 replaces the switch unit of a power conversion device (or inverter) mounted on a hybrid vehicle, an electric vehicle, etc., the control signal generating circuit 5 can be set in front of an existing GDIC, thereby enabling the switch unit 20 to be driven without changing the control program for the power conversion device in the ECU.

[0106] The Si-IGBT is a lower-cost device than the SiC-MOSFET, and therefore, compared to a case where all of the switching elements of the switch unit 20 are configured with SiC-MOSFETs, it is possible to reduce the manufacturing costs of the switch unit 20 and the power conversion device 1 including the switch unit 20 while maintaining the characteristics of the SiC-MOSFET.

[0107] The delay circuit 11 includes a parallel circuit 12 and a capacitor 15. The parallel circuit 12 is configured by connecting in parallel a first series circuit 13 that contributes to delaying the rising edge of the input pulse signal and a second series circuit 14 that contributes to delaying the falling edge of the input pulse signal. Therefore, the delay time td1 for the rising edge of the input pulse signal and the delay time td2 for the falling edge of the input pulse signal can be adjusted separately.

[0108] Specifically, as described above, the delay time td1 [s] is expressed as the product of the resistance value R1 [Ω] of the first resistor 132 and the capacitance C [F] of the capacitor 15, and the delay time td2 [s] is expressed as the product of the resistance value R2 [Ω] of the second resistor 142 and the capacitance C [F] of the capacitor 15. In the equations for calculating the delay times td1 and td2, the capacitance C [F] of the capacitor 15 is common, so that the delay times td1 and td2 can be adjusted by adjusting the resistance value R1 [Ω] of the first resistor 132 and the resistance value R2 [Ω] of the second resistor 142.

[0109] Second Embodiment Fig. 4 is a circuit diagram of a drive circuit including a signal generating circuit according to a second embodiment. Fig. 4 also illustrates a switch unit 20. The configuration of the switch unit 20 is the same as in the first embodiment. That is, the switch unit 20 is configured by connecting a first switching element 21 and a second switching element 22 in parallel. In the second embodiment, the first switching element 21 is also a Si-IGBT, and the second switching element 22 is also a SiC-MOSFET. The connection relationship between the first switching element 21 and the second switching element 22 is the same as in the first embodiment, and therefore will not be described again.

[0110] The control signal generating circuit 5A according to the second embodiment differs from the control signal generating circuit 5 mainly in that it has a signal generating unit 52A instead of the signal generating unit 52. An example of the control signal generating circuit 5A will be described based on the configuration shown in FIG.

[0111] As shown in FIG. 4, the control signal generation circuit 5A, like the control signal generation circuit 5, has an input terminal 5a, a first output terminal 5b, a second output terminal 5c, a first high potential input terminal 5d, a first reference potential input terminal 5e, a second high potential input terminal 5f, and a second reference potential input terminal (first input terminal) 5g.

[0112] The input terminal 5a is electrically connected to the external control device 7. The first output terminal 5b is electrically connected to the gate of the first switching element 21. The second output terminal 5c is electrically connected to the gate of the second switching element 22. A first high potential is input to the first high potential input terminal 5d from an external power supply 61. A first reference potential is input to the first reference potential input terminal 5e from an external reference potential wiring 63 (or reference potential source). A second high potential is input to the second high potential input terminal 5f from an external power supply 62. A second reference potential is input to the second reference potential input terminal 5g from the outside. As shown in FIG. 4 , the second reference potential input terminal 5g is electrically connected to node 20b, and therefore the second reference potential is the potential of node 20b. As described above, the potential of node 20b is the potential of the emitter of the first switching element 21 and the source of the second switching element 22.

[0113] As in the first embodiment, within the control signal generating circuit 5A, the wiring that provides the first high potential, the wiring that provides the first reference potential, the wiring that provides the second high potential, and the wiring that provides the second reference potential are referred to as the first high potential line 56a, the first reference potential line 56b, the second high potential line 57a, and the second reference potential line 57b, respectively.

[0114] [Control Signal Generation Circuit] The control signal generation circuit 5A has an insulated gate driver 51 and a signal generation unit 52A.

[0115] <Insulated Gate Driver> The isolated gate driver 51 outputs a control pulse signal from an output terminal 51b corresponding to an input pulse signal input to an input terminal 51a. The isolated gate driver 51 is the same as in the first embodiment, so a description of the isolated gate driver 51 will be omitted. In the second embodiment, the isolated gate driver 51 is also an isolated circuit, and the control pulse signal is substantially the same as the input pulse signal.

[0116] <Signal Generator> The signal generator 52A includes a delay signal generator 10A and a logic synthesis unit 16A. The delay signal generator 10A generates a first delay pulse signal and a second delay pulse signal that are different in delay state from the control pulse signal.

[0117] (Delay Signal Generator) The delay signal generator 10A included in the signal generator 52A includes a first delay circuit 11A and a second delay circuit 11B.

[0118] (First Delay Circuit) The first delay circuit 11A is configured to be able to set a resistance value for delaying the rising edge of the control pulse signal and a resistance value for delaying the falling edge of the control pulse signal. The first delay circuit 11A has a first parallel circuit (resistance unit) 12A in which a first series circuit 13A and a second series circuit 14A are connected in parallel, and a first capacitor 15a.

[0119] The first parallel circuit 12A has a node (first terminal) 12c and a node (second terminal) 12d. The node 12c is electrically connected to the output terminal 51b. A control pulse signal is input to the node 12c from the insulated gate driver 51. The node 12d is electrically connected to the logic synthesis unit 16A.

[0120] The first series circuit 13A is configured by connecting a first diode 131a and a first resistor 132a in series. The anode of the first diode 131a is connected to the node 12c. The first resistor 132a is connected between the cathode of the first diode 131a and the node 12d. Examples of the forward voltage of the first diode 131a and the resistance value of the first resistor 132a are the same as those of the first diode 131 and the first resistor 132 described in the first embodiment.

[0121] The second series circuit 14A is configured by connecting a second diode 141a and a second resistor 142a in series. The anode of the second diode 141a is connected to the node 12d. The second resistor 142a is connected between the cathode of the second diode 141a and the node 12c. Examples of the forward voltage of the second diode 141a and the resistance value of the second resistor 142a are the same as those of the second diode 141 and the second resistor 142 described in the first embodiment.

[0122] The first capacitor 15a is electrically connected between the node 12d and the first reference potential line 56b. An example of the capacitance of the first capacitor 15a is the same as that of the capacitor 15 described in the first embodiment.

[0123] In the first delay circuit 11A, the first series circuit 13A functions as a signal path that delays the rising edge of the control pulse signal, and the first series circuit 13A (specifically, the first resistor 132a) and the first capacitor 15a form a delay circuit that delays the rising edge of the control pulse signal. The delay time for the rising edge is determined by the resistance value of the first resistor 132a and the capacitance of the first capacitor 15a. In other words, the delay time for the rising edge that is applied to the control pulse signal in the first delay circuit 11A is set to Td1. ＯＮ [s], the resistance value of the first resistor 132a is R1a [Ω], and the capacitance of the first capacitor 15a is C1 [F], then Td1 ＯＮ is expressed by the formula (1). ＯＮ = R1a × C1 (1)

[0124] In the first delay circuit 11A, the second series circuit 14A functions as a signal path that delays the falling edge of the control pulse signal, and the second series circuit 14A and the first capacitor 15a form a delay circuit that delays the falling edge of the control pulse signal. The delay time for the falling edge is determined by the resistance value of the second resistor 142a and the capacitance of the first capacitor 15a. In other words, the delay time for the falling edge that is applied to the control pulse signal in the first delay circuit 11A is set to Td1. ＯＦＦ [s] and the resistance value of the second resistor 142a is R2a [Ω], Td1 ＯＦＦ is expressed by the formula (2). ＯＦＦ = R2a × C1 (2)

[0125] The second delay circuit 11B is configured to be able to set a resistance value for delaying the rising edge of the control pulse signal and a resistance value for delaying the falling edge of the control pulse signal. The second delay circuit 11B has a second parallel circuit (resistance unit) 12B in which a third series circuit 13B and a fourth series circuit 14B are connected in parallel, and a second capacitor 15b.

[0126] The second parallel circuit 12B has a node (third terminal) 12e and a node (fourth terminal) 12f. The node 12e is electrically connected to the output terminal 51b. A control pulse signal is input to the node 12e from the insulated gate driver 51. The node 12f is electrically connected to the logic synthesis unit 16A.

[0127] The third series circuit 13B is configured by connecting a third diode 131b and a third resistor 132b in series. The anode of the third diode 131b is connected to the node 12e. The third resistor 132b is connected between the cathode of the third diode 131b and the node 12f. Examples of the forward voltage of the third diode 131b and the resistance value of the third resistor 132b are the same as those of the first diode 131 and the first resistor 132 described in the first embodiment. The third diode 131b may be the same as or different from the first diode 131a. The third resistor 132b may be the same as or different from the first resistor 132a.

[0128] The fourth series circuit 14B is configured by connecting a fourth diode 141b and a fourth resistor 142b in series. The anode of the fourth diode 141b is electrically connected to the node 12f. The fourth resistor 142b is electrically connected between the cathode of the fourth diode 141b and the node 12e. Examples of the forward voltage of the fourth diode 141b and the resistance value of the fourth resistor 142b are the same as those of the first diode 131 and the first resistor 132 described in the first embodiment. The fourth diode 141b may be the same as or different from the second diode 141a. The fourth resistor 142b may be the same as or different from the second resistor 142a.

[0129] The second capacitor 15b is electrically connected between the node 12f and the first reference potential line 56b. An example of the capacitance of the second capacitor 15b is the same as that of the capacitor 15 described in the first embodiment. The second capacitor 15b may be the same as or different from the first capacitor 15a.

[0130] In the second delay circuit 11B, the third series circuit 13B functions as a signal path that delays the rising edge of the control pulse signal, and the third series circuit 13B (specifically, the third resistor 132b) and the second capacitor 15b form a delay circuit that delays the rising edge of the control pulse signal. The delay time for the rising edge is determined by the resistance value of the third resistor 132b and the capacitance of the second capacitor 15b. In other words, the delay time for the rising edge that is applied to the input pulse signal in the second delay circuit 11B is set to Td2 ＯＮ [s], the resistance value of the third resistor 132b is R1b [Ω], and the capacitance of the second capacitor 15b is C2 [F], then Td2 ＯＮ is expressed by the formula (3). ＯＮ = R1b × C2 (3)

[0131] In the second delay circuit 11B, the fourth series circuit 14B functions as a signal path that delays the falling edge of the control pulse signal, and the fourth series circuit 14B (specifically, the fourth resistor 142b) and the second capacitor 15b form a delay circuit that delays the falling edge of the control pulse signal. The delay time for the falling edge is determined by the resistance value of the fourth resistor 142b and the capacitance of the second capacitor 15b. In other words, the delay time for the falling edge that is applied to the control pulse signal in the second delay circuit 11B is set to Td2 ＯＦＦ [s] and the resistance value of the fourth resistor 142b is R2b [Ω], Td2 ＯＦＦ is expressed by the formula (4). ＯＦＦ = R2b × C2 (4)

[0132] In the second embodiment, the delay time Td1 defined by the formulas (1), (2), (3), and (4) ＯＮ , Td1 ＯＦＦ , Td2 ＯＮ , Td2 ＯＦＦ satisfies the relationships of Equation (5) and Equation (6). ＯＮ <Td2 ＯＮ ... (5) Td1 ＯＦＦ <Td2 ＯＦＦ...(6) In other words, the resistance value R1a of the first resistor 132a, the resistance value R2a of the second resistor 142a, the capacitance C1 of the first capacitor 15a, the resistance value R1b of the third resistor 132b, the resistance value R2b of the fourth resistor 142b, and the capacitance C2 of the second capacitor 15b are set to satisfy equations (5) and (6).

[0133] (Logic synthesis unit) The logic synthesis unit 16A generates a first control pulse signal by performing a logical AND on a signal set of first delay pulse signals, and generates a second control pulse signal by performing an exclusive OR on a signal set of the second delay pulse signal and the control pulse signal.

[0134] The logic synthesis unit 16A includes an AND circuit 161 for generating a first control pulse signal and an XOR circuit 163 for generating a second control pulse signal. The logic synthesis unit 16A may be driven by a third voltage stepped down by the step-down circuit 55.

[0135] The AND circuit 161 is electrically connected to the first delay circuit 11A. A signal set of first delay pulse signals is input to the AND circuit 161. That is, a pair of first delay pulse signals is input to the AND circuit 161 from the delay signal generating unit 10A. The AND circuit 161 is a logical product circuit that outputs a first control pulse signal by performing a logical product of the input first delay pulse signals. The AND circuit 161 may be electrically connected between the step-down circuit 55 and the second reference potential line 57b. In this case, the AND circuit 161 is driven by a third voltage that is obtained by stepping down the second voltage by the step-down circuit 55. An example of the drive voltage of the AND circuit 161 is 5V.

[0136] The XOR circuit 163 is electrically connected to the insulated gate driver 51 and the second delay circuit 11B. A signal set of a control pulse signal and a second delay pulse signal is input to the XOR circuit 163. The XOR circuit 163 is an exclusive-OR circuit that outputs a second control pulse signal by performing an exclusive-OR operation on the input control pulse signal and the second delay pulse signal. The XOR circuit 163 may be electrically connected between the step-down circuit 55 and the second reference potential line 57b. In this case, the XOR circuit 163 is driven by a third voltage obtained by stepping down the second voltage by the step-down circuit 55. An example of the drive voltage of the XOR circuit 163 is 5V.

[0137] 4, the control signal generating circuit 5A may include a first push-pull circuit 53a, a second push-pull circuit 53b, a first gate resistor 54a, and a second gate resistor 54b downstream of the logic synthesis unit 16A. The configurations and connections of the first push-pull circuit 53a and the second push-pull circuit 53b are the same as those in the first embodiment, and therefore a description of the first push-pull circuit 53a and the second push-pull circuit 53b will be omitted. The layout of the first gate resistor 54a and the second gate resistor 54b is also the same as in the first embodiment. Therefore, in the control signal generating circuit 5A, the circuit configuration for generating a first gate signal in response to the first control pulse signal generated by the signal generating unit 52A and the circuit configuration for generating a second gate signal in response to the second control pulse signal generated by the signal generating unit 52A are the same as those in the first embodiment.

[0138] 5 is a time chart of various signals in the second embodiment. In FIG. 5, the input pulse signal, the control pulse signal, the first delay pulse signal, the second delay pulse signal, the first control pulse signal, the second control pulse signal, and the main circuit current are respectively represented as the input pulse signal S0, the control pulse signal S1, the first delay pulse signal S2a, the second delay pulse signal S2b, the first control pulse signal S3, the second control pulse signal S4, and the main circuit current I Ｍ In the second embodiment, the control pulse signal S1 is the same as the input pulse signal S0, so the input pulse signal S0 and the control pulse signal S1 are shown together in FIG. 5. The main circuit current I Ｍis the current flowing through the switch section 20, as in the first embodiment.

[0139] In FIG. 5, the AND circuit 161 and the XOR circuit 163 have threshold voltages (threshold signal levels) for regarding an input signal as High and Low, respectively. ＩＨ and V ＩＬ In the AND circuit 161 and the XOR circuit 163, the input signal is V ＩＨ Once it exceeds V ＩＬ is considered to be in a High state unless the input signal falls below V ＩＬ Once it falls below V ＩＨ It is considered to be in a low state unless it exceeds V. ＩＨ An example of V is 3V, ＩＬ An example is 2V.

[0140] An example of the operation of the control signal generating circuit 5A and the switch unit 20 will be described with reference to Figures 4 and 5. The meaning of "rising after a delay time from time α" and "falling after a delay time from time β" is the same as in the first embodiment. In the example shown in Figure 5, the threshold level that determines the delay time of the rise is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the XOR circuit 163 as High. ＩＨ The threshold level that determines the delay time of the falling edge is V, which is the same as the threshold voltage for regarding the signals input to the AND circuit 161 and the XOR circuit 163 as Low. ＩＬ is.

[0141] When an input pulse signal S0 is input to an insulated gate driver 51 included in the control signal generation circuit 5A, the insulated gate driver 51 outputs a control pulse signal S1 based on the input pulse signal S0. In this embodiment, the control pulse signal S1 is the same signal as the input pulse signal S0. As shown in FIG. 5 , the input pulse signal S0 and the control pulse signal S1 have pulses that rise at time T1 and fall at time T4. When the control pulse signal S1 is input to the delay signal generation unit 10A, the delay signal generation unit 10A generates a first delay pulse signal S2a and a second delay pulse signal S2b.

[0142] The first delay circuit 11A included in the delay signal generating unit 10A includes a first parallel circuit 12A and a first capacitor 15a. The first parallel circuit 12A includes a first series circuit 13A that contributes to delaying the rising edge and a second series circuit 14A that contributes to delaying the falling edge. Therefore, as shown in FIG. 5, the first delay pulse signal S2a is generated from time T1 for a delay time Td1. ＯＮ It rises at time T2 after that, and starts at time T4 with a delay time Td1 ＯＦＦ It falls later at time T5.

[0143] The first delay pulse signal S2a generated by the first delay circuit 11A is input to the logic synthesis unit 16A. Specifically, a pair of first delay pulse signals S2a are input to an AND circuit 161. The AND circuit 161 performs a logical AND operation on the signal set of the first delay pulse signals S2a to generate a first control pulse signal S3.

[0144] In the example shown in FIG. 5, the signal level (voltage) of the first delayed pulse signal S2a is equal to or exceeds the threshold voltage V ＩＨ At time T5, the threshold voltage V ＩＬ Therefore, the first delayed pulse signal S2a input to the AND circuit 161 is in a High state from time T2 to time T5, and thereafter, the first delayed pulse signal S2a is again below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0145] The first control pulse signal S3 is generated by ANDing the first delay pulse signals S2a together. Due to the relationship between the high and low states of the first delay pulse signal S2a in the AND circuit 161, the first control pulse signal S3 is a pulse signal that rises at time T2 and falls at time T5.

[0146] The second delay circuit 11B included in the delay signal generating unit 10A includes a second parallel circuit 12B and a second capacitor 15b. The second parallel circuit 12B includes a third series circuit 13B that contributes to delaying the rising edge and a fourth series circuit 14B that contributes to delaying the falling edge. Furthermore, in this embodiment, the resistance value R1a of the first resistor 132a, the resistance value R2a of the second resistor 142a, the capacitance C1 of the first capacitor 15a, the resistance value R1b of the third resistor 132b, the resistance value R2b of the fourth resistor 142b, and the capacitance C2 of the second capacitor 15b are set so as to satisfy equations (5) and (6).

[0147] Therefore, as shown in FIG. 5, the second delay pulse signal S2b is generated from time T1 for a delay time Td2. ＯＮ It rises at time T3 after that, and the delay time Td2 ＯＦＦ It falls later at time T6.

[0148] The second delay pulse signal S2b generated by the second delay circuit 11B is input to the logic synthesis unit 16A. Specifically, the second delay pulse signal S2b is input to an XOR circuit 163. The control pulse signal S1 is also input to the XOR circuit 163. The XOR circuit 163 performs an exclusive OR on the signal set of the control pulse signal S1 and the second delay pulse signal S2b to generate a second control pulse signal S4.

[0149] In the example shown in FIG. 5, the signal level (voltage) of the control pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, the control pulse signal S1 input to the XOR circuit 163 is in a High state from time T1 to time T4, and thereafter, the control pulse signal S1 again falls below the threshold voltage V ＩＨ The signal level (voltage) of the second delayed pulse signal S2b is processed as a signal that is maintained in a low state until it exceeds the threshold voltage V at time T3. ＩＨ At time T6, the threshold voltage V ＩＬ Therefore, the second delayed pulse signal S2b input to the XOR circuit 163 is in a High state from time T3 to time T6, and thereafter, the second delayed pulse signal S2b is again below the threshold voltage VＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0150] The second control pulse signal S4 is generated by the exclusive OR of the signal set of the control pulse signal S1 and the second delay pulse signal S2b. Due to the relationship between the high and low states of the control pulse signal S1 and the second delay pulse signal S2b in the XOR circuit 163, the second control pulse signal S4 is a pulse signal that rises at time T1, falls at time T3, rises again at time T4, and falls at time T6.

[0151] In this way, the control signal generating circuit 5A can generate two different control pulse signals, the first control pulse signal S3 and the second control pulse signal S4, based on one input pulse signal S0 (control pulse signal S1).

[0152] 4, the first control pulse signal S3 is input to the first push-pull circuit 53a and output as a first gate signal. The first gate signal is input to the first output terminal 5b. The first output terminal 5b is electrically connected to the gate of the first switching element 21, and therefore the first switching element 21 is driven by the first gate signal.

[0153] The first gate signal is a pulse signal obtained by amplifying the first control pulse signal, and therefore has the same waveform as the first control pulse signal S3.

[0154] 4, the second control pulse signal S4 is input to the second push-pull circuit 53b and output as a second gate signal. The second gate signal is input to the second output terminal 5c. The second output terminal 5c is electrically connected to the gate of the second switching element 22, so that the second switching element 22 is driven by the second gate signal.

[0155] The second gate signal is a pulse signal obtained by amplifying the second control pulse signal S4, and therefore has the same waveform as the second control pulse signal S4.

[0156] The first switching element 21 is driven by a first gate signal having a waveform similar to that of the first control pulse signal S3, and is therefore turned on at time T2 and turned off at time T5. The second switching element 22 is driven by a second gate signal having a waveform similar to that of the second control pulse signal S4, and is therefore turned on at time T1, turned off once at time T3, turned on again at time T4, and then turned off at time T6. Therefore, the second switching element 22 is in an on state from time T1 to time T3, an off state from time T3 to time T4, and an on state from time T4 to time T6. Of the two on states of the second switching element 22, the on state from time T1 to time T3 is referred to as a first on state, and the on state from time T4 to time T6 after the first on state is referred to as a second on state.

[0157] As described above, the first switching element 21 is turned on at time T2, and therefore the first switching element 21 is turned on between time T1 and time T3 (while the second switching element 22 is in the first on state). ＯＮ and delay time Td2 ＯＮ is realized by satisfying the formula (5).

[0158] As described above, the first switching element 21 is turned off at time T5, and therefore the first switching element 21 is turned off between time T4 and time T6 (while the second switching element 22 is in the second on state). ＯＦＦ and delay time Td2 ＯＦＦ is realized by satisfying the formula (6).

[0159] The switch unit 20 is configured by connecting a first switching element 21 and a second switching element 22 in parallel. Therefore, as in the first embodiment, when either the first switching element 21 or the second switching element 22 is in the on state, the switch unit 20 is in the on state, and when both the first switching element 21 and the second switching element 22 are in the off state, the switch unit 20 is in the off state. Therefore, the switch unit 20 is in the on state from time T1 to time T6, and as shown in FIG. 5, the main circuit current I Ｍ is playing.

[0160] 5 , in the configuration of the control signal generation circuit 5A included in the signal generation unit 52A, the second switching element 22, which is a SiC-MOSTET, is in the ON state from time T1 to time T3, is in the OFF state from time T3 to time T4, and is in the ON state from time T4 to time T6. On the other hand, in the configuration of the control signal generation circuit 5A included in the signal generation unit 52A, the first switching element 21, which is a Si-IGBT, is in the ON state from time T2 to time T5. Therefore, in this embodiment, the second switching element 22 essentially only performs the function of turning on and off the switch unit 20, and the first switching element 21 essentially functions as a current path when the switch unit 20 is in the ON state.

[0161] The Si-IGBT has smaller conduction loss at high currents than the SiC-MOSFET and is resistant to overcurrent. Therefore, since the current path when the switch unit 20 is in the on state is the first switching element 21 (Si-IGBT), the switch unit 20 has improved resistance to overcurrent. The second switching element 22 (SiC-MOSFET) is responsible for the turn-on and turn-off functions of the switch unit 20, enabling high-speed switching of the switch unit 20.

[0162] The control signal generation circuit 5A can generate different first and second control pulse signals from a common input pulse signal for the first switching element 21 and the second switching element 22. As described above, the control signal generation circuit 5A can output a first gate signal for driving the first switching element 21 and a second gate signal for driving the second switching element 22 in response to the first control pulse signal and the second control pulse signal. Furthermore, in the control signal generation circuit 5A as well, the isolated gate driver 51 is provided in a stage preceding the signal generation unit 52. Therefore, the control signal generation circuit 5A has the same effects as in the first embodiment.

[0163] The combination of the control signal generating circuit 5A and the switch unit 20 can be applied to the power conversion device 1 shown in Fig. 1 in place of the combination of the control signal generating circuit 5 and the switch unit 20. Since the control signal generating circuit 5A has the same effects as in the first embodiment, the power conversion device 1 to which the combination of the control signal generating circuit 5A and the switch unit 20 is applied also has the same effects as in the first embodiment.

[0164] In the first and second embodiments, the number of first switching elements and the number of second switching elements included in the switch unit are both 1. However, the number of first switching elements is not limited to 1, and the number of second switching elements is also not limited to 1.

[0165] In the third embodiment, a case will be described in which the switch section includes one first switching element 21 and two second switching elements.

[0166] 6 is a circuit diagram of a control signal generating circuit 5B according to the third embodiment. The control signal generating circuit 5B is a circuit for driving the switch section 20A shown in FIG.

[0167] The switch unit 20A has a first switching element 21, a second-a switching element 22A, and a second-b switching element 22B. In the third embodiment, the first switching element 21 is also a Si-IGBT, and the second-a switching element 22A and the second-b switching element 22B are SiC-MOSFETs. A freewheeling diode 23 may be connected in anti-parallel to each of the second-a switching element 22A and the second-b switching element 22B.

[0168] The first switching element 21, the 2a switching element 22A, and the 2b switching element 22B are connected in parallel between nodes 20a and 20b. Specifically, the collector of the first switching element 21, the drain of the 2a switching element 22A, and the drain of the 2b switching element 22B are electrically connected to node 20a, and the emitter of the first switching element 21, the source of the 2a switching element 22A, and the source of the 2b switching element 22B are electrically connected to node 20b. Therefore, the potential of node 20b is the potential of the emitter of the first switching element 21, the source of the 2a switching element 22A, and the source of the 2b switching element 22B.

[0169] The switch unit 20A is applied to the power conversion device 1 shown in FIG.

[0170] Control signal generating circuit 5B differs from control signal generating circuit 5A (or control signal generating circuit 5) mainly in that control signal generating circuit 5B has signal generating unit 52B instead of signal generating unit 52 and in that control signal generating circuit 5B has second output terminals 5c1 and 5c2. An example of control signal generating circuit 5B will be described based on the configuration shown in FIG.

[0171] In the control signal generating circuit 5B, the second output terminal 5c1 is electrically connected to the gate of the 2a switching element 22A, and the second output terminal 5c2 is electrically connected to the gate of the 2b switching element 22B.

[0172] As shown in FIG. 6, the control signal generation circuit 5B, like the control signal generation circuit 5, has an input terminal 5a, a first output terminal 5b, a first high potential input terminal 5d, a first reference potential input terminal 5e, a second high potential input terminal 5f, and a second reference potential input terminal 5g.

[0173] The input terminal 5a is electrically connected to the external control device 7. The first output terminal 5b is electrically connected to the gate of the first switching element 21. The first high potential input terminal 5d receives a first high potential from an external power supply 61. The first reference potential input terminal 5e receives a first reference potential from an external reference potential wiring 63 (or reference potential source). The second high potential input terminal 5f receives a second high potential from an external power supply 62. The second reference potential input terminal 5g receives a second reference potential from the outside. As shown in FIG. 6 , the second reference potential input terminal 5g is electrically connected to node 20b, and therefore the second reference potential is the potential of node 20b. As described above, the potential of node 20b is the potential of the emitter of the first switching element 21, the source of the 2a switching element 22A, and the source of the 2b switching element 22B.

[0174] As in the first embodiment, in the control signal generating circuit 5B, the wiring that provides the first high potential, the wiring that provides the first reference potential, the wiring that provides the second high potential, and the wiring that provides the second reference potential are referred to as the first high potential line 56a, the first reference potential line 56b, the second high potential line 57a, and the second reference potential line 57b, respectively.

[0175] [Control Signal Generation Circuit] The control signal generation circuit 5B has an insulated gate driver 51 and a signal generation unit 52B.

[0176] <Insulated Gate Driver> The isolated gate driver 51 outputs a control pulse signal from an output terminal 51b corresponding to an input pulse signal input to an input terminal 51a. The isolated gate driver 51 is the same as in the first embodiment, so a description of the isolated gate driver 51 will be omitted. In the third embodiment, the isolated gate driver 51 is also an isolated circuit, and the control pulse signal is substantially the same as the input pulse signal.

[0177] <Signal Generator> The signal generator 52B includes a delayed signal generator 10B and a logic synthesis unit 16B.

[0178] (Delay Signal Generator) The delay signal generator 10B generates a first delay pulse signal, a second a delay pulse signal, and a second b delay pulse signal that are different in delay state from the control pulse signal. The second a delay pulse signal is a pulse signal that is delayed with respect to the rising edge of the control pulse signal, and the second b delay pulse signal is a pulse signal that is delayed with respect to the falling edge of the control pulse signal.

[0179] The delay signal generating section 10B includes a first delay circuit 11A, a second delay circuit 11C, and a second delay circuit 11D.

[0180] (First Delay Circuit) The configuration of the first delay circuit 11A is the same as that of the first delay circuit 11A in the second embodiment, and therefore a description thereof will be omitted.

[0181] (2a Delay Circuit) The 2a delay circuit 11C has a 2a parallel circuit 12C in which a third series circuit (3a series circuit) 13B and a fourth diode (3b diode) 141b are connected in parallel, and a second capacitor (2a capacitor) 15b.

[0182] The 2a-th parallel circuit 12C has a node (3a-th terminal) 121a and a node (3b-th terminal) 121b. The node 121a is electrically connected to the output terminal 51b. An input pulse signal is input to the node 121a from the external control device 7. The node 121b is electrically connected to the logic synthesis unit 16B.

[0183] The third series circuit 13B has the same configuration as the third series circuit 13B described in the second embodiment. That is, the third series circuit 13B is configured by connecting a third diode (3a diode) 131b and a third resistor (3a resistor) 132b in series. The anode of the third diode 131b is connected to the node 121a. The third resistor 132b is connected between the cathode of the third diode 131b and the node 121b.

[0184] The anode of the fourth diode 141b is connected to the node 121b, and the cathode of the fourth diode 141b is connected to the node 121a.

[0185] The second capacitor 15b is electrically connected between the node 121b and the first reference potential line 56b.

[0186] In the 2a delay circuit 11C, the third series circuit 13B functions as a signal path that delays the rising edge of the control pulse signal, as described in the second embodiment, and the third series circuit 13B (specifically, the third resistor 132b) and the second capacitor 15b form a delay circuit that delays the rising edge of the control pulse signal. In the 2a parallel circuit 12C, instead of the fourth series circuit 14B, only the fourth diode 141b is connected in parallel to the third series circuit 13B as described above. Therefore, the 2a delay circuit 11C does not have the function of delaying the falling edge of the input pulse signal.

[0187] Therefore, the 2a delay circuit 11C is a circuit that corresponds to the function of delaying the rising edge of the control pulse signal, among the functions of the second delay circuit 11B in the second embodiment. ＯＮ is defined by the formula (3) described in the second embodiment.

[0188] (2b Delay Circuit) The 2b delay circuit 11D has a 2b parallel circuit 12D in which a fourth series circuit (3b series circuit) 14B and a third diode (3c diode) 131b are connected in parallel, and a second capacitor (2b capacitor) 15b.

[0189] The 2b parallel circuit 12D has a node (3c terminal) 122a and a node (3d terminal) 122b. The node 122a is electrically connected to the output terminal 51b. An input pulse signal is input to the node 122a from the insulated gate driver 51. The node 122b is electrically connected to the logic synthesis unit 16B.

[0190] The fourth series circuit 14B has the same configuration as the fourth series circuit 14B described in the second embodiment. That is, the fourth series circuit 14B is configured by connecting a fourth diode (3d diode) 141b and a fourth resistor (3b resistor) 142b in series. The anode of the fourth diode 141b is connected to the node 122b. The fourth resistor 142b is connected between the cathode of the fourth diode 141b and the node 122a.

[0191] The anode of the third diode 131b is connected to the node 122a, and the cathode of the third diode 131b is connected to the node 122b.

[0192] The second capacitor 15b is electrically connected between the node 122b and the first reference potential line 56b.

[0193] In the 2b delay circuit 11D, the fourth series circuit 14B functions as a signal path that delays the falling edge of the control pulse signal, as described in the second embodiment, and the fourth series circuit 14B (specifically, the fourth resistor 142b) and the second capacitor 15b form a delay circuit that delays the falling edge of the control pulse signal. In the 2b parallel circuit 12D, instead of the third series circuit 13B, only the third diode 131b is connected in parallel to the fourth series circuit 14B as described above. Therefore, the 2b delay circuit 11D does not have the function of delaying the rising edge of the control pulse signal.

[0194] Therefore, the 2b delay circuit 11D is a circuit corresponding to the function of delaying the falling edge of the control pulse signal, which is one of the functions of the second delay circuit 11B in the second embodiment. ＯＦＦ is defined by the formula (4) described in the second embodiment.

[0195] (Logic Synthesis Unit) The logic synthesis unit 16B generates the first control pulse signal by performing a logical AND on a signal set of the first delay pulse signals. The logic synthesis unit 16B generates the second a control pulse signal by performing an exclusive OR on a signal set of the control pulse signal and the second a delay pulse signal. The logic synthesis unit 16B generates the second b control pulse signal by performing an exclusive OR on a signal set of the control pulse signal and the second b delay pulse signal.

[0196] The logic synthesis unit 16 includes an AND circuit 161, a first XOR circuit 163a, and a second XOR circuit 163b.

[0197] The AND circuit 161 is electrically connected to the first delay circuit 11A. A signal set of first delay pulse signals is input to the AND circuit 161. That is, a pair of first delay pulse signals is input to the AND circuit 161 from the first delay circuit 11A. The AND circuit 161 is a logical product circuit that outputs a first control pulse signal by performing a logical product of the input first delay pulse signals. The AND circuit 161 may be electrically connected between the step-down circuit 55 and the second reference potential line 57b. In this case, the AND circuit 161 is driven by a third voltage that is obtained by stepping down the second voltage by the step-down circuit 55. An example of the drive voltage of the AND circuit 161 is 5V.

[0198] The first XOR circuit 163a is electrically connected to the insulated gate driver 51 and the 2a delay circuit 11C. A signal set of a control pulse signal and a 2a delay pulse signal is input to the first XOR circuit 163a. ​​The first XOR circuit 163a is an exclusive-OR circuit that outputs a 2a control pulse signal by performing an exclusive-OR operation on the input control pulse signal and the 2a delay pulse signal. The first XOR circuit 163a may be electrically connected between the step-down circuit 55 and the second reference potential line 57b. In this case, the first XOR circuit 163a is driven by a third voltage obtained by stepping down the second voltage by the step-down circuit 55. An example of the drive voltage of the first XOR circuit 163a is 5V.

[0199] The second XOR circuit 163b is electrically connected to the insulated gate driver 51 and the 2b delay circuit 11D. A signal set of a control pulse signal and a 2b delay pulse signal is input to the second XOR circuit 163b. The second XOR circuit 163b is an exclusive-OR circuit that outputs a 2b control pulse signal by performing an exclusive-OR operation on the input control pulse signal and the 2b delay pulse signal. The second XOR circuit 163b may be electrically connected between the step-down circuit 55 and the second reference potential line 57b. In this case, the second XOR circuit 163b is driven by a third voltage obtained by stepping down the second voltage by the step-down circuit 55. An example of the drive voltage of the second XOR circuit 163b is 5V.

[0200] 6, the control signal generating circuit 5B may include a first push-pull circuit 53a, a second push-pull circuit 53b1, a second push-pull circuit 53b2, a first gate resistor 54a, a second gate resistor 54b1, and a second gate resistor 54b2 downstream of the logic synthesis unit 16B. The configuration and connection of the first push-pull circuit 53a are the same as those in the first embodiment, and therefore a description of the first push-pull circuit 53a will be omitted. The layout of the first gate resistor 54a is also the same as in the first embodiment. Therefore, the circuit configuration of the control signal generating circuit 5B for generating the first gate signal in response to the first control pulse signal generated by the signal generating unit 52B is the same as that in the first embodiment.

[0201] The second push-pull circuit 53b1 has a first transistor Tr1 and a second transistor Tr2 connected in series between the second high potential line 57a and the second reference potential line 57b. The second push-pull circuit 53b1 is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series. The first transistor Tr1 and the second transistor Tr2 are an npn transistor and a pnp transistor, respectively.

[0202] The electrical connections of the first transistor Tr1 and the second transistor Tr2, the second high potential line 57a, and the second reference potential line 57b included in the second push-pull circuit 53b1 are the same as those in the second push-pull circuit 53b described in Embodiment 1. The gates of the first transistor Tr1 and the second transistor Tr2 included in the second push-pull circuit 53b1 are electrically connected to the first XOR circuit 163a, and a 2a control pulse signal is input from the first XOR circuit 163a.

[0203] In the second push-pull circuit 53b1, a node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 is electrically connected to the second output terminal 5c1 via a second gate resistor 54b1, the example of which is the same as that of the second gate resistor 54b described in the first embodiment.

[0204] In the second push-pull circuit 53b1 configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the 2a control pulse signal from the first XOR circuit 163a. ​​As a result, the 2a control pulse signal is amplified to produce a 2a gate signal (2a drive pulse signal). The 2a gate signal is input to the second output terminal 5c1 via the second gate resistor 54b1. Since the second output terminal 5c1 is electrically connected to the gate of the 2a switching element 22A, the 2a gate signal is input to the gate of the 2a switching element 22A.

[0205] The second push-pull circuit 53b2 has a first transistor Tr1 and a second transistor Tr2 connected in series between the second high potential line 57a and the second reference potential line 57b. The second push-pull circuit 53b2 is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series. The first transistor Tr1 and the second transistor Tr2 are an npn transistor and a pnp transistor, respectively.

[0206] The electrical connections of the first transistor Tr1 and the second transistor Tr2, the second high potential line 57a, and the second reference potential line 57b included in the second push-pull circuit 53b2 are the same as those in the second push-pull circuit 53b described in Embodiment 1. The gates of the first transistor Tr1 and the second transistor Tr2 included in the second push-pull circuit 53b2 are electrically connected to the second XOR circuit 163b, and a 2b control pulse signal is input from the second XOR circuit 163b.

[0207] In the second push-pull circuit 53b2, a node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 is electrically connected to the second output terminal 5c2 via a second gate resistor 54b2, the resistance value of which is the same as that of the second gate resistor 54b.

[0208] In the second push-pull circuit 53b2 configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the 2b control pulse signal from the second XOR circuit 163b. As a result, the 2b control pulse signal is amplified to produce a 2b gate signal (2b drive pulse signal). The 2b gate signal is input to the second output terminal 5c2 via the second gate resistor 54b2. Since the second output terminal 5c2 is electrically connected to the gate of the 2b switching element 22B, the 2b gate signal is input to the gate of the 2b switching element 22B.

[0209] 7 is a time chart of various signals in the third embodiment. In FIG. 7, the input pulse signal, the first delay pulse signal, the second-a delay pulse signal, the second-b delay pulse signal, the first control pulse signal, the second-a control pulse signal, the second-b control pulse signal, and the main circuit current are respectively represented as the input pulse signal S0, the control pulse signal S1, the first delay pulse signal S2a, the second-a delay pulse signal S2b1, the second-b delay pulse signal S2b2, the first control pulse signal S3, the second-a control pulse signal S4a, the second-b control pulse signal S4b, and the main circuit current I ＭIn the third embodiment, the control pulse signal S1 is the same as the input pulse signal S0, so the input pulse signal S0 and the control pulse signal S1 are shown together in FIG. 7. The main circuit current I Ｍ is the current flowing through the switch section 20A, as in the first embodiment.

[0210] In FIG. 7, the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b have threshold voltages (threshold signal levels) for regarding an input signal as High and for regarding an input signal as Low, respectively, set as V ＩＨ and V ＩＬ In the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b, the input signals are V ＩＨ Once it exceeds V ＩＬ is considered to be in a High state unless the input signal falls below V ＩＬ Once it falls below V ＩＨ It is considered to be in a low state unless it exceeds V. ＩＨ An example of V is 3V, ＩＬ An example is 2V.

[0211] In the example shown in FIG. 7, as in the second embodiment, the threshold level that determines the delay time of the rising edge is V, which is the same as the threshold voltage for regarding the signals input to the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b as High. ＩＨ The threshold level that determines the delay time of the falling edge is also V, which is the same as the threshold voltage for regarding the signals input to the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b as Low. ＩＬ is.

[0212] When an input pulse signal S0 is input to an insulated gate driver 51 included in the control signal generation circuit 5B, the insulated gate driver 51 outputs a control pulse signal S1 based on the input pulse signal S0. In this embodiment, the control pulse signal S1 is the same as the input pulse signal S0. As shown in FIG. 7 , the control pulse signal S1 has a pulse that rises at time T1 and falls at time T4, similar to the second embodiment. When the control pulse signal S1 is input to the delay signal generation unit 10B, the delay signal generation unit 10B generates a first delay pulse signal S2a, a second-a delay pulse signal S2b1, and a second-b delay pulse signal S2b2.

[0213] The first delay circuit 11A included in the delay signal generating unit 10B has the same configuration as the first delay circuit 11A described in the second embodiment. Therefore, as shown in FIG. 7, the first delay pulse signal S2a is generated from time T1 for a delay time Td1, as in the second embodiment. ＯＮ It rises at time T2 after time T4 and starts at delay time Td1 ＯＦＦ It falls later at time T5.

[0214] In the example shown in FIG. 7, the signal level (voltage) of the first delayed pulse signal S2a is equal to or exceeds the threshold voltage V ＩＨ At time T5, the threshold voltage V ＩＬ Therefore, in the AND circuit 161, the first delayed pulse signal S2a is in a High state from time T2 to time T5, as in the second embodiment, and thereafter falls below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0215] The first control pulse signal S3 is generated in response to the first delay pulse signal S2a generated by the first delay circuit 11A in the same manner as in the second embodiment. Therefore, the first control pulse signal S3 is a pulse signal that rises at time T2 and falls at time T5, similar to the second embodiment.

[0216] As described above, the second delay circuit 11C provided in the delay signal generating unit 10B is a circuit corresponding to the function of delaying the rising edge of the control pulse signal S1, which is one of the functions of the second delay circuit 11B in the second embodiment, but does not have the function of delaying the falling edge of the control pulse signal S1. Therefore, as shown in FIG. 7, the second delay pulse signal S2b1 is generated from time T1 for a delay time Td2. ＯＮ It rises later at time T3 and falls at time T4.

[0217] The 2a-th delay pulse signal S2b1 generated by the 2a-th delay circuit 11C is input to the logic synthesis unit 16B. Specifically, the 2a-th delay pulse signal S2b1 is input to a first XOR circuit 163a. ​​The control pulse signal S1 is also input to the first XOR circuit 163a. ​​The first XOR circuit 163a performs an exclusive OR on the signal set of the control pulse signal S1 and the 2a-th delay pulse signal S2b1 to generate the 2a-th control pulse signal S4a.

[0218] In the example shown in FIG. 7, the signal level (voltage) of the control pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, in the first XOR circuit 163a, the control pulse signal S1 is in a High state from time T1 to time T4, and thereafter, the control pulse signal S1 again falls below the threshold voltage V ＩＨ The signal level (voltage) of the 2a delayed pulse signal S2b1 is processed as a signal that is maintained in a low state until it exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, in the first XOR circuit 163a, the 2a delayed pulse signal S2b1 is in a High state from time T3 to time T4, and thereafter, the 2a delayed pulse signal S2b1 is again below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0219] The 2a control pulse signal S4a is generated by the exclusive OR of the signal set of the control pulse signal S1 and the 2a delayed pulse signal S2b 1. Due to the relationship between the high and low states of the control pulse signal S1 and the 2a delayed pulse signal S2b 1 in the first XOR circuit 163a, the 2a control pulse signal S4a is a pulse signal that rises at time T1 and falls at time T3.

[0220] As described above, the 2b delay circuit 11D provided in the delay signal generating unit 10B is a circuit corresponding to the function of delaying the falling edge of the control pulse signal S1, which is one of the functions of the second delay circuit 11B in the second embodiment, but does not have the function of delaying the rising edge of the control pulse signal S1. Therefore, as shown in FIG. 7, the 2b delay pulse signal S2b2 rises from time T1 and is held for a delay time Td2 from time T4. ＯＦＦ It falls later at time T6.

[0221] The 2b delay pulse signal S2b2 generated by the 2b delay circuit 11D is input to the logic synthesis unit 16B. Specifically, the 2b delay pulse signal S2b2 is input to a second XOR circuit 163b. The control pulse signal S1 is also input to the second XOR circuit 163b. The second XOR circuit 163b performs an exclusive OR on the signal set of the control pulse signal S1 and the 2b delay pulse signal S2b2 to generate the 2b control pulse signal S4b.

[0222] In the example shown in FIG. 7, the signal level (voltage) of the control pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, in the second XOR circuit 163b, the control pulse signal S1 is also in a High state from time T1 to time T4, and thereafter, the control pulse signal S1 again falls below the threshold voltage V ＩＨ The signal level (voltage) of the 2b delayed pulse signal S2b2 is processed as a signal that is maintained in a low state until it exceeds the threshold voltage V ＩＨ At time T6, the threshold voltage V ＩＬTherefore, in the second XOR circuit 163b, the 2b delayed pulse signal S2b2 is in a High state from time T1 to time T6, and thereafter, the 2b delayed pulse signal S2b2 is again below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0223] The 2b control pulse signal S4b is generated by the exclusive OR of the signal set of the control pulse signal S1 and the 2b delayed pulse signal S2b2. Due to the relationship between the high and low states of the control pulse signal S1 and the 2b delayed pulse signal S2b2 in the second XOR circuit 163b, the 2b control pulse signal S4b is a pulse signal that rises at time T4 and falls at time T6.

[0224] In this way, the control signal generating circuit 5B can generate the first control pulse signal S3, the second-a control pulse signal S4a, and the second-b control pulse signal S4b based on one input pulse signal S0 (control pulse signal S1).

[0225] In the control signal generating circuit 5B, the first control pulse signal S3 is input to the first push-pull circuit 53a and output as a first gate signal. The first gate signal is input to the first output terminal 5b via the first gate resistor 54a. The first output terminal 5b is electrically connected to the gate of the first switching element 21, so that the first switching element 21 is driven by the first gate signal.

[0226] The first gate signal is a pulse signal obtained by amplifying the first control pulse signal, and therefore has the same waveform as the first control pulse signal S3.

[0227] In the control signal generating circuit 5B, the 2a control pulse signal S4a is input to the second push-pull circuit 53b1 and output as the 2a gate signal. The 2a gate signal is input to the second output terminal 5c1 via the second gate resistor 54b1. Since the second output terminal 5c1 is electrically connected to the gate of the 2a switching element 22A, the 2a gate signal drives the 2a switching element 22A.

[0228] The 2a gate signal is a pulse signal obtained by amplifying the 2a control pulse signal, and therefore has the same waveform as the 2a control pulse signal S4a.

[0229] In the control signal generation circuit 5B, the 2b control pulse signal S4b is input to the second push-pull circuit 53b2 and output as the 2b gate signal. The 2b gate signal is input to the second output terminal 5c2 via the second gate resistor 54b2. Since the second output terminal 5c2 is electrically connected to the gate of the 2b switching element 22B, the 2b gate signal drives the 2b switching element 22B.

[0230] The 2b gate signal is a pulse signal obtained by amplifying the 2b control pulse signal, and therefore has the same waveform as the 2b control pulse signal S4b.

[0231] The first switching element 21 is driven by a first gate signal having a waveform similar to that of the first control pulse signal S3, so it turns on at time T2 and turns off at time T5. The second-a switching element 22A is driven by a second-a gate signal having a waveform similar to that of the second-a control pulse signal S4a, so it turns on at time T1 and turns off at time T3. The second-b switching element 22B is driven by a second-b gate signal having a waveform similar to that of the second-b control pulse signal S4b, so it turns on at time T4 and turns off at time T6.

[0232] The first switching element 21, the 2-a switching element 22A, and the 2-b switching element 22B are driven as described above. Therefore, the 2-a control pulse signal S4a and the 2-b control pulse signal S4b are signals for controlling the 2-a switching element 22A and the 2-b switching element 22B so that the on-state periods of the 2-a switching element 22A and the 2-b switching element 22B are shorter than the on-state period of the first switching element 21 and so that the on-state period of the 2-b switching element 22B occurs after the on-state period of the 2-a switching element 22A. Furthermore, the first control pulse signal S3 is a signal for controlling the first switching element 21 so that the first switching element 21 transitions from the off state to the on state during the on-state period of the 2-a switching element 22A and transitions from the on state to the off state during the on-state period of the 2-b switching element 22B.

[0233] The switch unit 20A is configured by connecting a first switching element 21, a second-a switching element 22A, and a second-b switching element 22B in parallel. Therefore, as in the first embodiment, when any one of the first switching element 21, the second-a switching element 22A, and the second-b switching element 22B is in the on state, the switch unit 20A is in the on state, and when all of the first switching element 21, the second-a switching element 22A, and the second-b switching element 22B are in the off state, the switch unit 20A is in the off state. Therefore, as shown in FIG. 7, the main circuit current I Ｍ flows from time T1 to time T6.

[0234] The 2a delay circuit 11C included in the delay signal generating unit 10B is a circuit that corresponds to the function of delaying the rising edge of a control pulse signal, which is one of the functions of the second delay circuit 11B in the second embodiment. The 2a switching element 22A is driven in response to a 2a control pulse signal S4a generated based on the 2a delay pulse signal S2b1 from the 2a delay circuit 11C. The 2b delay circuit 11D included in the delay signal generating unit 10B is a circuit that corresponds to the function of delaying the falling edge of a control pulse signal, which is one of the functions of the second delay circuit 11B in the second embodiment. The 2b switching element 22B is driven in response to a 2b control pulse signal S4b generated based on the 2b delay pulse signal S2b2 from the 2b delay circuit 11D.

[0235] Therefore, in the third embodiment, the function of turning on and off the switch unit 20, which was performed by the second switching element 22 in the second embodiment, is shared by the second-a switching element 22A and the second-b switching element 22B. Therefore, the control signal generating circuit 5B and the switch unit 20A have the same effects as those in the second embodiment.

[0236] The combination of the control signal generating circuit 5B and the switch unit 20A can be applied to the power conversion device 1 shown in Fig. 1 in place of the combination of the control signal generating circuit 5 and the switch unit 20. Since the control signal generating circuit 5B and the switch unit 20A have the same effects as those in the second embodiment, the power conversion device 1 to which the combination of the control signal generating circuit 5B and the switch unit 20A is applied also has the same effects as those in the second embodiment.

[0237] (Fourth Embodiment) Another example in which the switch unit has a plurality of first switching elements and a plurality of second switching elements will be described as a fourth embodiment. In the fourth embodiment, the first switching elements are Si-IGBTs and the second switching elements are SiC-MOSFETs. In the fourth embodiment, a configuration in which the switch unit has three first switching elements and three second switching elements will be described. FIG. 8 is a circuit diagram for explaining the fourth embodiment.

[0238] The switch unit 20B according to the fourth embodiment has three first switching elements 21A1, 21A2, and 21A3 and three second switching elements 22C1, 22C2, and 22C3. The three first switching elements 21A1, 21A2, and 21A3 have the same configuration and are Si-IGBTs, as in the first embodiment. The three second switching elements 22C1, 22C2, and 22C3 have the same configuration and are SiC-MOSFETs, as in the first embodiment.

[0239] The three first switching elements 21A1, 21A2, and 21A3 correspond to the first switching element 21 described in the first embodiment. The first switching elements 21A1, 21A2, and 21A3 have the same configuration. Therefore, the configuration of the first switching element 21A1 will be described, and descriptions of the configurations of the first switching elements 21A2 and 21A3 will be omitted.

[0240] The first switching element 21A1 has an element body 211 and a package 212 that houses the element body 211. The element body 211 is a Si-IGBT body (i.e., a bare Si-IGBT chip) mounted on a semiconductor substrate. Therefore, the element body 211 has a collector (first main terminal), an emitter (second main terminal), and a gate (control terminal). The first switching element 21A1 has a first terminal 213a, a second terminal 213b, and a third terminal 213c for externally connecting the element body 211 housed in the package 212. The first terminal 213a is electrically connected to the collector of the element body 211. The second terminal 213b is electrically connected to the emitter of the element body 211. The third terminal 213c is electrically connected to the gate of the element body 211.

[0241] The three second switching elements 22C1, 22C2, and 22C3 correspond to the second switching element 22 described in the first embodiment. The second switching elements 22C1, 22C2, and 22C3 have the same configuration. Therefore, the configuration of the second switching element 22C1 will be described, and descriptions of the configurations of the second switching elements 22C2 and 22C3 will be omitted.

[0242] The second switching element 22C1 has an element body 221 and a package 223 that houses the element body 221. The element body 221 is a SiC-MOSFET body (i.e., a bare chip of a SiC-MOSFET) mounted on a semiconductor substrate. Therefore, the element body 221 has a drain (first main terminal), a source (second main terminal), and a gate (control terminal). The second switching element 22C1 has a first terminal 224a, a second terminal 224b, and a third terminal 224c for externally connecting the element body 221 housed in the package 223. The first terminal 224a is electrically connected to the drain of the element body 221. The second terminal 224b is electrically connected to the source of the element body 221. The third terminal 224c is electrically connected to the gate of the element body 221.

[0243] The second switching element 22C1 may have a free wheel diode 222 housed in a package 223. The cathode of the free wheel diode 222 is electrically connected to the drain (or the first terminal 224a) of the element body 221, and the anode of the free wheel diode 222 is electrically connected to the source (or the second terminal 224b) of the element body 221. A parasitic diode included in the SiC-MOSFET body may be used as the free wheel diode.

[0244] The three first switching elements 21A1, 21A2, and 21A3 and the three second switching elements 22C1, 22C2, and 22C3 are connected in parallel between the node 20a and the node 20b.

[0245] A control signal generation circuit 5C that drives the switch section 20B differs from the control signal generation circuit 5 according to the first embodiment mainly in that it has three first output terminals 5b1, 5b2, and 5b3 and three second output terminals 5c1, 5c2, and 5c3. The configuration of the control signal generation circuit 5C other than the above differences is the same as that of the first embodiment, and therefore a description of the configuration of the control signal generation circuit 5C other than the above differences will be omitted.

[0246] In the following, a configuration will be described in which the control signal generating circuit 5C includes a first push-pull circuit 53a, a second push-pull circuit 53b, a first gate resistor 54a, and a second gate resistor 54b as shown in FIG.

[0247] The three first output terminals 5b1, 5b2, and 5b3 are electrically connected to the first push-pull circuit 53a via the first gate resistor 54a. Specifically, the three first output terminals 5b1, 5b2, and 5b3 are electrically connected to a node between the first transistor Tr1 and the second transistor Tr2 of the first push-pull circuit 53a via the first gate resistor 54a. Therefore, the same first gate signal is input to the first output terminals 5b1, 5b2, and 5b3.

[0248] The first output terminal 5b1 is electrically connected to the third terminal 213c of the first switching element 21A1. The first output terminal 5b2 is electrically connected to the third terminal 213c of the first switching element 21A2. The first output terminal 5b3 is electrically connected to the third terminal 213c of the first switching element 21A3. The same first gate signal is input to the first output terminals 5b1, 5b2, and 5b3, and therefore the same first gate signal is input to the third terminal 213c of each of the first switching elements 21A1, 21A2, and 21A3. In other words, the first switching elements 21A1, 21A2, and 21A3 are driven by the same first gate signal.

[0249] The three second output terminals 5c1, 5c2, and 5c3 are electrically connected to the second push-pull circuit 53b via the second gate resistor 54b. Specifically, the three second output terminals 5c1, 5c2, and 5c3 are electrically connected to a node between the first transistor Tr1 and the second transistor Tr2 of the second push-pull circuit 53b via the second gate resistor 54b. Therefore, the same second gate signal is input to the second output terminals 5c1, 5c2, and 5c3.

[0250] The second output terminal 5c1 is electrically connected to the third terminal 224c of the second switching element 22C1. The second output terminal 5c2 is electrically connected to the third terminal 224c of the second switching element 22C2. The second output terminal 5c3 is electrically connected to the third terminal 224c of the second switching element 22C3. Since the same second gate signal is input to the second output terminals 5c1, 5c2, and 5c3, the same second gate signal is input to the third terminal 224c of each of the second switching elements 22C1, 22C2, and 22C3. In other words, the second switching elements 22C1, 22C2, and 22C3 are driven by the same second gate signal.

[0251] The control signal generation circuit 5C is the same as the control signal generation circuit 5 described in the first embodiment, except that it outputs first gate signals from three first output terminals 5b1, 5b2, and 5b3 and outputs second gate signals from three second output terminals 5c1, 5c2, and 5c3. Therefore, the control signal generation circuit 5C has the same effects as the control signal generation circuit 5 described in the first embodiment.

[0252] The switch unit 20B has first switching elements 21A1, 21A2, and 21A3 driven by a first gate signal, and second switching elements 22C1, 22C2, and 22C3 driven by a second gate signal. The first switching elements 21A1, 21A2, and 21A3 correspond to the first switching element 21 described in the first embodiment, and the second switching elements 22C1, 22C2, and 22C3 correspond to the second switching element 22 described in the first embodiment. Thus, the switch unit 20B corresponds to a configuration in which three first switching elements 21 and three second switching elements 22 are connected in parallel. Therefore, the switch unit 20B, which is driven by the control signal generation circuit 5C, has the same functions and effects as the switch unit 20 described in the first embodiment.

[0253] The set of switch unit 20B and control signal generating circuit 5C described in the fourth embodiment can be applied to power conversion device 1 shown in Fig. 1 in place of control signal generating circuit 5 and switch unit 20. As described above, the action and effect of switch unit 20B and control signal generating circuit 5C is similar to that of switch unit 20 and control signal generating circuit 5 in the first embodiment, and therefore power conversion device 1 in which the set of switch unit 20B and control signal generating circuit 5C is applied in place of control signal generating circuit 5 and switch unit 20 also has the same action and effect as in the first embodiment.

[0254] The switch section 20B has three first switching elements 21A1, 21A2, and 21A3 and three second switching elements 22C1, 22C2, and 22C3, which are connected in parallel, making it easier for a larger current to flow through the switch section 20B.

[0255] Fifth Embodiment A fifth embodiment will be described below, which illustrates yet another example in which the switch unit has a plurality of first switching elements and a plurality of second switching elements. In the fifth embodiment, the first switching elements are Si-IGBTs and the second switching elements are SiC-MOSFETs.

[0256] Fig. 9 is a circuit diagram for explaining the fifth embodiment. Fig. 9 shows a switch section 20C according to the fifth embodiment and a control signal generation circuit 5C for driving the switch section 20C. The control signal generation circuit 5C is the same as that in the fourth embodiment, and therefore a description of the control signal generation circuit 5C will be omitted.

[0257] The switch unit 20C differs from the switch unit 20B described in the fourth embodiment mainly in that the first switching elements 21A1, 21A2, 21A3 and the second switching elements 22C1, 22C2, 22C3 described in the fourth embodiment are housed in a package 200. That is, the switch unit 20C is configured as a semiconductor module (or a switching module) including the first switching elements 21A1, 21A2, 21A3 and the second switching elements 22C1, 22C2, 22C3.

[0258] The package 200 has a first terminal 201, a second terminal 202, a third terminal 203a, a fourth terminal 203b, a fifth terminal 203c, a sixth terminal 204a, a seventh terminal 204b, and an eighth terminal 204c for externally connecting the first switching elements 21A1, 21A2, and 21A3 and the second switching elements 22C1, 22C2, and 22C3 housed in the package 200. The package 200 may also have a ninth terminal 205.

[0259] The first terminal 201 is electrically connected to the node 20a. The second terminal 202 is electrically connected to the node 20b. The first terminal 201 may be the node 20a, and the second terminal 202 may be the node 20b.

[0260] The third terminal 203a is electrically connected to the third terminal 213c of the first switching element 21A1 and is also electrically connected to the first output terminal 5b1 of the control signal generating circuit 5C, so that the first gate signal from the first output terminal 5b1 is input to the third terminal 213c of the first switching element 21A1.

[0261] The fourth terminal 203b is electrically connected to the third terminal 213c of the first switching element 21A2 and to the first output terminal 5b2 of the control signal generating circuit 5C, so that the first gate signal from the first output terminal 5b2 is input to the third terminal 213c of the first switching element 21A2.

[0262] The fifth terminal 203c is electrically connected to the third terminal 213c of the first switching element 21A3 and is also electrically connected to the first output terminal 5b3 of the control signal generation circuit 5C, so that the first gate signal from the first output terminal 5b3 is input to the third terminal 213c of the first switching element 21A3.

[0263] The sixth terminal 204a is electrically connected to the third terminal 224c of the second switching element 22C1 and is also electrically connected to the second output terminal 5c1 of the control signal generating circuit 5C, so that the second gate signal from the second output terminal 5c1 is input to the third terminal 224c of the second switching element 22C1.

[0264] The seventh terminal 204b is electrically connected to the third terminal 224c of the second switching element 22C2 and is also electrically connected to the second output terminal 5c2 of the control signal generating circuit 5C. Therefore, the second gate signal from the second output terminal 5c2 is input to the third terminal 224c of the second switching element 22C2.

[0265] The eighth terminal 204c is electrically connected to the third terminal 224c of the second switching element 22C3 and is also electrically connected to the second output terminal 5c3 of the control signal generation circuit 5C. Therefore, the second gate signal from the second output terminal 5c3 is input to the third terminal 224c of the second switching element 22C3.

[0266] The ninth terminal 205 is electrically connected to the node 20b and is also electrically connected to the second reference potential input terminal 5g of the control signal generating circuit 5C.

[0267] The switch section 20C described in the fifth embodiment is the same as the switch section 20B according to the fourth embodiment, except that the first switching elements 21A1, 21A2, and 21A3 and the second switching elements 22C1, 22C2, and 22C3 are housed in a package 200. Furthermore, the control signal generating circuit 5C is also the same as that of the fourth embodiment. Therefore, the switch section 20C driven by the control signal generating circuit 5C has the same effects as those of the fourth embodiment.

[0268] The set of switch unit 20C and control signal generating circuit 5C can be applied to power conversion device 1 shown in Fig. 1 in place of control signal generating circuit 5 and switch unit 20. Power conversion device 1 in which the set of switch unit 20C and control signal generating circuit 5C is applied in place of the set of control signal generating circuit 5 and switch unit 20 also has the same effects as those of the fourth embodiment.

[0269] Sixth Embodiment A modified example of the drive circuit will be described as a sixth embodiment. Fig. 10 is a circuit diagram for explaining the sixth embodiment.

[0270] The control signal generating circuit 5D according to the sixth embodiment is a circuit for driving the switch section 20B described in the fourth embodiment. That is, the control signal generating circuit 5D is a modified example of the control signal generating circuit 5C.

[0271] The control signal generation circuit 5D differs from the control signal generation circuit 5C described in the fourth embodiment mainly in that a set of a first push-pull circuit and a first gate resistor is provided corresponding to each of the three first output terminals 5b1, 5b2, and 5b3, and a set of a second push-pull circuit and a second gate resistor is provided corresponding to each of the three second output terminals 5c1, 5c2, and 5c3. The configuration of the control signal generation circuit 5D other than the above differences is the same as that of the control signal generation circuit 5C, and therefore a description of the configuration of the control signal generation circuit 5D other than the above differences will be omitted.

[0272] The control signal generation circuit 5D has three first push-pull circuits 53a1, 53a2, and 53a3 for the AND circuit 161 of the logic synthesis unit 16. The configurations and functions of the first push-pull circuits 53a1, 53a2, and 53a3 are the same as those of the first push-pull circuit 53a described in the fourth embodiment (i.e., the first push-pull circuit 53a described in the first embodiment). Similar to the first push-pull circuit 53a in the first embodiment, each of the first push-pull circuits 53a1, 53a2, and 53a3 is connected between the second high potential line 57a and the second reference potential line 57b.

[0273] The first push-pull circuit 53a1 is electrically connected to the AND circuit 161. The first push-pull circuit 53a1 generates a first gate signal from the first control pulse signal input from the AND circuit 161. The first gate signal generated by the first push-pull circuit 53a1 is input to the first output terminal 5b1 via the first gate resistor 54a1.

[0274] The first push-pull circuit 53a2 is electrically connected to the AND circuit 161. The first push-pull circuit 53a2 generates a first gate signal from the first control pulse signal input from the AND circuit 161. The first gate signal generated by the first push-pull circuit 53a2 is input to the first output terminal 5b2 via the first gate resistor 54a2.

[0275] The first push-pull circuit 53a3 is electrically connected to the AND circuit 161. The first push-pull circuit 53a3 generates a first gate signal from the first control pulse signal input from the AND circuit 161. The first gate signal generated by the first push-pull circuit 53a3 is input to the first output terminal 5b3 via the first gate resistor 54a3.

[0276] The resistance values ​​of the first gate resistors 54a1, 54a2, and 54a3 are the same as those of the first gate resistor 54a in the fourth embodiment (i.e., the first gate resistor 54 in the first embodiment). The first gate resistors 54a1, 54a2, and 54a3 may be the same or different gate resistors.

[0277] The control signal generation circuit 5D has three second push-pull circuits 53b1, 53b2, and 53b3 for the OR circuit 162 of the logic synthesis unit 16. The configurations and functions of the second push-pull circuits 53b1, 53b2, and 53b3 are the same as those of the second push-pull circuit 53b described in the fourth embodiment (i.e., the second push-pull circuit 53b described in the first embodiment). Similar to the second push-pull circuit 53b in the first embodiment, each of the second push-pull circuits 53b1, 53b2, and 53b3 is connected between the second high potential line 57a and the second reference potential line 57b.

[0278] The second push-pull circuit 53b1 is electrically connected to the OR circuit 162. The second push-pull circuit 53b1 generates a second gate signal from the second control pulse signal input from the OR circuit 162. The second gate signal generated by the second push-pull circuit 53b1 is input to the second output terminal 5c1 via the second gate resistor 54b1.

[0279] The second push-pull circuit 53b2 is electrically connected to the OR circuit 162. The second push-pull circuit 53b2 generates a second gate signal from the second control pulse signal input from the OR circuit 162. The second gate signal generated by the second push-pull circuit 53b2 is input to the second output terminal 5c2 via the second gate resistor 54b2.

[0280] The second push-pull circuit 53b3 is electrically connected to the OR circuit 162. The second push-pull circuit 53b3 generates a second gate signal from the second control pulse signal input from the OR circuit 162. The second gate signal generated by the second push-pull circuit 53b3 is input to the second output terminal 5c3 via the second gate resistor 54b3.

[0281] The resistance values ​​of the second gate resistors 54b1, 54b2, and 54b3 are the same as those of the second gate resistor 54b in the fourth embodiment (i.e., the second gate resistor 54b in the first embodiment). The second gate resistors 54b1, 54b2, and 54b3 may be the same or different gate resistances.

[0282] As with the control signal generation circuit 5C, the control signal generation circuit 5D having the above configuration can output first gate signals from the three first output terminals 5b1, 5b2, and 5b3, and can output second gate signals from the three second output terminals 5c1, 5c2, and 5c3. Therefore, the control signal generation circuit 5D can drive the switch section 20B in the same way as the control signal generation circuit 5C. In other words, the control signal generation circuit 5D has the same effects as the control signal generation circuit 5C.

[0283] The set of switch unit 20B and control signal generating circuit 5D described in the sixth embodiment can be applied to power conversion device 1 shown in Fig. 1 in place of control signal generating circuit 5 and switch unit 20. Power conversion device 1 in which the set of switch unit 20B and control signal generating circuit 5D described in the sixth embodiment is applied in place of the set of control signal generating circuit 5 and switch unit 20 has the same effects as in the fourth embodiment.

[0284] A combination of a push-pull circuit and a gate resistor provided downstream of the signal generating section 52 (specifically, downstream of the logic synthesis section 16 ) functions as an amplifier for the control pulse signal generated by the signal generating section 52 .

[0285] In the configuration of the control signal generating circuit 5D, a pair of a push-pull circuit and a gate resistor is provided corresponding to each of the first switching elements 21A1, 21A2, and 21A3, and a pair of a push-pull circuit and a gate resistor is provided corresponding to each of the second switching elements 22C1, 22C2, and 22C3.

[0286] For example, control signal generating circuit 5D has a first push-pull circuit 53a1 and a first gate resistor 54a1 corresponding to first switching element 21A1, and a second push-pull circuit 53b1 and a second gate resistor 54b1 corresponding to second switching element 22C1. Although the correspondence has been described using first switching element 21A1 and second switching element 22C1 as an example, the same applies to first switching elements 21A2 and 21A3 and second switching elements 22C2 and 22C3.

[0287] Therefore, the configuration of control signal generation circuit 5D makes it possible to adjust the amplification factor when generating the first gate signal from the first control pulse signal in accordance with each of first switching elements 21A1, 21A2, and 21A3. Similarly, the configuration of control signal generation circuit 5D makes it possible to adjust the amplification factor when generating the second gate signal from the second control pulse signal in accordance with each of second switching elements 22C1, 22C2, and 22C3.

[0288] For example, in the control signal generation circuit 5D, when an insulated gate driver is arranged in the subsequent stage of the signal generation unit 52, it is conceivable to arrange an insulated gate driver in each of the first push-pull circuits 53a1, 53a2, 53a3 and the second push-pull circuits 53b1, 53b2, 53b3.

[0289] In contrast to this, in the control signal generation circuit 5D as well, the insulated gate driver 51 is provided in the stage preceding the signal generation unit 52. Therefore, the number of insulated gate drivers 51 included in the control signal generation circuit 5D can be significantly reduced.

[0290] 11 is a diagram for explaining a modification of the sixth embodiment. As shown in FIG. 11, the control signal generation circuit 5D can be applied to the switch unit 20C described in the fifth embodiment instead of the switch unit 20B.

[0291] Seventh Embodiment As the seventh embodiment, a modified example of the control signal generation circuit 5 will be described. Fig. 12 is a circuit diagram for explaining the seventh embodiment. The control signal generation circuit 5E shown in Fig. 12 has the same configuration as the control signal generation circuit 5, except that it includes a signal generation unit 52C instead of the signal generation unit 52. Therefore, a description of the configuration other than the point that it includes a signal generation unit 52C instead of the signal generation unit 52 will be omitted.

[0292] The signal generating unit 52C has a delay circuit 11E and a logic synthesis unit 16. The logic synthesis unit 16 is the same as in the first embodiment, and therefore a description of the logic synthesis unit 16 will be omitted.

[0293] The delay circuit 11E is electrically connected to the insulated gate driver 51. The delay circuit 11E generates a delay signal that is delayed with respect to the control pulse signal input from the insulated gate driver 51. The delay circuit 11E is electrically connected to the logic synthesis unit 16. The delay circuit 11E inputs the generated delay signal to the logic synthesis unit 16.

[0294] The delay circuit 11E is composed of a resistor 132c and a capacitor 15c. An example of the resistance value of the resistor 132c is the same as that of the first resistor 132 in the first embodiment. An example of the capacitance of the capacitor 15c is the same as that of the capacitor 15 in the first embodiment.

[0295] A first end of the resistor 132c is electrically connected to the output terminal 51b, and a second end (opposite to the first end) of the resistor 132c is electrically connected to a first end of the capacitor 15c. The second end (opposite to the first end) of the capacitor 15c is electrically connected to the first reference potential line 56b. A node between the resistor 132c and the capacitor 15c is electrically connected to an AND circuit 161 and an OR circuit 162.

[0296] In the delay circuit 11E, a delay signal is generated in which the rising and falling edges of the control pulse signal are delayed by a delay time determined by the resistance value of resistor 132c and the capacitance of capacitor 15c. In the delay circuit 11E, the delay times for the rising and falling edges of the control pulse signal are the same. In other words, the delay circuit 11E does not have the function of individually adjusting the delay time for the rising edge and the delay time for the falling edge of the control pulse signal. The delayed pulse signal generated by the delay circuit 11E is input to an AND circuit 161 and an OR circuit 162.

[0297] The signal generating unit 52C is the same as the signal generating unit 52 according to the first embodiment, except that it uses a delay circuit 11E instead of the delay circuit 11. Therefore, like the signal generating unit 52, the signal generating unit 52C can generate different first and second control pulse signals from a single input pulse signal (control pulse signal).

[0298] The control signal generation circuit 5E is the same as the control signal generation circuit 5 according to the first embodiment, except that it uses a signal generation unit 52C instead of the signal generation unit 52. Therefore, like the control signal generation circuit 5, the control signal generation circuit 5E can generate a first gate signal from the first control pulse signal generated by the signal generation unit 52C, and generate a second gate signal from the second control pulse signal. Furthermore, in the control signal generation circuit 5E, the isolated gate driver 51 is also arranged upstream of the signal generation unit 52. Therefore, the effects of the control signal generation circuit 5E are similar to those of the signal generation unit 52 and control signal generation circuit 5 according to the first embodiment.

[0299] The effects of driving the switch unit 20 by the control signal generating circuit 5E and the effects of the power conversion device 1 in which the set of the control signal generating circuit 5E and the switch unit 20 is applied instead of the set of the control signal generating circuit 5 and the switch unit 20 shown in FIG. 1 are the same as those in the first embodiment.

[0300] The delay circuit 11E has a simpler configuration than, for example, the delay circuit 11 described in the first embodiment. Therefore, if there is no need to individually adjust the delay times of the rising and falling edges of the control pulse signal, the control signal generation circuit 5C can be easily manufactured by employing the delay circuit 11E.

[0301] Eighth Embodiment As an eighth embodiment, a configuration example of a vehicle X to which the power conversion device 1 shown in Fig. 1 is applied will be described. Fig. 13 is a diagram showing a configuration example of a vehicle on which the power conversion device 1 is mounted.

[0302] The vehicle X includes an engine unit 81 with a generator, an ECU 82, a high-power DC / DC converter 83, a power conversion device 1, a motor 2, a drive device 84, a high-voltage battery 85, a DC / DC converter 86, and a power supply 87. For convenience of illustration, the mounting positions of the components in Fig. 13 differ from the actual positions. The vehicle X shown in Fig. 13 is a so-called series hybrid vehicle.

[0303] The generator-equipped engine section 81 includes a generator, a dedicated engine for generating electricity that drives the generator, and an engine ignition device 81a. Because the energy conversion efficiency of the engine varies greatly depending on the timing of ignition, the ignition timing must be controlled by the ECU 82 in consideration of the rotation angle of the crank that converts the reciprocating motion of the pistons in the cylinders into rotational motion and the required amount of electricity generation. For this reason, an engine ignition device 81a is provided for each cylinder of the engine.

[0304] The high-power DC / DC converter 83 converts DC power generated by the generator of the generator-equipped engine unit 81 into high-voltage DC power. The high-power DC / DC converter 83 supplies the high-voltage DC power to the power conversion device 1 and the high-voltage battery 85. The high-power DC / DC converter 83 can supply discharge power discharged from the high-voltage battery 85 to the power conversion device 1. The high-power DC / DC converter 83 can also charge the high-voltage battery 85 with regenerative power supplied from the power conversion device 1 when the vehicle X decelerates. Therefore, the high-power DC / DC converter 83, or the high-power DC / DC converter 83 and the high-voltage battery 85, function as the DC power supply unit 3 shown in FIG. 1 .

[0305] The power conversion device 1 receives DC power from a high-power DC / DC converter 83 and converts the received DC power into three-phase AC power. The power conversion device 1 is controlled by an ECU 82. Therefore, the ECU 82 functions as the external control device 7 shown in FIG. 1 . FIG. 15 schematically illustrates an example configuration of a vehicle X to which the power conversion device 1 is applied, and therefore illustrates a generator-equipped engine unit 81 and a high-power DC / DC converter 83 interposed between the ECU 82 and the power conversion device 1. However, the ECU 82 only needs to be electrically connected to the control signal generating circuit 5 (see FIG. 1 ) of the power conversion device 1 so that an input pulse signal generated by the ECU 82 is supplied to the control signal generating circuit 5 (see FIG. 1 ) included in the power conversion device 1. Therefore, the input pulse signal may be supplied from the ECU 82 to the power conversion device 1 using a communication line common to the generator-equipped engine unit 81, etc., or the input pulse signal may be supplied from the ECU 82 to the power conversion device 1 via a communication line independent of the generator-equipped engine unit 81, etc.

[0306] The motor 2 has a shaft and rotates the shaft using three-phase AC power supplied from the power conversion device 1 .

[0307] The drive device 84 transmits power generated by the rotation of the shaft of the motor 2 to the drive wheels of the vehicle X. In Fig. 13, the rear wheels of the vehicle X are the drive wheels, but the drive wheels are not limited to the rear wheels. In other words, the front wheels may be the drive wheels, or both the front and rear wheels may be the drive wheels.

[0308] The DC / DC converter 86 receives DC power from the high-power DC / DC converter 83 and converts the received DC power into low-voltage DC power. The power supply 87, which is a low-voltage battery, is charged with the low-voltage DC power output from the DC / DC converter 86. The discharge power discharged from the power supply 87 is supplied to the engine ignition device 81 a and the like.

[0309] The vehicle on which the power conversion device 1 according to the embodiment is mounted is not limited to a hybrid vehicle such as the vehicle X shown in FIG. 13, but may be any vehicle equipped with an engine.

[0310] According to the embodiment described above, it is possible to provide a technique that can generate a first control pulse signal and a second control pulse signal for controlling two switching elements with different characteristics from a single input pulse signal.

[0311] Various embodiments relating to one aspect of the present disclosure have been described above, but these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0312] The switch unit may include elements other than the first switching element and the second switching element. For example, as in a switch unit 20D shown in Fig. 14, a freewheeling diode 24 may be connected in parallel to the first switching element 21 and the second switching element 22 between the node 20a and the node 20b. Alternatively, as in a switch unit 20E shown in Fig. 15, a Schottky barrier diode 25 may be connected in parallel to the first switching element 21 and the second switching element 22 between the node 20a and the node 20b.

[0313] The delay signal generating unit is configured to generate at least one delay pulse signal using a common control pulse signal for a first switching element and a second switching element that have different transition times between an on state, which is a conductive state, and an off state, which is a non-conductive state, and the logic synthesis unit is configured to generate a first control pulse signal for the first switching element and a second control pulse signal for the second switching element by performing different logic synthesis on two signal sets out of a plurality of signal sets defined by the at least one delay pulse signal and the input pulse signal.

[0314] In this case, different logical synthesis is performed on two of the multiple signal sets defined by at least one delay pulse signal and a control pulse signal, so that different first and second control pulse signals can be generated from one control pulse signal.

[0315] Examples of the multiple signal sets defined by at least one delay pulse signal and a control pulse signal include a signal set of a delay pulse signal and a control pulse signal, two identical delay pulse signals, and two control pulse signals. When the delay signal generating unit generates delay pulse signals with different delay states, different delay pulse signals may be adopted as a signal set.

[0316] The logic synthesis unit may be configured to generate a second control pulse signal based on the set of a delay pulse signal and a control pulse signal or a set of delay pulse signals when generating a first control pulse signal based on a set of delay pulse signals and a control pulse signal, and may be configured to generate a second control pulse signal based on the set of delay pulse signals and a control pulse signal when generating a first control pulse signal based on a set of delay pulse signals.

[0317] The logical synthesis may be a logical NOT in addition to the logical AND, OR, and EXCLUSIVE OR shown above. For example, if the characteristics of the circuit used require inverting the logical state of the delayed pulse signal, the logical NOT can be used. Therefore, the logical synthesis unit may include at least two of an AND circuit, an OR circuit, an XOR circuit, and a NOT circuit, for example.

[0318] From the viewpoint of utilizing the high-speed switching characteristics of the SiC-MOSFET for turning on and off the switch section, the case where the first switching element is an SiC-IGBT and the second switching element is an SiC-MOSFET has been described. However, the first switching element may be an SiC-MOSFET and the second switching element may be an Si-IGBT.

[0319] When the delay circuit included in the delayed signal generating section includes a parallel circuit together with a capacitor, the parallel circuit may be a series circuit of a diode and a resistor, and a parallel circuit of a resistor, as illustrated.

[0320] In the various exemplary embodiments, examples have been described in which a push-pull circuit is arranged downstream of the signal generating unit, but the control signal generating circuit may also be configured to output the first control pulse signal and the second control pulse signal generated by the signal generating unit from the control signal generating circuit.

[0321] The control signal generation circuit may be configured as a module in which the isolated gate driver and the signal generation unit are housed in a package, or may be an unpackaged circuit in which the isolated gate driver and the signal generation unit are mounted on a single circuit board.

[0322] In the various embodiments (including modified examples) described above, one or more elements of one embodiment may be combined with one or more elements of another embodiment.

[0323] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0324] [A1] (First embodiment, FIG. 2) A signal generation circuit comprising: an isolation circuit (51) having insulation between an input terminal (51a) and an output terminal (51b), the isolation circuit (51) being configured to output, from the output terminal, a control pulse signal corresponding to an input pulse signal input to the input terminal that is common to a first switching element (21) and a second switching element (22) having different transition times between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state; a delay signal generation unit (10) configured to generate at least one delay pulse signal using the control pulse signal; and a logic synthesis unit (16) configured to generate a first control pulse signal for the first switching element and a second control pulse signal for the second switching element by performing different logic synthesis on two signal sets out of a plurality of signal sets defined by the at least one delay pulse signal and the control pulse signal, wherein the first control pulse signal is different from the input pulse signal, and the second control pulse signal is different from the input pulse signal and the first control pulse signal.

[0325] [A2] (First to Sixth Embodiments) The control signal generating circuit according to [A1], wherein the control pulse signal is the same signal as the input pulse signal.

[0326] [A3] (First to sixth embodiments, FIGS. 2, 6, 8 to 12) The control signal generation circuit according to [A1] or [A2], further comprising a step-down circuit (55) that converts a first voltage potential supplied from an external power supply (62) into a second voltage potential to be supplied to the logic synthesis unit.

[0327] [A4] (First to Sixth Embodiments) The control signal generating circuit according to any one of [A1] to [A3], wherein the second switching element is a switching element whose transition time is shorter than that of the first switching element.

[0328] [A5] (First to sixth embodiments, FIGS. 2, 6, 8 to 11) The control signal generation circuit according to any one of [A1] to [A4], wherein the first switching elements (21, 21A1 to 21A3) are insulated gate bipolar transistors, and the second switching elements (22, 22A, 22B, 22C1 to 22C3) are metal oxide semiconductor field effect transistors.

[0329] [A6] (First to Seventh Embodiments, FIGS. 2, 6, 8 to 12) The control signal generation circuit according to any one of [A1] to [A5], wherein the delay signal generation unit has at least one delay circuit (11, 11E) including a resistor (132, 132a to 132c, 142, 142a, 142b) and a capacitor (15, 15a to 15c).

[0330] [A7] (First to sixth embodiments, FIGS. 2, 6, 8 to 11) The control signal generation circuit according to any one of [A1] to [A6], wherein the delay signal generation unit has at least one delay circuit (11), and the delay circuit has: a resistance unit (12, 12A to 12D) having two signal paths connected in parallel and configured to have resistances (132, 132a, 132b, 142, 142a, 142b) for delaying the rising edge and for delaying the falling edge of the pulse of the control pulse signal; and a capacitor (15, 15a, 15b).

[0331] [A8] (First embodiment, second embodiment, FIGS. 2 and 4) The control signal generation circuit according to any one of [A1] to [A7], wherein the logic synthesis unit (16, 16A) has at least two of an AND circuit (161), an OR circuit (162), and an XOR circuit (163) to perform different logic synthesis.

[0332] [A9] (First embodiment, FIG. 3) The control signal generation circuit according to any one of [A1] to [A8], wherein the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal such that the second switching element is turned on before the first switching element is turned on, and the second switching element is turned off after the first switching element is turned off.

[0333] [A10] (Second embodiment, FIG. 5) The control signal generation circuit according to any one of [A1] to [A8], wherein the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal so that the first switching element is turned on in a first on state of the two on states of the second switching element, and the first switching element is turned off in a second on state of the two on states of the second switching element that is subsequent to the first on state.

[0334] [A11] (First embodiment, second embodiment, FIGS. 2 and 4) The control signal generation circuit according to any of [A1] to [A10], wherein the delay signal generation unit (10, 10A) has a delay circuit (11, 11A) that generates the delay pulse signal, and the two signal sets are a set of the delay pulse signal and the control pulse signal or a set of the delay pulse signals themselves, and the logic synthesis unit (16, 16A) is configured to: when generating the first control pulse signal based on the set of the delay pulse signal and the control pulse signal, generate the second control pulse signal based on the set of the delay pulse signal and the control pulse signal or the set of the delay pulse signals themselves, and when generating the first control pulse signal based on the set of the delay pulse signals themselves, generate the second control pulse signal based on the set of the delay pulse signal and the control pulse signal.

[0335] [A12] (First embodiment, FIG. 2) The control signal generation circuit according to [A11], comprising: a first input terminal (5g) to which a reference potential is supplied; the delay circuit (11) having a first end (12a) to which the control pulse signal is input and a second end (12b) electrically connected to the logic synthesis unit, a parallel circuit (12) in which a first series circuit (13) of a first diode (131) and a first resistor (132) and a second series circuit (14) of a second diode (141) and a second resistor (142) are connected in parallel; and a first capacitor (15) electrically connected between the second end and the first input terminal, wherein an anode of the first diode is electrically connected to the first end, the first resistor is disposed between a cathode of the first diode and the second end, the cathode of the second diode is electrically connected to the second end, and the second resistor is disposed between an anode of the second diode and the first end.

[0336] [A13] (First embodiment, FIG. 2) The control signal generation circuit according to [A11] or [A12], wherein the logic synthesis unit (16) has: an AND circuit (161) that receives the delay pulse signal and the control pulse signal as inputs and outputs the first control pulse signal; and an OR circuit (162) that receives the delay pulse signal and the control pulse signal as inputs and outputs the second control pulse signal.

[0337] [A14] (Second embodiment, FIG. 4) The control signal generation circuit according to any one of [A1] to [A8] and [A10], wherein the delay signal generation unit (10A) has: a first delay circuit (11A) that generates a first delay pulse signal; and a second delay circuit (11B) that generates a second delay pulse signal different from the first delay pulse signal; and the logic synthesis unit (16A) generates the first control pulse signal based on a set of the first delay pulse signals, and generates the second control pulse signal based on a set of the second delay pulse signal and the control pulse signal.

[0338] [A15] (Second embodiment, FIG. 4) A first delay circuit includes a first input terminal (5g) to which a reference potential is supplied, the first delay circuit having a first end (12c) to which the control pulse signal is input and a second end (12d) electrically connected to the logic synthesis unit, the first parallel circuit (12A) including a first series circuit (13A) of a first diode (131a) and a first resistor (132a) and a second series circuit (14A) of a second diode (141a) and a second resistor (142a) connected in parallel, and a first capacitor (15a) electrically connected between the second end and the first input terminal, wherein an anode of the first diode is connected to the first end, the first resistor is disposed between a cathode of the first diode and the second end, the anode of the second diode is connected to the second end, and the second resistor is disposed between a cathode of the second diode and the first end, the second delay circuit (11B) has a third terminal (12e) to which the control pulse signal is input and a fourth terminal (12f) electrically connected to the logic synthesis unit, and has a second parallel circuit (12B) in which a third series circuit (13B) of a third diode (131b) and a third resistor (132b) and a fourth series circuit (14B) of a fourth diode (141b) and a fourth resistor (142b) are connected in parallel, and a second capacitor (15b) electrically connected between the fourth terminal and a first input terminal, wherein an anode of the third diode is connected to the third terminal, the third resistor is disposed between a cathode of the third diode and the fourth terminal, an anode of the fourth diode is connected to the fourth terminal, and the fourth resistor is disposed between a cathode of the fourth diode and the third terminal.

[0339] [A16] (Second embodiment, FIG. 4) The control signal generation circuit according to [A14] or [A15], wherein the logic synthesis unit (16) has: an AND circuit (161) that receives the two first delay pulse signals as inputs and outputs the first control pulse signal; and an XOR circuit (163) that receives the second delay pulse signal and the control pulse signal as inputs and outputs the second control pulse signal.

[0340] [A17] (Third embodiment, FIG. 6) The delay signal generating unit (10B) is configured to generate a first delay pulse signal for the first switching element and two second delay pulse signals for the two second switching elements (22A, 22B), The logic synthesis unit (16B) is configured to generate the first control pulse signal and the two second control pulse signals for the two second switching elements by performing logic synthesis on three signal sets out of the plurality of signal sets defined by the first delay pulse signal, the two second delay pulse signals, and the control pulse signal, The logic synthesis unit performs different logic synthesis on at least two of the three signal sets, A second a delay pulse signal out of the two second delay pulse signals is different from the first delay pulse signal and is a signal for a second a switching element out of the two second switching elements, the 2b delay pulse signal of the two second delay pulse signals is different from the first delay pulse signal and the 2a delay pulse signal and is a signal for the 2b switching element of the two second switching elements; the 2a control pulse signal of the two second control pulse signals is a signal for the 2a switching element; the 2b control pulse signal of the two second control pulse signals is a signal for the 2b switching element; the 2a control pulse signal and the 2b control pulse signal are signals for controlling the 2a switching element and the 2b switching element such that an on-state period of the 2a switching element and the 2b switching element is shorter than an on-state period of the first switching element and such that an on-state period of the 2b switching element occurs after an on-state period of the 2a switching element; the first control pulse signal is a signal for controlling the first switching element so as to transition the first switching element from an off state to an on state during a period in which the second a switching element is in an on state, and to transition the first switching element from an on state to an off state during a period in which the second b switching element is in an on state.A control signal generating circuit according to any one of [A1] to [A8] and [A10].

[0341] [A18] (Third embodiment, FIG. 6) A control signal generating unit (10B) includes a first input terminal (5g) to which a reference potential is supplied, wherein the delay signal generating unit (10B) includes: a first delay circuit (11A) that generates the first delay pulse signal; a 2a delay circuit (11C) that generates the 2a delay pulse signal; and a 2b delay circuit (11D) that generates the 2b delay pulse signal, wherein the first delay circuit includes: a first terminal (12c) to which the control pulse signal is input and a second terminal (12d) electrically connected to the logic synthesis unit, and a first parallel circuit (12A) in which a first series circuit (13A) of a first diode (131a) and a first resistor (132a) and a second series circuit (14A) of a second diode (141a) and a second resistor (142a) are connected in parallel; and a first capacitor (15a) electrically connected between the second terminal and the first input terminal, the anode of the first diode is connected to the first end, the first resistor is arranged between the cathode of the first diode and the second end, the cathode of the second diode is connected to the second end, and the second resistor is arranged between the anode of the second diode and the first end, the 2a delay circuit has a 3a end (121a) to which the control pulse signal is input and a 3b end (121b) electrically connected to the logic synthesis unit, and has a 2a parallel circuit (12C) in which a 3a series circuit (13B) of a 3a diode (131b) and a 3a resistor (132b) and a 3b diode (141b) are connected in parallel, and a 2a capacitor (15b) electrically connected between the 3b end and the first input terminal, the anode of the 3a diode is connected to the 3a end, and the 3a resistor is arranged between the cathode of the 3a diode and the 3b end, The cathode of the 3b diode is connected to the 3a terminal, and the anode of the 3b diode is connected to the 3b terminal; and the 2b delay circuit isa 3d terminal (122b) electrically connected to the logic synthesis unit, a 3b series circuit (14B) of a 3c diode (141b) and a 3b resistor (142b) and a 2b parallel circuit (12D) in which a 3d diode (131b) is connected in parallel with a 3b series circuit (14B) of a 3c diode (141b) and a 3b resistor (142b); a 2b capacitor (15b) electrically connected between the 3d terminal and the first input terminal, wherein an anode of the 3d diode is connected to the 3c terminal and a cathode of the 3d diode is connected to the 3d terminal, an anode of the 3c diode is connected to the 3d terminal, and the 3b resistor is arranged between the cathode of the 3c diode and the 3c terminal.

[0342] [A19] (Third embodiment, FIG. 6) The control signal generating circuit according to [A17] or [A18], wherein the logic synthesis unit (16B) has: an AND circuit (161) that receives the first delay pulse signal and the control pulse signal as inputs and outputs the first control pulse signal; a first XOR circuit (163a) that receives the 2a delay pulse signal and the control pulse signal as inputs and outputs the 2a control pulse signal; and a second XOR circuit (163b) that receives the 2b delay pulse signal and the control pulse signal as inputs and outputs the 2b control pulse signal.

[0343] [A20] (First to Seventh Embodiments, FIGS. 2, 6, 8 to 12) The control signal generation circuit according to [A1] to [A19], comprising: a first push-pull circuit (53a, 53a1 to 53a3) driven by the first control pulse signal to generate a first drive pulse signal for driving the first switching element; and a second push-pull circuit (53b, 53b1 to 53b3) driven by the second control pulse signal to generate a second drive pulse signal for driving the second switching element.

[0344] [A21] (First to Seventh Embodiments, FIGS. 2, 6, 8 to 12) The control signal generation circuit according to [A20], comprising: a first input terminal (5g) to which a reference potential is supplied; a second input terminal (5f) to which a first voltage potential higher than the reference potential is supplied; and a voltage step-down circuit (55) that steps down the first voltage potential supplied to the second input terminal to a second voltage potential higher than the reference potential and to be supplied to the logic synthesis unit, wherein a high potential end (531a) of the first push-pull circuit is electrically connected to the second input terminal, and a low potential end of the first push-pull circuit is electrically connected to the first input terminal; and a high potential end of the second push-pull circuit is electrically connected to the second input terminal, and a low potential end of the second push-pull circuit is electrically connected to the first input terminal.

[0345] [A22] (FIG. 1) A power conversion device comprising: an inverter circuit (4) in which two switch units, which are switched between an on state that is a conductive state and an off state that is a non-conductive state, have at least one leg (41u, 41v, 41w) connected in series between a high potential line (6a) and a low potential line (6b), and connection points (42u, 42v, 42w) of the two switch units are AC input / output points; and a control signal generation circuit according to any one of [A1] to [A18] provided for each of the two switch units, wherein each of the two switch units has: the first switching element (21); and the second switching element (22) connected in parallel with the first switching element.

[0346] [A23] (Eighth embodiment, FIG. 13) A vehicle comprising: the power conversion device according to [A22]; and a motor driven by the power conversion device.

[0347] REFERENCE SIGNS LIST 1... Power conversion device 2... Motor 3... DC power supply unit 4... Inverter circuit 5, 5A, 5B, 5C, 5D, 5E... Control signal generation circuit 5a... Input terminal 5b, 5b1, 5b2, 5b3... First output terminal 5c, 5c1, 5c2, 5c3... Second output terminal 5d... First high potential input terminal 5e... First reference potential input terminal 5f... Second high potential input terminal (second input terminal) 5g... Second reference potential input terminal (first input terminal) 6a... High potential line 6b... Low potential line 7... External control device 10, 10A, 10B... Delay signal generation unit 11... Delay circuit 11A... First delay circuit 11B... Second delay circuit 11C... 2a delay circuit 11D... 2b delay circuit 11E... Delay circuit 12... Parallel circuit (resistance unit) 12A...First parallel circuit (resistance section) 12B...Second parallel circuit (resistance section) 12C...2a parallel circuit 12D...2b parallel circuit 12a...Node (first end) 12b...Node (second end) 12c...Node (first end) 12d...Node (second end) 12e...Node (third end) 12f...Node (fourth end) 13...First series circuit 13A...First series circuit 13B...Third series circuit (3a series circuit) 14...Second series circuit 14A...Second series circuit 14B...Fourth series circuit (3b series circuit) 15...Capacitor 15a...First capacitor 15b...Second capacitor (2a capacitor, 2b capacitor) 15c...Capacitor 16, 16A, 16B...Logic synthesis section 20A, 20B, 20C, 20D... Switch section 20a, 20b... Node 21, 21A1, 21A2, 21A3... First switching element 22... Second switching element 22A... 2a-th switching element 22B... 2b-th switching element 22C1, 22C2, 22C3... Second switching element 23, 24... Freewheeling diode 25... Schottky barrier diode 41u, 41v, 41w... Leg 42u, 42v, 42w... Node (connection point) 43... Capacitor 51... Insulated gate driver (insulation circuit) 51a... Input terminal (input end) 51b... Output terminal (output end) 52, 52A, 52B, 52C... Signal generation section 53a, 53a1, 53a, 53a3... First push-pull circuit 53b, 53b1, 53b2, 53b3... second push-pull circuit 54a. 54a1, 54a2, 54a3... first gate resistors 54b, 54b1, 54b2,54b3...Second gate resistor 55...Step-down circuit 56a...First high potential line 56b...First reference potential line 57a...Second high potential line 57b...Second reference potential line 61, 62...External power supply 63...Reference potential wiring 81...Engine section with generator 81a...Engine ignition device 82...ECU 83...High power DC / DC converter 84...Drive device 85...High voltage battery 86...DC / DC converter 87...Power supply 121a...Node (3a terminal) 121b...Node (3b terminal) 122a...Node (3c terminal) 122b...Node (3d terminal) 131...First diode 131a...First diode 131b...Third diode (3a diode, 3c diode)) 132...First resistor 132a...First resistor 132b...Third resistor (3a-th resistor) 132c...Resistor 141...Second diode 141a...Second diode 141b...Fourth diode (3b-th diode, 3d-th diode) 142...Second resistor 142a...Second resistor 142b...Fourth resistor (3b-th resistor) 161...AND circuit 162...OR circuit 163a...First XOR circuit 163b...Second XOR circuit 200...Package 201...First terminal 202...Second terminal 203a...Third terminal 203b...Fourth terminal 203c...Fifth terminal 204a...Sixth terminal 204b...Seventh terminal 204c...Eighth terminal 205...Ninth terminal 212...Package 213a...First terminal 213b...Second terminal 213c...Third terminal 222...Freewheeling diode 223...Package 224a...First terminal 224b...Second terminal 224c...Third terminal 531a, 532a...High potential terminal 531b, 532b...Low potential terminal S0...Input pulse signal S1...Control pulse signal S2...Delay pulse signal S2a...First delay pulse signal S2b1...Second a delay pulse signal S2b2...Second b delay pulse signal S3...First control pulse signal S4...Second control pulse signal S4a...Second a control pulse signal S4b...Second b control pulse signal td1...Delay time Td1, ＯＦＦ ...Delay time Td1 ＯＮ ...Delay time td2...Delay time Td2 ＯＦＦ ...Delay time Td2 ＯＮ ...delay time Tr1...first transistor Tr2...second transistor V ＩＨ ...Threshold voltage V ＩＬ...Threshold voltage X...Vehicle

Claims

an isolation circuit configured to have an input terminal and an output terminal electrically isolated from each other, and to output from the output terminal a control pulse signal corresponding to an input pulse signal input to the input terminal, the input pulse signal being common to a first switching element and a second switching element having different transition times between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state; a delay signal generator configured to generate at least one delay pulse signal using the control pulse signal; a logic synthesis unit configured to generate a first control pulse signal for the first switching element and a second control pulse signal for the second switching element by performing different logic synthesis on two signal sets among a plurality of signal sets defined by at least one of the delay pulse signal and the control pulse signal; Equipped with the first control pulse signal is different from the control pulse signal; the second control pulse signal is different from the control pulse signal and the first control pulse signal; Control signal generation circuit. 　 the control pulse signal is the same signal as the input pulse signal; 2. The control signal generating circuit according to claim 1. 　 a step-down circuit that converts a first voltage potential supplied from an external power supply into a second voltage potential to be supplied to the logic synthesis unit; 3. The control signal generating circuit according to claim 1. 　 the second switching element is a switching element whose transition time is shorter than that of the first switching element; 4. The control signal generating circuit according to claim 1. 　 the first switching element is an insulated gate bipolar transistor, the second switching element is a metal oxide semiconductor field effect transistor; 5. The control signal generating circuit according to claim 1. 　 the delay signal generating unit has at least one delay circuit including a resistor and a capacitor; 6. The control signal generating circuit according to claim 1. 　 the delay signal generating unit has at least one delay circuit, The delay circuit a resistor section having two signal paths connected in parallel and configured to have resistances for delaying the rising edge and the falling edge of the pulse of the control pulse signal; A capacitor; having 7. The control signal generating circuit according to claim 1. 　 the logic synthesis unit has at least two of an AND circuit, an OR circuit, and an XOR circuit to perform different logic synthesis; 8. The control signal generating circuit according to claim 1. 　 the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal so that the second switching element is turned on before the first switching element is turned on and the second switching element is turned off after the first switching element is turned off.

9. The control signal generating circuit according to claim 1. 　 the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal so that the first switching element is turned on in a first on state of the two on states of the second switching element, and so that the first switching element is turned off in a second on state of the two on states of the second switching element that is subsequent to the first on state.

9. The control signal generating circuit according to claim 1. 　 the delay signal generating unit has a delay circuit that generates the delay pulse signal, the two signal sets are a set of the delay pulse signal and the control pulse signal or a set of the delay pulse signals; The logic synthesis unit When the first control pulse signal is generated based on the set of the delay pulse signal and the control pulse signal, the second control pulse signal is generated based on the set of the delay pulse signal and the control pulse signal or the set of the delay pulse signals themselves, When the first control pulse signal is generated based on the set of the delay pulse signals, the second control pulse signal is generated based on the set of the delay pulse signal and the control pulse signal.

11. The control signal generating circuit according to claim 1. 　 a first input terminal to which a reference potential is supplied; The delay circuit a parallel circuit having a first terminal to which the control pulse signal is input and a second terminal electrically connected to the logic synthesis unit, in which a first series circuit of a first diode and a first resistor and a second series circuit of a second diode and a second resistor are connected in parallel; a first capacitor electrically connected between the second end and the first input terminal; and the anode of the first diode is electrically connected to the first end; the first resistor is disposed between the cathode of the first diode and the second end; the cathode of the second diode is electrically connected to the second end; the second resistor is disposed between the anode of the second diode and the first end; 12. The control signal generating circuit according to claim 11. 　 The logic synthesis unit an AND circuit that receives the delay pulse signal and the control pulse signal as inputs and outputs the first control pulse signal; an OR circuit that receives the delay pulse signal and the control pulse signal as inputs and outputs the second control pulse signal; having 13. The control signal generating circuit according to claim 11 or 12. 　 The delay signal generation unit a first delay circuit that generates a first delayed pulse signal; a second delay circuit that generates a second delay pulse signal different from the first delay pulse signal; and The logic synthesis unit generating the first control pulse signal based on the set of the first delay pulse signals, and generating the second control pulse signal based on the set of the second delay pulse signal and the control pulse signal; 11. The control signal generating circuit according to claim 1. 　 a first input terminal to which a reference potential is supplied; The first delay circuit a first parallel circuit having a first terminal to which the control pulse signal is input and a second terminal electrically connected to the logic synthesis unit, in which a first series circuit of a first diode and a first resistor and a second series circuit of a second diode and a second resistor are connected in parallel; a first capacitor electrically connected between the second end and the first input terminal; and The anode of the first diode is connected to the first end, the first resistor is disposed between the cathode of the first diode and the second end; The anode of the second diode is connected to the second end, the second resistor is disposed between the cathode of the second diode and the first end; The second delay circuit a second parallel circuit having a third terminal to which the control pulse signal is input and a fourth terminal electrically connected to the logic synthesis unit, in which a third series circuit of a third diode and a third resistor and a fourth series circuit of a fourth diode and a fourth resistor are connected in parallel; a second capacitor electrically connected between the fourth end and a first input terminal; and The anode of the third diode is connected to the third terminal, the third resistor is disposed between the cathode of the third diode and the fourth terminal, the anode of the fourth diode is connected to the fourth end; the fourth resistor is disposed between the cathode of the fourth diode and the third terminal; 15. The control signal generating circuit according to claim 14. 　 The logic synthesis unit an AND circuit that receives the two first delay pulse signals as inputs and outputs the first control pulse signal; an XOR circuit that receives the second delay pulse signal and the control pulse signal as inputs and outputs the second control pulse signal; having 16. The control signal generating circuit according to claim 14 or 15. 　 the delay signal generating unit is configured to generate a first delay pulse signal for the first switching element and two second delay pulse signals for the two second switching elements; the logic synthesis unit is configured to generate the first control pulse signal and the two second control pulse signals for the two second switching elements by performing logic synthesis on three of the plurality of signal sets defined by the first delay pulse signal, the two second delay pulse signals, and the control pulse signal; the logic synthesis unit performs different logic synthesis on at least two of the three signal sets; a second-a delay pulse signal of the two second delay pulse signals is different from the first delay pulse signal and is a signal for a second-a switching element of the two second switching elements; a 2b delay pulse signal of the two second delay pulse signals is different from the first delay pulse signal and the 2a delay pulse signal and is a signal for a 2b switching element of the two second switching elements, a second-a control pulse signal of the two second control pulse signals is a signal for the second-a switching element, a second-b control pulse signal of the two second control pulse signals is a signal for the second-b switching element, the second-a control pulse signal and the second-b control pulse signal are signals for controlling the second-a switching element and the second-b switching element such that an on-state period of the second-a switching element and the second-b switching element is shorter than an on-state period of the first switching element, and such that an on-state period of the second-b switching element occurs after an on-state period of the second-a switching element, the first control pulse signal is a signal for controlling the first switching element so as to transition the first switching element from an off state to an on state during a period in which the second a switching element is in an on state, and to transition the first switching element from an on state to an off state during a period in which the second b switching element is in an on state.

11. The control signal generating circuit according to claim 1. 　 a first input terminal to which a reference potential is supplied; The delay signal generation unit a first delay circuit that generates the first delayed pulse signal; a 2a delay circuit for generating the 2a delay pulse signal; a second b delay circuit that generates the second b delayed pulse signal; and The first delay circuit a first parallel circuit having a first terminal to which the control pulse signal is input and a second terminal electrically connected to the logic synthesis unit, in which a first series circuit of a first diode and a first resistor and a second series circuit of a second diode and a second resistor are connected in parallel; a first capacitor electrically connected between the second end and the first input terminal; and The anode of the first diode is connected to the first end, the first resistor is disposed between the cathode of the first diode and the second end; The cathode of the second diode is connected to the second end, the second resistor is disposed between the anode of the second diode and the first end; The 2a delay circuit is a second-a parallel circuit having a third-a terminal to which the control pulse signal is input and a third-b terminal electrically connected to the logic synthesis unit, the second-a parallel circuit being formed by connecting a third-a series circuit of a third-a diode and a third-a resistor in parallel with a third-b diode; a second capacitor electrically connected between the third terminal and the first input terminal; and the anode of the 3a diode is connected to the 3a end; the 3a resistor is disposed between the cathode of the 3a diode and the 3b terminal; a cathode of the 3b diode connected to the 3a end and an anode of the 3b diode connected to the 3b end; The second delay circuit is a second b parallel circuit having a third c terminal to which the control pulse signal is input and a third d terminal electrically connected to the logic synthesis unit, the second b parallel circuit being formed by connecting a third b series circuit of a third c diode and a third b resistor in parallel with a third d diode; a second capacitor electrically connected between the third terminal and the first input terminal; and an anode of the 3d diode is connected to the 3c end, and a cathode of the 3d diode is connected to the 3d end; the anode of the third diode c is connected to the third terminal d; the third b resistor is disposed between the cathode of the third c diode and the third c terminal; 18. The control signal generating circuit according to claim 17. 　 The logic synthesis unit an AND circuit that receives the first delay pulse signal and the control pulse signal and outputs the first control pulse signal; a first XOR circuit that receives the second a-th delay pulse signal and the control pulse signal as inputs and outputs the second a-th control pulse signal; a second XOR circuit that receives the second b delay pulse signal and the control pulse signal as inputs and outputs the second b control pulse signal; having 19. The control signal generating circuit according to claim 17 or 18. 　 a first push-pull circuit driven by the first control pulse signal to generate a first drive pulse signal for driving the first switching element; a second push-pull circuit driven by the second control pulse signal to generate a second drive pulse signal for driving the second switching element; Equipped with 20. The control signal generating circuit according to claim 1. 　 a first input terminal to which a reference potential is supplied; a second input terminal to which a first voltage potential higher than the reference potential is supplied; a step-down circuit that steps down the first voltage potential supplied to the second input terminal to a second voltage potential that is higher than the reference potential and is to be supplied to the logic synthesis unit; Equipped with a high potential end of the first push-pull circuit electrically connected to the second input terminal, and a low potential end of the first push-pull circuit electrically connected to the first input terminal; a high potential end of the second push-pull circuit electrically connected to the second input terminal, and a low potential end of the second push-pull circuit electrically connected to the first input terminal; 21. The control signal generating circuit according to claim 20. 　 an inverter circuit in which two switch units, which are switched between an on state that is a conductive state and an off state that is a non-conductive state, have at least one leg connected in series between a high potential line and a low potential line, and a connection point of the two switch units is an AC input / output point; a control signal generating circuit according to any one of claims 1 to 18, which is provided for each of the two switch units; Equipped with Each of the two switch units has the first switching element; the second switching element connected in parallel with the first switching element; having Power conversion device. 　 The power conversion device according to claim 22; a motor driven by the power conversion device; A vehicle equipped with:

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