Data processing method, computing apparatus, and service apparatus

Abstract

Disclosed in the present application are a data processing method, a computing apparatus, and a service apparatus. The method comprises: a computing apparatus acquiring a first operator, wherein the first operator is included in a plurality of operators, and the plurality of operators are included in a computing model; then determining, on the basis of a first relationship, a first cacheline length corresponding to the first operator, wherein the first relationship is used for describing a mapping relationship between operators and cacheline lengths; and then determining, on the basis of the first cacheline length, data stored in at least one first cacheline corresponding to the first cacheline length. The method enables timely and dynamic adjustment of a cacheline in a cache on the basis of a cacheline length corresponding to each of a plurality of operators, such that the length of the cacheline in the cache can match the operator, flexible adjustment of the cacheline length is achieved, and the cacheline length corresponding to each operator is put to effective use. Therefore, the method can enhance the effective utilization rate of a bandwidth and facilitate an improvement in the hit rate of the cache.

Description

A data processing method, computing device, and service device Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, computing device, and service device. Background Technology

[0002] In fields such as artificial intelligence (AI) and machine learning (ML), different functions can be achieved by designing or training different AI models (such as deep learning models, neural network models, machine learning models, etc.).

[0003] AI models typically consist of multiple operators, where operators represent computational operations performed on data within the AI ​​model. Specifically, operators are the fundamental operations for building AI applications and encapsulate related hardware operations. AI software can utilize hardware resources to perform relevant calculations by calling operator interfaces. Different operators are interconnected, representing data transmission relationships between them. The computational flow of an operator typically includes data input (also known as data reading), data computation, and data output.

[0004] The cache (also called the cache area) used to store the data corresponding to the operator is generally divided into multiple cache lines. Each cache line can be used to store the corresponding data. Each cache line stores a specific valid part of the corresponding address as a unique identifier (denoted as a tag) to distinguish it from other cache lines. For example, when the cache receives a read request, it can determine whether the requested data is in a certain cache line based on the tag.

[0005] For example, consider a cache that is fixedly divided into multiple long cachelines (e.g., a cacheline length of 512 bytes). If the data to be read is continuous, multiple consecutive data points can be read from the longer cacheline, resulting in a higher cache hit rate and improved AI model performance. However, if the data to be read is discrete, only a portion of the data stored in the longer cacheline (e.g., 128 bytes) needs to be read, while the majority of the data is not needed (because it is useless for the current read). Therefore, the longer cacheline is not effectively utilized, resulting in low bandwidth utilization. Furthermore, since the majority of the data stored in the longer cacheline is not used, there will be more cache misses, leading to a lower cache hit rate.

[0006] Summary of the Invention

[0007] This application provides a data processing method, computing device, and service device to enable flexible adjustment of cache line length, which helps to improve both cache hit rate and bandwidth utilization.

[0008] Firstly, this application provides a data processing method, which can be executed by a computing device, a module of the computing device, or a logical node, logical module, or software capable of implementing all or part of the functions of the computing device. For example, the following describes a data processing method executed by a computing device. The method may include the following steps: the computing device obtains a first operator, wherein the first operator is included among multiple operators, and the multiple operators are included in a computing model; then, the computing device determines the length of a first cache line corresponding to the first operator according to a first relation, wherein the first relation describes the mapping relationship between the operator and the cache line length; then, the computing device determines the data stored in at least one first cache line corresponding to the first cache line length according to the first cache line length.

[0009] In this method, the computing device can flexibly determine (or dynamically determine) the length of the first cache line corresponding to (or matching, suitable, or reasonable) the first operator based on the first relationship, and can adjust the length of the cache lines included in the cache in a timely manner based on the length of the first cache line (which can be understood as re-dividing the cache lines included in the cache based on the length of the first cache line, or it can also be understood as re-blocking the cache based on the length of the first cache line (or reallocating the cache lines in the cache based on the length of the first cache line)), so that the length of the adjusted cache lines in the cache can match the first operator and meet the actual needs of the first operator (such as the continuous data read and write needs or the discrete data read and write needs corresponding to the first operator). In this way, the method can dynamically adjust (or dynamically divide or dynamically allocate) the cache lines in the cache based on the cache line length corresponding to each operator (or any one of the operators). This ensures that when executing the operation process of each operator, the length of the cache lines in the cache can be matched with that operator in a timely manner. This allows for flexible adjustment of the cache line length (flexibly determining the cache line length corresponding to any operator so as to effectively execute the data read and write operations corresponding to that operator). It ensures that the cache line length corresponding to any operator matches the data size required for the operation of that operator, thus making effective use of the cache line length corresponding to that operator. Therefore, it can help improve the cache hit rate and the effective utilization of bandwidth.

[0010] In one possible implementation, the first relationship may include a first mapping relationship and a second mapping relationship, wherein the first mapping relationship is used to describe the mapping relationship between the first operator and the first cache line length, and the second mapping relationship is used to describe the mapping relationship between the second operator and the second cache line length, and the second operator is also included in multiple operators.

[0011] In the above implementation, the first relationship can include multiple mapping relationships (i.e., mapping relationships between multiple operators and their corresponding cache line lengths). This allows the computing device to determine the cache line length corresponding to any operator in a timely and accurate manner based on the first relationship, making the determination of the cache line length more flexible. Furthermore, the determined cache line length matches the current operator, which helps to improve the hit rate of the data required for any operator to perform operations. Since the cache line length corresponding to any operator matches the data size required for the operator to perform operations, the cache line length corresponding to that operator is effectively utilized, thereby improving the effective utilization rate of bandwidth.

[0012] In one possible implementation, the first relation can be determined based on a model computation graph included in the computation model, wherein the model computation graph is used to describe the topological connection relationships of multiple operators.

[0013] In the above implementation, the computing device can also determine the first relationship based on the model computation graph included in the computing model. This eliminates the need to obtain it from the outside and helps the computing device to flexibly determine the cache line length corresponding to any one of the multiple operators based on the first relationship in a timely manner.

[0014] In one possible implementation, the computing device determines the length of the first cache line corresponding to the first operator based on the first relation, including:

[0015] If the first relation is used to describe the mapping relationship between the operator type of an operator and the cache line length, the computing device can determine the first cache line length corresponding to the operator type of the first operator from the first relation; or,

[0016] If the first relation describes the mapping between the operator identifier of an operator and the cache line length, the computing device can determine the first cache line length corresponding to the operator identifier of the first operator from the first relation; or,

[0017] If the first relation is used to describe the mapping relationship between the operator name of the operator and the cache line length, the computing device can determine the first cache line length corresponding to the operator name of the first operator from the first relation.

[0018] In the above implementation, the computing device can determine the cache line length corresponding to any one of the multiple operators (such as the first operator) in a flexible and diverse manner, which can meet the application needs of different scenarios.

[0019] In one possible implementation, the method further includes:

[0020] The computing device determines at least one first cache line, wherein the length of each first cache line in the at least one first cache line is the length of the first cache line.

[0021] In the above implementation, the computing device can determine at least one first cache line corresponding to the first operator based on the length of the first cache line. This facilitates the timely and efficient reading of data required for the first operator to perform operations based on at least one first cache line corresponding to the first operator, or it facilitates the timely and efficient storage of data required for the first operator to perform operations read from the mass storage based on at least one first cache line corresponding to the first operator, or it facilitates the timely and efficient storage of data generated by the first operator during the operation based on at least one first cache line corresponding to the first operator.

[0022] In one possible implementation, the computing device determines at least one first cache line, including:

[0023] The computing device divides the cache according to the length of the first cache line to obtain at least one first cache line.

[0024] In the above implementation, the computing device can accurately divide the cache based on the length of the first cache line (which can also be understood as reallocating cache lines in the cache) to obtain at least one first cache line corresponding to the first operator.

[0025] In one possible implementation, the first relationship can be pre-configured.

[0026] In the above implementation, the first relationship can be generated by the service device or by other external devices and pre-configured (or pre-deployed) on the computing device (or the control device where the computing device is located). This makes it easier for the computing device to flexibly determine the cache line length corresponding to any one of the multiple operators based on the first relationship in a timely manner.

[0027] In one possible implementation, before the computing device determines the length of the first cache line corresponding to the first operator, the method further includes:

[0028] The computing device receives the first relation from the service device.

[0029] In the above implementation, the first relation is generated by the service device and provided to the computing device. This can reduce the computational pressure on the computing device caused by determining the first relation and help the computing device to have more resources (such as computing resources, storage resources, etc.) to process other tasks.

[0030] In one possible implementation, each of the multiple operators can be an operator of one of the following operator types: mathematical calculation type, data transfer type.

[0031] In the above implementation, when the computing device determines the first relation, the computing device can reasonably configure the corresponding cache line length for operators of different operator types, so that the cache line length corresponding to each operator type is matched with the actual needs of that operator type. This allows the cache line length required for data reading and writing to be flexibly adjusted based on each operator type when executing the inference process of the computing model, so that the cache line length corresponding to any operator is matched with the data size required for the operation of that operator.

[0032] Secondly, this application provides a data processing method, which can be executed by a service device, a module of the service device, or a logical node, logical module, or software capable of implementing all or part of the functions of the service device. For example, the following describes a data processing method executed by a service device. The method may include the following steps: the service device obtains a computational model, wherein the computational model may include a model computation graph, which describes the topological connection relationships of multiple operators. Then, the service device determines the cache line length corresponding to each of the multiple operators based on the model computation graph. Finally, the service device generates a first relationship based on the cache line length corresponding to each of the multiple operators.

[0033] In this method, the service device accurately classifies (or categorizes) the multiple operators included in the computation model. It can then rationally configure corresponding cache line lengths for operators of different types, ensuring that the cache line length for any operator type matches the actual needs of that operator. This allows for flexible adjustment of the cache line length required for data reading and writing during the inference process of the computation model, ensuring that the cache line length for any operator matches the data size required for its computational operations. This effectively utilizes the cache line length for that operator, thus improving both cache hit rate and bandwidth utilization.

[0034] In one possible implementation, the first relationship may include a first mapping relationship and a second mapping relationship, wherein the first mapping relationship is used to describe the mapping relationship between the first operator and the first cache line length, and the second mapping relationship is used to describe the mapping relationship between the second operator and the second cache line length, and the second operator is also included in multiple operators.

[0035] The technical effects achievable by the above implementation method can be referred to the technical effects achievable by the corresponding implementation method provided in the first aspect above, and will not be repeated here.

[0036] In one possible implementation, the service device determines the cache line length corresponding to each of the multiple operators based on the model computation graph, including:

[0037] The service device can determine the operator type of each operator among multiple operators based on the model computation graph. Then, the service device can determine the cache line length corresponding to each operator based on the operator type of each operator among multiple operators.

[0038] In the above implementation, the service device accurately classifies the multiple operators included in the computation model. Based on the operator type of any operator after classification, it can accurately and reasonably configure the corresponding cache line length for the operator of that operator type, so that the cache line length corresponding to the operator of that operator type matches the actual needs of the operator of that operator type.

[0039] In one possible implementation, the model computation graph may include operator information for multiple operators, and the operator information for each operator may include the operator type of the operator;

[0040] Based on the model calculation diagram, the service device determines the operator type of each operator among multiple operators, including:

[0041] The service device can determine the matching degree between the operator type of the third operator and the multiple operator types included in the operator type table, wherein the third operator can be any one of the multiple operators. Then, if the matching degree between the operator type of the third operator and the first operator type included in the operator type table is greater than or equal to the matching degree threshold, the service device can determine the first operator type as the operator type of the third operator.

[0042] In the above implementation, by comparing the operator type included in the operator information of any one of the multiple operators with the multiple operator types included in the operator type table, the specific operator type of the operator can be accurately determined, thereby providing effective support for the subsequent reasonable configuration of the cache line length corresponding to the operator.

[0043] In one possible implementation, the operator information for each of the multiple operators may further include the data index corresponding to the operator and the input / output data size;

[0044] The service device determines the cache line length for each operator based on the operator type of each operator among multiple operators, including:

[0045] If the operator type of the third operator is a mathematical calculation type, then the service device can determine that the cache line length corresponding to the third operator is the third cache line length; or,

[0046] If the operator type of the third operator is a data transport type, the service device can determine the cache line length corresponding to the third operator based on the data index corresponding to the third operator.

[0047] In the above implementation, the service device configures corresponding cache line lengths for operators of different operator types, which makes the configuration of cache line lengths for operators of different operator types more accurate and reasonable, and more in line with the actual needs of operators of different operator types (for example, some operators have continuous read and write requirements for data, while some operators have discrete read and write requirements for data), which helps to improve the hit rate of data required for different operator types to perform operations.

[0048] In one possible implementation, the service device determines the cache line length corresponding to the third operator based on the data index corresponding to the third operator, including:

[0049] If the data index corresponding to the third operator is a preset value, the service device can determine the cache line length corresponding to the third operator based on the distribution of the data index corresponding to the third operator; or,

[0050] If the data index corresponding to the third operator is not a preset value, the service device can determine the cache line length corresponding to the fourth operator as the cache line length corresponding to the third operator, wherein the output data corresponding to the fourth operator is used as the input data of the third operator.

[0051] In the above implementation, when the operator type of the third operator is a data transfer type, the service device can configure the corresponding cache line length for the third operator with a preset data index and the third operator with a non-preset data index according to whether the data index corresponding to the third operator is a preset value or not. This makes the configuration of the cache line length more accurate and reasonable, and more in line with the cache line length requirements under different situations (such as the data index being a preset value or the data index being a non-preset value). This helps to improve the hit rate of the data required for the third operator to perform operations under different situations.

[0052] In one possible implementation, the service device determines the cache line length corresponding to the third operator based on the distribution of the data indexes corresponding to the third operator, including:

[0053] If the data index corresponding to the third operator is continuously distributed, the service device can determine that the cache line length corresponding to the third operator is the fourth cache line length; or,

[0054] If the distribution of the data index corresponding to the third operator is discrete, the service device can determine the cache line length corresponding to the third operator as the fifth cache line length based on the size of the input and output data corresponding to the third operator. The fifth cache line length is different from the fourth cache line length.

[0055] In the above implementation, when the third operator's operator type is a data transfer type, the service device can accurately configure appropriate cache line lengths for third operators with different data index distributions based on the distribution of the corresponding data indexes. This satisfies the cache line length requirements for different data index distributions. For example, when the data indexes corresponding to the third operator are continuously distributed, configuring a larger cache line length for the third operator in this case can satisfy its continuous data read / write requirements. When the data indexes corresponding to the third operator are discretely distributed, configuring a smaller cache line length for the third operator in this case can satisfy its discrete data read / write requirements.

[0056] In one possible implementation, after the service device generates the first relationship, the method further includes:

[0057] The service device can send the first relationship to the computing device.

[0058] The technical effects achievable by the above implementation method can be referred to the technical effects achievable by the corresponding implementation method provided in the first aspect above, and will not be repeated here.

[0059] Thirdly, this application provides a data processing apparatus, which may be a computing device or a module (such as a processor) within a computing device. This data processing apparatus has the function of implementing the method in any possible implementation of the first aspect described above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the aforementioned function.

[0060] Fourthly, this application provides a data processing apparatus, which may be a service device or a module (such as a processor) within a service device. This data processing apparatus has the function of implementing the method in any possible implementation of the second aspect described above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the aforementioned function.

[0061] Fifthly, this application provides a data processing apparatus that has the functions described in the first aspect above. For example, the data processing apparatus includes modules, units, or means that perform the operations described in the first to second aspects above. The functions, units, or means can be implemented by software, or by hardware, or by hardware executing corresponding software.

[0062] In one possible implementation, the data processing device includes a transceiver unit (or communication module, used for sending and receiving data) and a processing unit (or processing module). The transceiver unit can be used to send and receive signals to enable communication between the data processing device and other devices, for example, to send data to other devices. The processing unit can be used to perform some internal operations of the data processing device. The functions performed by the transceiver unit and the processing unit can correspond to the operations described in the first and second aspects above.

[0063] In one possible implementation, the data processing apparatus includes a processor that can be coupled to a memory. The memory can store computer programs or instructions necessary to implement the functions described in the first aspect above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the data processing apparatus to implement the methods in any possible implementation of any of the first to second aspects above.

[0064] In one possible implementation, the data processing apparatus includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in the first aspect described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the data processing apparatus to implement the methods in any possible implementation of any of the first to second aspects described above.

[0065] In one possible implementation, the data processing device includes a processor and a communication interface (or interface circuitry), wherein the processor is configured to communicate with other devices via the communication interface and execute the methods in any possible implementation of any of the first to second aspects described above. The communication interface enables the data processing device to communicate with other devices, for example, to receive signals from other devices and transmit them to the processor, or to send signals from the processor of the data processing device to other devices, such as the transmission or reception of data and / or signals. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0066] It is understood that, in the fifth aspect mentioned above, the processor can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor, or the memory and processor can be separate. In specific implementations, the memory can be integrated with the processor on the same chip, or it can be set on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0067] Sixthly, this application provides a control device including the aforementioned computing device. The computing device can be used to execute the method in any possible implementation of the first aspect. For example, the control device may be a vehicle controller, a cockpit domain controller, a vehicle dynamics controller, or an intelligent driving computing platform, etc.

[0068] In a seventh aspect, this application provides a vehicle that includes the aforementioned control equipment.

[0069] Eighthly, this application provides a computer program product comprising a computer program or instructions that, when executed on a computer, cause the computer to perform the method in any possible implementation of any of the first to second aspects described above.

[0070] Ninthly, this application provides a computer-readable storage medium storing a computer program or instructions that, when executed by a computer, cause the computer to perform the method in any possible implementation of any of the first to second aspects described above.

[0071] In a tenth aspect, this application provides a chip that may include a processor and may also include a memory (or the chip may be coupled to the memory). The chip executes program instructions in the memory to cause the chip to perform any possible implementation of any of the first to second aspects described above. Here, "coupling" refers to two components being directly or indirectly connected to each other, such as coupling referring to an electrical connection between two components.

[0072] Eleventhly, this application also provides a chip system including a processor for supporting a computer device in implementing any possible implementation of the methods in any of the first to second aspects described above. In one possible implementation, the chip system further includes a memory for storing programs and data necessary for the computer device. The chip system may be composed of chips or may include chips and other discrete devices.

[0073] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0074] Figure 1 illustrates a possible application scenario provided by an embodiment of this application.

[0075] Figure 2a illustrates a schematic diagram of the functional module structure of a computing device provided in an embodiment of this application.

[0076] Figure 2b illustrates a schematic diagram of the functional module structure of another computing device provided in an embodiment of this application.

[0077] Figure 3 illustrates a flowchart of a data processing method provided in an embodiment of this application;

[0078] Figure 4 illustrates a schematic diagram of cache partitioning provided in an embodiment of this application;

[0079] Figure 5 illustrates a flowchart of another data processing method provided in an embodiment of this application;

[0080] Figure 6a illustrates, exemplarily, a computational model diagram including a computational model provided in an embodiment of this application;

[0081] Figure 6b exemplarily illustrates a model calculation diagram including another calculation model provided in an embodiment of this application;

[0082] Figure 7 illustrates an exemplary schematic diagram of a cache line length configuration provided in an embodiment of this application;

[0083] Figure 8 illustrates, for example, a histogram of the data index corresponding to a gather operator provided in an embodiment of this application;

[0084] Figure 9 is an exemplary schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0085] Figure 10 illustrates a schematic diagram of another data processing apparatus provided in an embodiment of this application. Detailed Implementation

[0086] Before introducing the technical solutions provided in this application, some of the terms used in this application will be explained in order to facilitate understanding by those skilled in the art.

[0087] (1) Cache: Also known as memory, it is a high-speed cache (also known as a high-speed buffer memory). The cache is a level 1 or multi-level cache located between the main memory and the processor, used to store data and instructions that are frequently accessed by the processor. By storing data in the cache, the access speed of data can be accelerated, the number of accesses to main memory can be reduced, thereby improving the overall performance of the computer system.

[0088] In practical applications, the cache is usually divided into multiple cache lines. When performing a read operation on the cache, it will first check whether the data to be read is in a certain cache line, thereby reducing the number of cache accesses and improving the cache access speed.

[0089] (2) AI Model: This refers to a model constructed using deep neural networks or convolutional neural networks, and trained using training samples to obtain a model that can be used for inference (or application) in a specific scenario. An AI model consists of multiple computational units, such as convolutions, activation functions (e.g., the sigmoid function), and other units used to perform corresponding calculations. Each computational unit can be called an "operator," such as a convolution operator or a sigmoid operator. The execution logic of an AI model refers to the order in which each computational unit is executed.

[0090] For example, a trained AI model can be deployed on computing devices such as servers and terminal devices. When applying the AI ​​model, the input data is processed by the model for inference on the computing device, and the inference results are output. The server can be a cloud server or a local server. The terminal device can be a handheld device such as a mobile phone or tablet, a smart wearable device such as a smart bracelet, smartwatch, or smart helmet, or a vehicle (such as a self-driving vehicle) or a wheeled mobile device such as a robot. This application does not limit the product form of the computing device. Optionally, the terminal device can also be a chip, processor, domain controller (such as a computing platform for self-driving vehicles), etc.

[0091] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0092] The following describes the application scenarios to which the data processing method provided in this application is applicable. It should be noted that these descriptions are for the purpose of facilitating understanding by those skilled in the art and do not constitute a limitation on the scope of protection claimed in this application.

[0093] Figure 1 illustrates a possible application scenario for which this application embodiment applies. The application scenario shown in Figure 1 uses a data processing method applied to a vehicle, where the vehicle has intelligent driving capabilities. As shown in Figure 1, this application scenario may include a vehicle 100 and a service device 200.

[0094] The vehicle 100 includes a computing platform 110 (also referred to as a computer system), and some or all of the functions of the vehicle 100 are controlled by the computing platform 110. For example, the computing platform 110 may include at least one processor 111, which can execute instructions 113 stored in a non-transitory computer-readable medium such as memory 112.

[0095] In some embodiments, the computing platform 110 may be multiple computing devices that control individual components or subsystems of the vehicle 100 in a distributed manner. The processor 111 may be any conventional processor, such as a central processing unit (CPU). Optionally, the processor 111 may also include a graphics processing unit (GPU), a field-programmable gate array (FPGA), a system-on-chip (SoC), an application-specific integrated circuit (ASIC), or a combination thereof. Optionally, the vehicle 100 described above may be a car, truck, motorcycle, bus, boat, airplane, helicopter, lawnmower, recreational vehicle, amusement park vehicle, construction equipment, tram, golf cart, train, etc., and this application does not impose any limitations on this.

[0096] Optionally, the computing device (also referred to as the first data processing device) can be a standalone device (such as a processor or chip), a chip or component within the vehicle 100, or a software module. The computing device can be deployed on relevant onboard equipment within the vehicle 100. For example, the computing device can be implemented as a vehicle control unit (VCU), or a vehicle domain controller (VDC), etc., integrated into the computing platform 110 within the vehicle 100 to implement vehicle control; or it can be an intelligent driving domain control unit or an intelligent driving computing platform (also referred to as an intelligent driving computing center, such as a mobile data center (MDC)), etc., used to implement intelligent driving or assisted driving functions. This application does not limit the product form or deployment method of the computing device.

[0097] The service device 200 (also referred to as the development device 200 or the second data processing device 200) can be used to provide the computing device with the required algorithms or computing strategies. For example, the service device 200 can provide the computing device with at least one AI model, which the computing device can then use to perform AI calculations. It should be understood that this is merely an illustrative example of the function of the service device 200, and not a limitation on the configuration of the computing device's algorithms or computing strategies. In specific implementations, the computing device itself may already be configured with relevant algorithms or computing strategies, and the service device 200 can be used to provide subsequent updates or version upgrades of the algorithms or computing strategies for the computing device; this will not be elaborated further here. For example, the service device 200 can be a standalone physical server, or a server cluster or distributed system composed of multiple physical servers. For example, the service device 200 can be a cloud server (also referred to as cloud, cloud computing, server-side, or cloud computing equipment, such as a vehicle cloud server or vehicle networking server) used to provide cloud services, cloud computing, cloud storage, cloud communication, network services, security services, and big data services, or it can be a regular data center, server, or other form of computing equipment.

[0098] It is understood that the data processing solution provided in this application embodiment can be applied to the field of vehicle networking, such as vehicle-to-everything (V2X), long-term evolution-vehicle (LTE-V), and vehicle-to-vehicle (V2V). For example, the data processing solution provided in this application embodiment can be applied to vehicles with intelligent driving functions, or other devices in vehicles with AI computing functions. Other devices may include, but are not limited to, vehicle terminals, vehicle control units, vehicle modules, vehicle components, vehicle chips, and vehicle units. Vehicles can implement the operator processing method provided in this application embodiment through these vehicle terminals, vehicle control units, vehicle modules, vehicle components, vehicle chips, and vehicle units. Of course, the data processing solution provided in this application embodiment can also be applied to other intelligent terminals besides vehicles, or components in other intelligent terminals (such as processors, chips, or control units). Other intelligent terminals or components in other intelligent terminals have AI computing functions. For example, other intelligent terminals may be intelligent transportation equipment, smart home devices, robots, etc.

[0099] It should be noted that Figure 1 only schematically provides one possible application scenario. This illustrative application scenario is intended to more clearly illustrate the technical solutions of the embodiments of this application and does not constitute a limitation on the application scenarios of the data processing method provided in this application. Furthermore, those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0100] For example, based on the application scenario shown in Figure 1, to facilitate understanding of this application, this application embodiment provides a functional module structure of a computing device. This computing device is configured in a vehicle 100. As shown in Figure 2a, according to logical functions, the computing device can be divided into the following functional modules: a cache line length configuration module (also called a cache line configuration module), a cache module, and an AI computing module. It should be understood that the number of AI computing modules can be one or more, and this application embodiment does not limit this. It is understood that Figure 2a illustrates a computing device including a cache line length configuration module, a cache module, and an AI computing module. The operator queue includes an addition operator, two aggregation operators (e.g., aggregation operator 1 and aggregation operator 2), and a convolution operator. The cache line length configuration table includes a cache line length of 512B corresponding to the addition operator, a cache line length of 64B corresponding to aggregation operator 1, a cache line length of 512B corresponding to the convolution operator, and a cache line length of 128B corresponding to aggregation operator 2. It should be understood that the cache line length configuration table shown in Figure 2a can also be replaced by a first relation, which describes the mapping relationship between operators and cache line lengths. Optionally, the computing device may also include a task scheduling module. For example, the cache line length configuration module may refer to a cache line length configurator (also called a cache line configurator), the cache module may refer to a register (or cache or other forms of memory (such as static random access memory)), and the AI ​​computing module may refer to an AI computing core. Optionally, when the computing device includes one cache line length configuration module, multiple cache modules, and multiple AI computing modules, the functional module structure of the computing device can be seen in Figure 2b. Figure 2b illustrates a computing device comprising a cache line length configuration module, four cache modules (e.g., cache module 1, cache module 2, cache module 3, and cache module 4), and four AI computing modules (e.g., AI computing module 1, AI computing module 2, AI computing module 3, and AI computing module 4). The operator queue includes an addition operator, two aggregation operators (e.g., aggregation operator 1 and aggregation operator 2), and a convolution operator. The cache line length configuration table includes a cache line length of 512B corresponding to the addition operator, a cache line length of 64B corresponding to aggregation operator 1, a cache line length of 512B corresponding to the convolution operator, and a cache line length of 128B corresponding to aggregation operator 2. It should be understood that the cache line length configuration table shown in Figure 2b can also be replaced by a first relation, which describes the mapping relationship between operators and cache line lengths.

[0101] In one example, in the computing device shown in Figure 2a, the mapping relationship between operators and cache line lengths (or a cache line length configuration table) and the computing model (or a queue of operators comprising multiple operators included in the computing model) can be used as inputs to the computing device. Specifically, the mapping relationship between operators and cache line lengths (or a cache line length configuration table) and the computing model can be used as inputs for model inference, input into a given interface. For example, the mapping relationship between operators and cache line lengths (or a cache line length configuration table) is input into the interface of the cache line length configuration module, and the computing model (or a queue of operators comprising multiple operators included in the computing model) is input into the interface of the AI ​​computing module.

[0102] In another example, in the computing device shown in Figure 2b, the mapping relationship between operators and cache line lengths (or cache line length configuration table), the computing model (or the operator queue consisting of multiple operators included in the computing model), and the number of computational cores of the computing model (also known as the number of running cores, which can be understood as the number of AI computing modules) can be used as inputs to the computing device. Specifically, the mapping relationship between operators and cache line lengths (or cache line length configuration table), the computing model, and the number of computational cores of the computing model can be used as inputs for model inference, input into a given interface. For example, the mapping relationship between operators and cache line lengths (or cache line length configuration table) is input into the interface of the cache line length configuration module, and the computing model (or the operator queue consisting of multiple operators included in the computing model) is input into the interfaces of the four AI computing modules respectively. In other words, it can be understood that the four AI computing modules can share a mapping relationship (or cache line length configuration table) between operators and cache line lengths. The cache module corresponding to each of the four AI computing modules can adjust (or update or determine) the cache line length according to the operator that needs to be executed at the moment, so that the adjusted cache line length matches the operator. This can help improve the effective utilization of bandwidth while improving the cache hit rate.

[0103] It should be understood that the connection relationships between the functional modules shown in Figure 2a or Figure 2b are merely examples and do not constitute a limitation of this application. The functions of each functional module are described below.

[0104] The cache line length configuration module is used to provide the cache module with the cache line length corresponding to each operator among multiple operators included in a certain computational model (also known as a certain AI model). For example, consider the addition operator included in the computational model. In one example, when the computing device includes a task scheduling module, the cache line length configuration module receives first information from the task scheduling module. This first information indicates the computational flow (also known as the computational operation or process) for executing the addition operator, or it indicates the execution of the addition operator. For example, the first information may include the operator identifier (or operator name or operator type) of the addition operator. Then, the cache line length configuration module can determine the cache line length s1 corresponding to the addition operator based on the first information. Then, the cache line length configuration module can send second information to the cache module. This second information may include the cache line length s1 corresponding to the addition operator. Optionally, the second information may also include the operator identifier (or operator name or operator type) of the addition operator.

[0105] In another example, when the computing device includes a task scheduling module, the cache line length configuration module receives third information from the cache module. This third information is used to request the cache line length corresponding to the addition operator. For example, the third information may include the operator identifier (or operator name or operator type) of the addition operator. The cache line length configuration module can then determine the cache line length s1 corresponding to the addition operator based on the third information. Then, the cache line length configuration module can send second information to the cache module.

[0106] For example, the following examples illustrate the implementation process of the cache line length configuration module determining the cache line length s1 corresponding to the addition operator based on the first information.

[0107] Example 1: The cache line length configuration module determines the cache line length s1 corresponding to the operator identifier (or operator name or operator type) of the addition operator from the cache line length configuration table. The cache line length configuration table includes the cache line lengths corresponding to the operator identifiers (or operator names or operator types) of multiple operators, and the operator identifier (or operator name or operator type) of the addition operator is contained within the operator identifiers (or operator names or operator types) of multiple operators. In other words, the cache line length configuration table describes the mapping relationship (also called correspondence or association) between the operator identifiers (or operator names or operator types) of multiple operators and their respective cache line lengths. For example, the cache line length configuration table can be pre-configured (e.g., pre-configured (or pre-deployed) in the computing device), or it can be provided by the service device 200.

[0108] Example 2: The cache line length configuration module determines the cache line length s1 corresponding to the addition operator based on the mapping relationship between the operator and the cache line length.

[0109] For example, when the mapping relationship between operators and cache line lengths is used to indicate the mapping relationship between the operator identifier of an operator and the cache line length, the cache line length configuration module can determine the cache line length s1 corresponding to the operator identifier of the addition operator from the mapping relationship between operators and cache line lengths.

[0110] For example, when the mapping relationship between operators and cache line lengths is used to indicate the mapping relationship between operator names and cache line lengths, the cache line length configuration module can determine the cache line length s1 corresponding to the operator name of the addition operator from the mapping relationship between operators and cache line lengths.

[0111] For example, when the mapping relationship between operators and cache line lengths is used to indicate the mapping relationship between operator types and cache line lengths, the cache line length configuration module can determine the cache line length s1 corresponding to the operator type of the addition operator from the mapping relationship between operators and cache line lengths.

[0112] The caching module is used to adjust (or divide or block) the cache (or cache region or cache space region) according to the cache line length corresponding to a specific operator included in a certain computation model, to obtain at least one cache line corresponding to that operator. The length of this at least one cache line is the same as the cache line length corresponding to that operator. In other words, the caching module can adjust the cache separately based on the cache line length corresponding to each of the multiple operators included in a certain computation model, to obtain at least one cache line corresponding to each operator.

[0113] For example, the following section continues to use the addition operator included in the above calculation model as an example to introduce the implementation process of the cache module adjusting the cache through the following possible examples.

[0114] Example a: The caching module receives second information from the cache line length configuration module. This second information may include the cache line length s1 corresponding to the operator identifier (or operator name or operator type) of the addition operator. Optionally, the second information may also include the operator identifier (or operator name or operator type) of the addition operator. Then, the caching module can divide the cache according to the cache line length s1 included in the second information to obtain at least one cache line corresponding to the addition operator.

[0115] Example b: The caching module receives first information from the task scheduling module and can send third information to the cache line length configuration module based on the first information. Then, the caching module receives second information from the cache line length configuration module. Finally, the caching module can divide the cache according to the cache line length s1 included in the second information to obtain at least one cache line corresponding to the addition operator.

[0116] For example, let's take a cache line length s1 of 512 bytes and a cache size of 1536 bytes. The cache module can divide the cache according to the cache line length s1, resulting in three cache lines corresponding to the addition operator, such as cache line 1, cache line 2, and cache line 3. Each of these three cache lines has a length of 512 bytes.

[0117] Optionally, the caching module can also be used to determine the data stored in at least one cache line corresponding to a certain operator based on the read / write request from the AI ​​computing module for that operator.

[0118] For example, continuing with the addition operator included in the above calculation model, the caching module receives a first request from the AI ​​calculation module. This first request requests to read the first data corresponding to the addition operator. Exemplarily, the first data can refer to all data related to the addition operator, or it can refer to one piece of data (or a portion of data) from all the data related to the addition operator (because in multiple consecutive requests, each request only requests a portion or one piece of data, which is considered the first data). The first request may include the operator identifier (or operator name or operator type) of the addition operator.

[0119] In one example, if the cache module does not store the first data, it can send a second request to a mass storage device (such as Double Rate Synchronous Dynamic Random Access Memory (DDR)) based on the first request. The second request requests the first data based on the cache line length s1 corresponding to the addition operator. For example, the second request may include the cache line length s1 corresponding to the addition operator. Upon receiving the second request, the mass storage device can send at least one piece of data with a cache line length s1 to the cache module. The first data is contained within at least one piece of data with a cache line length s1 (this can be understood as at least one piece of data with a cache line length s1 being the first data, or as at least one piece of data with a cache line length s1 including the first data). After receiving at least one piece of data with a cache line length s1, the cache module can store the at least one piece of data with a cache line length s1 into at least one cache line. Then, the cache module can read the first data from the at least one cache line corresponding to the addition operator. Finally, the cache module can send the first data corresponding to the addition operator to the AI ​​computing module.

[0120] For example, assuming the cache module does not store the first data, the first data is 512 bytes in size, the cache line length s1 corresponding to the addition operator is 512 bytes, and the large-capacity memory is DDR, the cache module can send a second request to the DDR based on the first request. The second request requests the retrieval of second data based on the cache line length of 512 bytes. The second data includes the first data. After receiving the second request, the DDR can send the second data to the cache module based on the cache line length of 512 bytes (this can also be understood as the DDR sending second data matching the cache line length of 512 bytes, or as the DDR reading second data of size 512 bytes from the storage area according to the cache line length of 512 bytes). After receiving the second data of size 512 bytes, the cache module can store the second data of size 512 bytes into a cache line of size 512 bytes. Then, the cache module can read the first data of size 512 bytes from the cache line of size 512 bytes. Then, the caching module can send the first data, which is 512 bytes in size, to the AI ​​computing module.

[0121] For example, consider a scenario where the cache module does not store the first data, the first data is 128 bytes in size, the cache line length s1 corresponding to the addition operator is 512 bytes, and the large-capacity memory is DDR. The cache module can send a second request to the DDR based on a first request (the first request can be one of several consecutive requests corresponding to the addition operator, and each request only requests a portion of the data corresponding to the addition operator). The second request requests the retrieval of third data based on the cache line length of 512 bytes. The third data includes the second data. Upon receiving the second request, the DDR can send the third data to the cache module based on the cache line length of 512 bytes (this can also be understood as the DDR sending third data matching the cache line length of 512 bytes, or the DDR reading 512 bytes of third data from the storage area according to the cache line length of 512 bytes). After receiving the 512 bytes of third data, the cache module can store the 512 bytes of third data into a cache line with a cache line length of 512 bytes. Next, the caching module can read 128 bytes of first data from a cache line with a cache line length of 512 bytes. Then, the caching module can send the 128 bytes of first data to the AI ​​computing module.

[0122] In another example, if the cache module stores first data (for example, first data stored in the cache module based on cache line length s1, i.e., the first data stored in at least one cache line corresponding to cache line length s1), then the cache module can read the first data from at least one cache line corresponding to cache line length s1. Afterward, the cache module can send the first data corresponding to the addition operator to the AI ​​calculation module.

[0123] For example, consider a cache module storing 512 bytes of first data, where the cache line length s1 corresponding to the addition operator is also 512 bytes. The cache module can read 512 bytes of the first data from at least one cache line with a cache line length of 512 bytes, based on a first request. Then, the cache module can send the 512 bytes of the first data to the AI ​​calculation module.

[0124] For example, consider a cache module storing 128 bytes of first data, where the cache line length s1 corresponding to the addition operator is 512 bytes. The cache module can read 128 bytes of the first data from at least one cache line with a cache line length of 512 bytes, based on a first request (which can be one of multiple consecutive requests corresponding to the addition operator, and each request only requests a portion of the data corresponding to the addition operator). Then, the cache module can send the 128 bytes of the first data to the AI ​​calculation module.

[0125] The AI ​​computing module is used to execute the operation process of each operator among multiple operators included in a computing model (or, as some might say, to execute each operator among multiple operators included in a computing model). For example, continuing with the addition operator included in the aforementioned computing model, when the computing device includes a task scheduling module, the AI ​​computing module receives first information from the task scheduling module. Then, based on the first information, the AI ​​computing module can schedule (or acquire or determine) the addition operator from the operator queue and execute the operation process of the addition operator. During the execution of the addition operator, the AI ​​computing module needs to read the data required for the addition operator operation from the cache module, or needs to write relevant data generated by the addition operator operation (such as result data) to the cache module. For example, the operator queue stores multiple operators included in a computing model. Optionally, the multiple operators stored in the operator queue can be sorted according to the order of operation of the multiple operators.

[0126] For example, consider the data reading operation included in the addition operator performed by the AI ​​computing module. When performing the data reading operation included in the addition operator, the AI ​​computing module can send a first request to the caching module. Subsequently, the AI ​​computing module can receive the first data corresponding to the addition operator from the caching module.

[0127] Optionally, when the computing device does not include a task scheduling module, if the AI ​​computing module schedules an operator (such as an addition operator) from the operator queue, the AI ​​computing module can send a fourth piece of information to the caching module. This fourth piece of information indicates the computational flow for executing the addition operator, or it indicates the execution of the addition operator. For example, the fourth piece of information may include the operator identifier (or operator name or operator type) of the addition operator. After receiving the fourth piece of information, the caching module can then send a fifth piece of information to the cache line length configuration module. This fifth piece of information requests the cache line length corresponding to the addition operator. For example, the fifth piece of information may include the cache line length s1 corresponding to the operator identifier (or operator name or operator type) of the addition operator. Then, after receiving the fifth piece of information from the cache line length configuration module, the caching module can divide the cache according to the cache line length s1 included in the fifth piece of information to obtain at least one cache line corresponding to the addition operator.

[0128] The task scheduling module is used to perform task scheduling, such as scheduling the execution of each operator among multiple operators in a computational model. It can be understood that the operation of each operator among multiple operators can be considered as one task, thus each operator's operation can be considered as an operator task.

[0129] For example, consider the scheduling of the addition operator included in the above-mentioned computational model by the task scheduling module. When the task scheduling module determines to execute the addition operator included in the above-mentioned computational model, the task scheduling module can send the first information to the cache line length configuration module, the cache module, and the AI ​​computation module respectively.

[0130] Optionally, the cache line length configuration module, caching module, AI computing module, and task scheduling module can all be implemented in software or hardware. For example, the implementation of the cache line length configuration module will be described below. Similarly, the implementation of the caching module, AI computing module, and task scheduling module can refer to the implementation of the cache line length configuration module, and will not be repeated here.

[0131] When implemented in software, the cache line length configuration module can be an application or code block running on a cache line length configurator (also known as a cache line length configuration device or cache line length configuration hardware) in the vehicle. The cache line length configurator can be at least one of a physical host, virtual machine, container, or other computing device. Furthermore, there can be one or more cache line length configurators. For example, the cache line length configuration module can be an application running on multiple hosts / virtual machines / containers.

[0132] When implemented in hardware, the cache line length configuration module may include at least one server (or processor or chip, etc.). Alternatively, the cache line length configuration module may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0133] Furthermore, it is understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. The functional modules in the embodiments of this application can be integrated into one module, or each module can exist physically separately, or two or more modules can be integrated into one module. For example, taking the cache line length configuration module and the cache module as examples, the cache line length configuration module and the cache module can be integrated into one module, or the cache line length configuration module and the cache module can be the same module. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0134] As described in the background section, when the data to be read is discrete, if the cacheline length is large, the larger cachelines will not be effectively utilized, resulting in low bandwidth utilization. Furthermore, since a large portion of the data stored in the larger cachelines will not be used, this leads to more cache misses. To address these issues, a current solution for adjusting cacheline length is as follows: Step 1: Using the original cacheline size as the base unit, merge consecutive base cachelines to form a new cacheline. The size is denoted as Xn, indicating that this cacheline is the size of n base cachelines, where n is at least 1 and at most includes all base cachelines in the cache. Step 2: All tags corresponding to the base cacheline size are retained in the cache. The original cache processing of requests is equivalent to working in the X1 level. When a cache request hits, X1 and Xn levels remain consistent. When a cache miss occurs, X1 only updates and replaces one base cacheline. Switching to the Xn level increases the processing unit by enlarging the original replacement logic, changing from replacing one to replacing n base cachelines. However, in actual program execution, operators cannot monitor and determine whether the request data is continuous in real time. For example, increasing n when the request data is considered relatively continuous, or decreasing n when the request data is considered relatively discrete. Once n is set, adjusting it during actual operation is cumbersome and lacks operability. Furthermore, this scheme essentially involves concatenating multiple consecutive cachelines, and the tags, valid, and dirty attributes of each cacheline are retained, leading to cache waste.

[0135] In view of this, this application provides a data processing method to achieve flexible adjustment (or selection) of cache line length, which helps to improve both the cache hit rate (also known as the cache hit rate, which can be understood as the hit rate of data in the cache line) and the effective utilization of bandwidth. Furthermore, the data processing method provided in this application divides (or reallocates) cache lines in the cache based on the cache line length corresponding to each operator, making the adjustment of cache lines in the cache more flexible and more in line with actual needs, rather than concatenating them based on a baseline cacheline. It also does not retain the original cache line allocation strategy, i.e., it does not retain the tag, valid, or dirty attributes corresponding to the original cache lines, thus avoiding cache waste to a certain extent.

[0136] The following section provides a detailed description of the specific implementation of the data processing method in this application embodiment, based on the application scenario shown in Figure 1.

[0137] Figure 3 illustrates a flowchart of a data processing method provided in an embodiment of this application. This method can be applied, but is not limited to, the application scenario shown in Figure 1. It is understood that the data processing method shown in Figure 3 is illustrated using a computing device as the execution subject, but this application does not limit the execution subject used in the interactive illustration. It should be understood that the method executed by the computing device in this application can also be executed by a module applied to the computing device (such as a cache module, cache line length configuration module, processor, or processing unit), or by a logical node, logical module, or software capable of implementing all or part of the functions of the computing device.

[0138] As shown in Figure 3, the method includes:

[0139] Step 301: The computing device acquires the first operator.

[0140] For example, when a computing device acquires a first operator, it can acquire the operator identifier, operator name, or operator type of the first operator.

[0141] The first operator is one of several operators included in the computational model. For example, the computational model can refer to an AI model or other forms of model.

[0142] It is understood that the aforementioned computational model can refer to a model that, after training, is to be deployed on computing devices such as service devices, terminal devices, or computing devices. For example, the aforementioned model can be an ONNX model, a Tensorflow model, a DaVinci model, or a Mindspore model, etc.

[0143] Optionally, the computing device can read the model file of the computational model from a local database (or local cache or local memory, etc.), obtain the model file of the computational model from a service device, or directly input the model file of the computational model through an external input device. This application embodiment does not limit the method by which the computing device obtains the computational model.

[0144] For example, a computational model can include a multi-layered network structure. Each layer of this network structure can include at least one operator. After deploying the computational model, the computing device can utilize (or apply) the model through a corresponding model inference process. Model inference can be understood as the process by which the computing device runs the computational model; that is, the computing device uses the operators in each layer of the computational model to perform corresponding operations on the input data, thereby outputting the corresponding inference results. For example, the computational model can be used for speech recognition, object detection / recognition, image classification / recognition, etc.

[0145] In this embodiment, the computational model may include a model computation graph. Optionally, the computational model may also include model parameters or model weights, etc.

[0146] The model computation graph can be used to describe the topological connections between multiple operators included in the computation model. For example, the model computation graph can include the topological connections between multiple operators included in the computation model and operator information for each operator. Exemplarily, the operator information for each operator can include at least one of the following: the operator type, the operator name, the input and output data information corresponding to the operator (e.g., the input data size, the output data size, the weight (W) and bias (B), or the data indices), the operator information corresponding to the input data (e.g., operator type or operator name), or the operator information corresponding to the output data (e.g., operator type or operator name). Optionally, the operator information for each operator can also include the operator's attribute information. For example, taking convolution operators as an example, the attribute information of convolution operators may include dilations, number of groups, kernel shape, pads, and strides.

[0147] It is understandable that the topological connection relationship of multiple operators can be used to represent the data transmission relationship between multiple operators. Each of the multiple operators can perform corresponding computational operations on the data input to that operator.

[0148] For example, consider an AI model as a computational model. An AI model can include at least one of the following operators: reducesum operator, convolution operator (simply called conv operator), multiplication operator (Mul), addition operator, matrix multiplication operator (MatMul), rectified linear unit (ReLU) operator, sigmoid operator (also called sigmoid function operator), Tanh operator (also called Tanh function operator), softmax function operator, gather operator, scatter operator, transpose operator, slice operator, or gatherElements operator, etc.

[0149] In the embodiments of this application, the multiple operators included in the calculation model are divided according to the operator type. Each operator included in the multiple operators can be divided into a mathematical calculation type (also known as a mathematical calculation category or mathematical calculation class) operator or a data transport type (also known as a data transport category or data transport class) operator.

[0150] For example, continuing with the computational model as the AI ​​model, the AI ​​model includes operators such as reducesum, convolution, Mul, add, MatMul, ReLU, sigmoid, Tanh, softmax, gather, scatter, transpose, slice, and gatherElements. Classifying these operators within the AI ​​model by operator type, we can obtain mathematical computation operators, including but not limited to: reducesum, convolution, Mul, add, MatMul, ReLU, sigmoid, Tanh, and softmax, as well as data transfer operators, including but not limited to: gather, scatter, transpose, slice, and gatherElements.

[0151] Step 302: The computing device determines the length of the first cache line corresponding to the first operator based on the first relation.

[0152] The first relation can be used to describe the mapping between operators and cache line lengths. In other words, the first relation can be used to describe the mapping between at least one operator and its corresponding cache line length. That is to say, the first relation can include at least one mapping relationship.

[0153] For example, consider a first relation that includes two mapping relations (e.g., a first mapping relation and a second mapping relation). The first mapping relation describes the mapping between a first operator and a first cache line length, and the second mapping relation describes the mapping between a second operator and a second cache line length. Optionally, the second operator and the first operator can be different or the same. For instance, if the first operator and the second operator are contained in the same computational model, then the first operator and the second operator are different. If the first operator and the second operator are contained in different computational models, then the first operator and the second operator can be the same, or the first operator and the second operator can be different.

[0154] For example, consider five operators (operator 1, operator 2, operator 3, operator 4, and operator 5). Operator 1 corresponds to a cache line length of l1, operator 2 to l2, operator 13 to l3, operator 4 to l4, and operator 5 to l5. Thus, the first relationship can include the mapping between operator 1 and cache line length l1, operator 2 and cache line length l2, operator 3 and cache line length l3, operator 4 and cache line length l4, and operator 5 and cache line length l5.

[0155] For example, the process of obtaining the first relation is illustrated below through several possible examples.

[0156] Example 1: The first relation can be pre-configured, or it can be pre-defined.

[0157] Example 2: The first relation is determined (or generated) by the service device. The service device can then send the first relation to the computing device. The computing device can then receive the first relation from the service device. It is understood that the process of the service device determining the first relation can be seen in the data processing method shown in Figure 5, and will not be elaborated here.

[0158] Example 3: The first relation is determined by the computing device. Here, the first relation is determined by the computing device based on the model computation graph included in the computation model.

[0159] For example, the computing device can determine the cache line length corresponding to each operator among the multiple operators included in the computation model based on the model computation graph. Then, the computing device can generate a first relation based on the cache line length corresponding to each of the multiple operators. That is, the computing device can establish a mapping relationship between each of the multiple operators and its corresponding cache line length, thereby generating the first relation.

[0160] It is understandable that the process by which the computing device determines the cache line length corresponding to each of the multiple operators included in the computing model based on the model computing graph can be referred to the relevant description in step 502 below, and will not be repeated here.

[0161] The following describes the implementation process of the computing device determining the length of the first cache line corresponding to the first operator based on the first relation through several possible implementation methods.

[0162] Implementation Method 1: If the first relation is used to describe the mapping relationship between the operator type of the operator and the cache line length, the computing device can determine the first cache line length corresponding to the operator type of the first operator from the first relation.

[0163] For example, taking the first operator as a convolution operator, and the operator type of the convolution operator as type A, when the first relation is used to describe the mapping relationship between the operator type and the cache line length, the computing device can determine the cache line length 'a' corresponding to type A from the first relation.

[0164] Implementation Method 2: If the first relation is used to describe the mapping relationship between the operator identifier of the operator and the cache line length, the computing device can determine the first cache line length corresponding to the operator identifier of the first operator from the first relation.

[0165] For example, taking the first operator as a convolution operator and the operator identifier of the convolution operator as identifier d, when the first relation is used to describe the mapping relationship between the operator identifier and the cache line length, the computing device can determine the cache line length a corresponding to identifier d from the first relation.

[0166] Implementation Method 3: If the first relation is used to describe the mapping relationship between the operator name of the operator and the cache line length, the computing device can determine the first cache line length corresponding to the operator name of the first operator from the first relation.

[0167] For example, taking the first operator as a convolution operator, and the operator name of the convolution operator as conv_0, when the first relation is used to describe the mapping relationship between the operator name and the cache line length, the computing device can determine the cache line length 'a' corresponding to conv_0 from the first relation.

[0168] Optionally, the first relation can also be used to represent a cache line length configuration table. This cache line length configuration table includes the cache line lengths corresponding to the operator identifiers (or operator names or operator types) of multiple operators. In other words, the cache line length configuration table can be understood as describing the mapping relationship between the operator identifiers (or operator names or operator types) of multiple operators and their respective cache line lengths. When the first relation is used to represent the cache line length configuration table, the computing device can also determine the first cache line length from the cache line length configuration table based on the operator identifier (or operator name or operator type) of the first operator.

[0169] Step 303: The computing device determines the data stored in at least one first cache line corresponding to the first cache line length based on the first cache line length.

[0170] In this embodiment of the application, after obtaining the length of the first cache line corresponding to the first operator, the computing device can determine the data corresponding to the first operator (such as the data required to execute the operation process of the first operator) from at least one first cache line corresponding to the length of the first cache line.

[0171] Optionally, before determining the data corresponding to the first operator from at least one first cache line corresponding to the first cache line length, the computing device may determine at least one first cache line corresponding to the first operator. The length of each first cache line in the at least one first cache line corresponding to the first operator is the first cache line length. In one example, the computing device may partition the cache (or virtually partition the cache) according to the first cache line length corresponding to the first operator to obtain at least one first cache line corresponding to the first operator. In another example, the computing device may reallocate cache lines in the cache according to the first cache line length corresponding to the first operator to obtain at least one first cache line corresponding to the first operator.

[0172] For example, consider a computing device partitioning the cache based on the length of the first cache line corresponding to the first operator. Assume the first operator is an addition operator, the cache line length corresponding to the addition operator is 512 bytes, and the cache space size is 3072 bytes. After obtaining the cache line length of 512 bytes corresponding to the formic acid addition operator, the computing device can partition the cache according to this length, resulting in six cache lines, as shown in Figure 4: cache line 1, cache line 2, cache line 3, cache line 4, cache line 5, and cache line 6.

[0173] The following examples illustrate the process by which a computing device determines the data corresponding to the first operator from at least one first cache line corresponding to the first cache line length, based on the first cache line length.

[0174] In example a: When the cache stores the data corresponding to the first operator (which can be understood as at least one first cache line storing the data corresponding to the first operator), the computing device can retrieve the data corresponding to the first operator from at least one first cache line in the cache.

[0175] In example b: When the cache does not contain the data corresponding to the first operator, the computing device can send a third request to the mass storage device (e.g., DDR). This third request requests the data corresponding to the first operator based on the first cache line length. For example, the third request may include the first cache line length. After receiving the third request, the mass storage device can send at least one piece of data with the first cache line length to the computing device. The data corresponding to the first operator is contained within at least one piece of data with the first cache line length (this can be understood as at least one piece of data with the first cache line length being the data corresponding to the first operator, or it can be understood as at least one piece of data with the first cache line length including the data corresponding to the first operator). After receiving at least one piece of data with the first cache line length, the computing device can store the at least one piece of data with the first cache line length into at least one first cache line in the cache. Then, the computing device can read the data corresponding to the first operator from the at least one first cache line in the cache.

[0176] As can be seen from steps 301 to 303 above, the computing device can flexibly determine the length of the first cache line corresponding to (or matching, suitable, or reasonable) the first operator based on the first relationship, and can adjust the length of the cache lines included in the cache in a timely manner based on the length of the first cache line (which can be understood as re-dividing the cache lines included in the cache based on the length of the first cache line, or it can also be understood as re-blocking the cache based on the length of the first cache line (or reallocating the cache lines in the cache based on the length of the first cache line)), so that the length of the adjusted cache line in the cache can match the first operator and meet the actual needs of the first operator (such as the continuous data read and write needs or the discrete data read and write needs corresponding to the first operator). In this way, the method can dynamically adjust the cache lines in the cache based on the cache line length corresponding to each operator (or any one of the operators). This ensures that when executing the operation process of each operator, the length of the cache lines in the cache can be matched with that operator in a timely manner. This allows for flexible adjustment of the cache line length (flexibly determining the cache line length corresponding to any operator so as to effectively execute the data read and write operations corresponding to that operator). It ensures that the cache line length corresponding to any operator matches the data size required for the operation of that operator, thus making effective use of the cache line length corresponding to that operator. Therefore, it can help improve the effective utilization of bandwidth while improving the cache hit rate.

[0177] Figure 5 illustrates a flowchart of another data processing method provided in an embodiment of this application. This method can be applied, but is not limited to, the application scenario shown in Figure 1. It is understood that the data processing method shown in Figure 5 is illustrated using a service device as the execution subject, but this application does not limit the execution subject in the interactive illustration. It should be understood that the method executed by the service device in this application can also be executed by a module applied to the service device (such as a processor, processing unit, chip, chip system, or circuit), and can also be implemented by a logic node, logic module, or software capable of implementing all or part of the functions of the service device.

[0178] As shown in Figure 5, the method includes:

[0179] Step 501: The service device obtains the computational model.

[0180] For example, the service device can read the model file of the computational model from a local database (or local cache or local memory, etc.), or it can obtain the model file of the computational model from the service device, or it can directly input the model file of the computational model through an external input device. This application embodiment does not limit the method by which the service device obtains the computational model.

[0181] The specific description of the calculation model in step 501 can be found in the relevant introduction of the calculation model in step 301 above, and will not be repeated here.

[0182] Step 502: The service device determines the cache line length corresponding to each operator among the multiple operators based on the model calculation diagram.

[0183] The specific description of the model calculation graph in step 502 can be found in the relevant introduction of the calculation model in step 301 above, and will not be repeated here.

[0184] For example, in one example, the computational model includes a computational graph, which can be seen in Figure 6a. In Figure 6a, the computational graph includes two gather operators, one convolution operator (e.g., the convolution2D operator), and one add operator. The computational graph also includes operator information for each of these four operators. It should be understood that the operator information for each of these four operators is not shown in Figure 6a. The specific description of the operator information in step 502 can be found in the relevant introduction to operator information in step 301 above, and will not be repeated here.

[0185] In another example, the computational model includes a computational graph, which can be seen in Figure 6b. In Figure 6b, the computational graph includes three convolution operators, three sigmoid operators, and two Mul operators. The computational graph also includes operator information for each of these eight operators. For example, consider the first convolution operator shown in Figure 6b. The operator information for this convolution operator can include the operator type (convolution operator), the operator name (e.g., conv_0), the operator's attributes (e.g., dilations, group, kernel_shape, pads, and strides), the input data information (e.g., the input data size, weight, and bias), or the output data information (e.g., the output data size).

[0186] The following describes the process by which the service device determines the cache line length corresponding to each operator among multiple operators based on the model computation graph, using several possible implementation methods.

[0187] Method 1: The service device can determine the operator type of each operator among the multiple operators included in the computation model based on the model computation graph. Then, the service device can determine the cache line length corresponding to each operator based on the operator type of each operator among the multiple operators.

[0188] For example, let's take any one of multiple operators (such as the third operator) as an example to illustrate how a service device determines the operator type of each operator among multiple operators. In one example, the service device can determine the matching degree between the operator type of the third operator and the multiple operator types included in the operator type table (also known as the operator type whitelist). If the matching degree (or similarity) between the operator type of the third operator and the first operator type included in the operator type table is greater than or equal to the matching degree threshold (or similarity threshold), then the service device can determine the first operator type as the operator type of the third operator. For example, when determining the matching degree between the operator type of the third operator and the multiple operator types included in the operator type table, the service device can use a similarity algorithm (also known as a matching degree algorithm, such as the cosine similarity algorithm or the Euclidean distance similarity algorithm), or it can use a similarity model (such as a text semantic similarity model).

[0189] In another example, the service device can also query the operator type table to determine if the operator type of the third operator exists. If it does, the service device can determine the operator type of the third operator.

[0190] Method 2: The service device can traverse the model computation graph to obtain the operator information for each operator among the multiple operators included in the computation model. Then, the service device can obtain the operator type for each operator from the operator information of each operator among the multiple operators. In one example, the service device can directly determine the cache line length corresponding to each operator based on the operator type of each operator among the multiple operators.

[0191] In another example, for each of the multiple operators, the service device can also query the operator type table to determine if the operator type exists in the table. If it exists, the service device can determine the cache line length corresponding to the operator based on the operator type.

[0192] In another example, for each of multiple operators, the service device can also compare the operator type of that operator with each operator type included in the operator type table. If the similarity (or matching degree) between the operator type of that operator and an operator type in the operator type table is greater than or equal to a similarity threshold (or matching degree threshold), the service device can use that operator type in the operator type table as the operator type of that operator. Then, the service device can determine the cache line length corresponding to that operator based on its operator type. For example, when comparing the operator type of a given operator with each operator type included in the operator type table, the service device can use a similarity algorithm (such as a cosine similarity algorithm or a Euclidean distance similarity algorithm), or it can use a similarity model (such as a text semantic similarity model).

[0193] The following section uses any one of multiple operators (such as the third operator) as an example to illustrate how to determine the cache line length corresponding to each operator based on the operator type of each operator in the multiple operators in several possible ways.

[0194] Method a: If the operator type of the third operator is a mathematical calculation type, the service device can determine that the cache line length corresponding to the third operator is the third cache line length.

[0195] For example, consider the third operator as the convolution operator shown in Figure 6a. The operator type of the convolution operator shown in Figure 6a is a mathematical calculation type. Since the convolution operator is a mathematical calculation type, it requires continuous data reading and writing. Therefore, the server can configure the cache line length corresponding to the convolution operator shown in Figure 6a to a larger cache line length (or the maximum cache line length available to the operating system) (e.g., 512B), as shown in Figure 7.

[0196] For example, consider the Add operator shown in Figure 6a above as the third operator. The Add operator in Figure 6a is a mathematical calculation type. Since the Add operator is a mathematical calculation type, it requires continuous data reading and writing. Therefore, the service device can configure the cache line length corresponding to the Add operator shown in Figure 6a to a larger cache line length (or the maximum cache line length available to the operating system) (e.g., 512B), as shown in Figure 7.

[0197] Method b: If the operator type of the third operator is a data transport type, the service device can determine the cache line length corresponding to the third operator as the third cache line length based on the data index corresponding to the third operator.

[0198] In one possible implementation, if the data index corresponding to the third operator is a preset value, the service device can determine the cache line length corresponding to the third operator based on the distribution of the data index corresponding to the third operator.

[0199] The following examples illustrate the process by which the service device determines the cache line length corresponding to the third operator based on the distribution of the data index corresponding to the third operator.

[0200] Example 1: If the data index corresponding to the third operator is continuously distributed, the service device can determine that the cache line length corresponding to the third operator is the fourth cache line length.

[0201] Example 2: If the data index corresponding to the third operator is discretely distributed, the service device can determine the cache line length corresponding to the third operator as the fifth cache line length based on the input and output data size of the third operator. The fifth cache line length is different from the fourth cache line length.

[0202] For example, consider the `gather` operator as the third operator. The `gather` operator's operator type is data transport. When the `gather` operator's operator type is data transport, if the data indices corresponding to the `gather` operator are preset values ​​(also called pre-configured values, which can be understood as fixed or known values), the service device can determine the histogram of the data indices (which can be understood as a histogram determined based on the statistics of the data indices corresponding to the `gather` operator). Then, the service device can determine the distribution of the data indices based on the histogram. If the data index distribution is continuous (also called continuous data index distribution), the service device can configure the cache line length corresponding to the `gather` operator to a larger cache line length (or the maximum cache line length available to the operating system) (e.g., 512 bytes). For example, consider the histogram of the data indices corresponding to the `gather` operator shown in Figure 8. As shown in Figure 8, the value range of the data index is concentrated between 20,000 and 40,000. Therefore, according to Figure 8, the distribution of the data index corresponding to the gather operator is a continuous distribution.

[0203] It is understandable that the input and output data information corresponding to the `gather` operator includes the data index information corresponding to the `gather` operator. The service device can determine whether the data index corresponding to the `gather` operator is a preset value or a non-preset value based on the data index information. For example, when the `kind` value included in the data index information corresponding to the `gather` operator is `initializer`, the service device can determine that the data index corresponding to the `gather` operator is a preset value. When the `kind` value included in the data index information corresponding to the `gather` operator is not `initializer` (or the `kind` value included in the data index information corresponding to the `gather` operator is empty), the service device can determine that the data index corresponding to the `gather` operator is a non-preset value.

[0204] If the data index is distributed discretely (also known as discrete data index distribution), the service device can obtain the input and output data size corresponding to the gather operator from the operator information of the gather operator, and determine the cache line length corresponding to the gather operator to be a cache line length that matches (or corresponds to) the input and output data size corresponding to the gather operator.

[0205] For example, consider the first gather operator (e.g., gather operator 1) shown in Figure 6a. The input / output data size for this first gather operator is 1*64*1000*640. Here, 1 represents one batch, 64 represents 64 channels, 1000 represents a height of 1000, and 640 represents a width of 640. Each channel corresponds to 2 bytes of half-precision floating-point (fp16) data. Therefore, for the first gather operator, each batch reads 64 fp16 data points, totaling 128 bytes. In this way, the service device can configure the cache line length corresponding to the first gather operator to 128B, as shown in Figure 7.

[0206] For example, consider the second gather operator (e.g., gather operator 2) shown in Figure 6a. The input / output data size for this second gather operator is 1*32*256*640. Here, 1 represents one batch, 32 represents 32 channels, 256 represents a height of 256, and 640 represents a width of 640. Each channel's data belonging to fp16 occupies 2 bytes. Therefore, for the second gather operator, 32 fp16 data (64 bytes total) are read per cycle. The server can then configure the buffer line length for the second gather operator to 64 bytes, as shown in Figure 7.

[0207] In one possible implementation, if the data index corresponding to the third operator is not a preset value, the service device can determine the cache line length corresponding to the fourth operator as the cache line length corresponding to the third operator. The output data corresponding to the fourth operator is used as the input data for the third operator.

[0208] For example, consider the second `gather` operator (e.g., `gather` operator 2) shown in Figure 6a as the third operator. If the data index corresponding to the second `gather` operator shown in Figure 6a is a non-preset value (also known as a non-pre-configured value, which can be understood as a calculated value, a non-fixed value, or a non-known value), the service device can determine that the cache line length configuration strategy of the second `gather` operator shown in Figure 6a follows (or reuses) the cache line length configuration strategy of the previous layer operator. That is, the cache line length corresponding to the second `gather` operator shown in Figure 6a continues to use the cache line length of the previous layer operator. For example, if the previous layer operator of the second `gather` operator shown in Figure 6a is the `convolution` operator, then when the service device determines that the data index corresponding to the second `gather` operator shown in Figure 6a is a non-preset value, it can use the cache line length corresponding to the `convolution` operator (e.g., 512B) as the cache line length corresponding to the second `gather` operator shown in Figure 6a.

[0209] Step 503: The service device generates the first relation based on the cache line length corresponding to each operator among the multiple operators.

[0210] In this embodiment of the application, after determining the cache line length corresponding to each of the multiple operators included in the Dedao computing model, the service device can generate a first relation (or generate a cache line length configuration table) based on the cache line length corresponding to each of the multiple operators.

[0211] The first relation can be used to describe the mapping between operators and cache line lengths. In other words, the first relation can be used to describe the mapping between at least one operator and its corresponding cache line length. That is to say, the first relation can include at least one mapping relationship.

[0212] For example, consider a first relation that includes two mapping relations (e.g., a first mapping relation and a second mapping relation). The first mapping relation describes the mapping between a first operator and a first cache line length, and the second mapping relation describes the mapping between a second operator and a second cache line length. Optionally, the second operator and the first operator can be different or the same. For instance, if the first operator and the second operator are contained in the same computational model, then the first operator and the second operator are different. If the first operator and the second operator are contained in different computational models, then the first operator and the second operator can be the same, or the first operator and the second operator can be different.

[0213] The cache line length configuration table describes the mapping relationship between the operator identifiers (or operator names or operator types) of multiple operators and their respective cache line lengths. In other words, the cache line length configuration table includes the cache line length corresponding to the operator identifier (or operator name or operator type) of each of the multiple operators.

[0214] Optionally, after the service device generates the first relation or cache line length configuration table, developers can deploy the first relation or cache line length configuration table on the computing device, or they can deploy it on the control device where the computing device resides. For example, the control device can be a vehicle controller, a cockpit domain controller, a vehicle dynamics controller, or an intelligent driving computing platform, etc.

[0215] Optionally, after generating the first relation or cache line length configuration table, the service device can send the first relation or cache line length configuration table to the computing device, or it can send the first relation or cache line length configuration table to the control device where the computing device is located.

[0216] As can be seen from steps 501 to 503 above, the service device accurately classifies the multiple operators included in the computation model and can reasonably configure corresponding cache line lengths for operators of different operator types. This ensures that the cache line length corresponding to any operator type matches the actual needs of that operator type. In this way, when executing the inference process of the computation model, the cache line length required for data reading and writing can be flexibly adjusted based on each operator type. This ensures that the cache line length corresponding to any operator matches the data size required for the operation of that operator, thus making effective use of the cache line length corresponding to that operator. Therefore, it can help improve the effective utilization of bandwidth while increasing the cache hit rate.

[0217] It should be noted that in the description of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, and C" includes A, B, C, AB, AC, BC, or ABC. Furthermore, unless otherwise specified, the ordinal numbers "first," "second," "third," etc., mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects. In addition, the terms "including," "comprising," "having," and their variations appearing in this application all mean "including but not limited to," unless otherwise specifically emphasized.

[0218] Furthermore, it should be noted that each step in the above embodiments can be executed by the corresponding device, or by components such as chips, processors, or chip systems within that device. This application does not limit the scope of these steps. The above embodiments are only illustrated by examples of execution by the corresponding device.

[0219] It should be noted that in the above embodiments, some steps may be selected for implementation, and the order of the steps in the figures may be adjusted. This application does not limit this. It should be understood that performing some of the steps in the figures, adjusting the order of the steps, or combining them in a specific implementation all fall within the protection scope of this application.

[0220] It is understood that, in order to achieve the functions described in the above embodiments, each device involved in the above embodiments includes a hardware structure and / or software module corresponding to perform each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0221] It should be noted that the "steps" in the embodiments of this application are merely illustrative and are intended to better understand one method of presentation used in the embodiments. They do not constitute a substantial limitation on the execution of the solution of this application. For example, the "step" can also be understood as a "feature". Furthermore, the steps do not constitute any limitation on the execution order of the solution of this application. Any changes to the order of steps, or the merging or splitting of steps made on this basis without affecting the overall solution implementation, resulting in a new technical solution, are also within the scope of disclosure of this application.

[0222] The following are schematic diagrams of possible data processing apparatuses provided in embodiments of this application. These data processing apparatuses can be used to implement the functions of computing devices or service devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. In the embodiments of this application, the data processing apparatus can be a computing device (also referred to as a first data processing apparatus) or a service device (also referred to as a second data processing apparatus), or it can be a module (such as a processor) applied to a computing device or service device.

[0223] As shown in Figure 9, the data processing device 900 includes a transceiver module 901 (or a communication module or transceiver unit, used for sending and receiving data) and a processing module 902 (or a processing unit). The data processing device 900 implements the functions of the computing device or service device in the method embodiment shown in Figure 1. For example, the transceiver module 901 can perform the receiving and sending actions performed by the computing device or service device in the method embodiment. The processing module 902 can perform other actions besides the sending and receiving actions performed by the computing device or service device in the method embodiment.

[0224] Optionally, the transceiver module 901 may include a receiving module and / or a transmitting module. The receiving module can be used by the data processing device 900 to receive signals (or information or data, etc.); the transmitting module can be used by the data processing device 900 to transmit signals (or information or data, etc.). The transmitting module can transmit signals (or information or data, etc.) under the control of the processing module 902, and the receiving module can receive signals (or information or data, etc.) under the control of the processing module 902.

[0225] When the data processing device 900 is used to implement the functions of the computing device in the method embodiment shown in FIG3 above: the transceiver module 901 is used to obtain a first operator. The first operator is included among multiple operators, and the multiple operators are included in the computing model. The processing module 902 is used to determine the length of a first cache line corresponding to the first operator according to a first relationship. The first relationship describes the mapping relationship between the operator and the cache line length. The processing module 902 is also used to determine the data stored in at least one first cache line corresponding to the first cache line length, based on the first cache line length.

[0226] When the data processing device 900 is used to implement the function of the service device in the method embodiment shown in Figure 5 above: the transceiver module 901 is used to obtain a computational model. The computational model may include a model computation graph, which describes the topological connection relationships of multiple operators. The processing module 902 is used to determine the cache line length corresponding to each of the multiple operators based on the model computation graph. The processing module 902 is also used to generate a first relationship based on the cache line length corresponding to each of the multiple operators.

[0227] For a more detailed description of the transceiver module 901 and the processing module 902, please refer to the relevant descriptions in the method embodiments shown in Figure 3 or Figure 5 above, which will not be repeated here.

[0228] It should be understood that the transceiver module 901 in the embodiments of this application can be implemented by a communication interface or communication interface-related circuit components, and the processing module 902 can be implemented by a processor or processor-related circuit components.

[0229] It should be noted that the module division in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical entities, or have two or more units integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0230] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, or a server, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0231] The data processing apparatus 1000 shown in Figure 10 includes a processor 1002 and a communication interface 1001. The processor 1002 and the communication interface 1001 are coupled to each other. It is understood that the communication interface 1001 can be a transceiver or an input / output interface. Optionally, the data processing apparatus 1000 may further include a memory 1003 for storing instructions executed by the processor 1002, or storing input data required by the processor 1002 to execute instructions, or storing data generated after the processor 1002 executes instructions.

[0232] When the data processing device 1000 is used to implement the method embodiment shown in FIG3 or FIG5, the processor 1002 is used to implement the function of the processing module 902, and the communication interface 1001 is used to implement the function of the transceiver module 901.

[0233] Optionally, the communication interface 1001, processor 1002, and memory 1003 are interconnected via bus 1004. Bus 1004 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 10, but this does not indicate that there is only one bus or one type of bus.

[0234] Communication interface 1001 is used for receiving and sending data. For example, when the data processing device 1000 is a computing device as partially described in FIG1, communication interface 1001 can communicate with the service device 200 shown in FIG1, or it can communicate with other devices outside the application scenario shown in FIG1 (such as terminal devices, other vehicles, or vehicle servers). In one example, the communication interface can be a transceiver device with integrated data transmission and reception functions. In another example, the communication interface can also consist of a transmitter and a receiver, wherein the transmitter is used to send data and the receiver is used to receive data.

[0235] Optionally, the communication interface 1001 may include a transmitter and / or a receiver. The transmitter is used to send signals, messages, information, or data, etc. The receiver is used to receive signals, messages, information, or data, etc. Exemplarily, the transmitter sends signals, messages, information, or data, etc., under the control of the processor 1002. The receiver receives signals, messages, information, or data, etc., under the control of the processor 1002.

[0236] The functions of processor 1002 can be referred to the descriptions of the corresponding functions involved in the computing device or service device in the above embodiments, and will not be repeated here. Processor 1002 can be a central processing unit (CPU), a network processor (NP), or a combination of CPU and NP, etc. Processor 1002 may further include hardware chips. The aforementioned hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs can be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. When implementing the above functions, processor 1002 can be implemented through hardware, or it can be implemented by hardware executing corresponding software.

[0237] Memory 1003 is used to store program instructions, etc. Specifically, program instructions may include program code, which includes computer operation instructions. Memory 1003 may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Processor 1002 executes the program instructions stored in memory 1003 to implement the above-mentioned functions, thereby implementing the method steps required to be executed by the computing device or service device in the above embodiments.

[0238] Based on the same concept, this application also provides a control device, which may include the computing device involved in the above method embodiments. The computing device is used to implement the technical solutions involved in the computing device in the above method embodiments. For example, the control device may be a vehicle controller, a cockpit domain controller, a vehicle dynamics controller, or an intelligent driving computing platform, etc.

[0239] Based on the same concept, embodiments of this application also provide a vehicle that may include the aforementioned control device.

[0240] Based on the same concept, this application also provides a computer program product, which includes a computer program or instructions that, when run on a computer, cause the computer to perform the methods provided in the above embodiments.

[0241] Based on the same concept, embodiments of this application also provide a computer-readable storage medium storing a computer program or instructions, which, when executed by a computer, causes the computer to perform the methods provided in the above embodiments.

[0242] The storage medium can be any available medium that a computer can access. For example, but not limited to, a computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

[0243] Based on the same concept, embodiments of this application also provide a chip, which may include a processor and a memory (or the chip may be coupled to the memory). The chip executes program instructions in the memory to perform the methods provided in the above embodiments. Here, "coupling" refers to two components being directly or indirectly connected to each other; for example, coupling can refer to an electrical connection between two components.

[0244] Based on the same concept, embodiments of this application also provide a chip system, which includes a processor for supporting a computer device in implementing the functions involved in the computing device or service device in the above embodiments. In one possible implementation, the chip system further includes a memory for storing programs and data necessary for the computer device. This chip system may be composed of chips or may include chips and other discrete components.

[0245] The methods provided in this application can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0246] The steps of the methods described in the embodiments of this application can be directly embedded in hardware, a software unit executed by a processor, or a combination of both. The software unit can be stored in RAM, ROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and the storage medium can be housed in an ASIC.

[0247] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0248] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0249] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data processing method, characterized in that, Applied to a computing device, the method includes: Obtain a first operator, which is included in a plurality of operators, and the plurality of operators are included in a computational model; Based on the first relation, the first cache line length corresponding to the first operator is determined, and the first relation is used to describe the mapping relationship between the operator and the cache line length; Based on the length of the first cache line, determine the data stored in at least one first cache line corresponding to the length of the first cache line.

2. The method as described in claim 1, characterized in that, The first relationship includes a first mapping relationship and a second mapping relationship. The first mapping relationship describes the mapping relationship between the first operator and the first cache line length, and the second mapping relationship describes the mapping relationship between the second operator and the second cache line length. The second operator is included in the plurality of operators.

3. The method as described in claim 1 or 2, characterized in that, The first relationship is determined based on the model computation graph included in the computation model, which is used to describe the topological connection relationship of multiple operators.

4. The method according to any one of claims 1-3, characterized in that, Based on the first relation, the length of the first cache line corresponding to the first operator is determined, including: If the first relation describes the mapping between the operator type and the cache line length, then the first cache line length corresponding to the operator type of the first operator is determined from the first relation; or, If the first relation describes the mapping between the operator identifier and the cache line length, then the first cache line length corresponding to the operator identifier of the first operator is determined from the first relation; or, If the first relation is used to describe the mapping relationship between the operator name of the operator and the cache line length, then the first cache line length corresponding to the operator name of the first operator is determined from the first relation.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: The at least one first cache line is determined, wherein the length of each first cache line in the at least one first cache line is the length of the first cache line.

6. The method as described in claim 5, characterized in that, Determining the at least one first cache line includes: Based on the length of the first cache line, the cache is divided to obtain at least one first cache line.

7. The method according to any one of claims 1-6, characterized in that, The first relationship is pre-configured.

8. The method according to any one of claims 1-6, characterized in that, Before determining the length of the first cache line corresponding to the first operator, the method further includes: Receive the first relationship from the service device.

9. The method according to any one of claims 1-8, characterized in that, Each of the plurality of operators is an operator of one of the following operator types: mathematical calculation type, data transfer type.

10. A data processing method, characterized in that, Applied to a service device, the method includes: Obtain a computational model, which includes a model computational graph and is used to describe the topological connection relationships of multiple operators; Based on the model calculation graph, determine the cache line length corresponding to each of the plurality of operators; The first relation is generated based on the cache line length corresponding to each of the plurality of operators.

11. The method as described in claim 10, characterized in that, The first relationship includes a first mapping relationship and a second mapping relationship. The first mapping relationship describes the mapping relationship between a first operator and a first cache line length, and the second mapping relationship describes the mapping relationship between a second operator and a second cache line length. The first operator and the second operator are included in the plurality of operators.

12. The method as described in claim 10 or 11, characterized in that, Based on the model computation graph, the cache line length corresponding to each of the plurality of operators is determined, including: Based on the model calculation diagram, determine the operator type of each of the plurality of operators; The cache line length corresponding to each operator is determined based on the operator type of each of the multiple operators.

13. The method as described in claim 12, characterized in that, The model computation graph includes operator information for the plurality of operators, and the operator information for each operator in the plurality of operators includes the operator type of the operator; Based on the model computation graph, determine the operator type of each of the plurality of operators, including: Determine the matching degree between the operator type of the third operator and the multiple operator types included in the operator type table, wherein the third operator is any one of the multiple operators; If the matching degree between the operator type of the third operator and the first operator type included in the operator type table is greater than or equal to the matching degree... If the threshold is reached, then the first operator type is determined as the operator type of the third operator.

14. The method as described in claim 13, characterized in that, The operator information for each of the plurality of operators also includes the data index and input / output data size corresponding to the operator; Based on the operator type of each of the multiple operators, determine the cache line length corresponding to each operator, including: If the operator type of the third operator is a mathematical calculation type, then the cache line length corresponding to the third operator is determined to be the third cache line length; or, If the operator type of the third operator is a data transport type, then the cache line length corresponding to the third operator is determined according to the data index corresponding to the third operator.

15. The method as described in claim 14, characterized in that, Based on the data index corresponding to the third operator, the cache line length corresponding to the third operator is determined, including: If the data index corresponding to the third operator is a preset value, then the cache line length corresponding to the third operator is determined based on the distribution of the data index corresponding to the third operator; or, If the data index corresponding to the third operator is not a preset value, then the cache line length corresponding to the fourth operator is determined as the cache line length corresponding to the third operator, and the output data corresponding to the fourth operator is used as the input data of the third operator.

16. The method as described in claim 15, characterized in that, Based on the distribution of the data indexes corresponding to the third operator, the cache line length corresponding to the third operator is determined, including: If the data index corresponding to the third operator is continuously distributed, then the cache line length corresponding to the third operator is determined to be the fourth cache line length; or, If the distribution of the data index corresponding to the third operator is discrete, then the cache line length corresponding to the third operator is determined as the fifth cache line length based on the size of the input and output data corresponding to the third operator. The fifth cache line length is different from the fourth cache line length.

17. The method according to any one of claims 10-16, characterized in that, After generating the first relation, the method further includes: Send the first relationship to the computing device.

18. A computing device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1-9.

19. A service device, characterized in that, Includes modules or units for performing the method as described in any one of claims 10-17.

20. A control device, characterized in that, Includes a computing device for performing the method as described in any one of claims 1-9.

21. The control device as described in claim 20, characterized in that, The control device is one of the following: a vehicle controller, a cockpit domain controller, a vehicle dynamics controller, or an intelligent driving computing platform.

22. A vehicle, characterized in that, Includes the control device as described in claim 20 or 21.

23. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed by a computer, cause the method described in any one of claims 1-17 to be implemented.

24. A computer program product, characterized in that, The computer program product includes a computer program or instructions that, when executed on a computer, cause the method as described in any one of claims 1-17 to be implemented.

25. A chip, characterized in that, The chip includes a processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to implement the method as described in any one of claims 1-17.

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