Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. A light-shielding layer of the display panel comprises a first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern which are spaced apart in a first direction. A first light-shielding portion on the first light-shielding pattern can shield a first active portion, a second light-shielding portion on the second light-shielding pattern can shield a third active portion, and a third light-shielding portion on the third light-shielding pattern can shield a fourth active portion.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display devices, the requirements for power consumption and screen-to-body ratio are becoming increasingly stringent. To reduce power consumption and increase screen-to-body ratio, existing display devices employ Low Temperature Polysilicon Oxide (LTPO) technology. LTPO technology refers to the simultaneous use of low temperature polysilicon thin-film transistors (LTPTs) and oxide thin-film transistors (OTPTs), allowing the driving circuit to combine the advantages of both LTPTs and OPTs, thereby reducing power consumption and leakage current.

[0003] Existing display devices using LTPO technology have a large number of film layers, requiring a correspondingly large number of photomasks, resulting in complex manufacturing processes and high costs. To reduce the number of photomasks, existing display devices remove some gate layers and insulating layers, but this leads to the absence of the bottom gate of the oxide thin-film transistor, degrading the photosensitivity and electrical properties of the thin-film transistor.

[0004] Therefore, existing display devices using LTPO technology suffer from technical problems such as deteriorated photosensitivity and electrical properties due to the lack of a bottom gate in oxide thin-film transistors. Invention Overview

[0005] This application provides a display panel and a display device to alleviate the technical problem of degraded photosensitivity and electrical properties caused by the lack of bottom gate of oxide thin film transistors in existing display devices using LTPO technology.

[0006] The technical solution provided in this application is as follows:

[0007] In a first aspect, embodiments of this application provide a display panel, which includes a substrate and a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a driving transistor, a switching transistor, a compensation transistor, and a first initialization transistor. The switching transistor is connected to the driving transistor at a first node. One electrode of the compensation transistor and one electrode of the first initialization transistor are connected to the driving transistor at a second node. The other electrode of the compensation transistor is connected to the driving transistor at a third node. The gate of the compensation transistor is connected to a first scan signal line, and the gate of the first initialization transistor is connected to a second scan signal line. The display panel further includes:

[0008] A light-shielding layer is disposed on one side of the substrate;

[0009] A first semiconductor layer is disposed on the side of the light-shielding layer away from the substrate, and the first semiconductor layer includes a first active portion of the driving transistor and a second active portion of the switching transistor;

[0010] A second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate. The second semiconductor layer includes a third active portion of the compensation transistor and a fourth active portion of the first initialization transistor.

[0011] The light-shielding layer includes a first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern spaced apart in a first direction. The first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern all extend along a second direction, which is different from the first direction. The second light-shielding pattern is connected to the first scanning signal line, and the third light-shielding pattern is connected to the second scanning signal line. The first light-shielding pattern includes a first light-shielding part corresponding to the first active part, the second light-shielding pattern includes a second light-shielding part corresponding to the third active part, and the third light-shielding pattern includes a third light-shielding part corresponding to the fourth active part.

[0012] Secondly, embodiments of this application also provide a display device, the display device including a display panel as described in one of the foregoing embodiments. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 is a schematic diagram of the first type of contrast display device provided in the embodiments of this application.

[0015] Figure 2 is a schematic diagram of a second type of contrast display device provided in an embodiment of this application.

[0016] Figure 3 is a schematic diagram of a third type of comparison display device provided in an embodiment of this application.

[0017] Figure 4 is a schematic diagram of the film layer of the display panel provided in the embodiment of this application.

[0018] Figure 5 is a circuit diagram of the sub-pixels of the display panel provided in an embodiment of this application.

[0019] Figure 6 is a first type of stacking diagram of some film layers of the display panel provided in the embodiment of this application.

[0020] Figure 7 is an exploded view of the light-shielding layer of the display panel in Figure 6.

[0021] Figure 8 is an exploded view of the first semiconductor layer of the display panel in Figure 6.

[0022] Figure 9 is a schematic diagram of the stacking of the first semiconductor layer in Figure 8 and the light-shielding layer in Figure 7.

[0023] Figure 10 is an exploded view of the first gate layer of the display panel in Figure 6.

[0024] Figure 11 is a schematic diagram of the stacking of the first gate layer in Figure 10 and the structure in Figure 9.

[0025] Figure 12 is an exploded view of the second semiconductor layer of the display panel in Figure 6.

[0026] Figure 13 is a schematic diagram of the stacking of the second semiconductor layer in Figure 12 and the structure in Figure 11.

[0027] Figure 14 is an exploded view of the second gate layer of the display panel in Figure 6.

[0028] Figure 15 is a schematic diagram of the stacking of the second gate layer in Figure 14 and the structure in Figure 13.

[0029] Figure 16 is an exploded view of the first source-drain layer of the display panel in Figure 6.

[0030] Figure 17 is a schematic diagram of the stacking of the first source-drain layer in Figure 16 and the structure in Figure 15.

[0031] Figure 18 is an exploded view of the second source-drain layer of the display panel in Figure 6. Embodiments of the present invention

[0032] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.

[0033] Please refer to Figures 1 to 3 as an introduction to the embodiments of this application, and provide some contrast display devices. Figure 1 is a schematic diagram of the first type of contrast display device provided in the embodiments of this application, Figure 2 is a schematic diagram of the second type of contrast display device provided in the embodiments of this application, and Figure 3 is a schematic diagram of the third type of contrast display device provided in the embodiments of this application. Referring to Figure 1, a contrast display device employing LTPO technology includes a substrate 101, a light-shielding film 102, a blocking film 103, a buffer film 104, a low-temperature polycrystalline silicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarization film 117, a second source-drain film 118, a second planarization film 119, a third source-drain film 121, a third planarization film 122, an anode film 123, a pixel definition film 124, and a support film 125. As can be seen from Figure 1, the contrast display device includes three source-drain films and three gate films, requiring 16 photomasks for its formation, resulting in a complex process and high cost.

[0034] To address the issue of complex manufacturing processes in contrast display devices, another type of contrast display device removes one of the gate film and insulating film layers, as shown in Figure 2. It can be seen that the second gate film 109 and the second gate insulating film 108 are removed in the contrast display device, which can reduce the number of photomasks to 14. However, the problem of a large number of photomasks, complex manufacturing processes, and high costs still exists.

[0035] To address the complexity of the manufacturing process in contrast display devices, another type of contrast display device further removes a source / drain film and an insulating film, as shown in Figure 3. By removing the third source / drain film 121 and the third planarization film 122, the number of photomasks can be reduced to 13. However, as can be seen from Figures 2 and 3, the oxide semiconductor film 112 is unshielded, resulting in the absence of the bottom gate of the oxide thin-film transistor, which degrades the photosensitivity and electrical properties of the thin-film transistor.

[0036] To this end, this application provides a display panel and a display device. Referring to Figures 1 to 14, Figure 4 is a schematic diagram of the film layers of the display panel provided in an embodiment of this application. Figure 5 is a circuit diagram of the sub-pixels of the display panel provided in an embodiment of this application. Figure 6 is a first stacked diagram of a portion of the film layers of the display panel provided in an embodiment of this application. Figure 7 is an exploded view of the light-shielding layer of the display panel in Figure 6. Figure 8 is an exploded view of the first semiconductor layer of the display panel in Figure 6. Figure 9 is a stacked schematic diagram of the first semiconductor layer in Figure 8 and the light-shielding layer in Figure 7. Figure 10 is an exploded view of the first gate layer of the display panel in Figure 6. Figure 11 is a stacked schematic diagram of the first gate layer in Figure 10 and the structure in Figure 9. Figure 12 is an exploded view of the second semiconductor layer of the display panel in Figure 6. Figure 13 is a stacked schematic diagram of the second semiconductor layer in Figure 12 and the structure in Figure 11. Figure 14 is an exploded view of the second gate layer of the display panel in Figure 6. Figure 15 is a stacked schematic diagram of the second gate layer in Figure 14 and the structure in Figure 13. Figure 16 is an exploded view of the first source-drain layer of the display panel in Figure 6. Figure 17 is a schematic diagram of the stacked structure of the first source-drain layer in Figure 16 and the structure in Figure 15. Figure 18 is an exploded view of the second source-drain layer of the display panel in Figure 6.

[0037] Referring to Figures 4 to 18, the display panel 2 includes a substrate 201 and a plurality of sub-pixels 31 disposed on the substrate 201. Each sub-pixel 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, and a first initialization transistor T4. The switching transistor T2 and the driving transistor T1 are connected to a first node A. One electrode of the compensation transistor T3 and one electrode of the first initialization transistor T4 are connected to the driving transistor T1 at a second node Q. The other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B. The gate of the compensation transistor T3 is connected to a first scan signal line Nscan1, and the gate of the first initialization transistor T4 is connected to a second scan signal line Nscan2.

[0038] The display panel 2 also includes a light-shielding layer 202, a first semiconductor layer 207 and a second semiconductor layer 212 disposed on a substrate 201. The light-shielding layer 202 is disposed between the substrate 201 and the first semiconductor layer 207, and the first semiconductor layer 207 is disposed between the light-shielding layer 202 and the second semiconductor layer 212.

[0039] The first semiconductor layer 207 is disposed on the side of the light-shielding layer 202 away from the substrate 201. The first semiconductor layer 207 includes a first active portion T1A of the driving transistor T1 and a second active portion T2A of the switching transistor T2.

[0040] The second semiconductor layer 212 is disposed on the side of the first semiconductor layer 207 away from the substrate 201. The second semiconductor layer 212 includes the third active portion T3A of the compensation transistor T3 and the fourth active portion T4A of the first initialization transistor T4.

[0041] The light-shielding layer 202 includes a first light-shielding pattern 202a, a second light-shielding pattern 202b, and a third light-shielding pattern 202c, which are spaced apart in the first direction Y. All three patterns extend along the second direction X. The second light-shielding pattern 202b is connected to the first scan signal line Nscan1, and the third light-shielding pattern 202c is connected to the second scan signal line Nscan2. The first light-shielding pattern 202a includes a first light-shielding portion 311 corresponding to the first active portion T1A, the second light-shielding pattern 202b includes a second light-shielding portion 313 corresponding to the third active portion T3A, and the third light-shielding pattern 202c includes a third light-shielding portion 315 corresponding to the fourth active portion T4A. In this application, the first direction Y and the second direction X are different. For example, the first direction Y is the vertical direction and the second direction X is the horizontal direction, that is, the first direction Y is the column direction and the second direction X is the row direction. Of course, this application is not limited to this. In this application, the first direction Y and the second direction X can also form other angles, such as the angle is greater than 0 degrees and less than 90 degrees.

[0042] The display panel 2 provided in this embodiment includes a substrate 201 and a light-shielding layer 202, a first semiconductor layer 207, and a second semiconductor layer 212 disposed on the substrate 201. The first semiconductor layer 207 forms a first active portion T1A of a driving transistor T1, and the second semiconductor layer 212 forms a third active portion T3A of a compensation transistor T3 and a fourth active portion T4A of a first initialization transistor T4. The light-shielding layer 202 includes a first light-shielding pattern 202a, a second light-shielding pattern 202b, and a third light-shielding pattern 202c disposed at intervals along a first direction Y. The first light-shielding pattern 202a has a first light-shielding pattern 202a... The light-shielding part 311 can block the light from the first active part T1A, the second light-shielding part 313 on the second light-shielding pattern 202b can block the light from the third active part T3A, and the third light-shielding part 315 on the third light-shielding pattern 202c can block the light from the fourth active part T4A. This prevents the third active part T3A of the compensation transistor T3 and the fourth active part T4A of the first initialization transistor T4 from being affected by light, thereby improving the photosensitivity and electrical properties of the compensation transistor T3 and the first initialization transistor T4. This improves the problem of deteriorated photosensitivity and electrical properties caused by the lack of bottom gate of oxide thin film transistors in display devices using LTPO technology.

[0043] Specifically, in the embodiments of this application, the light-shielding portion on the light-shielding pattern formed by the light-shielding layer 202 corresponding to the active portion of the transistor means that the light-shielding portion is at least corresponding to the channel portion of the active portion of the transistor. The projection of the light-shielding portion on the substrate 201 coincides with the projection of the channel portion of the transistor on the substrate 201. It can be understood that the active portion of each transistor includes a doped portion and a channel portion. The channel portion is easily affected by light, which can cause changes in performance. Therefore, the light-shielding portion can be corresponding to the channel portion of the transistor. Specifically, for example, the second light-shielding portion 313 corresponding to the third active portion T3A of the compensation transistor T3 means that the second light-shielding portion 313 is at least corresponding to the third channel portion of the compensation transistor T3.

[0044] The first light-shielding part 311 is configured to correspond to the first active part T1A of the driving transistor T1, the second light-shielding part 313 is configured to correspond to the third active part T3A of the compensation transistor T3, and the third light-shielding part 315 is configured to correspond to the fourth active part T4A of the first initialization transistor T4.

[0045] Specifically, the orthographic projection of the first active portion T1A of the driving transistor T1 onto the substrate 201 is located within the orthographic projection of the first light-shielding portion 311 onto the substrate 201, the orthographic projection of the third active portion T3A of the compensation transistor T3 onto the substrate 201 is located within the orthographic projection of the second light-shielding portion 313 onto the substrate 201, and the orthographic projection of the fourth active portion T4A of the first initialization transistor T4 onto the substrate 201 is located within the orthographic projection of the third light-shielding portion 315 onto the substrate 201. This prevents light from shining onto the first active portion T1A of the driving transistor T1, the third active portion T3A of the compensation transistor T3, and the fourth active portion T4A of the first initialization transistor T4, thereby improving the electrical and photosensitivity of the driving transistor T1, the compensation transistor T3, and the first initialization transistor T4.

[0046] Specifically, the area of ​​the first light-shielding part 311 can be greater than or equal to the area of ​​the first active part T1A of the driving transistor T1, the area of ​​the second light-shielding part 313 can be greater than or equal to the area of ​​the third active part T3A of the compensation transistor T3, and the area of ​​the third light-shielding part 315 can be greater than or equal to the area of ​​the fourth active part T4A of the first initialization transistor T4.

[0047] Referring to Figures 6, 7, and 8, a plurality of first light-shielding portions 311 are arranged at intervals in the second direction X, a plurality of second light-shielding portions 313 are arranged at intervals in the second direction X, and a plurality of third light-shielding portions 315 are arranged at intervals in the second direction X. The first light-shielding pattern 202a also includes first connecting lines 312a and 312b connecting two adjacent first light-shielding portions 311, the second light-shielding pattern 202b also includes a second connecting line 314a connecting two adjacent second light-shielding portions 313, and the third light-shielding pattern 202c also includes a third connecting line 316a connecting two adjacent third light-shielding portions 315. The first connecting lines 312a and 312b, the second connecting line 314a, and the third connecting line 316a are arranged at intervals in the first direction Y.

[0048] The display panel 2 also includes a plurality of repeating units 30 arranged in an array on the substrate 201. Each repeating unit 30 includes two mirror-symmetrical sub-pixels 31, two mirror-symmetrical first light-shielding parts 311, two mirror-symmetrical second light-shielding parts 313, and two mirror-symmetrical third light-shielding parts 315. Within the same repeating unit 30, the first connecting line connecting the two first light-shielding parts 311 is a first type of first connecting line 312a, the second connecting line connecting the two second light-shielding parts 313 is a first type of second connecting line, and the third connecting line connecting the two third light-shielding parts 315 is a first type of third connecting line. In the second direction X, the length of the first type of first connecting line 312a is less than the length of the first type of second connecting line 314a, and the length of the first type of first connecting line 312a is less than the length of the first type of third connecting line 316a.

[0049] The first connecting line connecting the first light-shielding portions 311 within two adjacent repeating units 30 is a second type of first connecting line 312b. Similarly, the second connecting line 314a and the third connecting line 316a are also connecting lines connecting two adjacent repeating units 30. For example, the second connecting line connecting the second light-shielding portions 313 within two adjacent repeating units 30 is a second type of second connecting line, and the third connecting line connecting the third light-shielding portions 315 within two adjacent repeating units 30 is a second type of third connecting line. In the second direction X, the second type of first connecting line 312b and the first type of first connecting line 312a are staggered. The first type of second connecting line 314a includes a recess 321 located near the first type of first connecting line 312a, and the recess 321 is positioned corresponding to the gap between two adjacent first light-shielding portions 311.

[0050] The adjacent second light-shielding portions 313 and third light-shielding portions 315 coincide in the first direction Y. Within the repeating unit 30, the first light-shielding portion 311 is disposed corresponding to the gap between two adjacent second light-shielding portions 313, and in the first direction Y, the first light-shielding portion 311 partially overlaps with the second light-shielding portion 313, and the first light-shielding portion 311 partially overlaps with the third light-shielding portion 315.

[0051] The gate of the compensation transistor T3 is connected to the first scan signal line Nscan1, the gate of the first initialization transistor T4 is connected to the second scan signal line Nscan2, the second light-shielding pattern 202b is connected to the first scan signal line Nscan1, the third light-shielding pattern 202c is connected to the second scan signal line Nscan2, and the first light-shielding pattern 202a is connected to the high-potential power supply line VDD. Thus, by arranging the first light-shielding pattern 202a, the second light-shielding pattern 202b, and the third light-shielding pattern 202c at intervals in the first direction Y, and by isolating the first light-shielding pattern 202a, the second light-shielding pattern 202b, and the third light-shielding pattern 202c from each other, different signals can be connected to the first light-shielding pattern 202a, the compensation transistor T3 and the first initialization transistor T4 can be prevented from having a threshold voltage negative bias when the second light-shielding pattern 202b and the third light-shielding pattern 202c are connected to the same high-potential power supply signal as the first light-shielding pattern 202a.

[0052] Specifically, it is understood that the display panel 2 will include a plurality of repeating units 30 arranged in an array, and the sub-pixels 31 within each repeating unit 30 can refer to the design within a repeating unit 30 in the embodiments of this application.

[0053] In some embodiments, as shown in FIG5, the gate of the switching transistor T2 is connected to the third scan signal line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the first scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the second scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node B; the sub-pixel 31 further includes:

[0054] The first light-emitting control transistor T5 has its gate connected to the light-emitting control signal line EM, its first electrode connected to the high-potential power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0055] The second light-emitting control transistor T6 has its gate connected to the light-emitting control signal line EM, and its first electrode is connected to the second electrode of the driving transistor T1 at the third node B.

[0056] The second initialization transistor T7 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the second initialization signal line VI-ANO, and its second electrode connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C.

[0057] The third initialization transistor T8 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the third initialization signal line VI3, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0058] Storage capacitor Cst, one plate of storage capacitor Cst is connected to the high potential power line VDD, and the other plate of storage capacitor Cst is connected to the gate of driving transistor T1 at the second node Q;

[0059] The boost capacitor Cboost has one plate connected to the third scan signal line Pscan, and the other plate connected to the second electrode of the first initialization transistor T4.

[0060] Specifically, as shown in Figures 4 and 5, the display panel 2 also includes a light-emitting layer 23, which includes a light-emitting device LED. The positive electrode of the light-emitting device LED is connected to the second electrode of the second initialization transistor T7, and the negative electrode of the light-emitting device LED is connected to the low-potential power line VSS.

[0061] In some embodiments, as shown in FIG4, the display panel 2 further includes a first gate layer 209, a second gate layer 214, a first source-drain layer 216, and a second source-drain layer 218. The first gate layer 209 is disposed between the first semiconductor layer 207 and the second semiconductor layer 212, the second gate layer 214 is disposed between the second semiconductor layer 212 and the first source-drain layer 216, and the first source-drain layer 216 is disposed between the second gate layer 214 and the second source-drain layer 218. By including the first gate layer 209, the second gate layer 214, the first source-drain layer 216, and the second source-drain layer 218 in the display panel, the number of process steps in the display panel can be reduced, and the number of photomasks required to form the display panel can be reduced.

[0062] In some embodiments, as shown in Figures 4 to 6, 8, and 9, the first semiconductor layer 207 includes a first active portion T1A of a driving transistor T1, a second active portion T2A of a switching transistor T2, a fifth active portion T5A of a first light-emitting control transistor T5, a sixth active portion T6A of a second light-emitting control transistor T6, a seventh active portion T7A of a second initialization transistor T7, and an eighth active portion T8A of a third initialization transistor T8. A first light-shielding portion 311 on the first light-shielding pattern 202a is correspondingly disposed with respect to the first active portion T1A, as shown in Figure 9. The first active portion T1A of the driving transistor T1 is disposed along the second direction X, and the first active portion T1A of the driving transistor T1 is connected to the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light-emitting control transistor T5, and the sixth active portion T6A of the second light-emitting control transistor T6. The second active portion T2A of the switching transistor T2 and the fifth active portion T5A of the first light-emitting control transistor T5 are disposed along the first direction Y, and the sixth active portion T6A of the second light-emitting control transistor T6 is connected to the second initialization transistor T7. The seventh active part T7A is disposed along the first direction Y, and the sixth active part T6A of the second light-emitting control transistor T6 is connected to the seventh active part T7A of the second initialization transistor T7. The eighth active part T8A of the third initialization transistor T8 is disposed at intervals with the first active part T1A of the driving transistor T1, the second active part T2A of the switching transistor T2, the fifth active part T5A of the first light-emitting control transistor T5, the sixth active part T6A of the second light-emitting control transistor T6, and the seventh active part T7A of the second initialization transistor T7.

[0063] Specifically, it can be seen that within a repeating unit 30, the fifth active part T5A of two adjacent first light-emitting control transistors T5 is connected.

[0064] In some embodiments, as shown in Figures 4 to 6, 10, and 11, the first gate layer 209 includes a first initialization signal line VI-G, a third scan signal line Pscan, a light emission control signal line EM, a fourth scan signal line Pscan2, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light emission control transistor T5, a gate T6G of a second light emission control transistor T6, a gate T7G of a second initialization transistor T7, a gate T8G of a third initialization transistor T8, and a first plate Cst1 of a storage capacitor Cst. The first initialization signal line VI-G, the third scan signal line Pscan, the first plate Cst1 of the storage capacitor Cst, the light emission control signal line EM, and the fourth scan signal line Pscan2 are sequentially spaced along the first direction Y.

[0065] Specifically, as shown in Figure 10, the gate T2G of the switching transistor T2 is part of the third scan signal line Pscan. It can be understood that since the gates T2G of all the switching transistors T2 in a row of sub-pixels 31 are connected to the same third scan signal line Pscan, when forming the third scan signal line Pscan, the portion of the channel of the switching transistor T2 corresponding to each sub-pixel 31 on the third scan signal line Pscan serves as the gate of the switching transistor T2 of each pixel unit. Therefore, the same structure is identified by two labels. Similarly, the gate T1G of the driving transistor T1 serves as both the gate and the storage. The first plate Cst1 of capacitor Cst, the portion of the light emission control signal line EM corresponding to the channel of the first light emission control transistor T5 serves as the gate T5G of the first light emission control transistor T5, the portion of the light emission control signal line EM corresponding to the channel of the second light emission control transistor T6 serves as the gate T6G of the second light emission control transistor T6, the portion of the fourth scan signal line Pscan2 corresponding to the channel of the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the portion of the fourth scan signal line Pscan2 corresponding to the channel of the third initialization transistor T8 serves as the gate T8G of the third initialization transistor T8.

[0066] Referring to Figures 10 and 11, the position where the gate of each transistor overlaps with the first semiconductor layer 207 is the channel portion of the corresponding transistor. For example, the position where the gate T2G of the switching transistor T2 overlaps with the first semiconductor layer 207 is the channel portion of the switching transistor T2; the position where the gate T1G of the driving transistor T1 overlaps with the first semiconductor layer 207 is the channel portion of the driving transistor T1; the position where the gate T5G of the first light-emitting control transistor T5 overlaps with the first semiconductor layer 207 is the channel portion of the first light-emitting control transistor T5; the position where the gate T6G of the second light-emitting control transistor T6 overlaps with the first semiconductor layer 207 is the channel portion of the second light-emitting control transistor T6; the position where the gate T7G of the second initialization transistor T7 overlaps with the first semiconductor layer 207 is the channel portion of the second initialization transistor T7; and the position where the gate T8G of the third initialization transistor T8 overlaps with the first semiconductor layer 207 is the channel portion of the third initialization transistor T8.

[0067] In some embodiments, as shown in Figures 4 to 6, 12, and 13, the second semiconductor layer 212 includes a third active portion T3A of a compensation transistor T3, a fourth active portion T4A of a first initialization transistor T4, and a second electrode Cst2 of a storage capacitor Cst. The third active portion T3A of the compensation transistor T3 is connected to the fourth active portion T4A of the first initialization transistor T4, and both the third active portion T3A and the fourth active portion T4A extend along the first direction Y. The second electrode Cst2 of the storage capacitor Cst is disposed along the first direction Y on one side of the third active portion T3A of the compensation transistor T3, and the second electrode Cst2 of the storage capacitor Cst is disposed between adjacent third active portions T3A. The second electrode Cst2 is disposed corresponding to the first light-shielding portion 311, and the first electrode Cst2 is connected to the high-potential power line VDD. A through hole 331 is provided on the second electrode Cst of the storage capacitor Cst. By forming the second electrode plate Cst2 of the storage capacitor Cst in the second semiconductor layer 212, the storage capacitor Cst can be set in the sub-pixel 31, and the second electrode plate Cst2 of the storage capacitor Cst is provided with a through hole, so that the first electrode of the compensation transistor T3 can be normally connected to the gate of the driving transistor T1.

[0068] Specifically, it can be understood that the second semiconductor layer 212 forms the second electrode of the storage capacitor Cst. Therefore, it is necessary to make the second electrode of the storage capacitor Cst have good electrical properties. This can be achieved by doping the second electrode of the storage capacitor Cst to keep the electrical properties of the second electrode of the storage capacitor Cst consistent with or even exceed the electrical properties of the doped part of the active part, so that the electrical properties of the storage capacitor Cst are good.

[0069] Specifically, by providing a through hole on the second plate of the storage capacitor Cst, the first electrode of the compensation transistor T3 can pass through the second plate of the storage capacitor Cst and connect to the gate of the driving transistor T1, so that the sub-pixel 31 can work normally.

[0070] Specifically, as shown in Figures 10, 12, and 13, the first gate layer 209 further includes the first plate Cboost1 of the boost capacitor Cboost, the second semiconductor layer 212 further includes the second plate Cboost2 of the boost capacitor Cboost, the overlapping portion of the third scan signal line Pscan and the fourth active portion T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the fourth active portion T4A of the first initialization transistor T4 and the third scan signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0071] In some embodiments, as shown in Figures 4 to 6, 14, and 15, the second gate layer 214 includes a second scan signal line Nscan2, a first scan signal line Nscan1, a third initialization signal line VI3, a gate T3G of a compensation transistor T3, and a gate T4G of a first initialization transistor T4. The location where the gate T3G of the compensation transistor T3 overlaps with the second semiconductor layer 212 is the channel portion of the compensation transistor T3, and the location where the gate T4G of the first initialization transistor T4 overlaps with the second semiconductor layer 212 is the channel portion of the first initialization transistor T4.

[0072] Referring to Figures 14 and 15, the second scan signal line Nscan2, the first scan signal line Nscan1, and the third initialization signal line VI3 are sequentially arranged along the first direction Y. The orthographic projection of the first scan signal line Nscan1 on the substrate 201 at least partially overlaps with the orthographic projection of the second light-shielding pattern 202b on the substrate 201, and / or, the orthographic projection of the second scan signal line Nscan2 on the substrate 201 at least partially overlaps with the orthographic projection of the third light-shielding pattern 202c on the substrate 201. Specifically, the projection of the second light-shielding pattern 202b onto the substrate 201 can overlap with the projection of the first scan signal line Nscan1 onto the substrate 201, thereby reducing the coupling capacitance between the second light-shielding pattern 202b and other signal lines. Even if the second light-shielding pattern 202b is coupled to the first scan signal line Nscan1, since the second light-shielding part 313 blocks the third active part T3A of the compensation transistor T3, the potential of the second light-shielding pattern 202b is the same as the potential of the second light-shielding part 313, which can be the potential of the first scan signal line Nscan1, thereby improving the gate control capability of the compensation transistor T3.

[0073] Specifically, the projection of the second light-shielding pattern 202b onto the substrate 201 can overlap with the projection of the first scan signal line Nscan1 onto the substrate 201, and the projection of the third light-shielding part 315 onto the substrate 201 can overlap with the projection of the second scan signal line Nscan2 onto the substrate 201. This reduces the overlap area of ​​the second light-shielding pattern 202b and the third light-shielding pattern 202c with other traces, thus reducing the interference of the second light-shielding pattern 202b and the third light-shielding pattern 202c on other signals. When the second light-shielding pattern 202b is coupled with the first scan signal line Nscan1, and the third light-shielding pattern 202c is coupled with the second scan signal line Nscan2, the second light-shielding part 313 and the third light-shielding part 315 can be used as the bottom gate of the compensation transistor T3 and the first initialization transistor T4, respectively, thereby improving the gate control capability of the compensation transistor T3 and the first initialization transistor T4.

[0074] In some embodiments, as shown in Figures 4 to 6, 16 and 17, the first source-drain layer 216 includes a first electrode T2S of a switching transistor T2, a first electrode T3S of a compensation transistor T3, a second electrode T3D of a compensation transistor T3, a first electrode T4S of a first initialization transistor T4, a second electrode T4D of a first initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T5D of a first light-emitting control transistor T5, a first electrode T6S of a second light-emitting control transistor T6, a second electrode T6D of a second light-emitting control transistor T6, a first electrode T7S of a second initialization transistor T7, a second electrode T7D of a second initialization transistor T7, a first electrode T8S of a third initialization transistor T8, a second electrode T8D of a third initialization transistor T8, and a second initialization signal line VI-ANO, wherein the second initialization signal line VI-ANO is not shown in the stack-up diagram in Figure 17.

[0075] Specifically, as shown in Figure 16, it can be understood that since the electrodes of each transistor are connected together, in actual design, to improve the aperture ratio, the electrodes of each transistor will share the same structure. Therefore, in Figure 16, the same structure is identified by multiple labels. For example, one structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. As can be seen from Figure 5, this is the location where the second node Q is connected. Similarly, other structures will also serve as multiple electrodes, and the positions of each node can be determined accordingly.

[0076] Specifically, as shown in Figures 11, 16, and 17, the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4 are connected through a first connection terminal K1. Given the small distance between the projections of the first initialization signal line VI-G and the second scan signal line Nscan2 onto the substrate, directly forming vias in the corresponding region of the first electrode of the first initialization transistor to connect the first initialization signal line would result in vias forming on the second scan signal line Nscan2. Therefore, a first connection terminal K1 can be provided on the first source-drain layer, connecting the first electrode of the first initialization transistor T4. Simultaneously, a via is formed in the corresponding region of the first connection terminal K1, connecting the first connection terminal K1 to the first initialization signal line VI-G. This achieves the connection between the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4. Furthermore, since the first connection terminal K1 is located on the axis of symmetry of the two symmetrically arranged sub-pixels 31, the first electrodes of the first initialization transistor T4 in the two symmetrically arranged sub-pixels 31 can be connected to the first initialization signal line through the same first connection terminal K1, reducing the number of vias and improving yield.

[0077] Specifically, as shown in Figures 6 to 16, the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a second connection terminal K2 can be provided in the first source-drain layer. The second connection terminal K2 passes through the via 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0078] The third initialization signal line VI3 and the first electrode T8S of the third initialization transistor T8 are connected through the third connection terminal K3.

[0079] In some embodiments, as shown in Figures 4 to 6 and Figure 18, within a repeating unit 30, the second source-drain layer 218 includes two data lines DATA and two high-potential power lines VDD, with the two data lines and the two high-potential power lines VDD arranged in a mirror-symmetrical configuration.

[0080] Specifically, it is understood that due to the design of the sub-pixel 31 in the display area shown in the embodiments of this application, and the connection points of some traces located in the non-display area, some traces may not be connected together. However, in reality, they will be connected. For example, in order to adopt the technology of setting the fanout line in the display area (Fanout In AA, FIAA), the data line will be provided with a first data connection line set along the first direction Y and a second data connection line set along the second direction X, and will be connected to the data line outside the display area. However, the embodiments of this application show the design of the sub-pixel 31 in the display area, so its connection point is not shown, but in reality, it will be connected.

[0081] Meanwhile, in order to realize the mesh structure design of the initialization signal line, the embodiments of this application will set an initialization signal connection line. The initialization signal connection line can realize the mesh structure design of at least one of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3. Similarly, the initialization signal connection line will be connected to the initialization signal line.

[0082] For example, the first initialization signal line VI-G is connected to the initialization signal connection line outside the display area, thereby realizing the mesh structure design of the first initialization signal line VI-G. Similarly, the mesh structure design of the second initialization signal line VI-ANO and the third initialization signal line VI3 can be realized. However, the embodiments of this application are not limited to this. Some initialization signal connection lines can be connected to one of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3, and some initialization signal connection lines can be connected to another of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3. Alternatively, some initialization signal connection lines can be connected to another of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3, thereby realizing the mesh structure design of each initialization signal line.

[0083] Specifically, as shown in Figure 4, the display panel 2 also includes a first barrier layer 203, a second barrier layer 205, a buffer layer 206, a first gate insulating layer 208, a first interlayer insulating layer 211, a second gate insulating layer 213, a second interlayer insulating layer 215, a first planarization layer 217, and a second planarization layer 219.

[0084] Specifically, as shown in Figure 4, the display panel 2 also includes a light-emitting layer 23, which includes a pixel electrode layer 221, a pixel definition layer 222, a light-emitting material layer, a common electrode layer, and support pillars 223.

[0085] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0086] Specifically, the third scan signal line Pscan, the first scan signal line Nscan1, the second scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM can be connected to different gate driving circuits. Specifically, five sets of gate driving circuits can be used to output signals to the third scan signal line Pscan, the first scan signal line Nscan1, the second scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM, respectively. Among them, the gate driving circuit connected to the third scan signal line Pscan can use double-sided driving, while the other gate driving circuits use single-sided driving.

[0087] Specifically, the material of the first semiconductor layer 207 includes silicon semiconductor material, specifically low-temperature polycrystalline silicon.

[0088] Specifically, the material of the second semiconductor layer 212 includes oxide semiconductor materials, specifically metal oxide semiconductor materials, and more specifically, indium gallium zinc oxide.

[0089] Specifically, the material of the light-shielding layer 202 includes metallic materials.

[0090] Specifically, the driving transistor T1, the switching transistor T2, the first light-emitting transistor, the second light-emitting transistor, the second initialization transistor, and the third initialization transistor are P-type transistors, while the first initialization transistor T4 and the compensation transistor T3 are N-type transistors.

[0091] Specifically, the above embodiments have provided a detailed description of the display panel 2 from the perspectives of the sub-pixel 31 structure, film layer structure, specific structure of each layer, material, and potential. It is understood that when there is no conflict between the embodiments, the embodiments can be combined.

[0092] Meanwhile, this application provides a display device, which includes a display panel 2 as described in any of the above embodiments.

[0093] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0094] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel comprising a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel comprising a driving transistor, a switching transistor, a compensation transistor, and a first initialization transistor, wherein the switching transistor is connected to the driving transistor at a first node; one electrode of the compensation transistor and one electrode of the first initialization transistor are connected to the driving transistor at a second node, the other electrode of the compensation transistor is connected to the driving transistor at a third node, the gate of the compensation transistor is connected to a first scan signal line, and the gate of the first initialization transistor is connected to a second scan signal line; the display panel further comprising: A light-shielding layer is disposed on one side of the substrate; A first semiconductor layer is disposed on the side of the light-shielding layer away from the substrate, and the first semiconductor layer includes a first active portion of the driving transistor and a second active portion of the switching transistor; A second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate. The second semiconductor layer includes a third active portion of the compensation transistor and a fourth active portion of the first initialization transistor. The light-shielding layer includes a first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern spaced apart in a first direction. The first light-shielding pattern, the second light-shielding pattern, and the third light-shielding pattern all extend along a second direction, which is different from the first direction. The second light-shielding pattern is connected to the first scanning signal line, and the third light-shielding pattern is connected to the second scanning signal line. The first light-shielding pattern includes a first light-shielding part corresponding to the first active part, the second light-shielding pattern includes a second light-shielding part corresponding to the third active part, and the third light-shielding pattern includes a third light-shielding part corresponding to the fourth active part.

2. The display panel according to claim 1, wherein, A plurality of first light-shielding portions are spaced apart in the second direction, a plurality of second light-shielding portions are spaced apart in the second direction, and a plurality of third light-shielding portions are spaced apart in the second direction; The first light-shielding pattern further includes a first connecting line connecting two adjacent first light-shielding parts, the second light-shielding pattern further includes a second connecting line connecting two adjacent second light-shielding parts, and the third light-shielding pattern further includes a third connecting line connecting two adjacent third light-shielding parts. The first connecting line, the second connecting line, and the third connecting line are arranged at intervals in the first direction.

3. The display panel according to claim 2, wherein, The display panel further includes a plurality of repeating units arranged in an array on the substrate. Each repeating unit includes two mirror-symmetrical sub-pixels, two mirror-symmetrical first light-shielding portions, two mirror-symmetrical second light-shielding portions, and two mirror-symmetrical third light-shielding portions. Within the same repeating unit, the first connecting line connecting two first light-shielding portions is a first type of first connecting line, the second connecting line connecting two second light-shielding portions is a first type of second connecting line, and the third connecting line connecting two third light-shielding portions is a first type of third connecting line. In the second direction, the length of the first type of first connecting line is less than the length of the first type of second connecting line, and the length of the first type of first connecting line is less than the length of the first type of third connecting line.

4. The display panel according to claim 3, wherein, The first connecting line connecting the first light-shielding part in two adjacent repeating units is a second type of first connecting line. In the second direction, the second type of first connecting line and the first type of first connecting line are staggered.

5. The display panel according to claim 4, wherein, The first type of second connecting line includes a recessed portion disposed near the first type of first connecting line, the recessed portion being disposed between two adjacent first light-shielding portions.

6. The display panel according to claim 3, wherein, The adjacent second and third light-shielding portions coincide in the first direction.

7. The display panel according to claim 6, wherein, Within the repeating unit, the first light-shielding part is arranged at the gap between two adjacent second light-shielding parts.

8. The display panel according to claim 7, wherein, In the first direction, the first light-shielding part partially overlaps with the second light-shielding part, and the first light-shielding part partially overlaps with the third light-shielding part.

9. The display panel according to claim 1, wherein, The orthographic projection of the first scanning signal line on the substrate at least partially overlaps with the orthographic projection of the second light-shielding pattern on the substrate, and / or the orthographic projection of the second scanning signal line on the substrate at least partially overlaps with the orthographic projection of the third light-shielding pattern on the substrate.

10. The display panel according to claim 1, wherein, The area of ​​the first light-shielding part is greater than or equal to the area of ​​the first active part, the area of ​​the second light-shielding part is greater than or equal to the area of ​​the third active part, and the area of ​​the third light-shielding part is greater than or equal to the area of ​​the fourth active part.

11. The display panel according to claim 10, wherein, The orthographic projection of the first active part on the substrate is located within the orthographic projection of the first light-shielding part on the substrate, the orthographic projection of the third active part on the substrate is located within the orthographic projection of the second light-shielding part on the substrate, and the orthographic projection of the fourth active part on the substrate is located within the orthographic projection of the third light-shielding part on the substrate.

12. The display panel according to any one of claims 1 to 11, wherein, The display panel also includes high-potential power lines located on the side of the light-shielding layer away from the substrate. The high-potential power lines extend along the first direction and are spaced apart along the second direction. The first light-shielding pattern is connected to the high-potential power lines.

13. The display panel according to claim 12, wherein, The gate of the switching transistor is connected to the third scan signal line, the first electrode of the switching transistor is connected to the data line, and the second electrode of the switching transistor is connected to the first electrode of the driving transistor at a first node; the first electrode of the compensation transistor is connected to the gate of the driving transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor; the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the driving transistor at a second node. The sub-pixel also includes: The first light-emitting control transistor has its gate connected to the light-emitting control signal line, its first electrode connected to the high-potential power supply line, and its second electrode connected to the first electrode of the driving transistor at the first node. The second light-emitting control transistor has its gate connected to the light-emitting control signal line, and its first electrode is connected to the second electrode of the driving transistor at the third node. The second initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the second initialization signal line, and its second electrode connected to the second light-emitting control transistor at the fourth node. The third initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the third initialization signal line, and its second electrode connected to the first electrode of the driving transistor at the first node. A storage capacitor, one plate of which is connected to the high-potential power line, and the other plate of which is connected to the gate of the driving transistor at a second node; A boost capacitor, one plate of which is connected to the third scan signal line, and the other plate of which is connected to the second electrode of the first initialization transistor.

14. The display panel according to claim 13, wherein, The driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor, the second initialization transistor, and the third initialization transistor are all P-type transistors, while the first initialization transistor and the compensation transistor are both N-type transistors.

15. The display panel according to claim 13, wherein, The material of the first semiconductor layer includes silicon semiconductor material, and the material of the second semiconductor layer includes oxide semiconductor material.

16. The display panel according to claim 13, wherein, The second semiconductor layer further includes a second electrode plate of the storage capacitor. The second electrode plate is disposed corresponding to the first light-shielding part and is connected to the high-potential power line. A through hole is provided on the second electrode plate.

17. The display panel according to claim 16, wherein, The first semiconductor layer further includes a fifth active portion of the first light-emitting control transistor, a sixth active portion of the second light-emitting control transistor, a seventh active portion of the second initialization transistor, and an eighth active portion of the third initialization transistor. The first active portion is disposed along the second direction and is connected to the second active portion, the fifth active portion, and the sixth active portion. The second active portion and the fifth active portion are disposed along the first direction. The sixth active portion and the seventh active portion are disposed along the first direction and are connected to each other. The eighth active portion is spaced apart from the first active portion, the second active portion, the fifth active portion, the sixth active portion, and the seventh active portion, and is located between the fifth active portion and the seventh active portion.

18. The display panel according to claim 17, wherein, The display panel further includes a first gate layer disposed between the first semiconductor layer and the second semiconductor layer. The first gate layer includes a first initialization signal line, a third scan signal line, a light emission control signal line, a fourth scan signal line, the gate of the driving transistor, the gate of the switching transistor, the gate of the first light emission control transistor, the gate of the second light emission control transistor, the gate of the second initialization transistor, the gate of the third initialization transistor, and the first plate of the storage capacitor. The first initialization signal line, the third scan signal line, the first plate of the storage capacitor, the light emission control signal line, and the fourth scan signal line are arranged sequentially at intervals along the first direction.

19. The display panel according to claim 18, wherein, The display panel further includes a second gate layer, which is disposed on the side of the second semiconductor layer away from the substrate. The second gate layer includes a first scan signal line, a second scan signal line, a third initialization signal line, the gate of the compensation transistor, and the gate of the first initialization transistor. The third initialization signal line, the first scan signal line, and the second scan signal line are arranged at intervals along the first direction.

20. A display device comprising a display panel as claimed in any one of claims 1 to 19.

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