Display apparatus and driving method therefor

Abstract

The present application provides a display apparatus and a driving method therefor. Each pixel driving circuit of the display apparatus comprises a pulse amplitude modulation driving module and a pulse width modulation driving module. The pulse width modulation driving module comprises a comparator, a plurality of transistors, and a capacitor. The comparator is used for comparing the voltages of a ramp signal and a data signal so as to control the on / off state of light-emitting devices of the display apparatus. The driving method comprises: in the light-emitting stage, comparing the voltages of a ramp signal and a data signal so as to control the light-emitting time of light-emitting devices. The present application can improve the low-grayscale display effect and improve the display uniformity.

Description

Display device and its driving method Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] In Micro-LED display technology, the pixel driving circuit plays a crucial role in display quality.

[0003] Traditional Micro-LED pixel driving circuits use pulse amplitude modulation (PAM) to switch between different gray levels by changing the current amplitude. However, this driving method can cause pixelation and poor uniformity in the actual image display when the current is low and the gray level is low.

[0004] To address the shortcomings of pure PAM driving, the industry has introduced a hybrid driving circuit combining PAM and Pulse Width Modulation (PWM), known as a PHM circuit. In a PHM driving circuit, high grayscale levels are switched by adjusting the current through the PAM circuit, while low grayscale levels are switched by adjusting the emission time through the PWM circuit. This hybrid driving method improves the display effect to some extent.

[0005] However, traditional PHM driving circuits still have some problems in PWM driving mode. The main issue is the longer transition time (rise edge time) from dark to bright during the dark-to-bright transition, which shortens the actual light-emitting time. Since rise edge times may vary at different gray levels, this phenomenon affects display uniformity, especially at lower gray levels.

[0006] Furthermore, traditional PHM driving circuits still struggle to completely resolve the issue of pixelation in the displayed image at low grayscale levels, which further affects the uniformity of the display.

[0007] Therefore, how to further optimize the PWM circuit module based on the PHM driving circuit, shorten the rise time during the dim-to-bright switching process, improve the precise control of the actual light emission time, and effectively improve the display uniformity under low grayscale have become the technical problems that urgently need to be solved in the current Micro-LED display technology field. Invention Overview

[0008] Embodiments of this application provide a display device and a driving method thereof, which aim to improve the display uniformity of the display device at low gray levels.

[0009] This application provides a display device, including: a plurality of pixel units, each pixel unit including: a light-emitting device; and a pixel driving circuit, the pixel driving circuit including a pulse width modulation module and a pulse amplitude modulation module; wherein, the pulse width modulation module includes a comparator, a first transistor, a second transistor, a fourth transistor, a sixth transistor, and a first capacitor; the comparator is electrically connected to the high-level signal input terminal, a first node, a second node, and a low-level signal input terminal of the pulse width modulation module; the gate of the first transistor is electrically connected to a first light-emitting control signal input terminal, one of the source and drain of the first transistor is electrically connected to a first ramp signal input terminal, and the other of the source and drain of the first transistor is electrically connected to a third node; the gate of the second transistor is electrically connected to a second pulse width modulation signal input terminal, and so on. One of the source and drain of the second transistor is electrically connected to the first data signal input terminal, and the other of the source and drain of the second transistor is electrically connected to the third node; the first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the third node; the gate of the fourth transistor is electrically connected to either the first pulse width modulation signal input terminal or the second pulse width modulation signal input terminal, one of the source and drain of the fourth transistor is electrically connected to the first node, and the other of the source and drain of the fourth transistor is electrically connected to the second node; the gate of the sixth transistor is electrically connected to the first node, one of the source and drain of the sixth transistor is electrically connected to the first power supply signal input terminal, and the other of the source and drain of the sixth transistor is electrically connected to the pulse amplitude modulation module.

[0010] Embodiments of this application also provide a driving method for a display device, the driving method comprising the following steps: in a reset phase, a low-level signal is input through the first pulse width modulation signal input terminal, so that the potentials of the first node and the second node are both initial signal potentials; in a data signal writing phase, a first data signal is written to the third node through the first data signal input terminal; in a light-emitting phase, a high-level signal is input through the first light-emitting control signal input terminal, so that the first transistor is turned on; when the voltage of the ramp signal is greater than the voltage of the first data signal, the comparator outputs a low-level signal, the sixth transistor is turned on, and the light-emitting device emits light; when the voltage of the ramp signal is less than the voltage of the first data signal, the comparator outputs a high-level signal, the sixth transistor is turned off, and the light-emitting device stops emitting light. Beneficial effects

[0011] The technical solution of this application significantly improves the display uniformity of the display device at low grayscale levels by optimizing the pulse width modulation module. Specifically, this application introduces a comparator into the pulse width modulation module, enabling precise control of the switching process between dark and bright states of the light-emitting device. Specifically, the comparator compares the voltage of the ramp signal with the voltage of the first data signal, and controls the conduction state of the light-emitting device in a timely manner based on the comparison result, significantly shortening the transition time from dark to bright state, i.e., the rise time. Compared with traditional PHM driving circuits, the technical solution of this application optimizes the rise time from approximately 1 millisecond to approximately 0.1 milliseconds, achieving an optimization effect of approximately 90%. The shortened rise time directly increases the actual light-emitting time of the light-emitting device, thereby improving the brightness utilization rate of the display device. Simultaneously, because the rise time is more consistent across grayscale levels, the uniformity of the image displayed by the display device is significantly improved.

[0012] Furthermore, this application adds a duty cycle control module to the pulse width modulation module. This module achieves flexible adjustment of the emission duty cycle by selectively outputting ramp signals with different slopes. This technical solution is particularly suitable for low grayscale display scenarios, effectively improving the speckle problem caused by defects in the light-emitting device itself by adjusting the emission duty cycle at low grayscale levels. Compared with traditional PHM driving circuits, this application further improves the uniformity of the image displayed at low grayscale levels. Attached Figure Description

[0013] Figure 1 is a schematic diagram of the display device provided in this application.

[0014] Figure 2 is a circuit diagram of the pixel unit of the first embodiment of the display device provided in this application.

[0015] Figure 3 is a timing diagram of the pixel unit shown in Figure 2.

[0016] Figure 4 is a simulation diagram of the bright / dark switching speed of the light-emitting device in the pixel unit shown in Figure 2.

[0017] Figure 5 is a schematic diagram of the driving mode of the pixel driving circuit in the pixel unit shown in Figure 2.

[0018] Figure 6 is a circuit diagram of the pixel unit of a second embodiment of the display device provided in this application.

[0019] Figure 7 is a timing diagram of the pixel unit shown in Figure 6.

[0020] Figure 8 is a circuit diagram of the pixel unit of the third embodiment of the display device provided in this application.

[0021] Figure 9 is a timing diagram of the pixel unit shown in Figure 8.

[0022] Figure 10 is a circuit diagram of the pixel unit of the fourth embodiment of the display device provided in this application.

[0023] Figure 11 is a timing diagram of the pixel unit shown in Figure 10.

[0024] Figure 12 is a circuit diagram of the pixel unit of the fifth embodiment of the display device provided in this application.

[0025] Figure 13(a) is a timing diagram of the pixel unit shown in Figure 12 at high grayscale.

[0026] Figure 13(b) is a timing diagram of the pixel unit shown in Figure 12 at low gray levels. Embodiments of the present invention

[0027] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0028] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0029] The embodiments of this application can be combined with each other.

[0030] In traditional hybrid drive circuits combining pulse amplitude modulation (PAM) and pulse width modulation (PWM), the time for the light-emitting device to switch from a dark state to a bright state can exceed 1 millisecond, significantly impacting the actual light-emitting time of the device. Fluctuations in the time it takes for the light-emitting device to switch from a dark state to a bright state at different grayscale levels can cause display inconsistencies.

[0031] To address the problem of excessively long switching time for light-emitting devices from dark to bright states in traditional hybrid pulse amplitude modulation and pulse width modulation driving circuits, this application optimizes the pulse width modulation module 101. This application can shorten the bright / dark switching time of the light-emitting device and significantly improve the response speed of the light-emitting device from dark to bright states.

[0032] In addition, in order to further improve the problem of pixelation in display devices at low grayscale, this application further optimizes the pulse width modulation module 101 and adds a duty cycle control module, which effectively improves the problem of pixelation in the display screen of the display device at low grayscale.

[0033] As shown in Figure 1, the display device of the embodiments of this application may be, for example, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The display device includes a gate driving circuit, a source driving circuit, a timing controller, a light-emitting controller, a power management chip, a substrate, a data line (DATA), a scan line (SCAN), power lines (VDD, VSS), a light-emitting control signal line (EM), a pixel array, a packaging layer, a polarizer, a color filter, etc.

[0034] The substrate can be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array consists of multiple pixel units PX arranged in rows and columns. Each pixel unit PX includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes TFT devices. The light-emitting device is electrically connected to the pixel driving circuit and includes a light-emitting layer, an electron transport layer, a hole transport layer, a cathode, and an anode. Different light-emitting layer materials can emit light of different wavelengths. The encapsulation layer includes a multilayer structure of alternating organic and inorganic materials. The gate driving circuit controls the TFT devices to select the pixel units PX. Each gate driving circuit controls one row of pixel units PX. Each gate driving circuit mainly consists of thin-film transistors (TFTs) and capacitors. The source driving circuit provides data signals to the pixel units PX. The timing controller receives externally input image data and synchronization signals, generating the signals required by the gate driving circuit and the source driving circuit. The power management chip provides the necessary operating voltages to various parts of the display device.

[0035] In addition, the display device of this application can also integrate an embedded touch circuit, which is electrically connected to a timing controller, and uses time-division multiplexing to realize touch and display functions.

[0036] This application proposes a novel hybrid drive circuit combining pulse amplitude modulation (PAM) and pulse width modulation (PWM). A comparator is incorporated into the pulse width modulation module 101, thereby shortening the circuit's dim-to-bright switching time. The operating principle of this circuit is as follows:

[0037] First embodiment:

[0038] As shown in Figures 2, 3, 4, and 5, the pulse width modulation module 101 of this embodiment includes a comparator, a first transistor PT1, a second transistor PT2, a fourth transistor PT4, a sixth transistor PT6, and a first capacitor C1. The first transistor PT1, the second transistor PT2, the fourth transistor PT4, and the sixth transistor PT6 are all P-type transistors.

[0039] The comparator consists of a third transistor PT3 and a fifth transistor PT5. PT3 is a P-type transistor, and PT5 is an N-type transistor. The gates of PT3 and PT5 are electrically connected. One of the sources and drains of PT3 is electrically connected to the high-level signal input terminal VGH, and the other is electrically connected to the first node A. One of the sources and drains of PT5 is electrically connected to the low-level signal input terminal VGL, and the other is electrically connected to the first node A. When PT3 is on, PT5 is off; when PT3 is off, PT5 is on.

[0040] The gate of the first transistor PT1 is electrically connected to the first light-emitting control signal input terminal EM_PWM1, one of its source and drain is electrically connected to the first ramp signal input terminal Sweep1, and the other of its source and drain is electrically connected to the third node C.

[0041] The gate of the second transistor PT2 is electrically connected to the second pulse width modulation signal input terminal PWM[n], one of its source and drain is electrically connected to the first data signal input terminal Data_PWM, and the other of its source and drain is electrically connected to the third node C.

[0042] One end of the first capacitor C1 is electrically connected to the second node B, and the other end is electrically connected to the third node C.

[0043] The gate of the fourth transistor PT4 is electrically connected to the first pulse width modulation signal input terminal PWM[n-1], one of its source and drain is electrically connected to the first node A, and the other of its source and drain is electrically connected to the second node B.

[0044] The gate of the sixth transistor PT6 is electrically connected to the first node A, one of its source and drain is electrically connected to the first power signal input terminal VDD_PAM, and the other of its source and drain is electrically connected to the pulse amplitude modulation module 102.

[0045] The pulse amplitude modulation module 102 of this application includes a seventh transistor PT7, an eighth transistor PT8, a ninth transistor PT9, a tenth transistor PT10, an eleventh transistor PT11, and a twelfth transistor PT12. All of these transistors are P-type transistors.

[0046] The gate of the seventh transistor PT7 is electrically connected to the second pulse amplitude modulation signal input terminal PAM[n], one of its source and drain is electrically connected to the second data signal input terminal Data_PAM, and the other of its source and drain is electrically connected to the source or drain of the sixth transistor PT6.

[0047] One of the source and drain of the eighth transistor PT8 is electrically connected to the source or drain of the sixth transistor PT6, and the other of the source and drain is electrically connected to the fourth node D.

[0048] The gate of the ninth transistor PT9 is electrically connected to the second pulse amplitude modulation signal input terminal PAM[n], one of its source and drain is electrically connected to the gate of the eighth transistor PT8, and the other of its source and drain is electrically connected to the fourth node D.

[0049] The gate of the tenth transistor PT10 is electrically connected to the third light-emitting control signal input terminal EM_PAM, one of its source and drain is electrically connected to the fourth node D, and the other of its source and drain is electrically connected to the anode of the light-emitting device.

[0050] The cathode of the light-emitting device is electrically connected to the second power signal input terminal VSS.

[0051] The gate of the eleventh transistor PT11 is electrically connected to the first pulse amplitude modulation signal input terminal PAM[n-1], one of its source and drain is electrically connected to the reset signal input terminal Vi, and the other of its source and drain is electrically connected to the gate of the eighth transistor PT8.

[0052] The gate of the twelfth transistor PT12 is electrically connected to the reset control signal input terminal Discharge, one of its source and drain is electrically connected to the reset signal input terminal Viled of the anode of the light-emitting device, and the other of its source and drain is electrically connected to the anode of the light-emitting device.

[0053] The pixel driving circuit of this application has three operating stages: reset stage, data signal writing stage, and light emission stage.

[0054] Reset Phase: A low-level signal is input to the first pulse width modulation signal input terminal PWM[n-1], making the potentials of the first node A and the second node B equal to the initial signal potential Vcm. A low-level signal is input to the first pulse amplitude modulation signal input terminal PAM[n-1], turning on the eleventh transistor PT11. The reset signal input terminal Vi writes a low level to the gate of the eighth transistor PT8 (driving transistor) through the eleventh transistor PT11, resetting node Qa. A low-level signal is also input to the reset control signal input terminal Discharge, turning on the twelfth transistor PT12. The reset signal input terminal Viled resets the anode of the light-emitting device through the twelfth transistor PT12.

[0055] Data signal writing stage: The first data signal input terminal, Data_PWM, writes the potential Vdata_pwm into the third node C. At this time, the first capacitor C1 stores the voltage difference between Vdata_pwm and Vcm. The second pulse amplitude modulation signal input terminal, PAM[n], inputs a low-level signal, turning on the seventh transistor PT7 and the ninth transistor PT9. The data signal from the second data signal input terminal, Data_PAM, is written to the gate of the eighth transistor PT8, performing threshold voltage compensation on the eighth transistor PT8.

[0056] Light-emitting stage: The first transistor PT1 is turned on, and a ramp signal is input to the first ramp signal input terminal Sweep1. This ramp signal is compared with the first data signal to determine the circuit's light-emitting duty cycle (the proportion of time the light-emitting device emits light within one frame). The voltage of the ramp signal gradually changes. A low-level signal is input to the third light-emitting control signal input terminal EM_PAM, the tenth transistor PT10 is turned on, and the current provided by the first power supply signal input terminal VDD_PAM flows through the light-emitting device, causing the device to start emitting light.

[0057] When the voltage Vsweep of the ramp signal is greater than the voltage Vdata_pwm of the first data signal, the comparator (including the third transistor PT3 and the fifth transistor PT5) outputs a low-level signal. This causes the potential of the first node A to become greater than Vcm through the first capacitor C1, resulting in the sixth transistor PT6 turning on, and the light-emitting device starting to emit light.

[0058] When the voltage Vsweep of the ramp signal is less than the voltage Vdata_pwm of the first data signal, the comparator outputs a high-level signal, which turns off the sixth transistor PT6 and stops the light-emitting device from emitting light.

[0059] In this embodiment, the third light emission control signal input at the third light emission control signal input terminal EM_PAM can be the same signal as the first light emission control signal input at the first light emission control signal input terminal EM_PWM1 and the second light emission control signal input at the second light emission control signal input terminal EM_PWM2, or they can be different signals.

[0060] As shown in Figure 4, Figure 4 is divided into three parts: upper, middle, and lower. The upper part shows the waveform of the current signal flowing through the light-emitting device at different gray levels (represented by different colors), the middle part shows the waveform of the ramp signal, and the lower part shows the waveform of the light-emitting control signal. It can be observed from the upper part that the rise time of each waveform is approximately 0.1 milliseconds.

[0061] As shown in Figure 5, this figure illustrates waveforms at multiple different gray levels within the high, medium, and low gray level ranges. The display effect of gray levels is determined by both current and time (i.e., the duration of light emission).

[0062] The high grayscale range can be, for example, 200-255. Within this range, the waveform time (duty cycle) remains constant, while the current value varies. This means that the display of different grayscale levels within the high grayscale range can be achieved by adjusting the magnitude of the current.

[0063] The mid-grayscale range can be, for example, 100-199. Within this range, the current value (peak current) of the waveform remains constant, while the time varies. This indicates that the display between different grayscale levels within the mid-grayscale range can be achieved by adjusting the emission time.

[0064] The low grayscale range can be, for example, 0-99. Within this range, a shorter time (duty cycle) is selected, and a relatively high current is used to drive the light-emitting device to emit light. This method can, to some extent, compensate for differences between different chips and improve the uniformity of low grayscale displays.

[0065] Second embodiment:

[0066] The main difference between this embodiment and the first embodiment lies in the connection method of the fourth transistor PT4. As shown in Figures 6 and 7, in this embodiment, the gate of the fourth transistor PT4 is electrically connected to the second pulse width modulation signal input terminal PWM[n].

[0067] This embodiment optimizes the pulse width modulation module 101. When the second pulse width modulation signal input terminal PWM[n] receives a low-level signal, the first data signal input terminal Data_PWM writes data to the third node C. Simultaneously, the fourth transistor PT4 is turned on, allowing the third node C to directly control the first node A after being charged through the first capacitor C1, thereby preventing the internal nodes of the circuit from being in a floating state.

[0068] Third embodiment:

[0069] The third embodiment is similar to the first embodiment, except that:

[0070] As shown in Figures 8 and 9, this embodiment adds a thirteenth transistor PT13 based on the first embodiment. The gate of the thirteenth transistor PT13 is electrically connected to the first pulse width modulation signal input terminal PWM[n-1], one of its source and drain is electrically connected to the reference voltage signal input terminal Vref, and the other of its source and drain is electrically connected to the first node A.

[0071] This improvement further reduces the possibility of nodes inside the drive circuit being in a floating state. When the first pulse width modulation signal input terminal PWM[n-1] receives a low-level signal, the thirteenth transistor PT13 turns on, resetting the first node A. Simultaneously, the fourth transistor PT4 turns on, making the voltage VA of the first node A equal to the voltage VB of the second node B. Other operating states remain unchanged.

[0072] The pixel driving circuit of this application optimizes the time for the light-emitting device to switch from dark to bright state to about 0.1 milliseconds, which is about 90% better than the 1 millisecond of the traditional circuit.

[0073] Fourth embodiment:

[0074] The fourth embodiment is similar to the first embodiment, except that:

[0075] To reduce production costs and improve process yield, the circuitry in this embodiment has been optimized. The main change is that the N-type transistor in the comparator has been replaced with a P-type transistor.

[0076] As shown in Figures 10 and 11, in this embodiment, the third transistor PT3 and the fifth transistor PT5 of the comparator are both P-type transistors. The gate of the third transistor PT3 is still electrically connected to the second node B, but the gate of the fifth transistor PT5 is changed to be electrically connected to the low-level signal input terminal VGL.

[0077] Fifth embodiment:

[0078] The fifth embodiment is similar to the first embodiment, except that:

[0079] As shown in Figures 12, 13(a), and 13(b), this embodiment adds a duty cycle control module to address the potential speckle problem in display devices at low grayscale levels. This improvement helps to mitigate uniformity issues caused by defects in the light-emitting devices themselves, thereby enhancing the display effect.

[0080] At low grayscale, this embodiment improves the speckle problem by further reducing the light emission duty cycle. Compared to the first embodiment, in this embodiment, the gate of the first transistor PT1 in the pulse width modulation module 101 is electrically connected to the first light emission control signal input terminal EM_PWM1, and one of the source and drain is electrically connected to the first ramp signal input terminal Sweep1.

[0081] In addition, a fourteenth transistor PT14 is added to the pulse width modulation module 101. The gate of the fourteenth transistor PT14 is electrically connected to the second light emission control signal input terminal EM_PWM2, one of its source and drain is electrically connected to the second ramp signal input terminal Sweep2, and the other of its source and drain is electrically connected to the third node C.

[0082] The first transistor PT1 and the fourteenth transistor PT14 together constitute a duty cycle control module, which is used to selectively output the first ramp signal or the second ramp signal to the third node C.

[0083] By optimizing the pulse width modulation module 101, this application improves the bright / dark switching speed of the light-emitting device, enhances the light emission reduction characteristics, and increases the actual light emission duty cycle, thereby improving display uniformity. By adding a duty cycle control module, this application further optimizes the pulse width modulation module 101, effectively improving the speckle problem at low grayscale levels.

[0084] The display device provided in the embodiments of this application includes a plurality of pixel units PX, each pixel unit PX including a light-emitting device and a pixel driving circuit, the light-emitting device and the pixel driving circuit being electrically connected, and the pixel driving circuit including a pulse amplitude modulation module 102 and a pulse width modulation module 101.

[0085] The pulse width modulation module 101 includes a comparator, a first transistor PT1, a second transistor PT2, a fourth transistor PT4, a sixth transistor PT6, and a first capacitor C1.

[0086] The comparator is electrically connected to the high-level signal input terminal VGH, the first node A, the second node B, and the low-level signal input terminal VGL of the pulse width modulation module 101. Specifically, the comparator includes a third transistor PT3 and a fifth transistor PT5. One of the source and drain of the third transistor PT3 is electrically connected to the high-level signal input terminal VGH, and the other of the source and drain of the third transistor PT3 is electrically connected to the first node A. The third transistor PT3 is also electrically connected to the second node B. One of the source and drain of the fifth transistor PT5 is electrically connected to the low-level signal input terminal VGL, and the other of the source and drain of the fifth transistor PT5 is electrically connected to the first node A. The gate of the fifth transistor PT5 is electrically connected to either the second node B or the low-level signal input terminal VGL.

[0087] The gate of the first transistor PT1 is electrically connected to the first light-emitting control signal input terminal EM_PWM1, one of the source and drain of the first transistor PT1 is electrically connected to the first ramp signal input terminal Sweep1, and the other of the source and drain of the first transistor PT1 is electrically connected to the third node C.

[0088] The gate of the second transistor PT2 is electrically connected to the second pulse width modulation signal input terminal PWM[n]. One of the source and drain of the second transistor PT2 is electrically connected to the first data signal input terminal Data_PWM. The other of the source and drain of the second transistor PT2 is electrically connected to the third node C.

[0089] The first plate of the first capacitor C1 is electrically connected to the second node B, and the second plate of the first capacitor C1 is electrically connected to the third node C.

[0090] The gate of the fourth transistor PT4 is electrically connected to either the first pulse width modulation signal input terminal PWM[n-1] or the second pulse width modulation signal input terminal PWM[n]. One of the sources and drains of the fourth transistor PT4 is electrically connected to the first node A, and the other of the sources and drains of the fourth transistor PT4 is electrically connected to the second node B.

[0091] The gate of the sixth transistor PT6 is electrically connected to the first node A, one of the source and drain of the sixth transistor PT6 is electrically connected to the first power signal input terminal VDD_PAM, and the other of the source and drain of the sixth transistor PT6 is electrically connected to the pulse amplitude modulation module 102.

[0092] In this embodiment, the first transistor PT1 and the second transistor PT2 are single-gate structures.

[0093] As an improvement, the first transistor PT1 and the second transistor PT2 are dual-gate structures. Specifically, the back gates of the first transistor PT1 and the second transistor PT2 are connected to an adjustable voltage source. By adjusting the voltage of this voltage source, the threshold voltages of the first transistor PT1 and the second transistor PT2 can be controlled, thereby optimizing the switching characteristics of the first transistor PT1 and the second transistor PT2.

[0094] When the voltage at the ramp signal input terminals (Sweep1, Sweep2) is higher than the voltage at the first data signal input terminal (Data_PWM), the third transistor PT3 is turned on, and the fifth transistor PT5 is turned off. At this time, a high-level signal is transmitted to the first node A through the third transistor PT3. Conversely, when the voltage at the ramp signal input terminals (Sweep1, Sweep2) is lower than the voltage at the first data signal input terminal (Data_PWM), the third transistor PT3 is turned off, and the fifth transistor PT5 is turned on, and a low-level signal is transmitted to the first node A. The embodiments of this application enable the comparator to complete state switching in a very short time (typically less than 1 microsecond), thereby greatly shortening the dimming / brightness switching time of the light-emitting device.

[0095] In the duty cycle control module, the ramp signal input terminals (Sweep1, Sweep2) are electrically connected to the digital-to-analog converter (DAC), meaning that the ramp signal is generated by the digital-to-analog converter (DAC), which enables more grayscale levels.

[0096] When a display device displays a large area of ​​dark image, the slope of the ramp signal is lower than the preset value to extend the display time of low grayscale, thereby improving the display quality of dark images.

[0097] The pulse amplitude modulation module 102 includes a seventh transistor PT7, an eighth transistor PT8, a ninth transistor PT9, a tenth transistor PT10, an eleventh transistor PT11, and a twelfth transistor PT12.

[0098] The gate of the seventh transistor PT7 is electrically connected to the second pulse amplitude modulation signal input terminal PAM[n]. One of the sources and drains of the seventh transistor PT7 is electrically connected to the second data signal input terminal Data_PAM. The other of the sources and drains of the seventh transistor PT7 is electrically connected to the other of the sources and drains of the sixth transistor PT6.

[0099] One of the source and drain of the eighth transistor PT8 is electrically connected to the other of the source and drain of the sixth transistor PT6, and the other of the source and drain of the eighth transistor PT8 is electrically connected to the fourth node D.

[0100] The gate of the ninth transistor PT9 is electrically connected to the second pulse amplitude modulation signal input terminal PAM[n]. One of the source and drain of the ninth transistor PT9 is electrically connected to the gate of the eighth transistor PT8. The other of the source and drain of the ninth transistor PT9 is electrically connected to the fourth node D.

[0101] The gate of the tenth transistor PT10 is electrically connected to the third light-emitting control signal input terminal EM_PAM. One of the source and drain of the tenth transistor PT10 is electrically connected to the fourth node D. The other of the source and drain of the tenth transistor PT10 is electrically connected to the anode of the light-emitting device.

[0102] The gate of the eleventh transistor PT11 is electrically connected to the first pulse amplitude modulation signal input terminal PAM[n-1]. One of the source and drain of the eleventh transistor PT11 is electrically connected to the reset signal input terminal Vi. The other of the source and drain of the eleventh transistor PT11 is electrically connected to the gate of the eighth transistor PT8.

[0103] The gate of the twelfth transistor PT12 is electrically connected to the reset control signal input terminal Discharge. One of the sources and drains of the twelfth transistor PT12 is electrically connected to the reset signal input terminal Viled of the anode of the light-emitting device. The other of the sources and drains of the twelfth transistor PT12 is electrically connected to the anode of the light-emitting device.

[0104] The first transistor PT1, the second transistor PT2, the third transistor PT3, the fourth transistor PT4 and the sixth transistor PT6 are all P-type transistors, and the fifth transistor PT5 is an N-type transistor. The gate of the fifth transistor PT5 is electrically connected to the second node B.

[0105] The first transistor PT1, the second transistor PT2, the third transistor PT3, the fourth transistor PT4, the fifth transistor PT5, and the sixth transistor PT6 are all P-type transistors. The gate of the fifth transistor PT5 is electrically connected to the low-level signal input terminal VGL.

[0106] The pulse width modulation module 101 also includes a thirteenth transistor PT13. The gate of the thirteenth transistor PT13 is electrically connected to the first pulse width modulation signal input terminal PWM[n-1]. One of the source and drain of the thirteenth transistor PT13 is electrically connected to the reference voltage signal input terminal Vref. The other of the source and drain of the thirteenth transistor PT13 is electrically connected to the first node A.

[0107] The pulse width modulation module 101 also includes a duty cycle control module, which includes a first transistor PT1 and a fourteenth transistor PT14. The gate of the fourteenth transistor PT14 is electrically connected to the second light emission control signal input terminal EM_PWM2, one of its source and drain is electrically connected to the second ramp signal input terminal Sweep2, and the other of its source and drain is electrically connected to the third node C.

[0108] Among them, the first transistor PT1 and the fourteenth transistor PT14 are used to selectively output the first ramp signal and the second ramp signal to the third node C.

[0109] The waveforms of the first ramp signal and the second ramp signal have different slopes.

[0110] The voltages of the first and second ramp signals change linearly with time.

[0111] The pulse amplitude modulation module 102 is used to switch gray levels (control the display of different gray levels) by adjusting the current amplitude when the gray level corresponding to the displayed data is within the range of the second predetermined gray level (high gray level) (above the preset threshold). The pulse width modulation module 101 is used to switch gray levels (control the display of different gray levels) by adjusting the light emission time when the gray level corresponding to the displayed data is within the range of the first predetermined gray level (low gray level) (below or equal to the preset threshold).

[0112] The duty cycle control module is used to reduce the light emission duty cycle (the proportion of the light emission time of the light emission device in the cycle of one frame) when the gray level corresponding to the displayed data is within the range of the first predetermined gray level (low gray level) (lower than or equal to the preset threshold), so as to improve the display uniformity.

[0113] As an improvement, an inverter is placed between the third transistor PT3 and the fifth transistor PT5. The inverter consists of two additional transistors. Adding an inverter can improve the switching speed of the comparator while reducing power consumption caused by transient currents during transistor switching.

[0114] The first capacitor C1 serves as a coupler in this circuit, and its capacitance value directly affects the circuit's response speed and stability. A larger capacitance value can provide better noise suppression, but it will also increase the circuit's response time.

[0115] As an improvement, the first capacitor C1 is a variable capacitor. The variable capacitor dynamically adjusts its capacitance value according to different display scenarios. For example, when displaying rapidly changing dynamic images, the capacitance value of the variable capacitor decreases to improve response speed; when displaying static or slowly changing images, the capacitance value of the variable capacitor increases to improve noise immunity. This variable capacitor can be implemented by switching between multiple fixed capacitors connected in parallel, and the switching process of the variable capacitor is controlled by an independent control circuit.

[0116] As an improvement, the display device of this application also includes an image processing module and a drive control module.

[0117] The image processing module is used to analyze the image data input to the display device and calculate the grayscale value of each pixel and the local average brightness of the area where the pixel is located.

[0118] The drive control module is used to generate a ramp signal for each pixel, such as a first ramp signal (lower slope) and a second ramp signal (higher slope), based on the grayscale value of each pixel and the local average brightness of the area where the pixel is located, provided by the image processing module, and to transmit the ramp signal to the duty cycle control module.

[0119] For example, if a low grayscale pixel is surrounded by high-brightness pixels, the drive control module generates a ramp signal with a larger slope to control the light-emitting device to emit light for a shorter time, thereby reducing the contrast with the surrounding high-brightness pixels and making the image transition smoother.

[0120] The drive control module also includes the aforementioned digital-to-analog converter (DAC) and programmable voltage generator. The programmable voltage generator contains multiple capacitors and switches, which are used to generate ramp signals with different slopes and starting voltages by controlling the switches and capacitors.

[0121] The drive control module is used to read the corresponding parameters from a preset lookup table (LUT) according to the current gray level of the pixel at the beginning of each frame period, and then generate the corresponding ramp signal through the aforementioned digital-to-analog converter (DAC) and programmable voltage generator.

[0122] The duty cycle control module is used to selectively output the corresponding ramp signal based on the received light emission control signal and ramp signal. If the first light emission control signal input terminal EM_PWM1 receives a low-level signal, the first transistor PT1 is turned on, and the first ramp signal (lower ramp) is output to the third node C. If the second light emission control signal input terminal EM_PWM2 receives a low-level signal, the fourteenth transistor PT14 is turned on, and the second ramp signal (higher ramp) is output to the third node C.

[0123] During the light emission stage, the pulse width modulation module 101 is used to control the light emission time of the light-emitting device according to the ramp signal output to the third node C.

[0124] The display device provided in the embodiments of this application displays a frame of image in a cycle that includes a reset phase, a data signal writing phase, and a light emission phase.

[0125] The driving method for a display device provided in the embodiments of this application includes the following steps:

[0126] During the reset phase, a low-level signal is input through the first pulse width modulation signal input terminal PWM[n-1], so that the potentials of the first node A and the second node B are both the initial signal potentials.

[0127] During the data signal writing phase, the first data signal is written to the third node C through the first data signal input terminal Data_PWM.

[0128] During the light-emitting phase, a high-level signal is input to the first light-emitting control signal input terminal EM_PWM1, turning on the first transistor PT1. When the voltage of the ramp signals (first ramp signal and second ramp signal) is greater than the voltage of the first data signal, the comparator outputs a low-level signal, turning on the sixth transistor PT6, and the light-emitting device emits light. When the voltage of the ramp signals is less than the voltage of the first data signal, the comparator outputs a high-level signal, turning off the sixth transistor PT6, and the light-emitting device stops emitting light.

[0129] The driving method also includes:

[0130] During the reset phase, a low-level signal is input through the first pulse width modulation signal input terminal PWM[n-1] to turn on the thirteenth transistor PT13 and reset the first node A.

[0131] The driving method also includes:

[0132] When the gray level corresponding to the displayed data is within the range of the first predetermined gray level (low gray level), the duty cycle control module selectively outputs the first ramp signal or the second ramp signal to the third node C to reduce the light emission duty cycle.

[0133] The voltages of the first and second ramp signals change linearly with time.

[0134] The first and second ramp signals have different slopes, which are used to control different emission duty cycles.

[0135] When the gray level corresponding to the displayed data is within the range of the second predetermined gray level (high gray level) (above the preset threshold), the pulse amplitude modulation module 102 switches the gray level by adjusting the current amplitude (controlling the display of different gray levels).

[0136] When the gray level corresponding to the displayed data is within the range of the first predetermined gray level (low gray level) (lower than or equal to the preset threshold), the pulse width modulation module 101 switches the gray level by adjusting the light emission time (controlling the display of different gray levels).

[0137] When the gray level corresponding to the displayed data is within the range of the first predetermined gray level (low gray level) (lower than or equal to the preset threshold), the duty cycle control module reduces the light emission duty cycle to improve display uniformity.

[0138] As an improvement, the first capacitor C1 is a variable capacitor.

[0139] The driving method also includes:

[0140] The variable capacitor dynamically adjusts its capacitance value according to different display scenarios. For example, when displaying rapidly changing dynamic images, the capacitance value of the variable capacitor decreases to improve response speed; when displaying static or slowly changing images, the capacitance value of the variable capacitor increases to improve noise immunity. This variable capacitor is implemented by switching between multiple fixed capacitors connected in parallel, and the switching process of the variable capacitor is controlled by an independent control circuit.

[0141] As an improvement, the display device of this application also includes an image processing module and a drive control module.

[0142] The driving method also includes:

[0143] The image processing module analyzes the image data input to the display device and calculates the grayscale value of each pixel and the local average brightness of the area where the pixel is located.

[0144] The drive control module generates a ramp signal for each pixel based on the grayscale value of each pixel and the local average brightness of the area where the pixel is located, such as a first ramp signal (lower slope) and a second ramp signal (higher slope), and transmits the ramp signal to the duty cycle control module.

[0145] For example, if a low grayscale pixel is surrounded by high-brightness pixels, the drive control module generates a ramp signal with a larger slope to control the light-emitting device to emit light for a shorter time, thereby reducing the contrast with the surrounding high-brightness pixels and making the image transition smoother.

[0146] The drive control module also includes the aforementioned digital-to-analog converter (DAC) and programmable voltage generator. The programmable voltage generator contains multiple capacitors and switches, which are used to generate ramp signals with different slopes and starting voltages by controlling the switches and capacitors.

[0147] At the beginning of each frame period, the drive control module reads the corresponding parameters from a preset lookup table (LUT) based on the current gray level of the pixel, and then generates the corresponding ramp signal through the aforementioned digital-to-analog converter (DAC) and programmable voltage generator.

[0148] The duty cycle control module selectively outputs the corresponding ramp signal based on the received light emission control signal and ramp signal. If the first light emission control signal input terminal EM_PWM1 receives a low-level signal, the first transistor PT1 is turned on, and the first ramp signal (lower ramp) is output to the third node C. If the second light emission control signal input terminal EM_PWM2 receives a low-level signal, the fourteenth transistor PT14 is turned on, and the second ramp signal (higher ramp) is output to the third node C.

[0149] During the light-emitting stage, the pulse width modulation module 101 controls the light-emitting time of the light-emitting device according to the ramp signal output to the third node C.

[0150] As shown in Figures 4 and 5, the technical solution of this application significantly improves the display uniformity of the display device at low gray levels by optimizing the pulse width modulation module 101. Specifically, this application introduces a comparator into the pulse width modulation module 101 to achieve precise control over the switching process of the light-emitting device between dark and bright states. Specifically, the comparator compares the voltage of the ramp signal with the voltage of the first data signal, and controls the conduction state of the light-emitting device in a timely manner based on the comparison result, significantly shortening the transition time from dark to bright state, i.e., the rise time. As shown in Figure 4, the upper part of the figure represents the waveform of the current signal flowing through the light-emitting device at different gray levels. It can be observed that the rise time of each waveform is approximately 0.1 milliseconds.

[0151] Compared to traditional PHM driving circuits, the technical solution in this application optimizes the rise time from approximately 1 millisecond to approximately 0.1 milliseconds, achieving an optimization effect of about 90%. The shortened rise time directly increases the actual light-emitting time of the light-emitting device, thereby improving the brightness utilization rate of the display device. Simultaneously, due to the more consistent rise time across different gray levels, the uniformity of the displayed image is significantly improved.

[0152] As shown in Figure 5, this figure illustrates waveforms of multiple different gray levels within the high gray level range (e.g., 200-255), the medium gray level range (e.g., 100-199), and the low gray level range (e.g., 0-99). The gray level display effect is determined by both the current and the duration of light emission.

[0153] Within the high grayscale range, the waveform's time (duty cycle) remains constant, while the current value varies. This means that the display between different grayscale levels within the high grayscale range can be achieved by adjusting the current magnitude.

[0154] Within the mid-grayscale range, the current value (peak current) of the waveform remains constant, while the timing varies. This indicates that the display between different grayscale levels within the mid-grayscale range is achieved by adjusting the emission time.

[0155] In the low grayscale range, a shorter duty cycle is selected, and a relatively higher current is used to drive the light-emitting device to emit light. This method can, to some extent, compensate for the differences between different chips and improve the uniformity of low grayscale displays.

[0156] Furthermore, this application adds a duty cycle control module to the pulse width modulation module 101. This module achieves flexible adjustment of the emission duty cycle by selectively outputting ramp signals with different slopes. This technical solution is particularly suitable for low grayscale display scenarios, effectively improving the speckle problem caused by defects in the light-emitting device itself by adjusting the emission duty cycle at low grayscale levels. Compared with traditional PHM driving circuits, this application further improves the uniformity of the image displayed at low grayscale levels.

[0157] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, wherein, include: A plurality of pixel units (PX), each of the pixel units (PX) comprising: Light-emitting devices; and A pixel driving circuit, the pixel driving circuit including a pulse width modulation module (101) and a pulse amplitude modulation module (102); The pulse width modulation module (101) includes a comparator, a first transistor (PT1), a second transistor (PT2), a fourth transistor (PT4), a sixth transistor (PT6), and a first capacitor (C1). The comparator is electrically connected to the high-level signal input terminal (VGH), the first node (A), the second node (B), and the low-level signal input terminal (VGL) of the pulse width modulation module (101); The gate of the first transistor (PT1) is electrically connected to the first light emission control signal input terminal (EM_PWM1), one of the source and drain of the first transistor (PT1) is electrically connected to the first ramp signal input terminal (Sweep1), and the other of the source and drain of the first transistor (PT1) is electrically connected to the third node (C). The gate of the second transistor (PT2) is electrically connected to the second pulse width modulation signal input terminal (PWM[n]), one of the source and drain of the second transistor (PT2) is electrically connected to the first data signal input terminal (Data_PWM), and the other of the source and drain of the second transistor (PT2) is electrically connected to the third node (C). The first plate of the first capacitor (C1) is electrically connected to the second node (B), and the second plate of the first capacitor (C1) is electrically connected to the third node (C). The gate of the fourth transistor (PT4) is electrically connected to either the first pulse width modulation signal input terminal (PWM[n-1]) or the second pulse width modulation signal input terminal (PWM[n]). One of the source and drain of the fourth transistor (PT4) is electrically connected to the first node (A), and the other of the source and drain of the fourth transistor (PT4) is electrically connected to the second node (B). The gate of the sixth transistor (PT6) is electrically connected to the first node (A), one of the source and drain of the sixth transistor (PT6) is electrically connected to the first power signal input terminal (VDD_PAM), and the other of the source and drain of the sixth transistor (PT6) is electrically connected to the pulse amplitude modulation module (102).

2. The display device according to claim 1, wherein, The comparator includes a third transistor (PT3) and a fifth transistor (PT5). One of the source and drain of the third transistor (PT3) is electrically connected to a high-level signal input terminal (VGH), and the other of the source and drain of the third transistor (PT3) is electrically connected to the first node (A). The third transistor (PT3) is also electrically connected to the second node (B). One of the source and drain of the fifth transistor (PT5) is electrically connected to the low-level signal input terminal (VGL), and the other of the source and drain of the fifth transistor (PT5) is electrically connected to the first node (A). The gate of the fifth transistor (PT5) is electrically connected to either the second node (B) or the low-level signal input terminal (VGL).

3. The display device according to claim 2, wherein, The first transistor (PT1), the second transistor (PT2), the third transistor (PT3), the fourth transistor (PT4), and the sixth transistor (PT6) are all P-type transistors, and the fifth transistor (PT5) is an N-type transistor. The gate of the fifth transistor (PT5) is electrically connected to the second node (B).

4. The display device according to claim 2, wherein, The first transistor (PT1), the second transistor (PT2), the third transistor (PT3), the fourth transistor (PT4), the fifth transistor (PT5), and the sixth transistor (PT6) are all P-type transistors, and the gate of the fifth transistor (PT5) is electrically connected to the low-level signal input terminal (VGL).

5. The display device according to claim 2, wherein, The pulse width modulation module (101) further includes a thirteenth transistor (PT13), the gate of which is electrically connected to the first pulse width modulation signal input terminal (PWM[n-1]), one of the source and drain of the thirteenth transistor (PT13) is electrically connected to the reference voltage signal input terminal (Vref), and the other of the source and drain of the thirteenth transistor (PT13) is electrically connected to the first node (A).

6. The display device according to claim 2, wherein, The pulse width modulation module (101) further includes a duty cycle control module, which includes the first transistor (PT1); The duty cycle control module also includes: The fourteenth transistor (PT14) has its gate electrically connected to the second light emission control signal input terminal (EM_PWM2), one of its source and drain electrically connected to the second ramp signal input terminal (Sweep2), and the other of its source and drain electrically connected to the third node (C). The first transistor (PT1) and the fourteenth transistor (PT14) are used to selectively output the first ramp signal and the second ramp signal to the third node (C).

7. The display device according to claim 6, wherein, The waveforms of the first ramp signal and the second ramp signal have different slopes.

8. The display device according to claim 6 or 7, wherein, The voltages of the first ramp signal and the second ramp signal change linearly with time.

9. The display device according to claim 6, wherein, The duty cycle control module is used to reduce the light emission duty cycle when the gray level corresponding to the displayed data is within a first predetermined gray level range.

10. The display device according to claim 1, wherein, The pulse width modulation module (101) is used to switch gray levels by adjusting the light emission time when the gray level corresponding to the displayed data is within a first predetermined gray level range; the pulse amplitude modulation module (102) is used to switch gray levels by adjusting the current amplitude when the gray level corresponding to the displayed data is within a second predetermined gray level range.

11. The display device according to claim 1, wherein, The slope of the ramp signal is lower than a preset value when the display device displays a dark image.

12. The display device according to claim 1, wherein, The display device further includes a digital-to-analog converter for generating the first ramp signal and the second ramp signal; The first ramp signal input terminal (Sweep1) and the second ramp signal input terminal (Sweep2) are electrically connected to the digital-to-analog converter.

13. A driving method for a display device, wherein, The driving method includes the following steps: During the reset phase, a low-level signal is input through the first pulse width modulation signal input terminal (PWM[n-1]) so that the potentials of the first node (A) and the second node (B) are both the initial signal potentials; During the data signal writing phase, a first data signal is written to the third node (C) through the first data signal input terminal (Data_PWM); During the light-emitting phase, a high-level signal is input through the first light-emitting control signal input terminal (EM_PWM1) to turn on the first transistor (PT1). When the voltage of the ramp signal is greater than the voltage of the first data signal, the comparator outputs a low-level signal, the sixth transistor (PT6) turns on, and the light-emitting device emits light. When the voltage of the ramp signal is less than the voltage of the first data signal, the comparator outputs a high-level signal, the sixth transistor (PT6) turns off, and the light-emitting device stops emitting light.

14. The driving method according to claim 13, wherein, The driving method further includes: During the reset phase, a low-level signal is input through the first pulse width modulation signal input terminal (PWM[n-1]) to turn on the thirteenth transistor (PT13) and reset the first node (A).

15. The driving method according to claim 13, wherein, The ramp signal includes a first ramp signal or a second ramp signal; The driving method further includes: When the gray level corresponding to the displayed data is within the first predetermined gray level range, the duty cycle control module selectively outputs the first ramp signal or the second ramp signal to the third node (C).

16. The driving method according to claim 15, wherein, The waveforms of the first ramp signal and the second ramp signal have different slopes.

17. The driving method according to claim 15 or 16, wherein, The voltages of the first ramp signal and the second ramp signal change linearly with time.

18. The driving method according to claim 13, wherein, Also includes: When the gray level corresponding to the displayed data is within the second predetermined gray level range, the gray level is switched by adjusting the current amplitude; When the gray level corresponding to the displayed data is within the first predetermined gray level range, the gray level is switched by adjusting the emission time.

19. The driving method according to claim 13, wherein, Also includes: When the gray level corresponding to the displayed data is within the first predetermined gray level range, reduce the emission duty cycle.

20. The driving method according to claim 13, wherein, Also includes: When displaying a dark scene, reduce the slope of the ramp signal.

Images