Driving backplane and display panel

Abstract

The present application provides a driving backplane and a display panel. The driving backplane comprises a substrate, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a second conductive layer provided on the substrate. The first semiconductor layer forms an active portion of a polysilicon transistor, the first conductive layer forms a gate of the polysilicon transistor, the second semiconductor layer forms an active portion of an oxide transistor and a first electrode plate of a storage capacitor, and the second conductive layer forms a gate of the oxide transistor.

Description

Drive backplane and display panel Technical Field

[0001] This application relates to the field of display technology, and more particularly to a driving backplane and a display panel. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the resolution, power consumption, and image quality of display products. To meet these requirements, Low Temperature Polycrystalline Oxide (LTPO) technology is often used to fabricate the pixel driving circuits in the driving backplane of display products. LTPO technology combines the high mobility of Low Temperature Poly Silicon (LTPS) with the low leakage current of oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), offering advantages such as high resolution, high response speed, high brightness, high aperture ratio, low power consumption, and support for refresh rates from 1Hz to 120Hz.

[0003] However, the low-temperature polycrystalline oxide driving backplane requires the fabrication of two types of thin film transistor (TFT) devices, which involves many film layers, resulting in complex processes, low fabrication efficiency, and high manufacturing costs. Invention Overview

[0004] This application provides a driving backplane and a display panel to alleviate the technical problems of low-temperature polycrystalline oxide driving backplanes, such as the large number of film layers, complex processes, low preparation efficiency, and high manufacturing costs.

[0005] The technical solution provided in this application is as follows:

[0006] In a first aspect, embodiments of this application provide a driving backplane, which includes a display area and a non-display area located on one side of the display area. The display area is provided with a plurality of sub-pixels arranged in an array, each sub-pixel including a polysilicon transistor, an oxide transistor, and a storage capacitor. The driving backplane further includes:

[0007] Substrate;

[0008] A first semiconductor layer is disposed on one side of the substrate, and the first semiconductor layer includes the active portion of the polysilicon transistor;

[0009] A first conductive layer is disposed on the side of the first semiconductor layer away from the substrate, and the first conductive layer includes the gate of the polysilicon transistor;

[0010] A second semiconductor layer is disposed on the side of the first conductive layer away from the substrate. The second semiconductor layer includes a first electrode of a storage capacitor and an active portion of the oxide transistor. The first electrode of the storage capacitor is disposed corresponding to the gate of the polysilicon transistor.

[0011] A second conductive layer is disposed on the side of the second semiconductor layer away from the substrate, and the second conductive layer includes the gate of the oxide transistor;

[0012] A third conductive layer is disposed on the side of the second conductive layer away from the substrate, and the third conductive layer includes the source and drain of the polysilicon transistor and the source and drain of the oxide transistor.

[0013] The non-display area includes a fan-out area located near the display area. The fan-out area has alternating first fan-out traces and second fan-out traces. The first fan-out trace is located in at least one of the first conductive layer and the second conductive layer. The second fan-out trace is located in at least one of the second conductive layer and the third conductive layer. The first fan-out trace and the second fan-out trace are located on different layers, and the first fan-out trace and the second fan-out trace have the same impedance.

[0014] Secondly, embodiments of this application also provide a display panel, which includes a light-emitting device and a driving backplate as described in one of the foregoing embodiments, wherein the light-emitting device is disposed on the driving backplate. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 is a schematic diagram of a planar structure of a drive backplate provided in an embodiment of this application.

[0017] Figure 2 is a schematic diagram of a portion of the membrane structure of the drive backplate provided in an embodiment of this application.

[0018] Figure 3 is a schematic diagram showing the detailed structure of the fan-out region in Figure 1.

[0019] Figure 4 is a schematic diagram of a cross-sectional structure along the M-M' direction in Figure 3.

[0020] Figure 5 is a schematic diagram of another cross-sectional structure along the M-M' direction in Figure 3.

[0021] Figure 6 is a schematic diagram of another planar structure of the drive backplate provided in an embodiment of this application.

[0022] Figure 7 is a schematic diagram showing the detailed structure of the edge routing of the hole area in Figure 6.

[0023] Figure 8 is a circuit diagram of a sub-pixel provided in an embodiment of this application. Embodiments of the present invention

[0024] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.

[0025] This application provides a driving backplane, which includes a display area and a non-display area located on one side of the display area. The display area has multiple sub-pixels arranged in an array, and each sub-pixel includes a polysilicon transistor, an oxide transistor, and a storage capacitor. The driving backplane also includes:

[0026] Substrate;

[0027] A first semiconductor layer is disposed on one side of the substrate, and the first semiconductor layer includes the active portion of the polysilicon transistor;

[0028] A first conductive layer is disposed on the side of the first semiconductor layer away from the substrate, and the first conductive layer includes the gate of the polysilicon transistor;

[0029] A second semiconductor layer is disposed on the side of the first conductive layer away from the substrate. The second semiconductor layer includes a first electrode of a storage capacitor and an active portion of the oxide transistor. The first electrode of the storage capacitor is disposed corresponding to the gate of the polysilicon transistor.

[0030] A second conductive layer is disposed on the side of the second semiconductor layer away from the substrate, and the second conductive layer includes the gate of the oxide transistor;

[0031] A third conductive layer is disposed on the side of the second conductive layer away from the substrate, and the third conductive layer includes the source and drain of the polysilicon transistor and the source and drain of the oxide transistor.

[0032] The non-display area includes a fan-out area located near the display area. The fan-out area has alternating first fan-out traces and second fan-out traces. The first fan-out trace is located in at least one of the first conductive layer and the second conductive layer. The second fan-out trace is located in at least one of the second conductive layer and the third conductive layer. The first fan-out trace and the second fan-out trace are located on different layers, and the first fan-out trace and the second fan-out trace have the same impedance.

[0033] In one embodiment, the first fan-out trace is located in the first conductive layer, the second fan-out trace is located in the second conductive layer, the ratio of the length of the first fan-out trace to its cross-sectional area is a first ratio, the ratio of the length of the second fan-out trace to its cross-sectional area is a second ratio, and the second ratio is equal to the first ratio.

[0034] In one embodiment, the second fan-out trace includes a blocking portion and a conductive portion located on the side of the blocking portion away from the substrate, the thickness of the conductive portion being the same as the thickness of the first fan-out trace.

[0035] In one embodiment, the conductive portion is made of molybdenum, the blocking portion is made of titanium, and the first fan-out trace is made of the same material as the conductive portion.

[0036] In one embodiment, the first fan-out trace includes a first sub-trace located on the first conductive layer and a second sub-trace located on the second conductive layer, the first sub-trace and the second sub-trace being connected in parallel, and the second fan-out trace being located on the third conductive layer.

[0037] In one embodiment, the orthographic projection of the first sub-trace on the substrate overlaps with the orthographic projection of the second sub-trace on the substrate.

[0038] In one embodiment, the orthographic projection of the first fan-out trace on the substrate at least partially overlaps with the orthographic projection of the second fan-out trace on the substrate.

[0039] In one embodiment, the driving backplane further includes a fourth conductive layer disposed between the substrate and the first semiconductor layer, the fourth conductive layer including a first light-shielding portion disposed corresponding to the active portion and a second light-shielding portion disposed corresponding to the active portion.

[0040] In one embodiment, the second light-shielding portion is electrically connected to the gate of the oxide transistor.

[0041] In one embodiment, both the first fan-out trace and the second fan-out trace extend along a first direction, and the first fan-out trace and the second fan-out trace are staggered in the first direction; the drive backplate further includes a cutout area disposed in the display area, the first conductive layer further includes a first winding located in the display area, and the second conductive layer further includes a second winding located in the display area, both the first winding and the second winding extending along the first direction;

[0042] The drive backplate further includes a first winding group and a second winding group. The first winding group is configured to cooperate with the second winding group to surround the cut-out area. Both the first winding group and the second winding group include a plurality of first windings and second windings alternately arranged in a second direction. The first direction and the second direction are different. The angle between the second direction and the first direction is greater than 0 degrees and less than or equal to 90 degrees.

[0043] In one embodiment, there is a gap between the orthographic projection of the first winding on the substrate and the orthographic projection of the second winding on the substrate.

[0044] In one embodiment, each sub-pixel further includes:

[0045] A switching transistor, wherein the gate of the switching transistor is connected to a first scan signal line, and the first electrode of the switching transistor is connected to a data line;

[0046] A driving transistor, wherein the first electrode of the driving transistor is connected to the second electrode of the switching transistor at a first node;

[0047] A compensation transistor, wherein the gate of the compensation transistor is connected to a second scan signal line, the first electrode of the compensation transistor is connected to the gate of the driving transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor;

[0048] A first initialization transistor, the gate of the first initialization transistor is connected to a third scan signal line, the first electrode of the first initialization transistor is connected to a first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the driving transistor at a second node;

[0049] The first light-emitting control transistor has its gate connected to the light-emitting control signal line, its first electrode connected to the high-potential power supply line, and its second electrode connected to the first electrode of the driving transistor at the first node.

[0050] The second light-emitting control transistor has its gate connected to the light-emitting control signal line, and its first electrode is connected to the second electrode of the driving transistor at the third node.

[0051] The second initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the second initialization signal line, and its second electrode connected to the second light-emitting control transistor at the fourth node.

[0052] The third initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the third initialization signal line, and its second electrode connected to the first electrode of the driving transistor at the first node.

[0053] A first capacitor, one plate of which is connected to the high-potential power line, and the other plate of which is connected to the gate of the driving transistor at a second node;

[0054] The second capacitor has one plate connected to the first scan signal line and the other plate connected to the second electrode of the first initialization transistor.

[0055] The polysilicon transistor includes the switching transistor, the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the second initialization transistor, and the third initialization transistor; the oxide transistor includes the compensation transistor and the first initialization transistor; the first capacitor is the storage capacitor, and the second capacitor is the boost capacitor.

[0056] In one embodiment, the first winding and the second winding may be at least one of the following: the first scanning signal line, the second scanning signal line, the third scanning signal line, the fourth scanning signal line, the light emission control signal line, the first initialization signal line, the second initialization signal line, and the third initialization signal line.

[0057] In one embodiment, the first plate of the storage capacitor is disposed corresponding to the gate of the driving transistor.

[0058] This application also provides a display panel, which includes a light-emitting device and a driving backplate as described in one of the foregoing embodiments, wherein the light-emitting device is disposed on the driving backplate.

[0059] The driving backplane and display panel provided in this application include a driving backplane comprising multiple sub-pixels arranged in an array in the display area. Each sub-pixel includes a polysilicon transistor, an oxide transistor, and a storage capacitor. The driving backplane also includes a substrate and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer disposed on the substrate. The first semiconductor layer forms the active portion of the polysilicon transistor, and the first conductive layer forms the gate of the polysilicon transistor. The second semiconductor layer forms the active portion of the oxide transistor and the first electrode of the storage capacitor, the second conductive layer forms the gate of the oxide transistor, and the third conductive layer forms the source of the polysilicon transistor. The storage capacitor's first electrode and the active portion of the oxide transistor are arranged in the same layer as the drain and the source and drain of the oxide transistor. This eliminates the conductive layer between the second semiconductor layer and the first conductive layer, thereby simplifying the film layers of the driving backplane, simplifying the fabrication process, improving fabrication efficiency, and reducing manufacturing costs. In addition, at least one of the first and second conductive layers has a first fan-out trace, and at least one of the second and third conductive layers has a second fan-out trace. The first fan-out trace and the second fan-out trace are located on different layers, and the impedances of the first fan-out trace and the second fan-out trace are the same, thereby improving display uniformity.

[0060] The driving backplane and display panel of this application will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0061] Please refer to Figures 1 to 5. Figure 1 is a schematic planar structure of a driving backplane provided in an embodiment of this application. Figure 2 is a schematic diagram of a partial film layer structure of the driving backplane provided in an embodiment of this application. Figure 3 is a detailed structural diagram of the fan-out area in Figure 1. Figure 4 is a schematic cross-sectional structure diagram along the M-M' direction in Figure 3. Figure 5 is a schematic cross-sectional structure diagram along the M-M' direction in Figure 3. Referring to Figures 1 and 2, the driving backplane 100 includes a display area AA and a non-display area BA located on one side of the display area AA. Multiple sub-pixels SP are arranged in an array within the display area AA. For example, the multiple sub-pixels SP are arranged sequentially in a first direction X and sequentially in a second direction Y. The first direction X and the second direction Y are different. The angle between the first direction X and the second direction Y is greater than 0 degrees and less than or equal to 90 degrees. For example, the first direction X is perpendicular to the second direction Y, that is, the first direction X is the row direction and the second direction Y is the column direction. Each sub-pixel SP includes a polysilicon transistor 1, an oxide transistor 2, and a storage capacitor C1. The non-display area BA includes the fan-out area SA located near the display area AA. The fan-out area SA is used to fan out various signal traces within the display area AA.

[0062] The driving backplane 100 also includes a substrate 10 and a first semiconductor layer 20, a first conductive layer 30, a second semiconductor layer 40, and a second conductive layer 50 disposed on the substrate 10. The first semiconductor layer 20 is disposed on one side of the substrate 10 and includes the active portion 21 of a polysilicon transistor 1. The first conductive layer 30 is disposed on the side of the first semiconductor layer 20 away from the substrate 10 and includes the gate 31 of the polysilicon transistor 1, with the gate 31 corresponding to the active portion 21 of the polysilicon transistor 1. The second semiconductor layer 40 is disposed on the side of the first conductive layer 30 away from the substrate 10 and includes the first electrode 42 of a storage capacitor C1 and the active portion 41 of an oxide transistor 2, with the first electrode 42 of the storage capacitor C1 corresponding to the gate 31 of the polysilicon transistor 1. The second conductive layer 50 is disposed on the side of the second semiconductor layer 40 away from the substrate 10. The second conductive layer 50 includes the gate 51 of the oxide transistor 2, and the gate 51 of the oxide transistor 2 is disposed correspondingly to the active portion 41 of the oxide transistor 2. In this way, by making the first electrode 42 of the storage capacitor C1 and the active portion 41 of the oxide transistor 2 co-layered, the conductive layer between the second semiconductor layer 40 and the first conductive layer 30 can be removed, thereby simplifying the film layers of the driving backplane 100, simplifying the fabrication process, improving fabrication efficiency, and reducing manufacturing costs.

[0063] Specifically, the driving backplane 100 further includes a third conductive layer 60 and a fourth conductive layer 70. The third conductive layer 60 is disposed on the side of the second conductive layer 50 away from the substrate 10. The third conductive layer 60 includes the source 61 and drain 62 of the polysilicon transistor 1 and the source 64 and drain 63 of the oxide transistor 2. The fourth conductive layer 70 is disposed between the substrate 10 and the first semiconductor layer 20. The fourth conductive layer 70 includes a first light-shielding portion 71 and a second light-shielding portion 72. The first light-shielding portion 71 is disposed corresponding to the active portion 21 of the polysilicon transistor 1, and the second light-shielding portion 72 is disposed corresponding to the active portion 41 of the oxide transistor 2. Of course, the driving backplane 100 also includes an insulating layer located between each conductive layer and the semiconductor layer.

[0064] Specifically, referring to FIG2, a fourth conductive layer 70 is disposed on one side of the substrate 10, and a first buffer layer 11 and a second buffer layer 12 are disposed between the fourth conductive layer 70 and the first semiconductor layer 20. The first buffer layer 11 covers the fourth conductive layer 70 and the substrate 10, and the second buffer layer 12 covers the first buffer layer 11. Optionally, the substrate 10 can be an inorganic material substrate or an organic material substrate. For example, in one embodiment of this application, the material of the substrate 10 can be a glass material such as soda-lime glass, quartz glass, or sapphire glass, or a metal material such as stainless steel, aluminum, or nickel. In another embodiment of this application, the substrate 10 can also be a flexible substrate, for example, the material of the substrate 10 can be polyimide (PI). The substrate 10 can also be a composite of multilayer materials. The first buffer layer 11 and the second buffer layer 12 can be inorganic thin films, such as SiNx, SiOx, or a composite layer thereof. The material of the fourth conductive layer 70 includes a metal material with light-shielding properties.

[0065] A first semiconductor layer 20 is disposed on the second buffer layer 12. The material of the first semiconductor layer 20 includes semiconductor materials such as polysilicon. The active portion 21 of the polysilicon transistor 1 formed by the first semiconductor layer 20 includes a first channel portion 211 and a first source contact portion 212 and a first drain contact portion 213 located on opposite sides of the first channel portion 211. A first light-shielding portion 71 is disposed at least corresponding to the first channel portion 211 to shield the first channel portion 211 from light.

[0066] A first insulating layer 13 is disposed between the first semiconductor layer 20 and the first conductive layer 30. The material of the first insulating layer 13 includes inorganic materials such as SiNx and SiOx. The material of the first conductive layer 30 includes a metallic material with conductive properties, such as molybdenum. The gate 31 formed by the first conductive layer 30 is disposed correspondingly to the first channel portion 211.

[0067] A second insulating layer 14 is disposed between the first conductive layer 30 and the second semiconductor layer 40. The material of the second insulating layer 14 includes inorganic materials such as SiNx and SiOx. The material of the second semiconductor layer 40 includes metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO). The second semiconductor layer 40 forms the active portion 41 of the oxide transistor 2 and the first electrode 42 of the storage capacitor C1. The active portion 41 of the oxide transistor 2 includes a second channel portion 411 and a second source contact portion 412 and a second drain contact portion 413 located on opposite sides of the second channel portion 411. A second light-shielding portion 72 is disposed at least corresponding to the second channel portion 411 to shield the second channel portion 411 from light. The first electrode 42 of the storage capacitor C1 is disposed corresponding to the gate 31 of the polysilicon transistor 1 to form the storage capacitor C1. Of course, in some embodiments, the second light-shielding portion 72 may also be electrically connected to the gate 51 of the oxide transistor 2 to serve as the bottom gate of the oxide transistor 2.

[0068] A third insulating layer 15 is disposed between the second semiconductor layer 40 and the second conductive layer 50. The material of the third insulating layer 15 includes inorganic materials such as SiNx and SiOx. The material of the second conductive layer 50 includes metallic materials with conductive properties, such as molybdenum and titanium. That is, the second conductive layer 50 can be formed by two metal layers, a titanium layer and a molybdenum layer. The molybdenum layer is located on the side of the titanium layer away from the substrate 10. The titanium layer is used to block hydrogen from the upper layer to avoid affecting the active part 41.

[0069] A fourth insulating layer 16 is disposed between the second conductive layer 50 and the third conductive layer 60. The material of the fourth insulating layer 16 includes inorganic materials such as SiNx and SiOx. An opening 161 is formed on the fourth insulating layer 16. The material of the third conductive layer 60 includes conductive metals such as titanium, aluminum, and copper. The third conductive layer 60 forms the source 61 and drain 62 of the polysilicon transistor 1, and the source 64 and drain 63 of the oxide transistor 2. The source 61 of the polysilicon transistor 1 is connected to the first source contact 212, the drain 62 of the polysilicon transistor 1 is connected to the first drain contact 213, the source 64 of the oxide transistor 2 is connected to the second source contact 412, and the drain 63 of the oxide transistor 2 is connected to the second drain contact 413.

[0070] The drive backplane 100 also includes a fifth conductive layer 80 and a sixth conductive layer 90. The fifth conductive layer 80 is located on the side of the third conductive layer 60 away from the substrate 10, and the sixth conductive layer 90 is located on the side of the fifth conductive layer 80 away from the substrate 10. A first planarization layer 17 is disposed between the third conductive layer 60 and the fifth conductive layer 80. The first planarization layer 17 is made of an organic material and fills the opening 161. The fifth conductive layer 80 is made of the same material as the third conductive layer 60. The fifth conductive layer 80 forms a transition electrode 81, which is connected to the drain 62 of the polysilicon transistor 1.

[0071] A second planarization layer 18 is disposed between the fifth conductive layer 80 and the sixth conductive layer 90. The material of the second planarization layer 18 includes an organic material. The material of the sixth conductive layer 90 includes a transparent conductive material such as indium tin oxide. A first electrode 91 is formed on the sixth conductive layer 90, and the first electrode 91 is connected to the transition electrode 81.

[0072] The drive backplane 100 also includes a third planarization layer 19 and a barrier 92. The material of the third planarization layer 19 includes an organic material. The third planarization layer 19 covers the sixth conductive layer 90 and the second planarization layer 18, and the third planarization layer 19 has an opening 191 at the position corresponding to the first electrode 91, the opening 191 exposing a portion of the first electrode 91. The barrier 92 is disposed on the third planarization layer 19 and is located around the opening 191.

[0073] Referring to Figure 3, alternating first fan-out traces 32 and second fan-out traces 52 are provided in the fan-out area SA. The first fan-out trace 32 is located in at least one of the first conductive layer 30 and the second conductive layer 50, and the second fan-out trace 52 is located in at least one of the second conductive layer 50 and the third conductive layer 60. The first fan-out trace 32 and the second fan-out trace 52 are located in different layers, and the impedance of the first fan-out trace 32 and the second fan-out trace 52 is the same to improve display uniformity.

[0074] In one embodiment, the first fan-out trace 32 is located in the first conductive layer 30, and the second fan-out trace 52 is located in the second conductive layer 50. That is, the first conductive layer 30 also includes the first fan-out trace 32 located in the fan-out region SA, and the second conductive layer 50 also includes the second fan-out trace 52 located in the fan-out region SA. The first fan-out trace 32 and the second fan-out trace 52 are arranged alternately in the first direction X, and the impedance of the first fan-out trace 32 and the second fan-out trace 52 is the same to improve display uniformity.

[0075] The ratio of the length of the first outgoing trace 32 to its cross-sectional area is a first ratio, and the ratio of the length of the second outgoing trace 52 to its cross-sectional area is a second ratio. The second ratio is equal to the first ratio, so that the impedances of the first outgoing trace 32 and the second outgoing trace 52 are the same. Moreover, the fan-out region SA includes multiple first outgoing traces 32 and multiple second outgoing traces 52, with each first outgoing trace 32 having the same impedance, and each second outgoing trace 52 also having the same impedance.

[0076] Optionally, referring to FIG4, the width of the first outgoing trace 32 is the same as the width of the second outgoing trace 52. The second outgoing trace 52 includes a blocking portion 522 and a conductive portion 521 located on the side of the blocking portion 522 away from the substrate 10. The thickness H2 of the conductive portion 521 is the same as the thickness H1 of the first outgoing trace 32. The material of the conductive portion 521 includes molybdenum, the material of the blocking portion 522 includes titanium, and the material of the first outgoing trace 32 is the same as the material of the conductive portion 521.

[0077] The orthographic projection of the first outgoing trace 32 on the substrate 10 is separate from the orthographic projection of the second outgoing trace 52 on the substrate 10, meaning there is no overlap between them. This reduces the parasitic capacitance between the first and second outgoing traces 32. Furthermore, this application uses a first conductive layer 30 to form the first outgoing trace 32 and a second conductive layer 50 to form the second outgoing trace 52. The first conductive layer 30 and the second conductive layer 50 are separated by two insulating layers, a second insulating layer 14 and a third insulating layer 15, and a second semiconductor layer 40. This increases the distance between the first and second outgoing traces 32, further reducing the parasitic capacitance between them and improving display uniformity.

[0078] In some other embodiments, the orthographic projection of the first fan-out trace 32 on the substrate 10 is at least partially overlapping with the orthographic projection of the second fan-out trace 52 on the substrate 10, so as to reduce the area of ​​the non-display area BA occupied by the fan-out area SA, thereby increasing the screen ratio.

[0079] In another embodiment, referring to FIG5, the first fan-out trace 32 includes a first sub-trace 321 located on the first conductive layer 30 and a second sub-trace 322 located on the second conductive layer 50. The first sub-trace 321 and the second sub-trace 322 are connected in parallel. The second fan-out trace 52 is located on the third conductive layer 60. That is, the first conductive layer 30 also includes the first sub-trace 321 located in the fan-out region SA, the second conductive layer 50 also includes the second sub-trace 322 located in the fan-out region SA, and the third conductive layer 60 also includes the second fan-out trace 52 located in the fan-out region SA. The second sub-trace 322 is connected to the first sub-trace 321 through multiple contact holes on the third insulating layer 15 to realize the parallel connection of the first sub-trace 321 and the second sub-trace 322, thereby reducing the impedance of the first fan-out trace 32.

[0080] Optionally, the orthographic projection of the first sub-trace 321 on the substrate 10 overlaps with the orthographic projection of the second sub-trace 322 on the substrate 10, so as to reduce the area occupied by the first fan-out trace 32 in the fan-out region SA.

[0081] Of course, in some other embodiments, the first outgoing trace 32 may also be located in the first conductive layer 30, and the second outgoing trace 52 may be located in the second conductive layer 50 and the third conductive layer 60; or, the first outgoing trace 32 may also be located in the first conductive layer 30, and the second outgoing trace 52 may be located in the third conductive layer 60; or, the first outgoing trace 32 may also be located in the second conductive layer 50, and the second outgoing trace 52 may be located in the third conductive layer 60.

[0082] In one embodiment, referring to Figures 1 to 8, Figure 6 is a schematic diagram of another planar structure of the driving backplate 100 provided in an embodiment of this application, Figure 7 is a detailed structural diagram of the edge wiring of the punched area HA in Figure 6, and Figure 8 is a circuit diagram of the sub-pixel SP provided in an embodiment of this application. Referring to Figure 6, unlike the above embodiment, the driving backplate 100 further includes a punched area HA disposed in the display area AA. The punched area HA is formed by punching holes in the driving backplate 100. Functional components such as cameras can be disposed below the punched area HA. ​​The punched area HA is used to transmit light and improve the light-gathering effect of functional components such as cameras.

[0083] Referring to Figure 7, the first conductive layer 30 further includes a first winding 33 located within the display area AA, and the second conductive layer 50 further includes a second winding 53 located within the display area AA. Both the first winding 33 and the second winding 53 extend along the first direction X. The drive backplate 100 also includes a first winding group 331 and a second winding group 332. The first winding group 331 is configured to cooperate with the second winding group 332 to surround the cutout area HA. ​​Both the first winding group 331 and the second winding group 332 include a plurality of first windings 33 and second windings 53 alternately arranged in the second direction Y. The first winding group 331 and the second winding group 332 are symmetrically arranged about the cutout area HA.

[0084] Optionally, there is a gap between the orthographic projection of the first winding 33 on the substrate 10 and the orthographic projection of the second winding 53 on the substrate 10, that is, the orthographic projections of the first winding 33 and the second winding 53 on the substrate 10 do not overlap, so as to reduce the parasitic capacitance between the first winding 33 and the second winding 53. In addition, by using a first conductive layer 30 to form the first winding 33 and a second conductive layer 50 to form the second winding 53, and with two insulating layers, a second insulating layer 14 and a third insulating layer 15, and a second semiconductor layer 40 spaced between the first conductive layer 30 and the second conductive layer 50, the distance between the first winding 33 and the second winding 53 can be increased, thereby further reducing the parasitic capacitance between the first winding 33 and the second winding 53 and improving the uniformity of the display.

[0085] The first winding 33 and the second winding 53 can be various control signal lines or scan lines on the driving backplane 100. Specifically, referring to FIG8, taking each sub-pixel SP as an example including 8 transistors and 2 capacitors, the 8 transistors are driving transistor T1, switching transistor T2, compensation transistor T3, first initialization transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second initialization transistor T7, and third initialization transistor T8. The 2 capacitors are the first capacitor Cst and the second capacitor Cboost.

[0086] Specifically, the gate of the switching transistor T2 is connected to the first scan signal line Pscan, and the first electrode of the switching transistor T2 is connected to the data line DATA.

[0087] The first electrode of the driving transistor T1 and the second electrode of the switching transistor T2 are connected to the first node A.

[0088] The gate of the compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1.

[0089] The gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q.

[0090] The gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM, the first electrode of the first light-emitting control transistor T5 is connected to the high-potential power supply line VDD, and the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1 at the first node A.

[0091] The gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM, and the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T1 at the third node B.

[0092] The gate of the second initialization transistor T7 is connected to the fourth scan signal line Pscan2, the first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and the second electrode of the second initialization transistor T7 is connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C.

[0093] The gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2, the first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and the second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 at the first node A.

[0094] One plate of the first capacitor Cst is connected to the high-potential power line VDD, and the other plate of the first capacitor Cst is connected to the gate of the driving transistor T1 at the second node Q.

[0095] One plate of the second capacitor Cboost is connected to the first scan signal line Pscan, and the other plate of the second capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0096] The polysilicon transistor 1 includes a switching transistor T2, a driving transistor T1, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, and a third initialization transistor T8; the oxide transistor 2 includes a compensation transistor T3 and a first initialization transistor T4; the first capacitor Cst is a storage capacitor C1, and the second capacitor Cboost is a boost capacitor. The first winding 33 and the second winding 53 can be at least one of the following: a first scan signal line Pscan, a second scan signal line Nscan1, a third scan signal line Nscan2, a fourth scan signal line Pscan2, a light-emitting control signal line EM, a first initialization signal line VI-G, a second initialization signal line VI-ANO, and a third initialization signal line VI3.

[0097] Optionally, the first plate 42 of the storage capacitor C1 is configured to correspond to the gate of the driving transistor T1.

[0098] It should be noted that in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source. The first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM can be connected to different gate driving circuits respectively. Specifically, five sets of gate driving circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM respectively. Among them, the gate driving circuit connected to the first scan signal line Pscan can be double-sided driving, and the other gate driving circuits are single-sided driving.

[0099] Based on the same inventive concept, this application also provides a display panel, which includes a light-emitting device and a driving backplate 100 of one of the aforementioned embodiments. The light-emitting device is disposed on the driving backplate 100, and the driving backplate 100 is used to drive the light-emitting device to emit light.

[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0101] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A driving backplane, comprising a display area and a non-display area located on one side of the display area, wherein the display area is provided with a plurality of sub-pixels arranged in an array, each sub-pixel comprising a polysilicon transistor, an oxide transistor, and a storage capacitor; the driving backplane further comprising: Substrate; A first semiconductor layer is disposed on one side of the substrate, and the first semiconductor layer includes the active portion of the polysilicon transistor; A first conductive layer is disposed on the side of the first semiconductor layer away from the substrate, and the first conductive layer includes the gate of the polysilicon transistor; A second semiconductor layer is disposed on the side of the first conductive layer away from the substrate. The second semiconductor layer includes a first electrode of a storage capacitor and an active portion of the oxide transistor. The first electrode of the storage capacitor is disposed corresponding to the gate of the polysilicon transistor. A second conductive layer is disposed on the side of the second semiconductor layer away from the substrate, and the second conductive layer includes the gate of the oxide transistor; A third conductive layer is disposed on the side of the second conductive layer away from the substrate, and the third conductive layer includes the source and drain of the polysilicon transistor and the source and drain of the oxide transistor. The non-display area includes a fan-out area located near the display area. The fan-out area has alternating first fan-out traces and second fan-out traces. The first fan-out trace is located in at least one of the first conductive layer and the second conductive layer. The second fan-out trace is located in at least one of the second conductive layer and the third conductive layer. The first fan-out trace and the second fan-out trace are located on different layers, and the first fan-out trace and the second fan-out trace have the same impedance.

2. The drive backplane according to claim 1, wherein, The first fan-out trace is located in the first conductive layer, and the second fan-out trace is located in the second conductive layer. The ratio of the length of the first fan-out trace to its cross-sectional area is a first ratio, and the ratio of the length of the second fan-out trace to its cross-sectional area is a second ratio. The second ratio is equal to the first ratio.

3. The drive backplane according to claim 2, wherein, The second fan-out trace includes a blocking portion and a conductive portion located on the side of the blocking portion away from the substrate, and the thickness of the conductive portion is the same as the thickness of the first fan-out trace.

4. The drive backplane according to claim 3, wherein, The conductive part is made of molybdenum, the blocking part is made of titanium, and the first fan-out trace is made of the same material as the conductive part.

5. The drive backplane according to claim 1, wherein, The first fan-out trace includes a first sub-trace located on the first conductive layer and a second sub-trace located on the second conductive layer. The first sub-trace and the second sub-trace are connected in parallel, and the second fan-out trace is located on the third conductive layer.

6. The drive backplane according to claim 5, wherein, The orthographic projection of the first sub-trace on the substrate overlaps with the orthographic projection of the second sub-trace on the substrate.

7. The drive backplane according to claim 1, wherein, The orthographic projection of the first fan-out trace on the substrate at least partially overlaps with the orthographic projection of the second fan-out trace on the substrate.

8. The drive backplane according to claim 1, wherein, The driving backplane further includes a fourth conductive layer disposed between the substrate and the first semiconductor layer. The fourth conductive layer includes a first light-shielding portion disposed corresponding to the active portion of the polysilicon transistor and a second light-shielding portion disposed corresponding to the active portion of the oxide transistor.

9. The drive backplane according to claim 8, wherein, The second light-shielding portion is electrically connected to the gate of the oxide transistor.

10. The drive backplane according to any one of claims 1 to 9, wherein, The first sector outgoing cable and the second sector outgoing cable are arranged in an alternating manner in the first direction; The driving backplate further includes a cutout area disposed in the display area, the first conductive layer further includes a first winding located in the display area, and the second conductive layer further includes a second winding located in the display area, wherein both the first winding and the second winding extend along the first direction; The drive backplate further includes a first winding group and a second winding group. The first winding group is configured to cooperate with the second winding group to surround the cut-out area. Both the first winding group and the second winding group include a plurality of first windings and second windings alternately arranged in a second direction. The first direction and the second direction are different. The angle between the second direction and the first direction is greater than 0 degrees and less than or equal to 90 degrees.

11. The drive backplane according to claim 10, wherein, There is a gap between the orthographic projection of the first winding on the substrate and the orthographic projection of the second winding on the substrate.

12. The drive backplane according to claim 10, wherein, Each of the sub-pixels also includes: A switching transistor, wherein the gate of the switching transistor is connected to a first scan signal line, and the first electrode of the switching transistor is connected to a data line; A driving transistor, wherein the first electrode of the driving transistor is connected to the second electrode of the switching transistor at a first node; A compensation transistor, wherein the gate of the compensation transistor is connected to a second scan signal line, the first electrode of the compensation transistor is connected to the gate of the driving transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor; A first initialization transistor, the gate of the first initialization transistor is connected to a third scan signal line, the first electrode of the first initialization transistor is connected to a first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the driving transistor at a second node; The first light-emitting control transistor has its gate connected to the light-emitting control signal line, its first electrode connected to the high-potential power supply line, and its second electrode connected to the first electrode of the driving transistor at the first node. The second light-emitting control transistor has its gate connected to the light-emitting control signal line, and its first electrode is connected to the second electrode of the driving transistor at the third node. The second initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the second initialization signal line, and its second electrode connected to the second light-emitting control transistor at the fourth node. The third initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the third initialization signal line, and its second electrode connected to the first electrode of the driving transistor at the first node. A first capacitor, one plate of which is connected to the high-potential power line, and the other plate of which is connected to the gate of the driving transistor at a second node; The second capacitor has one plate connected to the first scan signal line and the other plate connected to the second electrode of the first initialization transistor. The polysilicon transistor includes the switching transistor, the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the second initialization transistor, and the third initialization transistor; the oxide transistor includes the compensation transistor and the first initialization transistor; the first capacitor is the storage capacitor, and the second capacitor is the boost capacitor.

13. The drive backplane according to claim 12, wherein, The first winding and the second winding can be at least one of the following: the first scanning signal line, the second scanning signal line, the third scanning signal line, the fourth scanning signal line, the light emission control signal line, the first initialization signal line, the second initialization signal line, and the third initialization signal line.

14. The drive backplane according to claim 12, wherein, The first plate of the storage capacitor is configured to correspond to the gate of the driving transistor.

15. A display panel, comprising a light-emitting device and a driving backplane, the light-emitting device being disposed on the driving backplane; the driving backplane comprising a display area and a non-display area located on one side of the display area, the display area having a plurality of sub-pixels arranged in an array, each sub-pixel comprising a polysilicon transistor, an oxide transistor, and a storage capacitor; the driving backplane further comprising: Substrate; A first semiconductor layer is disposed on one side of the substrate, and the first semiconductor layer includes the active portion of the polysilicon transistor; A first conductive layer is disposed on the side of the first semiconductor layer away from the substrate, and the first conductive layer includes the gate of the polysilicon transistor; A second semiconductor layer is disposed on the side of the first conductive layer away from the substrate. The second semiconductor layer includes a first electrode of a storage capacitor and an active portion of the oxide transistor. The first electrode of the storage capacitor is disposed corresponding to the gate of the polysilicon transistor. A second conductive layer is disposed on the side of the second semiconductor layer away from the substrate, and the second conductive layer includes the gate of the oxide transistor; A third conductive layer is disposed on the side of the second conductive layer away from the substrate, and the third conductive layer includes the source and drain of the polysilicon transistor and the source and drain of the oxide transistor. The non-display area includes a fan-out area located near the display area. The fan-out area has alternating first fan-out traces and second fan-out traces. The first fan-out trace is located in at least one of the first conductive layer and the second conductive layer. The second fan-out trace is located in at least one of the second conductive layer and the third conductive layer. The first fan-out trace and the second fan-out trace are located on different layers, and the first fan-out trace and the second fan-out trace have the same impedance.

16. The display panel according to claim 15, wherein, The first fan-out trace is located in the first conductive layer, and the second fan-out trace is located in the second conductive layer. The ratio of the length of the first fan-out trace to its cross-sectional area is a first ratio, and the ratio of the length of the second fan-out trace to its cross-sectional area is a second ratio. The second ratio is equal to the first ratio.

17. The display panel according to claim 15, wherein, The first fan-out trace includes a first sub-trace located on the first conductive layer and a second sub-trace located on the second conductive layer. The first sub-trace and the second sub-trace are connected in parallel, and the second fan-out trace is located on the third conductive layer.

18. The display panel according to claim 15, wherein, The driving backplane further includes a fourth conductive layer disposed between the substrate and the first semiconductor layer. The fourth conductive layer includes a first light-shielding portion disposed corresponding to the active portion of the polysilicon transistor and a second light-shielding portion disposed corresponding to the active portion of the oxide transistor.

19. The display panel according to any one of claims 15 to 18, wherein, The first sector outgoing cable and the second sector outgoing cable are arranged in an alternating manner in the first direction; The driving backplate further includes a cutout area disposed in the display area, the first conductive layer further includes a first winding located in the display area, and the second conductive layer further includes a second winding located in the display area, wherein both the first winding and the second winding extend along the first direction; The drive backplate further includes a first winding group and a second winding group. The first winding group is configured to cooperate with the second winding group to surround the cut-out area. Both the first winding group and the second winding group include a plurality of first windings and second windings alternately arranged in a second direction. The first direction and the second direction are different. The angle between the second direction and the first direction is greater than 0 degrees and less than or equal to 90 degrees.

20. The display panel according to claim 19, wherein, There is a gap between the orthographic projection of the first winding on the substrate and the orthographic projection of the second winding on the substrate.

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