Signal processing chip, electronic device, and signal processing method

Abstract

The present application provides a signal processing chip, an electronic device, and a signal processing method. The signal processing chip comprises: a low-pass filter, a comparator, and a first hysteresis voltage generation circuit, wherein an input end of the low-pass filter is connected to an input end of the signal processing chip, an output end of the low-pass filter is connected to a first input end of the comparator, an output end of the first hysteresis voltage generation circuit is connected to a second input end of the comparator, an output end of the comparator is connected to an input end of the first hysteresis voltage generation circuit, and the output end of the comparator is connected to an output end of the signal processing chip. According to the present application, large-swing noise can be suppressed.

Description

Signal processing chips, electronic devices and signal processing methods Technical Field

[0001] This application relates to the field of clock signal processing technology, and in particular to a signal processing chip, electronic device, and signal processing method. Background Technology

[0002] A phase-locked loop (PLL), as a feedback system that maintains phase synchronization between the output and input signals, requires a reference clock signal from a reference clock source. When a PLL is used in electronic devices, the radio frequency antenna can interfere with the reference clock signal, causing glitches and other noise. A reference clock signal with glitches input to the PLL will lead to lockout. To eliminate glitches in the reference clock signal, a clock signal processing module can be placed between the reference clock source and the PLL.

[0003] In related technologies, clock signal processing modules may include multiple transistors. The combination of multiple transistors can generate hysteresis voltage, and the hysteresis voltage can be varied by adjusting the size ratio between the transistors. However, generating a large hysteresis voltage would lead to some transistors becoming too large, resulting in adverse effects such as increased parasitic capacitance. Therefore, the hysteresis voltage generated by this approach is typically small, thus failing to suppress large-swing noise. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a signal processing chip, electronic device, and signal processing method capable of suppressing large-amplitude noise.

[0005] A first aspect of this application provides a signal processing chip, comprising: a low-pass filter, a comparator, and a first hysteresis voltage generation circuit. The input terminal of the low-pass filter is connected to the input terminal of the signal processing chip, the output terminal of the low-pass filter is connected to the input terminal of the comparator, the output terminal of the first hysteresis voltage generation circuit is connected to the second input terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the first hysteresis voltage generation circuit, and the output terminal of the comparator is connected to the output terminal of the signal processing chip.

[0006] During the signal processing chip's signal processing, a low-pass filter receives the signal to be processed from the chip's input terminal and performs low-pass filtering to reduce noise above the low-pass filter's cutoff frequency. For example, it can reduce noise swings above 1 GHz to within 50 mV, obtaining a low-pass filtered signal. The low-pass filter sends this filtered signal to the first input terminal of a comparator. The comparator compares the low-pass filtered signal with a reference signal to obtain a comparison result signal, which is then sent to a first hysteresis voltage generation circuit. This circuit generates a first hysteresis voltage based on the comparison result signal and sends it to the second input terminal of the comparator. Upon receiving the first hysteresis voltage, the comparator compares the low-pass filtered signal with the first hysteresis voltage, or it performs correlation operations on the first hysteresis voltage to obtain a calculated hysteresis voltage, and then compares the low-pass filtered signal with the calculated hysteresis voltage to obtain the comparison result signal. The comparator outputs the comparison result signal as its output signal.

[0007] In this application, the signal to be processed is first subjected to low-pass filtering, which significantly reduces the higher frequency noise in the signal. Then, a first hysteresis voltage is generated by a first hysteresis voltage generation circuit, and the low-pass filtered signal is compared with the first hysteresis voltage or its calculated hysteresis voltage, thereby suppressing the noise after reducing the swing amplitude. Therefore, this application can suppress large swing noise.

[0008] Based on this, the signal processing chip may further include a second hysteresis voltage generation circuit and an adder. The output of the comparator is also connected to the input of the second hysteresis voltage generation circuit, so that the comparator can send the comparison result signal to the second hysteresis voltage generation circuit, which can then generate a second hysteresis voltage upon receiving the comparison result signal.

[0009] The output of the second hysteresis voltage generation circuit is connected to the first input of the adder, the output of the first hysteresis voltage generation circuit is connected to the second input of the adder, and the output of the adder is connected to the second input of the comparator. Thus, the first hysteresis voltage generation circuit sends a first hysteresis voltage to the adder, and the second hysteresis voltage generation circuit sends a second hysteresis voltage to the adder. The adder performs an addition operation on the first and second hysteresis voltages to obtain a combined hysteresis voltage, which is then sent to the comparator for comparison.

[0010] Furthermore, the frequency of the second hysteresis voltage output by the second hysteresis voltage generation circuit is lower than the frequency of the first hysteresis voltage output by the first hysteresis voltage generation circuit. In other words, the second hysteresis voltage generation circuit can generate a lower frequency second hysteresis voltage, thereby suppressing lower frequency noise in the low-pass filtered signal output by the low-pass filter. The first hysteresis voltage generation circuit can generate a higher frequency first hysteresis voltage, thereby suppressing higher frequency noise in the low-pass filtered signal output by the low-pass filter. Therefore, this application can suppress both higher and lower frequency noise simultaneously, i.e., it can suppress wideband noise.

[0011] Furthermore, the comparator includes a cascaded first-stage comparator and a second-stage comparator. The input terminal of the first-stage comparator serves as the input terminal of the second-stage comparator, and the output terminal of the first-stage comparator is connected to the input terminal of the second-stage comparator. The output terminal of the first-stage comparator is connected to the input terminal of the first hysteresis voltage generation circuit, and the output terminal of the second-stage comparator is connected to the input terminal of the second hysteresis voltage generation circuit. In other words, the comparison result signal received by the first hysteresis voltage generation circuit is the result signal obtained after one stage of comparison, while the comparison result signal received by the second hysteresis voltage generation circuit is the result signal obtained after two stages of comparison. Therefore, compared to the second hysteresis voltage generation circuit, the comparison result signal received by the first hysteresis voltage generation circuit is faster and has a higher frequency. This results in the first hysteresis voltage generated by the first hysteresis voltage generation circuit having a higher frequency than the second hysteresis voltage generated by the second hysteresis voltage generation circuit.

[0012] In some embodiments of this application, the first-stage comparator includes a first transistor and a second transistor. The first terminals of the first transistor and the second transistor are both connected to a power supply terminal. The second terminal of the first transistor is connected to a control terminal, and the second terminal of the second transistor is also connected to a control terminal.

[0013] In one possible implementation of the first hysteresis voltage generation circuit, the circuit includes a third transistor and a fourth transistor. The first terminals of both the third and fourth transistors are connected to a power supply. The control terminal of the third transistor is connected to the second terminal of the fourth transistor and also connected to the second terminal of the first transistor. Similarly, the control terminal of the fourth transistor is connected to the second terminal of the third transistor and also connected to the second terminal of the second transistor. This allows for the generation of a first hysteresis voltage of approximately 50mV, and the generation speed is relatively fast, thus filtering out high-frequency glitches.

[0014] In another possible implementation, the first hysteresis voltage generating circuit includes a first current source and a second current source. The input terminals of both the first and second current sources are connected to a power supply. The output terminal of the first current source is connected to the second terminal of a first transistor, and the output terminal of the second current source is connected to the second terminal of a second transistor. The control terminals of the first and second current sources are respectively connected to the output terminals of a comparator. Thus, the comparator can send comparison result signals to the first and second current sources respectively. After receiving the comparison result signal, the control terminal of the first current source can adjust its current according to the comparison result signal, thereby adjusting the voltage at the output terminal of the first current source. Similarly, the voltage at the output terminal of the second current source can also be adjusted. Since the first hysteresis voltage generated by the first hysteresis voltage generating circuit is related to the voltages at the output terminals of both the first and second current sources, the first hysteresis voltage can also be adjusted. Therefore, this application also provides another way to implement the first hysteresis voltage generating circuit, and this implementation method has a relatively simple structure.

[0015] In one possible implementation of the second hysteresis voltage generation circuit, the circuit includes a first resistor and a second resistor, at least one of which is adjustable. The first terminal of the first resistor is connected to a power supply, and the second terminal of the first resistor is connected to the first terminal of the second resistor and to the first input terminal of an adder. The second terminal of the second resistor is grounded; that is, the first and second resistors are connected in series. The output of the second-stage comparator is connected to the control terminal of the adjustable resistor. Thus, the second-stage comparator can send a comparison result signal to the adjustable resistor, which can adjust its resistance value according to the received comparison result signal, thereby adjusting the voltage between the second terminal of the first resistor and the first terminal of the second resistor. This voltage is the second hysteresis voltage. Using a series connection between the first and second resistors makes the implementation simpler, more readily available, easier to implement, and less expensive.

[0016] Furthermore, in one example, one of the first and second resistors is an adjustable resistor; for instance, the first resistor is adjustable and the second resistor is constant; or, the second resistor is adjustable and the first resistor is constant. In another example, both the first and second resistors are adjustable. This allows for more flexible adjustment of the second hysteresis voltage.

[0017] In another possible implementation, the second hysteresis voltage generating circuit includes a voltage-controlled current source and a third resistor. The control terminal of the voltage-controlled current source is connected to the output terminal of the second-stage comparator, thereby allowing the voltage-controlled current source to receive a comparison result signal from the output terminal of the second-stage comparator and adjust its own current according to the comparison result signal.

[0018] The input terminal of the voltage-controlled current source is connected to the power supply terminal, and the output terminal of the voltage-controlled current source is also connected to the first terminal of the third resistor, while the second terminal of the third resistor is grounded. Thus, the voltage-controlled current source and the third resistor are connected in series. The output terminal of the voltage-controlled current source is connected to the first input terminal of the adder. When the current of the voltage-controlled current source is adjusted, the voltage at the output terminal of the voltage-controlled current source will also be adjusted accordingly; this voltage is the second hysteresis voltage. Therefore, this application also provides another way to implement the second hysteresis voltage generation circuit, and this implementation method has a relatively simple structure.

[0019] In some embodiments of this application, since the comparison result signal output by the comparator still contains a small number of small spikes, in order to eliminate these spikes and improve the noise suppression effect of the signal processing chip on the signal to be processed, the signal processing chip further includes a spike elimination circuit. The input terminal of the spike elimination circuit is connected to the output terminal of the comparator, and the output terminal of the spike elimination circuit is connected to the output terminal of the signal processing chip. Thus, the spike elimination circuit can receive the comparison result signal output by the comparator and perform spike elimination processing on the comparison result signal to eliminate remaining spikes.

[0020] Furthermore, the glitch elimination circuit includes a first delay circuit, an AND gate, a second delay circuit, and an OR gate. The input terminals of the first delay circuit and the first input terminal of the AND gate are both connected to the output terminal of the comparator, and the output terminal of the first delay circuit is connected to the second input terminal of the AND gate. In this way, the comparator can send the comparison result signal to the first delay circuit and the AND gate respectively. The first delay circuit can delay the comparison result signal to obtain a delayed comparison result signal, which is then sent to the AND gate. The AND gate can receive both the delayed comparison result signal and the undelayed comparison result signal directly sent by the comparator. Performing an AND operation on these two comparison result signals retains the common signal between them and removes glitches other than the common signal, obtaining the signal after the AND operation.

[0021] The input terminals of the second delay circuit and the first input terminal of the OR gate are both connected to the output terminal of the AND gate. The output terminal of the second delay circuit is connected to the second input terminal of the OR gate, and the output terminal of the OR gate is connected to the output terminal of the signal processing chip. In this way, the AND gate can send the AND-operated signal to both the second delay circuit and the OR gate. The second delay circuit can delay the AND-operated signal to obtain a delayed signal, which is then sent to the OR gate. The OR gate can receive both the delayed signal and the undelayed AND-operated signal directly sent by the AND gate. Performing an OR operation on these two signals retains either of the two comparison result signals, obtaining the AND-operated signal. This ensures that the comparison result signal output by the comparator is not lost, thus eliminating glitches.

[0022] A second aspect of this application provides an electronic device including a circuit board and a signal processing chip according to any of the above embodiments, wherein the circuit board and the signal processing chip are electrically connected. The electronic device is capable of achieving all the effects of the signal processing chip.

[0023] A third aspect of this application provides a signal processing method applied to a signal processing chip, the signal processing chip including a low-pass filter, a comparator, and a first hysteresis voltage generation circuit. The method includes: the low-pass filter receiving a signal to be processed and performing low-pass filtering on the signal, sending the low-pass filtered signal to the comparator; the comparator comparing the low-pass filtered signal with a reference signal, obtaining a comparison result signal, and outputting it; the first hysteresis voltage generation circuit receiving the comparison result signal and generating a first hysteresis voltage, outputting the first hysteresis voltage, the first hysteresis voltage being used to update the reference signal.

[0024] In this application, the signal to be processed is first subjected to low-pass filtering to reduce the large swing of higher frequency noise in the signal; then, a first hysteresis voltage is generated by a first hysteresis voltage generation circuit, and the low-pass filtered signal is compared with the first hysteresis voltage or its calculated hysteresis voltage, thereby suppressing the noise after the swing is reduced. Therefore, this application can suppress large swing noise.

[0025] Based on this, the signal processing chip also includes a second hysteresis voltage generation circuit and an adder. After the comparator compares the low-pass filtered signal with the reference signal, obtains the comparison result signal, and outputs it, the signal processing method further includes: the second hysteresis voltage generation circuit receives the comparison result signal and generates a second hysteresis voltage, and outputs the second hysteresis voltage to the adder; the adder receives the first hysteresis voltage and the second hysteresis voltage, and outputs a combined hysteresis voltage to the comparator. The combined hysteresis voltage is related to the first hysteresis voltage and the second hysteresis voltage, and the combined hysteresis voltage is used to update the reference signal.

[0026] Furthermore, the frequency of the second hysteresis voltage is lower than the frequency of the first hysteresis voltage. That is, the second hysteresis voltage generating circuit can generate a lower frequency second hysteresis voltage, thereby suppressing lower frequency noise in the low-pass filtered signal output by the low-pass filter. The first hysteresis voltage generating circuit can generate a higher frequency first hysteresis voltage, thereby suppressing higher frequency noise in the low-pass filtered signal output by the low-pass filter. Therefore, this application can suppress both higher and lower frequency noise simultaneously.

[0027] Furthermore, since the comparison result signal output by the comparator still contains a small number of small spikes, in order to eliminate these spikes and improve the noise suppression effect of the signal processing chip on the signal to be processed, the signal processing chip also includes a spike elimination circuit. After the step of the comparator comparing the low-pass filtered signal with the reference signal to obtain the comparison result signal and outputting it, the method further includes: the spike elimination circuit receiving the comparison result signal output by the comparator, and performing spike elimination on the comparison result signal before outputting it, thereby eliminating the remaining spikes in the comparison result signal. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a schematic diagram of the connection relationship between the reference clock source, PLL and RF antenna;

[0030] Figure 2 is a schematic diagram of the structure with the addition of a clock signal processing module based on Figure 1;

[0031] Figure 3 is one of the circuit structure diagrams of the clock signal processing module shown in Figure 2;

[0032] Figure 4 is a schematic diagram of the output signal of the clock signal processing module shown in Figure 3;

[0033] Figure 5 is a schematic diagram comparing the output signals of a general comparator and a comparator with hysteresis effect;

[0034] Figure 6 is the second circuit structure diagram of the clock signal processing module shown in Figure 2;

[0035] Figure 7 is a schematic diagram of the structural principle of the signal processing chip in the first embodiment of this application;

[0036] Figure 8 is a schematic diagram of the structural principle of the signal processing chip in the second embodiment of this application;

[0037] Figure 9 is one of the circuit structure diagrams of the signal processing chip shown in Figure 8;

[0038] Figure 10 is a port diagram of any of the transistors in Figure 9;

[0039] Figure 11 is a schematic diagram of the process by which the glitch elimination circuit in Figure 9 processes the comparison result signal sent by the comparator.

[0040] Figure 12 is the second circuit structure diagram of the signal processing chip shown in Figure 8;

[0041] Figure 13 is the third circuit structure diagram of the signal processing chip shown in Figure 8;

[0042] Figure 14 is the fourth circuit structure diagram of the signal processing chip shown in Figure 8;

[0043] Figure 15 is a schematic diagram of the signal processing amplification process applied to the signal processing chip shown in Figure 8;

[0044] Figure 16 is a schematic diagram of the signal processing amplification process applied to the signal processing chip shown in Figure 9.

[0045] Icons: 10 - Reference clock source; 20 - PLL; 30 - Clock signal processing module; 301 - Inverter; 302 - Hysteresis voltage generation circuit; 31 - Low-pass filter; 32 - Comparator; 321 - First-stage comparator; 322 - Second-stage comparator; 33 - First hysteresis voltage generation circuit; 34 - Second hysteresis voltage generation circuit; 35 - Adder; 36 - Glitch elimination circuit; 361 - First delay circuit; 362 - AND gate; 363 - Second delay circuit; 364 - OR gate; 2 - RF antenna; 3 - Reference clock trace. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, while "more" refers to two or more. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0048] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0049] Terms such as “connected” and “linked” are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Terms such as “upper,” “lower,” “left,” and “right” are used only relative to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and may vary accordingly depending on the orientation of the components in the drawings.

[0050] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0051] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0052] To facilitate understanding, the terms used in this application will be explained first.

[0053] Phase-locked loop (PLL): A feedback system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a target frequency, which can maintain the phase synchronization between the output signal and the input signal.

[0054] Reference clock: The reference clock provided to the PLL, which can be used by the PLL to perform operations such as frequency multiplication and phase alignment.

[0055] Wideband large swing noise: Due to external interference, the PLL's reference clock signal carries noise with complex frequency components and large amplitude. The frequency range of wideband large swing noise is 0.5MHz to 5GHz, and the amplitude reaches 500mV.

[0056] Hysteresis comparator: A comparator with hysteresis lap-loop propagation characteristics, which can also be understood as a single-limit comparator with positive feedback.

[0057] Digital-to-analog converter (DAC): Converts digital signals into analog signals.

[0058] In mobile phones and other electronic devices, a reference clock source 10, a PLL 20, and a radio frequency antenna 2 are typically included, as shown in Figure 1. The reference clock source 10 can send a reference clock signal to the PLL 20, which can receive the reference clock signal and other data signals, and forward the data signals to the radio frequency antenna 2. During the forwarding of data signals, the PLL 20 can maintain phase synchronization between the output data signal and the input data signal.

[0059] The port physical layer (PHY) Internet Protocol (IP) used in smart home open interconnection platforms, as a high-speed, low-power interface (SerDes) IP, effectively solves the bottlenecks of camera data bandwidth requirements and board-level signal integrity (SI). However, with the diversification of mobile phone motherboard layouts, especially the widespread popularity of foldable screen phones, the distance between the camera and the motherboard has increased. This increases the length of the reference clock trace 3 providing the reference clock signal to the PLL20, making the reference clock signal susceptible to interference from the RF antenna 2. Specifically, the RF antenna 2 introduces large-amplitude, wide-frequency interference noise into the reference clock signal during signal transmission and reception. This interference noise can also be referred to as glitches. For example, the amplitude of the interference noise VPP ≈ 500mV, and the frequency range is 0.7GHz-5.5GHz. When a reference clock signal with glitches is transmitted to the PLL20, it causes the PLL20 to lose lock. That is, the output signal of the PLL20 cannot maintain synchronization with the frequency and phase of the input signal. This situation may lead to communication interruptions, signal quality degradation, and other problems.

[0060] To eliminate the glitches in the reference clock signal brought by the RF antenna 2, as shown in Figure 2, a clock signal processing module 30 can be set between the reference clock source 10 and the PLL 20. The clock signal processing module 30 can receive the reference clock signal sent by the reference clock source 10, perform filtering and other processing on the reference clock signal, and send the filtered reference clock signal to the PLL 20, thereby ensuring the normal operation of the PLL 20.

[0061] In one related technology, as shown in Figure 3, the clock signal processing module 30 may include a capacitor C, a resistor R, and an inverter 301. The first terminal of capacitor C serves as the input terminal of the clock signal processing module 30, and the second terminal of capacitor C is connected to the input terminal of inverter 301. The output terminal of inverter 301 serves as the output terminal of the clock signal processing module 30. The first terminal of resistor R is connected to the input terminal of inverter 301, and the second terminal of resistor R is connected to the output terminal of inverter 301. Capacitor C can be used to isolate DC components, and resistor R can provide a common-mode bias point when providing negative feedback to inverter 301.

[0062] Capacitor C typically functions as a high-pass filter, meaning it can filter out or reduce noise frequencies below the cutoff frequency. If the noise occurs at the flip edge of the input signal, it will still produce glitches as shown in Figure 4 after being amplified by inverter 301. When the reference clock signal with glitches is input to PLL20, it will cause PLL20 to lose lock.

[0063] In another related technology, the clock signal processing module 30 includes multiple transistors. These transistors, when combined, can generate a hysteresis voltage, which can be varied by adjusting the size ratio between the transistors. A larger size ratio results in a larger hysteresis voltage. A larger hysteresis voltage allows for the filtering of a larger amplitude of noise. However, if the size ratio is too large, some transistors will become excessively large, leading to adverse effects such as increased parasitic capacitance. Therefore, this approach typically produces a relatively small hysteresis voltage, making it insufficient for suppressing large-amplitude noise.

[0064] Based on this, this application provides a signal processing chip. In one application scenario, the signal processing chip can be used for clock signal processing. In one example, the signal processing chip may only include a clock signal processing module 30. That is, the clock signal processing module 30 can be mounted as a separate chip on a circuit board, or packaged with other chips. In another example, in addition to the clock signal processing module 30 shown in FIG2, the signal processing chip may also include a reference clock source 10 and a PLL 20 as shown in FIG2.

[0065] In another application scenario, signal processing chips can be used to process signals other than clock signals, such as data signals.

[0066] In any of the above application scenarios, the signal processing chip can be used in electronic devices. Besides the signal processing chip, the electronic device may also include a circuit board, and the signal processing chip is electrically connected to the circuit board. In this embodiment, the electronic device can be, for example, a server, consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc., and this application embodiment does not impose any limitations on this. Illustrated, the aforementioned consumer electronics can be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics can be smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. Automotive electronics can be in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can be automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, memory, radar, base stations, and other communication equipment.

[0067] Noise in the reference clock signal sent by the reference clock source 10 shown in Figure 2 can be suppressed by setting a hysteresis comparator with a hysteresis effect in the clock signal processing module 30. Here, a general comparator and a hysteresis comparator are set in the clock signal processing module 30 respectively, and the signals output by the general comparator and the hysteresis comparator are compared. The comparison result is shown in Figure 5. As can be seen from Figure 5, when there is a lot of noise in the input signal (i.e., the reference clock signal), for example, the voltage Vin curve of the input signal is not a smooth transition curve, the general comparator will respond to the input signal multiple times on the voltage flip edge, thus generating glitches. When these glitches are input to the PLL20 shown in Figure 2, it will cause the PLL20 to lose lock. However, the comparator with a hysteresis effect will dynamically adjust the flip threshold voltage according to the voltage Vout of the output signal. For example, when the voltage Vout of the output signal changes from 1 to 0, the threshold voltage changes from VL to VH; when the voltage Vout of the output signal changes from 0 to 1, the threshold voltage changes from VH to VL, thus avoiding the generation of glitches. As can be seen from Figure 5, the output signal of a conventional comparator has more glitches, while the output signal of a hysteresis comparator has almost no glitches. This demonstrates that the hysteresis comparator can eliminate glitches (i.e., noise) in the input signal.

[0068] Furthermore, based on the working principle of the hysteresis comparator, a clock signal processing module 30 as shown in Figure 6 can be derived. In Figure 6, the clock signal processing module 30 includes a comparator 32 and a hysteresis voltage generation circuit 302. The hysteresis voltage generation circuit 302 generates a hysteresis voltage and sends it to the comparator 32. The hysteresis voltage generation circuit 302 and the comparator 32 are used together, and their function is equivalent to that of the hysteresis comparator. Therefore, the output signal of the clock signal processing module 30 shown in Figure 6 is the same as the output signal of the hysteresis comparator shown in Figure 5. The clock signal processing module 30 shown in Figure 6 also has the function of eliminating glitches, that is, suppressing noise.

[0069] Based on this, in this embodiment, as shown in FIG7, the clock signal processing module 30 may include: a low-pass filter 31, a comparator 32, and a first hysteresis voltage generation circuit 33. The input terminal of the low-pass filter 31 is connected to the input terminal of the signal processing chip 1, the output terminal of the low-pass filter 31 is connected to the first input terminal of the comparator 32, the output terminal of the first hysteresis voltage generation circuit 33 is connected to the second input terminal of the comparator 32, the output terminal of the comparator 32 is connected to the input terminal of the first hysteresis voltage generation circuit 33, and the output terminal of the comparator 32 is connected to the output terminal of the signal processing chip 1.

[0070] The clock signal processing module 30 can process the reference clock signal waiting signal sent by the reference clock source 10 shown in Figure 2. During the processing, as shown in Figure 7, the low-pass filter 31 can receive the signal to be processed input from the input terminal of the signal processing chip 1 and perform low-pass filtering on the signal to be processed to reduce the noise swing in the signal to be processed that is higher than the cutoff frequency of the low-pass filter 31. For example, the noise swing higher than 1 GHz can be reduced to less than 50 mV to obtain the low-pass filtered signal, and the low-pass filtered signal is sent to the first input terminal of the comparator 32.

[0071] Comparator 32 receives the low-pass filtered signal from low-pass filter 31, compares the low-pass filtered signal with a reference signal to obtain a comparison result signal, and sends the comparison result signal to the first hysteresis voltage generation circuit 33. Simultaneously, it outputs the comparison result signal as an output signal from clock signal processing module 30. When processing the signal to be processed for the first time, the voltage of the reference signal can be a preset value.

[0072] The first hysteresis voltage generation circuit 33 generates a first hysteresis voltage based on the comparison result signal and sends the first hysteresis voltage to the second input terminal of the comparator 32. The comparison result signal contains a comparison result of 1 or 0. When the comparison result is 1, the first hysteresis voltage can be Vref1 + ΔV1; when the comparison result is 0, the first hysteresis voltage can be Vref1 - ΔV1. Here, Vref1 can be a preset reference voltage value, and ΔV1 can be a preset voltage change.

[0073] After receiving the first hysteresis voltage, comparator 32 can compare the voltage of the low-pass filtered signal sent by low-pass filter 31 with the first hysteresis voltage. Alternatively, it can perform correlation operations on the first hysteresis voltage to obtain the calculated hysteresis voltage, and then compare the voltage of the low-pass filtered signal with the calculated hysteresis voltage to obtain a comparison result signal. Comparator 32 can continue to send the comparison result signal to the first hysteresis voltage generation circuit 33, and can also output the comparison result signal as an output signal from the clock signal processing module 30.

[0074] In this embodiment, the signal to be processed is first subjected to low-pass filtering, which significantly reduces higher-frequency noise in the signal. Then, a first hysteresis voltage is generated by the first hysteresis voltage generation circuit 33, and the low-pass filtered signal is compared with the first hysteresis voltage or its calculated hysteresis voltage. Since the first hysteresis voltage generation circuit 33 and the comparator 32 function similarly to a hysteresis comparator, the reduced-swing noise output from the low-pass filter 31 can be suppressed. Therefore, this embodiment can suppress large-swing noise.

[0075] To further improve the noise suppression effect on the signal to be processed, as shown in Figure 8, the clock signal processing module 30 may further include a second hysteresis voltage generation circuit 34 and an adder 35. The output of the comparator 32 is also connected to the input of the second hysteresis voltage generation circuit 34. Thus, the comparator 32 can send the comparison result signal to the second hysteresis voltage generation circuit 34, which generates a second hysteresis voltage upon receiving the comparison result signal. For example, the comparison result signal may contain a comparison result of 1 or 0. When the comparison result is 1, the second hysteresis voltage may be Vref2 + ΔV2; when the comparison result is 0, the second hysteresis voltage may be Vref2 - ΔV2. Vref2 can be a preset reference voltage value, and ΔV2 can be a preset voltage change. It is understood that Vref1 in the first hysteresis voltage and Vref2 in the second hysteresis voltage may be the same or different. Similarly, ΔV1 in the first hysteresis voltage and ΔV2 in the second hysteresis voltage may be the same or different.

[0076] As shown in Figure 8, the output of the second hysteresis voltage generation circuit 34 is connected to the first input of the adder 35, the output of the first hysteresis voltage generation circuit 33 is connected to the second input of the adder 35, and the output of the adder 35 is connected to the second input of the comparator 32. Thus, the first hysteresis voltage generation circuit 33 can send the first hysteresis voltage to the adder 35, and the second hysteresis voltage generation circuit 34 can send the second hysteresis voltage to the adder 35. The adder 35 can perform an addition operation on the first and second hysteresis voltages to obtain a combined hysteresis voltage, and then send the combined hysteresis voltage to the comparator 32 for comparison.

[0077] Furthermore, the frequency of the second hysteresis voltage output by the second hysteresis voltage generating circuit 34 in Figure 8 is lower than the frequency of the first hysteresis voltage output by the first hysteresis voltage generating circuit 33. That is, the second hysteresis voltage generating circuit 34 can generate a lower frequency second hysteresis voltage, thereby suppressing lower frequency noise in the low-pass filtered signal output by the low-pass filter 31. The first hysteresis voltage generating circuit 33 can generate a higher frequency first hysteresis voltage, thereby suppressing higher frequency noise in the low-pass filtered signal output by the low-pass filter 31. Therefore, the combination of the low-pass filter 31 and the first hysteresis voltage generating circuit 33 can suppress higher frequency noise, for example, noise with a frequency higher than 1 GHz. The second hysteresis voltage generating circuit 34 can suppress lower frequency noise, for example, noise with a frequency between 100 MHz and 1 GHz. In other words, this embodiment can suppress both higher and lower frequency noise simultaneously, i.e., it can suppress wideband noise, thereby reducing interference caused by the RF antenna 2 shown in Figure 1 to the clock signal trace 3.

[0078] Further, in this embodiment, comparator 32 can be a two-stage comparator. Specifically, as shown in FIG9, comparator 32 may include a cascaded first-stage comparator 321 and a second-stage comparator 322. The input terminal of the first-stage comparator 321 serves as the input terminal of comparator 32, and the output terminal of the first-stage comparator 321 is connected to the input terminal of the second-stage comparator 322. The output terminal of the second-stage comparator 322 serves as the output terminal of comparator 32. The output terminal of the first-stage comparator 321 is connected to the input terminal of the first hysteresis voltage generation circuit 33, and the output terminal of the second-stage comparator 322 is connected to the input terminal of the second hysteresis voltage generation circuit 34. The output terminal of the first hysteresis voltage generation circuit 33 is connected to the input terminal of the second-stage comparator 322. That is to say, the comparison result signal received by the first hysteresis voltage generation circuit 33 is the comparison result signal obtained after one stage of comparison; while the comparison result signal received by the second hysteresis voltage generation circuit 34 is the comparison result signal obtained after two stages of comparison. Therefore, compared to the second hysteresis voltage generating circuit 34, the comparison result signal received by the first hysteresis voltage generating circuit 33 is faster and has a higher frequency. This results in the first hysteresis voltage generating frequency being higher than the second hysteresis voltage generating frequency.

[0079] Specifically, as shown in Figure 9, comparator 32 may include transistor M1 (first transistor), transistor M2 (second transistor), transistor M5, transistor M6, transistor M7, transistor M8, transistor M9, transistor M10, transistor M1, resistor R2, and resistor R3.

[0080] In this configuration, the first terminals of transistors M1, M2, M5, and M6, and the first terminal of resistor R2 are all connected to the power supply terminal VDD1. The second terminal of transistor M1 is connected to its control terminal and also to the control terminal of transistor M5. The second terminal of transistor M2 is connected to its control terminal and also to the control terminal of transistor M6. The second terminal of transistor M5 is connected to the first terminal of transistor M8 and also to its control terminal; the second terminal of transistor M8 is grounded. The second terminal of transistor M6 is connected to the first terminal of transistor M11 and also to the control terminal of transistor M8; the second terminal of transistor M11 is grounded. The second terminal of resistor R2 is connected to the first terminal of resistor R3 and also to the control terminal of transistor M7. The second terminal of transistor M7 is grounded. The second terminal of transistor M3 is connected to the first terminal of transistor M10. The second terminal of transistor M10 is connected to the first terminal of transistor M9. The control terminal of transistor M9 is connected to the control terminal of transistor M7; the second terminal of transistor M9 is grounded. Transistors M7, M8, M9, and M11 are all used for starting current.

[0081] As shown in Figure 9, the control terminal of transistor M10 can be used as the first input terminal a1 of comparator 32, the control terminal of transistor M2 can be used as the second input terminal a2 of comparator 32, and the second terminal of transistor M6 can be used as the output terminal b of comparator 32.

[0082] As shown in Figure 9, transistors M1 and M2 can form a first-stage comparator 321, and transistors M5 and M6 can form a second-stage comparator 322.

[0083] It is understood that, for any transistor M in the embodiments of this application, the first electrode can be either the source (S) or the drain (D), and the second electrode can be either the source (S) or the drain (D). For example, the first electrode may be the source (S) and the second electrode may be the drain (D), or the first electrode may be the drain (D) and the second electrode may be the source (S). The control electrode can be the gate (G). The positional relationship of the three electrodes of transistor M can be seen in Figure 10.

[0084] As shown in Figure 9, in this embodiment, the low-pass filter 31 can be a resistor-capacitor (RC) filter. For example, the low-pass filter 31 may include a resistor R1 and a capacitor C1. The first terminal of the resistor R1 serves as the input terminal IN of the clock signal processing module 30 and is electrically connected to the reference clock source 10 shown in Figure 2. The second terminal of the resistor R1 is connected to the first terminal of the capacitor C1, and the second terminal of the capacitor C1 is grounded. In other embodiments, the low-pass filter 31 may also be a resistor-inductor-capacitor (RLC) filter, etc.

[0085] As shown in Figure 9, the clock signal processing module 30 may further include capacitor C2, resistor R4, and resistor R5. The second terminal of resistor R1 in the low-pass filter 31 is connected to the first terminal of capacitor C2. The first terminal of resistor R4 is connected to the power supply terminal VDD2. The second terminals of resistor R4 and the first terminals of resistor R5 are both connected to the second terminal of capacitor C2 and to the control electrode of transistor M10, i.e., to the first input terminal of comparator 32. The second terminal of resistor R5 is grounded. Capacitor C2 can be a DC blocking capacitor. The function of resistors R4 and R5 is to provide a voltage bias point for the control electrode of transistor M10.

[0086] As shown in Figure 9, the first hysteresis voltage generating circuit 33 includes transistor M3 (the third transistor) and transistor M4 (the fourth transistor). The first terminals of transistors M3 and M4 are both connected to the power supply terminal VDD1. The control terminal of transistor M3 is connected to the second terminal of transistor M4 and also connected to the second terminal of transistor M1. The control terminal of transistor M4 is connected to the second terminal of transistor M3 and also connected to the second terminal of transistor M2. In this way, a first hysteresis voltage of approximately 50mV can be generated, and the generation speed of the first hysteresis voltage is relatively fast to filter out high-frequency glitches.

[0087] As shown in Figure 9, the second hysteresis voltage generating circuit 34 may include resistor R6 (first resistor) and resistor R7 (second resistor), at least one of resistors R6 and R7 being an adjustable resistor. In one example, one of the first and second resistors is an adjustable resistor; for example, the first resistor is an adjustable resistor and the second resistor is a constant resistor; or, the second resistor is an adjustable resistor and the first resistor is a constant resistor. In another example, as shown in Figure 9, both the first and second resistors are adjustable resistors.

[0088] As shown in Figure 9, the first end of resistor R6 is connected to the power supply terminal VDD3. The second end of resistor R6 is connected to the first end of resistor R7 and to the first input terminal of adder 35. The second end of resistor R7 is grounded, meaning that resistors R6 and R7 are connected in series. The output terminal b of the second-stage comparator 322 is connected to the control terminal of the adjustable resistor. Since both resistors R6 and R7 are adjustable resistors in Figure 9, the output terminal b of the second-stage comparator 322 is connected to the control terminal of resistor R6 and also to the control terminal of resistor R7. Thus, the second-stage comparator 322 can send the comparison result signal to resistors R6 and R7. Resistors R6 and R7 can adjust their respective resistance values ​​according to the received comparison result signal, thereby adjusting the voltage at the connection point between the second end of resistor R6 and the first end of resistor R7. This connection point is the output terminal of the second hysteresis voltage generation circuit 34, and the voltage at this point is the second hysteresis voltage. The scheme using resistors R6 and R7 in series simplifies the implementation, makes the materials readily available, and is easy to implement at a low cost. Furthermore, when both resistors R6 and R7 are adjustable, the adjustment of the second hysteresis voltage becomes more flexible. However, since the resistance values ​​of resistors R6 and R7 need to be adjusted after receiving the comparison result signal from comparator 32, the response speed of the second hysteresis voltage generation circuit 34 is slower, resulting in a lower frequency of the generated second hysteresis voltage.

[0089] As shown in Figure 9, adder 35 may include transistor M12. The control terminal of transistor M12 can serve as the first input terminal of adder 35, connected to the output terminal of second hysteresis voltage generation circuit 34, i.e., connected to the second terminal of resistor R6 and the first terminal of resistor R7. The first terminal of transistor M12 can serve as the second input terminal of adder 35, connected to the output terminal of first hysteresis voltage generation circuit 33, i.e., connected to the second terminal of transistor M4. The second terminal of transistor M12 can serve as the output terminal of adder 35, connected to the input terminal of comparator 32. Second hysteresis voltage generation circuit 34 can control the voltage of control terminal of transistor M12, and first hysteresis voltage generation circuit 33 can control the voltage of first terminal of transistor M12. Transistor M12 can calculate the voltage of first terminal by the voltage of control terminal and the voltage of second terminal, thereby realizing the addition operation of first hysteresis voltage and second hysteresis voltage.

[0090] Since the comparison result signal output by comparator 32 still contains a small number of small glitches, in order to eliminate these glitches and improve the noise suppression effect of the clock signal processing module 30 on the signal to be processed, as shown in Figure 9, the clock signal processing module 30 also includes a glitch elimination circuit 36. The input terminal of the glitch elimination circuit 36 ​​is connected to the output terminal b of comparator 32, and the output terminal of the glitch elimination circuit 36 ​​is connected to the output terminal OUT of clock signal processing module 30. Thus, the glitch elimination circuit 36 ​​can receive the comparison result signal output by comparator 32 and perform glitch elimination processing on the comparison result signal to eliminate the remaining glitches.

[0091] Further, as shown in Figure 9, the glitch elimination circuit 36 ​​includes a first delay circuit 361, an AND gate 362, a second delay circuit 363, and an OR gate 364. The input terminals of the first delay circuit 361 and the first input terminal of the AND gate 362 are both connected to the output terminal of the comparator 32, and the output terminal of the first delay circuit 361 is connected to the second input terminal of the AND gate 362. Thus, as shown in Figure 11, the comparator 32 can send the comparison result signal to the first delay circuit 361 and the AND gate 362 respectively. The first delay circuit 361 can delay the comparison result signal to obtain a delayed comparison result signal, which is then sent to the AND gate 362. The AND gate 362 can receive both the delayed comparison result signal and the undelayed comparison result signal directly sent by the comparator 32. Performing an AND operation on these two comparison result signals retains the common signal between them and removes glitches other than the common signal, obtaining the signal after the AND operation.

[0092] As shown in Figure 9, the input terminal of the second delay circuit 363 and the first input terminal of the OR gate 364 are both connected to the output terminal of the AND gate 362. The output terminal of the second delay circuit 363 is connected to the second input terminal of the OR gate 364, and the output terminal of the OR gate 364 is connected to the output terminal OUT of the clock signal processing module 30. Thus, as shown in Figure 11, the AND gate 362 can send the AND-operated signal to the second delay circuit 363 and the OR gate 364 respectively. The second delay circuit 363 can delay the AND-operated signal to obtain a delayed signal, and then send the delayed signal to the OR gate 364. The OR gate 364 can receive the delayed signal and the undelayed AND-operated signal directly sent by the AND gate 362. By performing an OR operation on these two signals, it can retain either of the two comparison result signals, obtaining the OR-operated signal. This ensures that the comparison result signal output by the comparator 32 is not lost, thus eliminating glitches.

[0093] Furthermore, as shown in Figure 9, the clock signal processing module 30 may also include an inverter 301, which is connected between the comparator 32 and the glitch elimination circuit 36. Specifically, the input terminal of the inverter 301 is connected to the output terminal b of the comparator 32, and the output terminal of the inverter 301 is connected to the input terminal of the glitch elimination circuit 36.

[0094] In other embodiments of this application, as shown in FIG12, the difference between the embodiment shown in FIG9 and the embodiment is the structure of the first hysteresis voltage generating circuit 33 and the second hysteresis voltage generating circuit 34.

[0095] Specifically, as shown in Figure 12, the first hysteresis voltage generating circuit 33 includes a first current source A1 and a second current source A2. The input terminals of both current source A1 and A2 are connected to a power supply. The output terminal of the first current source A1 is connected to the second terminal of transistor M1, and the output terminal of the second current source A2 is connected to the second terminal of transistor M2. The control terminals of the first and second current sources A1 and A2 are respectively connected to the output terminals of comparator 32. Therefore, comparator 32 can send comparison result signals to the first current source A1 and A2 respectively. After receiving the comparison result signal, the control terminal of the first current source A1 can adjust its current according to the comparison result signal, thereby adjusting the voltage at the output terminal of the first current source A1. Similarly, it can also adjust the voltage at the output terminal of the second current source A2. The first hysteresis voltage generated by the first hysteresis voltage generating circuit 33 is related to the voltage at the output terminals of the first and second current sources A1 and A2, thus the first hysteresis voltage can also be adjusted. Therefore, this application embodiment also provides another way to implement the first hysteresis voltage generating circuit 33, and the structure of this implementation is also relatively simple.

[0096] As shown in Figure 12, the second hysteresis voltage generation circuit 34 includes a voltage-controlled current source A3 and a resistor R7 (the third resistor). The control terminal of the voltage-controlled current source A3 is connected to the output terminal b of the second-stage comparator 322. Thus, the voltage-controlled current source A3 can receive the comparison result signal from the output terminal b of the second-stage comparator 322 and adjust its current according to the comparison result signal.

[0097] As shown in Figure 12, the input terminal of the voltage-controlled current source A3 is connected to the power supply terminal VDD3, and the output terminal of the voltage-controlled current source A3 is also connected to the first terminal of the resistor R7, while the second terminal of the resistor R7 is grounded. Thus, the voltage-controlled current source A3 and the resistor R7 are connected in series. The output terminal of the voltage-controlled current source A3 is connected to the first input terminal of the adder 35 (i.e., the control electrode of the transistor M12). When the current of the voltage-controlled current source A3 is adjusted, the voltage at the output terminal of the voltage-controlled current source A3 will also be adjusted accordingly. The output terminal of the voltage-controlled current source A3 is the output terminal of the second hysteresis voltage generating circuit 34, and therefore, the voltage at the output terminal of the voltage-controlled current source A3 is the second hysteresis voltage. Therefore, this embodiment of the application also provides another way to implement the second hysteresis voltage generating circuit 34, and this implementation method has a relatively simple structure.

[0098] In other embodiments of this application, as shown in FIG13, the difference between the embodiment shown in FIG9 and the embodiment lies in the structure of the first hysteresis voltage generating circuit 33. Specifically, in this embodiment, the first hysteresis voltage generating circuit 33 adopts the structure shown in FIG12.

[0099] In other embodiments of this application, as shown in FIG14, the difference between this embodiment and the one shown in FIG9 lies in the structure of the second hysteresis voltage generating circuit 34. Specifically, in this embodiment, the second hysteresis voltage generating circuit 34 adopts the structure shown in FIG12.

[0100] This application also provides a signal processing method that can be applied to the signal processing chip 1 shown in FIG. 7. In FIG. 7, the signal processing chip includes a low-pass filter 31, a comparator 32, and a first hysteresis voltage generation circuit 33.

[0101] As shown in Figure 15, signal processing methods may include:

[0102] S151, the low-pass filter receives the signal to be processed, performs low-pass filtering on the signal to be processed, and sends the low-pass filtered signal to the comparator.

[0103] As shown in Figure 7, the low-pass filter 31 can receive the signal to be processed input from the input terminal of the clock signal processing module 30, and perform low-pass filtering on the signal to be processed to reduce the signal swing of the signal to be processed that is higher than the cutoff frequency of the low-pass filter 31. For example, the noise swing higher than 1 GHz can be reduced to less than 50 mV to obtain the low-pass filtered signal, and the low-pass filtered signal can be sent to the first input terminal of the comparator 32.

[0104] S152, the comparator compares the low-pass filtered signal with the reference signal to obtain the comparison result signal.

[0105] Comparator 32 compares the low-pass filtered signal with the reference signal to obtain a comparison result signal, and sends the comparison result signal to the first hysteresis voltage generation circuit 33. When the signal to be processed is processed for the first time, the voltage of the reference signal can be a preset value.

[0106] S153, the first hysteresis voltage generation circuit receives the comparison result signal and generates the first hysteresis voltage, and outputs the first hysteresis voltage.

[0107] In this embodiment, the first hysteresis voltage generation circuit 33 can output a first hysteresis voltage to the comparator 32, and the first hysteresis voltage is used to update the reference signal. That is, the voltage of the reference signal can be the first hysteresis voltage, or a hysteresis voltage obtained by performing calculations on the first hysteresis voltage. After receiving the first hysteresis voltage, the comparator 32 can compare the low-pass filtered signal sent by the low-pass filter 31 with the first hysteresis voltage, or it can perform correlation operations on the first hysteresis voltage to obtain the calculated hysteresis voltage, and compare the low-pass filtered signal with the calculated hysteresis voltage to obtain a comparison result signal.

[0108] S154, the comparator outputs the comparison result signal.

[0109] In this embodiment, the signal to be processed is first subjected to low-pass filtering to reduce the large swing of higher frequency noise in the signal; then, a first hysteresis voltage is generated by the first hysteresis voltage generation circuit 33, and the low-pass filtered signal is compared with the first hysteresis voltage or its calculated hysteresis voltage, thereby suppressing the noise after the swing is reduced. Therefore, this embodiment can suppress large swing noise.

[0110] Other embodiments of this application also provide a signal processing method that can be applied to the clock signal processing module 30 shown in FIG8. In FIG8, the clock signal processing module 30 includes a low-pass filter 31, a comparator 32, a first hysteresis voltage generation circuit 33, a second hysteresis voltage generation circuit 34, an adder 35, and a glitch elimination circuit 36.

[0111] As shown in Figure 16, signal processing methods may include:

[0112] S161, the low-pass filter receives the signal to be processed, performs low-pass filtering on the signal to be processed, and sends the low-pass filtered signal to the comparator.

[0113] Follow the steps S151 shown in Figure 15; they will not be repeated here.

[0114] S162, the comparator compares the low-pass filtered signal with the reference signal, obtains the comparison result signal and outputs it.

[0115] Comparator 32 can send the comparison result signal to the first hysteresis voltage generation circuit 33 and the second hysteresis voltage generation circuit 34.

[0116] S163, the first hysteresis voltage generating circuit receives the comparison result signal and generates the first hysteresis voltage, and outputs the first hysteresis voltage.

[0117] Perform step S153 as shown in Figure 15.

[0118] S164, the second hysteresis voltage generation circuit receives the comparison result signal and generates the second hysteresis voltage, and outputs the second hysteresis voltage to the adder.

[0119] The second hysteresis voltage generating circuit 34 can generate a second hysteresis voltage after receiving the comparison result signal. For example, the comparison result signal contains a comparison result of 1 or 0. When the comparison result is 1, the first hysteresis voltage can be Vref + ΔV; when the comparison result is 0, the first hysteresis voltage can be Vref - ΔV.

[0120] S165, the adder receives the first hysteresis voltage and the second hysteresis voltage, and outputs the combined hysteresis voltage to the comparator.

[0121] In this embodiment, the combined hysteresis voltage is related to the first hysteresis voltage and the second hysteresis voltage. For example, the combined hysteresis voltage can be obtained by adding the first hysteresis voltage and the second hysteresis voltage. The combined hysteresis voltage is used to update the reference signal, that is, the voltage of the reference signal is set to the combined hysteresis voltage.

[0122] Furthermore, the frequency of the second hysteresis voltage is lower than the frequency of the first hysteresis voltage. That is, the second hysteresis voltage generating circuit 34 can generate a lower frequency second hysteresis voltage, thereby suppressing lower frequency noise in the low-pass filtered signal output by the low-pass filter 31. The first hysteresis voltage generating circuit 33 can generate a higher frequency first hysteresis voltage, thereby suppressing higher frequency noise in the low-pass filtered signal output by the low-pass filter 31. Therefore, the embodiments of this application can suppress both higher and lower frequency noise simultaneously.

[0123] S166, the glitch elimination circuit receives the comparison result signal output by the comparator, and outputs the comparison result signal after glitch elimination.

[0124] The glitch elimination circuit 36 ​​can receive the comparison result signal output by the comparator 32 and perform glitch elimination processing on the comparison result signal to eliminate the remaining glitch.

[0125] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A signal processing chip, characterized in that, include: The system includes a low-pass filter, a comparator, and a first hysteresis voltage generation circuit. The input terminal of the low-pass filter is connected to the input terminal of the signal processing chip, and the output terminal of the low-pass filter is connected to the first input terminal of the comparator. The output terminal of the first hysteresis voltage generation circuit is connected to the second input terminal of the comparator, and the output terminal of the comparator is connected to the input terminal of the first hysteresis voltage generation circuit. The output terminal of the comparator is also connected to the output terminal of the signal processing chip.

2. The signal processing chip according to claim 1, characterized in that, The signal processing chip further includes a second hysteresis voltage generation circuit and an adder. The output terminal of the second hysteresis voltage generation circuit is connected to the first input terminal of the adder. The output terminal of the first hysteresis voltage generation circuit is connected to the second input terminal of the adder. The output terminal of the adder is connected to the second input terminal of the comparator. The output terminal of the comparator is also connected to the input terminal of the second hysteresis voltage generation circuit. The frequency of the hysteresis voltage output by the second hysteresis voltage generating circuit is lower than the frequency of the hysteresis voltage output by the first hysteresis voltage generating circuit.

3. The signal processing chip according to claim 2, characterized in that, The comparator includes a cascaded first-stage comparator and a second-stage comparator. The input terminal of the first-stage comparator serves as the input terminal of the comparator. The output terminal of the first-stage comparator is connected to the input terminal of the second-stage comparator, and the output terminal of the second-stage comparator serves as the output terminal of the comparator. The output of the first-stage comparator is connected to the input of the first hysteresis voltage generation circuit, and the output of the second-stage comparator is connected to the input of the second hysteresis voltage generation circuit.

4. The signal processing chip according to claim 3, characterized in that, The first stage comparator includes a first transistor and a second transistor. The first terminals of the first transistor and the second transistor are both connected to the power supply terminal. The second terminal of the first transistor is connected to the control terminal, and the second terminal of the second transistor is also connected to the control terminal. The first hysteresis voltage generating circuit includes a third transistor and a fourth transistor. The first terminals of the third transistor and the fourth transistor are both connected to a power supply terminal. The control terminal of the third transistor is connected to the second terminal of the fourth transistor and is also connected to the second terminal of the first transistor. The control terminal of the fourth transistor is connected to the second terminal of the third transistor and is also connected to the second terminal of the second transistor.

5. The signal processing chip according to claim 2, characterized in that, The comparator includes a cascaded first-stage comparator and a second-stage comparator. The first-stage comparator includes a first transistor and a second transistor. The first terminals of the first transistor and the second transistor are both connected to a power supply terminal. The second terminal of the first transistor is connected to a control terminal, and the second terminal of the second transistor is also connected to a control terminal. The first hysteresis voltage generating circuit includes a first current source and a second current source. The input terminals of the first current source and the second current source are both connected to a power supply terminal. The output terminal of the first current source is connected to the second terminal of the first transistor, and the output terminal of the second current source is connected to the second terminal of the second transistor. The control terminals of the first current source and the second current source are respectively connected to the output terminal of the comparator.

6. The signal processing chip according to any one of claims 3-5, characterized in that, The second hysteresis voltage generating circuit includes a first resistor and a second resistor, at least one of the first resistor and the second resistor being an adjustable resistor. The first end of the first resistor is connected to the power supply terminal, the second end of the first resistor is connected to the first end of the second resistor and connected to the first input terminal of the adder, the second end of the second resistor is grounded, and the output terminal of the second stage comparator is connected to the control terminal of the adjustable resistor.

7. The signal processing chip according to claim 6, characterized in that, Both the first resistor and the second resistor are adjustable resistors.

8. The signal processing chip according to any one of claims 3-5, characterized in that, The second hysteresis voltage generating circuit includes a voltage-controlled current source and a third resistor. The input terminal of the voltage-controlled current source is connected to the power supply terminal, the control terminal of the voltage-controlled current source is connected to the output terminal of the second stage comparator, the output terminal of the voltage-controlled current source is connected to the first input terminal of the adder, the output terminal of the voltage-controlled current source is also connected to the first terminal of the third resistor, and the second terminal of the third resistor is grounded.

9. The signal processing chip according to any one of claims 1-8, characterized in that, The signal processing chip also includes a glitch elimination circuit, the input of which is connected to the output of the comparator, and the output of which is connected to the output of the signal processing chip.

10. The signal processing chip according to claim 9, characterized in that, The glitch elimination circuit includes a first delay circuit, an AND gate, a second delay circuit, and an OR gate. The input terminal of the first delay circuit and the first input terminal of the AND gate are both connected to the output terminal of the comparator, and the output terminal of the first delay circuit is connected to the second input terminal of the AND gate. The input terminal of the second delay circuit and the first input terminal of the OR gate are both connected to the output terminal of the AND gate, the output terminal of the second delay circuit is connected to the second input terminal of the OR gate, and the output terminal of the OR gate is connected to the output terminal of the signal processing chip.

11. An electronic device, characterized in that, The device includes a circuit board and a signal processing chip as described in any one of claims 1-10, wherein the circuit board is electrically connected to the signal processing chip.

12. A signal processing method, characterized in that, Applied to a signal processing chip, the signal processing chip including a low-pass filter, a comparator, and a first hysteresis voltage generation circuit, the method includes: The low-pass filter receives the signal to be processed, performs low-pass filtering on the signal to be processed, and sends the low-pass filtered signal to the comparator. The comparator compares the low-pass filtered signal with the reference signal, obtains the comparison result signal, and outputs it. The first hysteresis voltage generating circuit receives the comparison result signal and generates a first hysteresis voltage, outputs the first hysteresis voltage, and uses the first hysteresis voltage to update the reference signal.

13. The signal processing method according to claim 12, characterized in that, The signal processing chip further includes a second hysteresis voltage generation circuit and an adder. After the comparator compares the low-pass filtered signal with a reference signal, obtains the comparison result signal, and outputs it, the method further includes: The second hysteresis voltage generating circuit receives the comparison result signal and generates a second hysteresis voltage, outputting the second hysteresis voltage to the adder. The frequency of the second hysteresis voltage is lower than the frequency of the first hysteresis voltage. The adder receives the first hysteresis voltage and the second hysteresis voltage, and outputs a combined hysteresis voltage to the comparator. The combined hysteresis voltage is related to the first hysteresis voltage and the second hysteresis voltage, and is used to update the reference signal.

14. The signal processing method according to claim 12 or 13, characterized in that, The signal processing chip further includes a glitch elimination circuit. After the comparator compares the low-pass filtered signal with a reference signal, obtains the comparison result signal, and outputs it, the method further includes: The glitch removal circuit receives the comparison result signal output by the comparator, performs glitch removal on the comparison result signal, and then outputs it.

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