Data processing method and apparatus

Abstract

A data processing method, comprising: acquiring first data, wherein the first data is a two-dimensional feature in a three-dimensional feature map; and obtaining a computation result on the basis of a first matrix and a plurality of second matrices, wherein the first matrix is obtained on the basis of the first data, each of the second matrices is a matrix constructed on the basis of some elements in a convolution kernel, and the computation result is a convolution operation result of the first data. In the present application, by decomposing a convolution kernel having a smaller data volume, zero-padding data expansion of an input feature map in H and W dimensions is avoided, thereby exponentially reducing both data transfer overhead and computation time. Particularly in the scenario having a small input feature size, a transformed matrix multiplication computation significantly increases a compute-to-memory access ratio, further enhancing the overall performance of the convolution operation and improving the operator performance in the convolution operation.

Description

A data processing method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411219477.9, filed with the State Intellectual Property Office of China on August 31, 2024, entitled “A Data Processing Method and Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of artificial intelligence, and more particularly to a data processing method and apparatus thereof. Background Technology

[0003] Artificial intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a branch of computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the functions of perception, reasoning, and decision-making.

[0004] Large-scale model training and inference have accelerated the technological advancement of neural networks in both academia and industry. Large-scale model inference can extract valuable information from complex models to solve a wide variety of problems, such as image recognition, speech recognition, and natural language processing. However, large-scale model inference typically requires substantial computational resources, which to some extent limits its widespread application and real-time performance. Therefore, how to accelerate large-scale model inference and improve its efficiency in practical applications is an urgent problem to be solved. Summary of the Invention

[0005] In a first aspect, this application provides a data processing method, the method comprising: acquiring first data; the first data being a two-dimensional feature in a three-dimensional feature map; obtaining a calculation result based on a first matrix and a plurality of second matrices; wherein the first matrix is ​​obtained based on the first data, each of the second matrices is a matrix constructed based on a portion of the elements in a convolution kernel, and the calculation result is the convolution operation result of the first data.

[0006] Compared to existing solutions that use zero-insertion to inflate feature maps with large amounts of data, this application splits convolution kernels with smaller amounts of data and uses the matrices obtained from the split sub-convolution kernels and the matrix obtained from the input data (first data) to perform operations to obtain the convolution operation result. This avoids zero-insertion data inflation in the H and W dimensions of the input feature map, saving data handling and computation time by a factor of two. Especially for scenarios with small input feature sizes, the computation-to-memory ratio of the transformed matrix multiplication is greatly improved, further enhancing the overall performance of convolution computation and improving the performance of operators in convolution computation.

[0007] In this first matrix, each matrix row can be composed of some elements from the first data. The elements included in each matrix row correspond to a convolution operation. That is, if convolution is to be performed on the first data, the elements in the first data corresponding to each slide of the convolution kernel can form a matrix row in the first matrix.

[0008] The second matrix can be a column matrix constructed from the elements contained in a sub-convolution kernel of the convolution kernel.

[0009] A column matrix can be understood as a column of a matrix in form, where each element of the column is multidimensional, for example, two-dimensional. Therefore, it is called a column matrix.

[0010] In one possible implementation, the method further includes: obtaining a convolution kernel; splitting the convolution kernel to obtain multiple sub-convolution kernels; obtaining the first matrix based on the first data; and obtaining the second matrix based on each of the sub-convolution kernels.

[0011] The first data includes width and height dimensions.

[0012] In one possible implementation, the three-dimensional feature map is the input feature map during the backpropagation process of training the machine learning model.

[0013] In one possible implementation, the convolution stride of the convolution operation corresponding to the convolution kernel during the feedforward process of training the machine learning model is greater than 1. Since the convolution stride is greater than 1 during forward propagation, the size of the features obtained by the convolution operation becomes smaller, while during backpropagation, it is necessary to obtain larger features based on smaller features.

[0014] In one possible implementation, the first remainders corresponding to different elements contained in each sub-convolutional kernel are the same, and the second remainders corresponding to different elements contained in each sub-convolutional kernel are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

[0015] Specifically, by performing congruential splitting and rearranging on convolution kernels with smaller data volumes, redundant data handling and computation are effectively avoided, resulting in a significant improvement in operator performance during convolution computation. For the congruential splitting of the convolution kernel, based on observation and analysis of the ordinal relationships between input and output related data, a method is proposed to split the convolution kernel and the inverse output feature map into several corresponding blocks, with each block being orthogonal to the others. Furthermore, for the rearrangement of the convolution kernel, during the transformation of convolution operations into matrix multiplication, the split convolution kernel blocks are rearranged along the N-dimensional matrix multiplication, thereby consolidating multiple matrix multiplication operations and significantly improving the computation-to-memory ratio of the transformed matrix multiplication, further enhancing operator performance.

[0016] In one possible implementation, the method further includes: concatenating each of the plurality of second matrices as column matrices to obtain a third matrix; obtaining the calculation result based on the first matrix and the plurality of second matrices includes: obtaining the calculation result by performing operations on the first matrix and the third matrix.

[0017] In one possible implementation, obtaining the calculation result based on the first matrix and the plurality of second matrices includes: obtaining the calculation result by performing operations on the first matrix and each of the second matrices respectively.

[0018] In one possible implementation, obtaining the calculation result based on the first matrix and multiple second matrices includes: performing matrix multiplication on the first matrix and multiple second matrices, and rearranging the elements in the matrix multiplication result to obtain the calculation result.

[0019] In one possible implementation, the three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data, and the second data and the third data are different two-dimensional features among the multiple two-dimensional features. The method further includes: performing operations on the second data and the corresponding convolution kernel through a first processing kernel to obtain a first result; writing the first result into the storage space corresponding to a first address in dedicated memory (GM); performing operations on the third data and the corresponding convolution kernel through the first processing kernel to obtain a second result; triggering the dedicated memory to perform the accumulation of the first result and the second result, and replacing the first result stored in the storage space corresponding to the first address with the accumulated result.

[0020] In one possible implementation, the first processing core is configured to process an output feature map, and the first processing core is configured to process a plurality of two-dimensional features arranged in the depth dimension of the three-dimensional feature map, the plurality of two-dimensional feature maps being partitioned from the three-dimensional feature map based on the output feature map, and the first processing core processing the plurality of two-dimensional features is performed in an outer loop based on the depth dimension of the input feature map.

[0021] In one possible implementation, the method further includes: the first processing core reads the second data from the dedicated memory, and the read second data is not repeated.

[0022] Therefore, the accumulation in the D dimension can be performed on the GM, so that the input feature map no longer needs additional inflation in the D dimension, which can save time in transport by a factor of two.

[0023] Secondly, this application provides a data processing apparatus, the apparatus comprising:

[0024] The acquisition module is used to acquire first data; the first data is a two-dimensional feature in a three-dimensional feature map;

[0025] The processing module is used to obtain a calculation result based on a first matrix and multiple second matrices; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

[0026] In one possible implementation, the first data includes a width dimension and a height dimension.

[0027] In one possible implementation, the three-dimensional feature map is the input feature map during the backpropagation process of training the machine learning model.

[0028] In one possible implementation, the convolution stride of the convolution operation corresponding to the convolution kernel during the feedforward process of training the machine learning model is greater than 1.

[0029] In one possible implementation, the first remainders corresponding to different elements contained in each sub-convolutional kernel are the same, and the second remainders corresponding to different elements contained in each sub-convolutional kernel are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

[0030] In one possible implementation, the processing module is further configured to: obtain a third matrix by concatenating each of the plurality of second matrices as column matrices;

[0031] The processing module is specifically used for:

[0032] The calculation result is obtained by performing operations on the first matrix and the third matrix.

[0033] In one possible implementation, the processing module is specifically used for:

[0034] The calculation results are obtained by performing operations on the first matrix and each of the second matrices respectively.

[0035] In one possible implementation, the processing module is specifically used for:

[0036] Perform matrix multiplication on the first matrix and multiple second matrices, and rearrange the elements in the matrix multiplication result to obtain the calculation result.

[0037] In one possible implementation, the three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data, and the second and third data are different two-dimensional features among the multiple two-dimensional features. The processing module is further configured to:

[0038] The first processing kernel performs operations on the second data and the corresponding convolution kernel to obtain the first result.

[0039] Write the first result into the storage space corresponding to the first address in the dedicated memory (GM);

[0040] The first processing kernel performs operations on the third data and the corresponding convolution kernel to obtain the second result.

[0041] The dedicated memory is triggered to accumulate the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

[0042] In one possible implementation, the processing module is further configured to:

[0043] The first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

[0044] Thirdly, embodiments of this application provide a data processing apparatus, which may include a memory, a processor, and a bus system, wherein the memory is used to store a program, and the processor is used to execute the program in the memory to perform the methods described in the first aspect above and any of its optional methods.

[0045] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any of its optional methods.

[0046] Fifthly, embodiments of this application provide a computer program that, when run on a computer, causes the computer to perform the first aspect and any of its optional methods described above.

[0047] Sixthly, this application provides a chip system including a processor for supporting an execution data processing device in implementing the functions involved in the foregoing aspects, such as transmitting or processing data involved in the foregoing methods; or, information. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the execution device or training device. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0048] Figure 1A is a schematic diagram of a structural framework for artificial intelligence.

[0049] Figures 1B and 1C are schematic diagrams of the application system framework of the present invention;

[0050] Figure 1D is a schematic diagram of an optional hardware structure for the terminal;

[0051] Figure 2 is a schematic diagram of a server structure;

[0052] Figure 3 is a schematic diagram of a system architecture according to this application;

[0053] Figure 4 is a schematic diagram of a system architecture according to this application;

[0054] Figure 5 is a flowchart illustrating a data processing method provided in an embodiment of this application;

[0055] Figures 6A, 6B, and 6C are schematic diagrams of the system architecture;

[0056] Figure 7 is a schematic diagram of a data processing method provided in an embodiment of this application;

[0057] Figure 8 is a schematic diagram of a data processing method provided in an embodiment of this application;

[0058] Figure 9 is a schematic diagram of a framework provided in an embodiment of this application;

[0059] Figure 10 is a schematic diagram of a data processing device provided in an embodiment of this application;

[0060] Figure 11 is a schematic diagram of an execution device provided in an embodiment of this application;

[0061] Figure 12 is a schematic diagram of a training device provided in an embodiment of this application;

[0062] Figure 13 is a schematic diagram of a chip structure provided in an embodiment of this application. Detailed Implementation

[0063] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention.

[0064] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0065] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0066] The terms “substantially,” “about,” and similar terms used herein are used as approximations rather than as terms of degree, and are intended to take into account the inherent biases of measurements or calculations known to those skilled in the art. Furthermore, the use of “may” in describing embodiments of the invention refers to “one or more possible embodiments.” The terms “use,” “using,” and “used” used herein are to be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Additionally, the term “exemplary” is intended to refer to an instance or illustration.

[0067] First, the overall workflow of an artificial intelligence system is described, as shown in Figure 1A. Figure 1A is a structural diagram of the main framework of artificial intelligence. The framework is then elaborated from two dimensions: the "intelligent information chain" (horizontal axis) and the "IT value chain" (vertical axis). The "intelligent information chain" reflects a series of processes from data acquisition to processing. For example, it could be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, and intelligent execution and output. In this process, data undergoes a condensation process of "data—information—knowledge—wisdom." The "IT value chain" reflects the value that artificial intelligence brings to the information technology industry, from the underlying infrastructure of human intelligence and information (provided and processed by technology) to the industrial ecosystem of the system.

[0068] (1) Infrastructure

[0069] Infrastructure provides computing power to support artificial intelligence systems, enabling communication with the external world and providing support through a basic platform. This communication occurs through sensors; computing power is provided by intelligent chips (hardware acceleration chips such as CPUs, NPUs, GPUs, ASICs, and FPGAs); and the basic platform includes distributed computing frameworks and related platform guarantees and support, which may include cloud storage and computing, interconnected networks, etc. For example, sensors communicate with the outside world to acquire data, and this data is provided to intelligent chips in the distributed computing system provided by the basic platform for computation.

[0070] (2) Data

[0071] The data at the next layer of infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, text, and IoT data from traditional devices, including business data from existing systems and sensor data such as force, displacement, liquid level, temperature, and humidity.

[0072] (3) Data processing

[0073] Data processing typically includes methods such as data training, machine learning, deep learning, search, reasoning, and decision-making.

[0074] Among them, machine learning and deep learning can perform intelligent information modeling, extraction, preprocessing, and training on data, including symbolization and formalization.

[0075] Reasoning refers to the process in which, in a computer or intelligent system, the machine thinks and solves problems by simulating human intelligent reasoning, based on reasoning control strategies and using formalized information. Typical functions include search and matching.

[0076] Decision-making refers to the process of making decisions based on intelligent information after reasoning, and it typically provides functions such as classification, sorting, and prediction.

[0077] (4) General ability

[0078] After the data processing mentioned above, the results of the data processing can be used to form some general capabilities, such as algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0079] (5) Smart Products and Industry Applications

[0080] Intelligent products and industry applications refer to products and applications of artificial intelligence systems in various fields. They are the encapsulation of overall artificial intelligence solutions, productizing intelligent information decision-making and realizing practical applications. Their application areas mainly include: intelligent terminals, intelligent transportation, intelligent healthcare, autonomous driving, smart cities, etc.

[0081] This application can be applied to the field of natural language processing in the field of artificial intelligence. The following will introduce several application scenarios that have been implemented in products, taking natural language processing as an example.

[0082] First, we will introduce the application scenarios of this application. This application can be used, but is not limited to, applications with generative artificial intelligence (AIGC) functionality (hereinafter referred to as synthetic applications) or cloud services provided by cloud-side servers, etc., which will be introduced separately below:

[0083] I. Synthesis Applications

[0084] The product form of this application embodiment can be a synthetic application. Synthetic applications can run on terminal devices or cloud-based servers.

[0085] In one possible implementation, a synthesis application can perform data generation tasks based on input data (e.g., images, text, audio, video, etc.), wherein the synthesis application can perform data generation tasks in response to the input data (e.g., images, text, audio, video, etc.) to obtain generated data.

[0086] For example, the task of generating the above data can be, but is not limited to:

[0087] Text generation task: It can generate various types of text content, including news reports, blog posts, product descriptions, social media posts, etc. It can generate logical and coherent text based on given themes and requirements.

[0088] Image generation task: This task can generate images, including illustrations, artworks, design drafts, etc. It can generate image content related to given descriptions or keywords.

[0089] Audio generation task: This task can generate speech content, including text readings and responses from voice assistants. It can simulate human speech characteristics and intonation, making the generated speech sound more natural.

[0090] Content summarization and conclusion tasks: It can read large amounts of text content and generate summaries or conclusions. It can extract key information from the text and present it to the user in a concise manner.

[0091] Language translation task: This function performs language translation, converting text from one language to another. It can handle multiple language pairs and provide accurate translation results.

[0092] Automated replies and customer service: This can be used to automatically answer user questions and provide customer service. It can understand the user's intent and provide accurate answers or suggestions.

[0093] In one possible implementation, a user can open a synthesis application installed on a terminal device and input data (such as images, text, audio, video, etc.). The synthesis application can generate data from the input data using the method provided in the embodiments of this application and present the generated data to the user (the presentation method may include, but is not limited to, displaying, saving, uploading to the cloud, etc.).

[0094] In one possible implementation, a user can open a synthesis application installed on a terminal device and input data. The synthesis application can then send the input data to a cloud-based server. The cloud-based server uses the method provided in this application to generate data from the input data and sends the generated data back to the terminal device. The terminal device can then present the generated data to the user (the presentation method may include, but is not limited to, displaying, saving, or uploading to the cloud).

[0095] The following sections will describe the synthetic application in this application from the perspectives of functional architecture and product architecture that implements the functions.

[0096] Referring to Figure 1B, which is a schematic diagram of the functional architecture of the synthetic application in an embodiment of this application:

[0097] In one possible implementation, as shown in FIG1B, the synthetic application 102 may receive input parameters 101 (e.g., containing input data) and generate generated data 103. The synthetic application 102 may execute on at least one computer system (for example) and includes computer code that, when executed by one or more computers, causes the computers to execute a natural language model trained by the methods provided in the embodiments of this application.

[0098] Referring to Figure 1C, which is a schematic diagram of the entity architecture for running a synthetic application in an embodiment of this application:

[0099] Referring to Figure 1C, which illustrates a system architecture, the system may include a terminal 100 and a server 200. The server 200 may include one or more servers (Figure 1C illustrates this using one server as an example), and the server 200 may provide synthesis function services to one or more terminals.

[0100] The terminal 100 may have a synthesis application installed or a webpage related to the synthesis function open. The application and webpage can provide an interface. The terminal 100 can receive relevant parameters input by the user on the synthesis function interface and send the parameters to the server 200. The server 200 can obtain the processing result based on the received parameters and return the processing result to the terminal 100.

[0101] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the processing result based on the received parameters on its own, without the need for the server to cooperate. This application embodiment is not limited to this.

[0102] The product form of terminal 100 in Figure 1C will be described next;

[0103] The terminal 100 in this application embodiment can be a mobile phone, tablet computer, wearable device, vehicle device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc., and this application embodiment does not impose any restrictions on it.

[0104] Figure 1D shows a schematic diagram of an optional hardware structure for terminal 100.

[0105] Referring to Figure 1D, terminal 100 may include components such as a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, and a power supply 190. Those skilled in the art will understand that Figure 1D is merely an example of a terminal or multi-functional device and does not constitute a limitation on the terminal or multi-functional device; it may include more or fewer components than illustrated, or combine certain components, or use different components.

[0106] The input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the portable multi-functional device. Specifically, the input unit 130 may include a touchscreen 131 (optional) and / or other input devices 132. The touchscreen 131 can collect touch operations performed by the user on or near it (such as operations performed by the user using fingers, knuckles, styluses, or any suitable object on or near the touchscreen), and drive the corresponding connection devices according to a pre-set program. The touchscreen can detect the user's touch actions, convert the touch actions into touch signals and send them to the processor 170, and can receive and execute commands sent by the processor 170; the touch signal includes at least touch point coordinate information. The touchscreen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, various types of touchscreens, such as resistive, capacitive, infrared, and surface acoustic wave, can be used to implement the touchscreen. Besides the touchscreen 131, the input unit 130 may also include other input devices. Specifically, other input devices 132 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons 132, power buttons 133, etc.), trackball, mouse, joystick, etc.

[0107] Among them, the input device 132 can receive input data, etc.

[0108] The display unit 140 can be used to display information input by the user or information provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playback of any multimedia file. In this embodiment, the display unit 140 can be used to display the interface of a synthesis application, generated data, etc.

[0109] The memory 120 can be used to store instructions and data. The memory 120 may primarily include an instruction storage area and a data storage area. The data storage area can store various types of data, such as multimedia files and text. The instruction storage area can store software units such as operating systems, applications, and instructions required for at least one function, or subsets or extended sets thereof. It may also include non-volatile random access memory. It provides the processor 170 with hardware, software, and data resources for managing the computing device, supporting control software and applications. It is also used for storing multimedia files, as well as storing running programs and applications.

[0110] The processor 170 is the control center of the terminal 100. It connects various parts of the terminal 100 via various interfaces and lines. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it performs various functions and processes data of the terminal 100, thereby controlling the terminal device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 170. In some embodiments, the processor and memory can be implemented on a single chip; in some embodiments, they can also be implemented separately on independent chips. The processor 170 can also be used to generate corresponding operation control signals, send them to the corresponding components of the computing processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that the various functional modules therein perform corresponding functions, thereby controlling the corresponding components to act according to the instructions.

[0111] The memory 120 can be used to store software code related to the data processing method, and the processor 170 can execute the steps of the chip's data processing method, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to achieve the corresponding functions.

[0112] The radio frequency unit 110 (optional) can be used for receiving and transmitting signals during information transmission or calls. For example, it can receive downlink information from the base station and process it for the processor 170; additionally, it can transmit uplink data to the base station. Typically, the RF circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, the radio frequency unit 110 can also communicate wirelessly with network devices and other devices. This wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0113] In this embodiment of the application, the radio frequency unit 110 can send input data to the server 200 and receive generated data sent by the server 200.

[0114] It should be understood that the radio frequency unit 110 is optional and can be replaced with other communication interfaces, such as a network port.

[0115] The terminal 100 also includes a power supply 190 (such as a battery) that supplies power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0116] Terminal 100 also includes an external interface 180, which can be a standard Micro USB interface or a multi-pin connector, which can be used to connect terminal 100 to other devices for communication or to connect a charger to charge terminal 100.

[0117] Although not shown, terminal 100 may also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, and sensors with various functions, which will not be described in detail here. Some or all of the methods described below can be applied to terminal 100 as shown in Figure 1D.

[0118] The product form of server 200 in Figure 1C is described below;

[0119] Figure 2 provides a schematic diagram of the structure of a server 200. As shown in Figure 2, the server 200 includes a bus 201, a processor 202, a communication interface 203, and a memory 204. The processor 202, the memory 204, and the communication interface 203 communicate with each other via the bus 201.

[0120] Bus 201 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, only one thick line is used in Figure 2, but this does not indicate that there is only one bus or one type of bus.

[0121] The processor 202 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0122] Memory 204 may include volatile memory, such as random access memory (RAM). Memory 204 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0123] The memory 204 can be used to store software code related to the data processing method, and the processor 202 can execute the steps of the chip's data processing method, and can also schedule other units to achieve corresponding functions.

[0124] It should be understood that the aforementioned terminal 100 and server 200 can be centralized or distributed devices. The processors (e.g., processor 170 and processor 202) in the aforementioned terminal 100 and server 200 can be hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the processor can be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0125] It should be understood that the steps related to the model inference process in the embodiments of this application involve AI-related operations. When performing AI operations, the instruction execution architecture of the terminal device and the server is not limited to the processor-memory architecture described above. The system architecture provided in the embodiments of this application will be described in detail below with reference to Figure 5.

[0126] Figure 5 is a schematic diagram of the system architecture provided in an embodiment of this application. As shown in Figure 5, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data acquisition system 560.

[0127] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, while the preprocessing modules 513 and 514 are optional.

[0128] The execution device 510 can be a terminal device or a server that runs the aforementioned synthetic application.

[0129] The data acquisition device 560 is used to collect training samples. Training samples can be program files (including program code and program input data), etc. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0130] The training device 520 can maintain training samples in the database 530 to obtain the target model / rule 501 from the neural network to be trained.

[0131] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0132] The target model / rule 501 trained by the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in Figure 5. The execution device 510 can be a terminal, such as a mobile terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server, etc.

[0133] Specifically, the training device 520 can transfer the trained model to the execution device 510.

[0134] In Figure 5, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with external devices. Users can input data to the I / O interface 512 through the client device 540 (e.g., input data in the embodiment of this application).

[0135] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0136] During the preprocessing of input data by the execution device 510, or during the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0137] Finally, the I / O interface 512 provides the processing results (such as generated data) to the client device 540, thereby providing them to the user.

[0138] In the scenario shown in Figure 5, the user can manually provide input data, which can be done through the interface provided by I / O interface 512. Alternatively, the client device 540 can automatically send input data to I / O interface 512. If user authorization is required for the client device 540 to automatically send input data, the user can set the corresponding permissions in the client device 540. The user can view the output results of the execution device 510 on the client device 540, which can be presented in various forms such as display, sound, or animation. The client device 540 can also act as a data acquisition terminal, collecting the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530. Alternatively, data can be collected directly from the I / O interface 512 without going through the client device 540, using the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530.

[0139] It is worth noting that Figure 5 is merely a schematic diagram of a system architecture provided in an embodiment of this application. The positional relationships between the devices, components, modules, etc., shown in the figure do not constitute any limitation. For example, in Figure 5, the data storage system 550 is an external memory relative to the execution device 510. In other cases, the data storage system 550 can also be placed in the execution device 510. It should be understood that the aforementioned execution device 510 can be deployed in the client device 540.

[0140] From the inference side of the model:

[0141] In this embodiment, the computing module 511 of the execution device 510 can obtain the code stored in the data storage system 550 to implement the steps related to the model reasoning process in this embodiment.

[0142] In this embodiment of the application, the computing module 511 of the execution device 510 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0143] Specifically, the computing module 511 of the execution device 510 can be a hardware system with the function of executing instructions. The steps related to the model inference process provided in this application embodiment can be software code stored in the memory. The computing module 511 of the execution device 510 can obtain the software code from the memory and execute the obtained software code to implement the steps related to the model inference process provided in this application embodiment.

[0144] It should be understood that the computing module 511 of the execution device 510 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the model reasoning process provided in the embodiments of this application can also be implemented by the hardware system in the computing module 511 of the execution device 510 without the function of executing instructions, which is not limited here.

[0145] From the training side of the model:

[0146] In this embodiment, the training device 520 can obtain the code stored in the memory (not shown in Figure 5, which can be integrated into the training device 520 or deployed separately from the training device 520) to implement the steps related to model training in this embodiment.

[0147] In this embodiment of the application, the training device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0148] It should be understood that the training device 520 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the training of the neutralization model provided in the embodiments of this application can also be implemented by the hardware system in the training device 520 without the function of executing instructions, which is not limited here.

[0149] II. Cloud services providing synthesis functionality provided by the server:

[0150] In one possible implementation, the server can provide composition services to the client side through an application programming interface (API).

[0151] In this process, the terminal device can send relevant parameters (such as input data) to the server through the API provided by the cloud. The server can obtain the processing result (such as generated data) based on the received parameters and return the processing result to the terminal.

[0152] The description of the terminal and server can be found in the above embodiments, and will not be repeated here.

[0153] Figure 6A illustrates the process of using a synthetic function cloud service provided by a cloud platform.

[0154] 1. Activate and purchase content moderation services.

[0155] 2. Users can download the software development kit (SDK) corresponding to the content moderation service. Cloud platforms usually provide multiple development versions of the SDK for users to choose from according to their development environment needs, such as JAVA version SDK, Python version SDK, PHP version SDK, Android version SDK, etc.

[0156] 3. After downloading the corresponding version of the SDK to their local machine according to their needs, users can import the SDK project into their local development environment, configure and debug it in the local development environment, and develop other functions in the local development environment, thus forming an application that integrates the capabilities of composite functional classes.

[0157] 4. When a composition application is used, it can trigger an API call for the composition function when the composition function is required. When the application triggers the composition function, it sends an API request to the running instance of the composition function service in the cloud environment. The API request carries the input data, which is processed by the running instance in the cloud environment to obtain the processing result (such as generated data).

[0158] 5. The cloud environment returns the processing result to the application, thus completing a synthesis function service call.

[0159] In addition to applications and cloud services, the implementation of this application can also be in a large model inference acceleration library or a large model application SDK.

[0160] To better understand the solutions of the embodiments of this application, the following uses text generation as an example and combines Figures 3 and 4 to briefly introduce the possible application scenarios of the embodiments of this application.

[0161] Figure 3 illustrates a natural language processing (NLP) system, which includes user devices and data processing devices. The user devices include smart terminals such as mobile phones, personal computers, or information processing centers. The user devices are the initiators of natural language data processing, acting as the initiators of requests such as language question answering or queries; typically, users initiate requests through their user devices.

[0162] The aforementioned data processing equipment can be cloud servers, network servers, application servers, management servers, or other devices or servers with data processing capabilities. The data processing equipment receives queries / voice / text from smart terminals via an interactive interface, then performs language data processing through a storage device and a data processing processor, employing methods such as machine learning, deep learning, search, reasoning, and decision-making. The processing results are then fed back to the user device. The storage device in the data processing equipment can be a general term, including local storage and a database storing historical data. The database can be located on the data processing equipment or on other network servers.

[0163] In the natural language processing system shown in Figure 3, the user device can receive instructions from the user. For example, the user device can receive a piece of text input by the user and then send a request to the data processing device, so that the data processing device can perform natural language processing applications (such as natural language generation, text classification, text reasoning, named entity recognition, translation, etc.) on the piece of text obtained by the user device, thereby obtaining the processing results of the corresponding natural language processing applications on the piece of text (such as prediction results, classification results, reasoning results, named entity recognition results, translation results, etc.).

[0164] In this embodiment of the application, the user equipment can receive instructions from the user. For example, the user equipment can receive a piece of text input by the user (e.g., input data) and then send a request to the data processing device, so that the data processing device performs a natural language processing application (e.g., text synthesis) on the piece of text obtained by the user equipment, thereby obtaining the processing result (e.g., generated data) of the corresponding natural language processing application on the piece of text.

[0165] The text is shown in Figure 3. The data processing device can process the above-mentioned text data using the method provided in the embodiments of this application.

[0166] Figure 4 illustrates another natural language processing system. In Figure 4, the user equipment directly acts as a data processing device. This user equipment can directly receive input from the user and process it directly by the hardware of the user equipment itself. The specific process is similar to that in Figure 3, and can be referred to the description above, so it will not be repeated here.

[0167] Figure 4 is a schematic diagram of the natural language processing related devices provided in the embodiments of this application.

[0168] The processors in Figures 3 and 4 can perform data training / machine learning / deep learning using neural network models or other models, and use the models finally trained or learned from the data (such as the natural language models in the embodiments of this application) to perform natural language processing applications (such as program synthesis, etc.) on text data (such as the input data text described in the embodiments of this application) to obtain the corresponding processing results.

[0169] Since the embodiments of this application involve a large number of neural network applications, for ease of understanding, the relevant terms and concepts such as neural networks involved in the embodiments of this application will be introduced below.

[0170] (1) Neural Network

[0171] A neural network can be composed of neural units, which can be defined as a computational unit that takes xs (i.e., input data) and an intercept of 1 as input. The output of this computational unit can be:

[0172] Where s = 1, 2, ..., n, where n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of this activation function can be used as the input of the next convolutional layer, and the activation function can be the sigmoid function. A neural network is a network formed by connecting multiple of the above-mentioned individual neural units together, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, which can be a region composed of several neural units.

[0173] (2) Transformer layer

[0174] The neural network includes an embedding layer and at least one transformer layer. The at least one transformer layer can be N transformer layers (N being an integer greater than 0). Each transformer layer includes sequentially adjacent attention layers, add and normalize layers, feed-forward layers, and add and normalize layers. In the embedding layer, the current input is embedded to obtain multiple embedding vectors. In the attention layer, P input vectors are obtained from the layer above the first transformer layer. Using any first input vector among the P input vectors as the center, intermediate vectors corresponding to the first input vector are obtained based on the correlation between each input vector within a preset attention window and the first input vector. This process determines P intermediate vectors corresponding to the P input vectors. In the pooling layer, the P intermediate vectors are merged into Q output vectors, where the multiple output vectors obtained from the last transformer layer are used as feature representations of the current input.

[0175] (3) Attention mechanism

[0176] Attention mechanisms mimic the internal processes of biological observation—aligning internal experience with external senses to increase the precision of observation in specific areas. They enable the rapid sifting of high-value information from a large volume of data using limited attentional resources. Attention mechanisms can quickly extract important features from sparse data and are therefore widely used in natural language processing tasks, particularly machine translation. Self-attention mechanisms, an improvement on attention mechanisms, reduce reliance on external information and are better at capturing the internal correlations of data or features. The core idea of ​​attention mechanisms can be rewritten as follows:

[0177] In this formula, Lx = ||Source|| represents the length of the Source. The meaning is that the elements in the Source are imagined as a series of data pairs. Given a Query element in the Target, the similarity or relevance between the Query and each Key is calculated to obtain the weight coefficient of the Value corresponding to each Key. Then, the Values ​​are weighted and summed to obtain the final Attention value. Therefore, the Attention mechanism essentially performs a weighted sum of the Values ​​of the elements in the Source, while the Query and Key are used to calculate the weight coefficients of their corresponding Values. Conceptually, Attention can be understood as selectively filtering a small amount of important information from a large amount of information and focusing on this important information, ignoring most of the unimportant information. The focusing process is reflected in the calculation of the weight coefficients; the larger the weight, the more focused it is on its corresponding Value. That is, the weight represents the importance of the information, and the Value is the corresponding information. Self-attention can be understood as intra attention. The attention mechanism occurs between the elements of the Target (Query) and all elements of the Source. Self-attention refers to the attention mechanism that occurs between elements within the Source or between elements within the Target. It can also be understood as the attention calculation mechanism in the special case where Target = Source. The specific calculation process is the same, only the calculation object changes.

[0178] (4) Natural Language Processing (NLP)

[0179] Natural language is human language, and Natural Language Processing (NLP) is the processing of human language. NLP is a systematic process of analyzing, understanding, and extracting information from text data in an intelligent and efficient manner. By using NLP and its components, we can manage very large amounts of text data, perform numerous automated tasks, and solve a wide variety of problems, such as automatic summarization, machine translation (MT), named entity recognition (NER), relation extraction (RE), information extraction (IE), sentiment analysis, speech recognition, question answering systems, and topic segmentation, among others.

[0180] (5) Pre-trained language model

[0181] A pre-trained language model is a natural language sequence encoder that encodes each word in a natural language sequence into a vector representation for prediction tasks. Its training consists of two phases. In the pre-training phase, the model is trained on a large-scale unsupervised text environment to learn word representations. In the fine-tuning phase, the model is initialized using the parameters learned in the pre-training phase and then trained on downstream tasks such as text classification and sequence labeling with fewer steps, successfully transferring the semantic information obtained in pre-training to these downstream tasks.

[0182] (6) Reasoning / Deployment: The forward computation process of a neural network.

[0183] (7) Large Language Model (LLM): A large language model is a natural language processing model trained on large-scale data, typically with billions or tens of billions of parameters. These models learn to capture the general features of language by learning from a large amount of text data during the pre-training stage, and can then be fine-tuned on downstream tasks to adapt to the needs of specific tasks.

[0184] (8) Matrix processing unit (cube unit): The unit in the NPU used to calculate matrix multiplication. It can only calculate matrix multiplication of data of the same type, such as integer matrix multiplication by integer matrix, or floating-point matrix multiplication by floating-point matrix. In general NPU chips, the cube unit has strong computing power.

[0185] (9) Vector processing unit: The unit used by the NPU to perform vector operations. It can perform a variety of vector operations, but its computing power is weaker than that of the Cube unit.

[0186] (10) Global memory (GM): Memory used to store data. It has a large space. The data involved in the calculation of Cube and Vector units need to be read from GM, but the bandwidth (reading speed) of reading data from GM is small.

[0187] (11) L2: L2 cache (secondary cache) is used to store data. It has a smaller space than GM and a higher read and write speed than GM. At the beginning of the calculation process, the data is located in GM and needs to enter L2 first and then enter Cube / UB; while the data coming out of Cube / UB can directly enter L2.

[0188] (12) L1: Level 1 cache, i.e., the cache in the Cube unit. The space is relatively smaller than L2, and the read and write speed is relatively higher than L2.

[0189] (13) L0A / L0B / L0C: Level 0 cache, which is a cache in the Cube cell specifically used to store computational data. It has the smallest space and the highest read and write speed. Among them, L0A / B / C are specifically used to store the left matrix / right matrix and the computation result matrix.

[0190] (14)Img2col: A hardware instruction that converts two-dimensional convolution operations into matrix multiplication. In the NPU, it is completed along the path during the data transfer process (MTE1 path).

[0191] (15)Conv2d / 3d: that is, 2D / 3D convolution forward calculation, the input is feature map X and convolution kernel W, and the output is feature map Y.

[0192] (16) Conv2d / 3ddx: That is, the reverse DX calculation of 2D / 3D convolution. The input is the feature map gradient DY = dE / dY and the convolution kernel W, and the output is the feature map gradient DX = dE / dX, where E is the loss function.

[0193] (17)Conv2d / 3ddw: That is, the reverse DW calculation of 2D / 3D convolution. The input is the feature map gradient DY = dE / dY and the feature map X, and the output is the convolution kernel gradient DW = dE / dW.

[0194] Large-scale model training and inference have accelerated the technological advancement of neural networks in both academia and industry. Large-scale model inference can extract valuable information from complex models to solve a wide variety of problems, such as image recognition, speech recognition, and natural language processing. However, large-scale model inference typically requires substantial computational resources, which to some extent limits its widespread application and real-time performance. Therefore, how to accelerate large-scale model inference and improve its efficiency in practical applications is an urgent problem to be solved.

[0195] With the emergence of large multimodal models such as Sora, GPT-4o, and Gemini, the industry's demand for efficient computing power for training and inference of large multimodal models has surged dramatically. Convolutional operators, as core operators in multimodal processing, require performance optimization to improve the overall network performance for training and inference. Especially in scenarios where the stride of conv2d / 3ddx (i.e., 2D or 3D convolutional inverse DX operators) is greater than 1, existing implementations have low effective MAC utilization, with overall performance less than 25% of the theoretical hardware limit.

[0196] Since most AI acceleration hardware currently only supports the Img2col instruction for expanding 2D feature maps, a common approach for 3D convolution operations is to expand the outermost dimension D of the three dimensions (D, H, W) of the 3D feature map using an outer loop. Specifically, this is a kernel-loop coupling method, where both the kernel and the outer loop along the D axis are divided according to the D dimension of the output feature map (D_out for the forward direction and D_in for the reverse direction), and all summations along the reduction axes are performed in registers as inner products. Figure 6B illustrates this with an example of calculating the reverse DX dimension of 3D convolution. As shown in Figure 6B, both the kernel and the outer loop are divided according to the D_in dimension of the output feature map DX. Figure 6B also shows the data change of the input feature map DY along the D dimension: from D_out to (D_in, D_k). In other words, the existing kernel-loop coupling scheme requires first performing data forward magnification on the input feature map in the D dimension, similar to Img2col, with a magnification factor of D_k / D_s (where D_k is the size of the convolution kernel in the D dimension, and D_s is the stride size in the D dimension).

[0197] After expanding the D dimension through the outer loop, the expansion of the two internal dimensions (H, W) of the 3D feature map is performed using the hardware instruction Img2col. However, for scenarios with a stride greater than 1 in the inverse convolution DX computation, since the input feature map DY is smaller than the output feature map DX in the (H, W) dimension, the hardware instruction Img2col cannot directly convert this type of convolution computation into matrix multiplication. Existing technical solutions (such as the convolution operator in the CANN package on the Ascend NPU) first perform zero-placing inflation on the input feature map DY according to the stride size, so that DY is expanded to the same size as the output feature map DX in the (H, W) dimension, and then perform convolution operation with the convolution matrix W(-H,-W) after the convolution kernel W is flipped by 180°, thereby obtaining the output feature map DX (as shown in Figure 6C).

[0198] The drawbacks of existing technologies can be summarized as the need to perform forward dilation on the input feature map data, which leads to excessive redundant handling and computation, resulting in poor operator performance.

[0199] Specifically, at the D-dimensional loop level, the kernel-loop coupling scheme inevitably requires forward scaling of the input feature map in the D dimension, resulting in significant data transport redundancy. Similarly, in scenarios where the stride in the inner dimension (H,W) is greater than 1, zero-placing inflation of the input feature map DY will also multiply the input data volume, introducing redundant transport and computation. For example, in conv3ddx, with a kernel W of size Dk=3 in the D dimension and a stride of 2 in the (H,W) dimension, existing techniques would forward scale the input feature map DY by 12 times and introduce 3 times the redundant computation.

[0200] In addition, the core-loop coupling scheme generally adopts complete sequential accumulation (or segmented accumulation on small granularities and sequential accumulation on large granularities), and the accumulation accuracy is generally lower than that of segmented accumulation on large granularities.

[0201] To address the aforementioned problems, embodiments of this application provide a data processing method. The data processing method of this application embodiment will be described in detail below with reference to the accompanying drawings.

[0202] Referring to Figure 7, which is a flowchart of a data processing method provided in an embodiment of this application, as shown in Figure 7, the data processing method provided in an embodiment of this application may include steps 701 to 702, which will be described in detail below.

[0203] 701. Obtain the first data; the first data is a two-dimensional feature in a three-dimensional feature map;

[0204] The three-dimensional feature map can include depth, height and width dimensions. The first data can be features on the same depth dimension, which can include width and height dimensions.

[0205] In one possible implementation, the 3D feature map is the input feature map during the backpropagation process of training the machine learning model. Alternatively, it could be the forward propagation feature map.

[0206] In one possible implementation, the convolution stride of the convolution operation corresponding to the convolution kernel during the feedforward process of training the machine learning model is greater than 1.

[0207] In one possible implementation, the elements contained in the convolutional kernel can be split to obtain multiple sub-convolutional kernels;

[0208] In one possible implementation, the first remainders corresponding to different elements contained in each sub-convolutional kernel are the same, and the second remainders corresponding to different elements contained in each sub-convolutional kernel are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

[0209] For the inner loop of the backward computation of conv3ddx in 3D convolution, when the stride is greater than 1, the original scheme also has another case of data forward dilation, namely, zero-placing dilation of the input feature map DY. Compared with the existing scheme that performs zero-placing dilation on the large feature map DY, the embodiment of this application only performs congruential splitting and rearrangement on the convolution kernel W with a smaller data volume. A schematic diagram of the specific operation process is as follows:

[0210] Convolutional kernel congruential partitioning: First, the convolutional kernel is partitioned along the H and W dimensions according to... The differences and similarities are divided into H s ·W s In this block, "%" stands for modulo operation. A 4x4 convolution kernel W is used in H... s =W s Taking the case of 2 as an example,

[0211] It can be decomposed into 4 ΔW matrices

[0212] In summary, the two dimensions H and W of the convolution kernel are divided into four dimensions, namely...

[0213] in, and These are the element indices H(W) of the convolution kernel. k Relative step size H(W) s The divisor and remainder.

[0214] Convolutional kernel rearrangement: Next, the segmented convolutional kernels are merged and rearranged. This merging and rearrangement can be divided into the following steps: a. Each convolutional kernel block ΔW is flipped 180 degrees, i.e. b. Perform `img2col` on each inverted convolutional kernel block to transform it into a column matrix; c. Concatenate each column matrix along its column dimension to form a new matrix. The four ΔW matrices in the example above become the following after these operations:

[0215] In addition, if the size of each dimension of the convolution kernel is not an integer multiple of the stride of the corresponding dimension, a certain amount of zero-padding will be involved in the rearrangement process.

[0216] Compared to existing solutions that use zero-insertion to inflate feature maps with large amounts of data, this application avoids zero-insertion in the H and W dimensions of the input feature map by splitting the convolution kernel with smaller data size, thus saving data transfer and computation time by a factor of two. Especially for scenarios with small Cin, the computation-to-memory ratio of the transformed matrix multiplication is greatly improved, further enhancing the overall performance of convolution computation and improving the performance of operators in convolution computation.

[0217] Specifically, by performing congruential splitting and rearranging on convolution kernels with smaller data volumes, redundant data handling and computation are effectively avoided, resulting in a significant improvement in operator performance during convolution computation. For the congruential splitting of the convolution kernel, based on observation and analysis of the ordinal relationships between input and output related data, a method is proposed to split the convolution kernel and the inverse output feature map into several corresponding blocks, with each block being orthogonal to the others. Furthermore, for the rearrangement of the convolution kernel, during the transformation of convolution operations into matrix multiplication, the split convolution kernel blocks are rearranged along the N-dimensional matrix multiplication, thereby consolidating multiple matrix multiplication operations and significantly improving the computation-to-memory ratio of the transformed matrix multiplication, further enhancing operator performance.

[0218] 702. Based on the first matrix and multiple second matrices, a calculation result is obtained; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

[0219] In this first matrix, each matrix row can be composed of some elements from the first data. The elements included in each matrix row correspond to a convolution operation. That is, if convolution is to be performed on the first data, the elements in the first data corresponding to each slide of the convolution kernel can form a matrix row in the first matrix.

[0220] The second matrix can be a column matrix constructed from the elements contained in a sub-convolution kernel of the convolution kernel.

[0221] A column matrix can be understood as a column of a matrix in form, where each element of the column is multidimensional, for example, two-dimensional. Therefore, it is called a column matrix.

[0222] In one possible implementation, the method further includes: concatenating each of the plurality of second matrices as column matrices to obtain a third matrix; and then obtaining a calculation result by performing operations (e.g., matrix multiplication) on the first matrix and the third matrix.

[0223] In one possible implementation, the calculation result can be obtained by performing operations on the first matrix and each of the second matrices respectively.

[0224] In one possible implementation, matrix multiplication can be performed on the first matrix and multiple second matrices, and the elements in the matrix multiplication result can be rearranged to obtain the calculation result.

[0225] For example, the convolution operation can be transformed into matrix multiplication: the input feature map DY is transformed into the left matrix in matrix multiplication using img2col, and then multiplied with the right matrix W′ to obtain the matrix. Due to the results obtained in the previous step According to The output feature map DX is arranged in (NCHW) format and needs to be rearranged to obtain the output feature map DX arranged in (NCHW) format.

[0226] The above steps can be illustrated in Figure 8.

[0227] In one possible implementation, the three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data. The second data and the third data are different two-dimensional features among the multiple two-dimensional features. The second data and the corresponding convolution kernel are processed by a first processing kernel to obtain a first result. The first result is written to the storage space corresponding to a first address in the dedicated memory (GM). The third data and the corresponding convolution kernel are processed by the first processing kernel to obtain a second result. The dedicated memory is triggered to perform the accumulation of the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

[0228] In one possible implementation, the first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

[0229] To address the pain point of requiring forward amplification of input data in the outermost dimension loop-kernel coupling scheme for 3D convolution computation, this application proposes a loop-kernel decoupling scheme. Taking the reverse computation of conv3ddx as an example, to avoid deterministic problems that may arise from the accumulation of different kernels on the same memory, the kernels are still divided according to the D dimension (i.e., D_in) of the output feature map (supplemented by meticulous write order management within a single kernel); however, the outermost loop of the computation within a single kernel takes the D dimension (i.e., D_out) of the input feature map, and the Dk dimension is accumulated using an outer product method on GM to maximize the reuse of data from the reverse input feature map.

[0230] Currently, because the `img2col` hardware instruction on NPU and other chips does not support direct manipulation of 3D feature maps and convolutional kernels, existing technologies for forward and backward computation of conv3d involve looping out the D dimension, with both the outer loop and kernels divided according to the D dimension of the output matrix, resulting in loop-kernel coupling. Taking the backward computation of conv3d as an example (the forward computation is similar), excluding the batch dimension, the outermost loop and kernel dimensions are both D_in (abbreviated as Di). Inevitably, during the data transfer from the GM to the L1 cache, the data storage format of the backward input feature map DY needs to be transformed from (N, Co, Do, Ho, Wo) to (N, Di, Dk, Co1, Ho, Wo, Co0). When the D-dimensional stride Ds equals 1, the data volume is magnified by approximately Dk times, causing significant data transfer redundancy.

[0231] This application addresses this problem in existing technologies by proposing a decoupling solution for the loop-kernel division. Taking the reverse computation of conv3d as an example, the outermost Di loop is transformed into a D_out (Do) loop. Then, in the innermost Dk (the kernel's index in dimension D) loop, the value of Di is derived by reverse calculation based on the relationship Do*Ds = Di + Dk - D_pad. Since the same Do corresponds to different Di values ​​as Dk changes, the accumulation in the Dk dimension can be performed on GM using atomic_add (i.e., the accumulation write instruction), while the accumulation in the (Co,Hk,Wk) dimension is still implemented in the register. This eliminates the need for additional inflation of the input feature map DY in the D dimension, significantly reducing processing time. Furthermore, to avoid the deterministic problems that may arise from multi-kernel accumulation and writing on GM, the outer loop-kernel division needs to be decoupled. That is, the kernel division still follows the Di dimension of the output feature map DX, and is managed with refined write logic. For specific core partitioning strategies, please refer to Figure 9 (note that the Do values ​​allocated to different cores may overlap) and the corresponding pseudocode.

[0232] By employing the above method, the forward data expansion of the input feature map is avoided, saving data transportation and computation time by a factor of two. Specifically, the forward data expansion of the input feature map in the D dimension is avoided, saving data transportation time by a factor of two. Furthermore, the segmented accumulation in this technique has higher accumulation accuracy than the sequential accumulation in the original technique.

[0233] Referring to Figure 10, which is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application, as shown in Figure 10, the data processing apparatus 1000 provided in this embodiment includes:

[0234] Acquisition module 1001 is used to acquire first data; the first data is a two-dimensional feature in a three-dimensional feature map;

[0235] The processing module 1002 is used to obtain a calculation result based on a first matrix and a plurality of second matrices; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

[0236] In one possible implementation, the first data includes a width dimension and a height dimension.

[0237] In one possible implementation, the three-dimensional feature map is the input feature map during the backpropagation process of training the machine learning model.

[0238] In one possible implementation, the convolution stride of the convolution operation corresponding to the convolution kernel during the feedforward process of training the machine learning model is greater than 1.

[0239] In one possible implementation, the first remainders corresponding to different elements contained in each sub-convolutional kernel are the same, and the second remainders corresponding to different elements contained in each sub-convolutional kernel are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

[0240] In one possible implementation, the processing module 1002 is further configured to: obtain a third matrix by concatenating each of the plurality of second matrices as column matrices;

[0241] The processing module 1002 is specifically used for:

[0242] The calculation result is obtained by performing operations on the first matrix and the third matrix.

[0243] In one possible implementation, the processing module 1002 is specifically used for:

[0244] The calculation results are obtained by performing operations on the first matrix and each of the second matrices respectively.

[0245] In one possible implementation, the processing module 1002 is specifically used for:

[0246] Perform matrix multiplication on the first matrix and multiple second matrices, and rearrange the elements in the matrix multiplication result to obtain the calculation result.

[0247] In one possible implementation, the three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data, and the second and third data are different two-dimensional features among the multiple two-dimensional features. The processing module 1002 is further configured to:

[0248] The first processing kernel performs operations on the second data and the corresponding convolution kernel to obtain the first result.

[0249] Write the first result into the storage space corresponding to the first address in the dedicated memory (GM);

[0250] The first processing kernel performs operations on the third data and the corresponding convolution kernel to obtain the second result.

[0251] The dedicated memory is triggered to accumulate the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

[0252] In one possible implementation, the processing module 1002 is further configured to:

[0253] The first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

[0254] The following describes a terminal device provided in an embodiment of this application. Please refer to Figure 11, which is a structural schematic diagram of a terminal device provided in an embodiment of this application. The terminal device 1100 can specifically be a virtual reality (VR) device, a mobile phone, a tablet, a laptop computer, a smart wearable device, etc., and is not limited here. Specifically, the terminal device 1100 includes: a receiver 1101, a transmitter 1102, a processor 1103, and a memory 1104 (the number of processors 1103 in the terminal device 1100 can be one or more; Figure 11 shows one processor as an example). The processor 1103 may include an application processor 11031 and a communication processor 11032. In some embodiments of this application, the receiver 1101, transmitter 1102, processor 1103, and memory 1104 can be connected via a bus or other means.

[0255] Memory 1104 may include read-only memory and random access memory, and provides instructions and data to processor 1103. A portion of memory 1104 may also include non-volatile random access memory (NVRAM). Memory 1104 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0256] Processor 1103 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram.

[0257] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1103. The processor 1103 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 1103 or by instructions in software form. The processor 1103 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 1103 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 1104. Processor 1103 reads the information in memory 1104 and, in conjunction with its hardware, completes the steps involved in the model training or model inference process described above.

[0258] Receiver 1101 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 1102 can be used to output digital or character information through the first interface; transmitter 1102 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 1102 may also include a display device such as a display screen.

[0259] This application embodiment also provides a server. Referring to Figure 12, Figure 12 is a schematic diagram of a server structure provided in this application embodiment. The server 1200 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1212 (e.g., one or more processors) and a memory 1232, and one or more storage media 1230 (e.g., one or more mass storage devices) for storing application programs 1242 or data 1244. The memory 1232 and storage media 1230 can be temporary or persistent storage. The program stored in the storage media 1230 may include one or more modules (not shown in the figure), each module may include a series of instruction operations on the server. Furthermore, the CPU 1212 may be configured to communicate with the storage media 1230 and execute the series of instruction operations in the storage media 1230 on the server 1200.

[0260] Server 1200 may also include one or more power supplies 1226, one or more wired or wireless network interfaces 1250, one or more input / output interfaces 1258; or, one or more operating systems 1241, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0261] In this embodiment, the central processing unit 1212 is used to perform actions related to model training or model inference in the above embodiments.

[0262] This application also provides a computer program product that, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0263] This application also provides a computer-readable storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0264] The execution device, training device, or terminal device provided in this application embodiment can specifically be a chip. The chip includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip within the execution device to execute the data processing method described in the above embodiments, or to cause the chip within the training device to execute the data processing method described in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0265] Specifically, please refer to Figure 13, which is a schematic diagram of a chip structure provided in an embodiment of this application. The chip can be represented as a neural network processor (NPU) 1300. The NPU 1300 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core part of the NPU is the arithmetic circuit 1303, which is controlled by the controller 1304 to extract matrix data from the memory and perform multiplication operations.

[0266] In some implementations, the arithmetic circuit 1303 internally includes multiple processing engines (PEs). In some implementations, the arithmetic circuit 1303 is a two-dimensional pulsating array. The arithmetic circuit 1303 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1303 is a general-purpose matrix processor.

[0267] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 1302 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 1301 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 1308.

[0268] Unified memory 1306 is used to store input and output data. Weight data is directly transferred to weight memory 1302 via Direct Memory Access Controller (DMAC) 1305. Input data is also transferred to unified memory 1306 via DMAC.

[0269] BIU stands for Bus Interface Unit, which is used for interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 1309.

[0270] The Bus Interface Unit (BIU) 1310 is used by the instruction fetch memory 1309 to fetch instructions from external memory, and also by the memory access controller 1305 to fetch the original data of the input matrix A or the weight matrix B from external memory.

[0271] The DMAC is mainly used to move input data from external memory DDR to unified memory 1306, or to weight data to weight memory 1302, or to input data to input memory 1301.

[0272] The vector computation unit 1307 includes multiple processing units that further process the output of the computation circuit 1303 when needed, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as Batch Normalization, pixel-level summation, and upsampling of feature planes.

[0273] In some implementations, the vector computation unit 1307 can store the processed output vector in the unified memory 1306. For example, the vector computation unit 1307 can apply a linear function, or a nonlinear function, to the output of the computation circuit 1303, such as performing linear interpolation on the feature planes extracted by the convolutional layer, or, for example, accumulating a vector of values ​​to generate activation values. In some implementations, the vector computation unit 1307 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as an activation input to the computation circuit 1303, for example, for use in subsequent layers of the neural network.

[0274] The instruction fetch buffer 1309 connected to the controller 1304 is used to store the instructions used by the controller 1304;

[0275] Unified memory 1306, input memory 1301, weighted memory 1302, and instruction fetch memory 1309 are all on-chip memories. External memory is proprietary to this NPU hardware architecture.

[0276] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program.

[0277] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0278] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0279] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0280] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A data processing method, characterized in that, The method includes: Obtain the first data; the first data is a two-dimensional feature in a three-dimensional feature map; The calculation result is obtained based on the first matrix and multiple second matrices; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

2. The method according to claim 1, characterized in that, The method further includes: Obtain the convolution kernel; The convolutional kernel is split to obtain multiple sub-convolutional kernels; Based on the first data, the first matrix is ​​obtained; A second matrix is ​​obtained based on each of the sub-convolution kernels.

3. The method according to claim 1 or 2, characterized in that, Each of the second matrices is specifically a matrix constructed based on a sub-convolution kernel in the convolution kernel, wherein the sub-convolution kernel is composed of a portion of the elements of the convolution kernel.

4. The method according to any one of claims 1 to 3, characterized in that, Each row of the matrix includes elements that are a subset of the elements in the first data, wherein the subset of elements is the elements in the first data covered by a single convolutional sliding window operation performed on the first data using a convolutional kernel.

5. The method according to any one of claims 1 to 4, characterized in that, The first data includes width and height dimensions.

6. The method according to any one of claims 1 to 5, characterized in that, The three-dimensional feature map is the input feature map during the backpropagation process of training the machine learning model.

7. The method according to claim 6, characterized in that, During the feedforward process of training the machine learning model, the convolution stride of the convolution operation corresponding to the convolution kernel is greater than 1.

8. The method according to any one of claims 1 to 7, characterized in that, The first remainders corresponding to different elements contained in each of the sub-convolutional kernels are the same, and the second remainders corresponding to different elements contained in each of the sub-convolutional kernels are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: concatenating each of the plurality of second matrices as column matrices to obtain a third matrix; The calculation results obtained based on the first matrix and multiple second matrices include: The calculation result is obtained by performing operations on the first matrix and the third matrix.

10. The method according to any one of claims 1 to 9, characterized in that, The calculation results obtained based on the first matrix and multiple second matrices include: The calculation results are obtained by performing operations on the first matrix and each of the second matrices respectively.

11. The method according to any one of claims 1 to 10, characterized in that, The calculation results obtained based on the first matrix and multiple second matrices include: Perform matrix multiplication on the first matrix and multiple second matrices, and rearrange the elements in the matrix multiplication result to obtain the calculation result.

12. The method according to any one of claims 1 to 11, characterized in that, The three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data. The second data and the third data are different two-dimensional features among the multiple two-dimensional features. The method further includes: The first processing kernel performs operations on the second data and the corresponding convolution kernel to obtain the first result. Write the first result into the storage space corresponding to the first address in the dedicated memory (GM); The first processing kernel performs operations on the third data and the corresponding convolution kernel to obtain the second result. The dedicated memory is triggered to accumulate the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

13. The method according to claim 12, characterized in that, The first processing core is configured to process multiple two-dimensional features arranged in the depth dimension of the three-dimensional feature map to obtain an output feature map. The multiple two-dimensional feature maps are determined from the three-dimensional feature map based on the data contained in the output feature map. The first processing core performs an outer loop based on the order of the depth dimension of the multiple two-dimensional features when processing the multiple two-dimensional features.

14. The method according to claim 12 or 13, characterized in that, The method further includes: The first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

15. A data processing apparatus, characterized in that, The device includes: The acquisition module is used to acquire first data; the first data is a two-dimensional feature in a three-dimensional feature map; The processing module is used to obtain a calculation result based on a first matrix and multiple second matrices; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

16. The apparatus according to claim 15, characterized in that, The first remainders corresponding to different elements contained in each of the sub-convolutional kernels are the same, and the second remainders corresponding to different elements contained in each of the sub-convolutional kernels are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

17. The apparatus according to claim 15 or 16, characterized in that, The processing module is further configured to: concatenate each of the plurality of second matrices as column matrices to obtain a third matrix; The processing module is specifically used for: The calculation result is obtained by performing operations on the first matrix and the third matrix.

18. The apparatus according to any one of claims 15 to 17, characterized in that, The processing module is specifically used for: The calculation results are obtained by performing operations on the first matrix and each of the second matrices respectively.

19. The apparatus according to any one of claims 15 to 18, characterized in that, The processing module is specifically used for: Perform matrix multiplication on the first matrix and multiple second matrices, and rearrange the elements in the matrix multiplication result to obtain the calculation result.

20. The apparatus according to any one of claims 15 to 19, characterized in that, The three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data. The second data and the third data are different two-dimensional features among the multiple two-dimensional features. The processing module is further configured to: The first processing kernel performs operations on the second data and the corresponding convolution kernel to obtain the first result. Write the first result into the storage space corresponding to the first address in the dedicated memory (GM); The first processing kernel performs operations on the third data and the corresponding convolution kernel to obtain the second result. The dedicated memory is triggered to accumulate the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

21. The apparatus according to claim 20, characterized in that, The processing module is further configured to: The first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

22. A computer storage medium, characterized in that, The computer storage medium stores one or more instructions, which, when executed by one or more computers, cause the one or more computers to perform the operation of the method according to any one of claims 1 to 14.

23. A computer program product, characterized in that, Includes computer-readable instructions that, when executed on a computer device, cause the computer device to perform the method as described in any one of claims 1 to 14.

24. A system comprising at least one processor and at least one memory; the processor and the memory are connected via a communication bus and communicate with each other. The at least one memory is used to store code; The at least one processor is used to execute the code to perform the method as described in any one of claims 1 to 14.

25. A chip, comprising a processor, characterized in that, The processor is used to support the data processing device in implementing the method as described in any one of claims 1 to 14.

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