Array substrate, display panel, and display apparatus

Abstract

Disclosed are an array substrate, a display panel, and a display apparatus. The array substrate comprises a base substrate, a first metal layer, a first insulating layer, and a first transparent electrode layer that are stacked; the base substrate is provided with a plurality of sub-pixels arranged in an array; the first metal layer comprises metal lines located between adjacent sub-pixels, the direction of extension of the metal lines being a first direction, and a direction intersecting the first direction being a second direction; the first transparent electrode layer comprises first transparent electrodes located at each of the sub-pixels and comprises first connecting portions and second connecting portions, two adjacent first transparent electrodes arranged in the second direction being electrically connected by means of a corresponding first connecting portion, two adjacent first transparent electrodes arranged in the first direction being electrically connected by means of a corresponding second connecting portion, and each second connecting portion being electrically connected to a corresponding metal line by means of a first via hole passing through the first insulating layer; a first notch is formed at the position of the metal line corresponding to each first via hole, and the orthographic projection of the first notch on the base substrate partially covers the orthographic projection of the first via hole on the base substrate.

Description

An array substrate, a display panel, and a display device.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411189174.7, filed on August 27, 2024, entitled "An Array Substrate, Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0004] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0005] This disclosure provides an array substrate, a display panel, and a display device for improving pixel aperture ratio. The specific solution is as follows:

[0006] This disclosure provides an array substrate having a plurality of sub-pixels arranged in an array, the array substrate comprising:

[0007] Substrate;

[0008] A first metal layer is located on one side of the substrate. The first metal layer includes metal lines located between adjacent sub-pixels. The extending direction of the metal lines is a first direction, and the direction intersecting the first direction is a second direction.

[0009] A first insulating layer is located on the side of the first metal layer that faces away from the substrate.

[0010] A first transparent electrode layer is located on the side of the first insulating layer facing away from the substrate. The first transparent electrode layer includes a first transparent electrode located in each sub-pixel and includes a first connection portion and a second connection portion. Two adjacent first transparent electrodes arranged along the second direction are electrically connected through the first connection portion, and two adjacent first transparent electrodes arranged along the first direction are electrically connected through the second connection portion. The second connection portion is electrically connected to the metal line through a first via penetrating the first insulating layer. The metal line has a first notch corresponding to the position of the first via, and the orthographic projection of the first notch on the substrate covers part of the orthographic projection of the first via on the substrate.

[0011] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the metal line includes a first portion corresponding to the first via location and a second portion corresponding to a location other than the first via location, the width of the first portion along the second direction is greater than the width of the second portion along the second direction, and the first portion has the first notch.

[0012] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the area of ​​the first notch is less than 1 / 4 of the sum of the areas of the first portion and the first notch.

[0013] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the orthographic projection of the inner wall of the first notch on the substrate is a polygonal shape.

[0014] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the orthographic projection of the inner wall of the first notch onto the substrate is arc-shaped.

[0015] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the first via is divided into four first sub-vias along the first direction and the second direction, and the orthogonal projection of the first notch on the substrate at least covers the orthogonal projection of a portion of one of the first sub-vias on the substrate.

[0016] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the first portion further has a second notch, the orthographic projection of the second notch on the substrate at least covering the orthographic projection of a portion of another first sub-via on the substrate.

[0017] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the first notch and the second notch are disposed opposite to each other.

[0018] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the first portion has a center point, and the first notch and the second notch are centrally symmetrical about the center point.

[0019] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the first notch and the second notch are arranged adjacent to each other.

[0020] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the metal line has a center line extending along the first direction, and the first notch and the second notch are symmetrically arranged about the center line.

[0021] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the area of ​​the second notch is the same as the area of ​​the first notch.

[0022] In one possible implementation, the array substrate provided in the embodiments of this disclosure further includes a second metal layer located between the substrate and the first metal layer. The second metal layer includes a plurality of gate lines extending along the second direction and arranged along the first direction. The first metal layer also includes a plurality of data lines extending along the first direction and arranged along the second direction. The data lines and the metal lines are alternately disposed between the sub-pixels of adjacent columns.

[0023] The multiple gate lines and the multiple data lines intersect to define the multiple sub-pixels. The sub-pixels in the same row have different colors, while the sub-pixels in the same column have the same color. Each row of sub-pixels is electrically connected to two corresponding gate lines.

[0024] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the two gate lines electrically connected to the sub-pixels in the same row are respectively located on both sides of the sub-pixel, and there are two gate lines between two adjacent rows of sub-pixels.

[0025] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the orthogonal projection of the first via on the substrate is located between the orthogonal projections of the two gate lines between adjacent sub-pixels on the substrate.

[0026] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the orthographic projection of the first portion on the substrate is located between the orthographic projections of the two gate lines between adjacent sub-pixels on the substrate.

[0027] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the width of the region of the second portion that overlaps with the gate line is greater than the width of the region of the second portion that does not overlap with the gate line.

[0028] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the two columns of the first transparent electrodes and the second connection portion between two adjacent data lines are an integral structure.

[0029] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the first transparent electrode layer further includes a third connection portion, and two adjacent second connection portions along the second direction are electrically connected through the third connection portion.

[0030] In one possible implementation, the array substrate provided in this embodiment further includes: a second transparent electrode layer located between the second metal layer and the substrate, a second insulating layer located between the second metal layer and the first metal layer, and an active layer located between the second insulating layer and the first metal layer; wherein...

[0031] The first metal layer further includes a source and a drain, the second transparent electrode layer includes a second transparent electrode located in each of the sub-pixels, the first transparent electrode layer further includes a fourth connection portion, the fourth connection portion is electrically connected to the drain and the second transparent electrode respectively through a second via penetrating the first insulating layer and the second insulating layer, and the data line is electrically connected to the source.

[0032] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the active layer includes a channel portion electrically connected to the source and the drain, and a dummy portion located between the metal line and the second insulating layer. The pattern of the dummy portion is the same as the pattern of the metal line, and the dummy portion has a third notch corresponding to the position of the first notch.

[0033] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the first transparent electrode is a common electrode, and the first transparent electrode includes a plurality of slits;

[0034] The second transparent electrode is a pixel electrode, and the second transparent electrode is a planar electrode.

[0035] Accordingly, this disclosure also provides a display panel, including: the array substrate provided in this disclosure, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

[0036] Accordingly, this disclosure also provides a display device, including the display panel provided in the embodiments of this disclosure.

[0037] The beneficial effects of the embodiments disclosed herein are as follows:

[0038] This disclosure provides an array substrate, display panel, and display device. By providing a first notch on a metal line and overlapping a portion of a first via for connecting a first transparent electrode layer and the metal line with the first notch and the other portion with the metal line, the first via is formed on the metal line in a semi-overlapping manner. This creates multiple stepped buffer structures at the first notch. During PI liquid coating, the PI liquid flows through the first via because the terrain at the location of the first via is relatively flat, which guides the flow of the PI liquid, improves PI fluidity, and facilitates the diffusion of the PI liquid toward the first via. This prevents the PI liquid from accumulating at the first via, improves the problem of uneven PI diffusion, avoids pixel display inhomogeneity (mura), and improves the product yield of the array substrate. Attached Figure Description

[0039] Figure 1 is a schematic diagram of a Dual Gate pixel architecture for an LCD array substrate;

[0040] Figure 2 is a layout diagram corresponding to some sub-pixels in Figure 1 provided in related technologies;

[0041] Figure 3 is a partially enlarged schematic diagram of Figure 2;

[0042] Figure 4 is an enlarged schematic diagram of the location of the first via in Figure 3;

[0043] Figure 5 is a schematic cross-sectional view of a portion of the membrane layer along the AA' direction in Figure 4;

[0044] Figure 6 is a schematic diagram of a layout corresponding to some sub-pixels in Figure 1 provided by an embodiment of this disclosure;

[0045] Figure 7 is a partially enlarged schematic diagram of Figure 6;

[0046] Figure 8 is a partially enlarged schematic diagram of Figure 7;

[0047] Figure 9 is a schematic diagram of the cross section along the CC' direction in Figure 8;

[0048] Figure 10 is a schematic diagram of the cross section along the FF' direction in Figure 8;

[0049] Figure 11 is an enlarged schematic diagram of the location of the first via in Figure 8;

[0050] Figure 12 is a schematic diagram of the cross section along the AA' direction in Figure 11;

[0051] Figure 13 is a partial enlarged schematic diagram of Figure 11;

[0052] Figure 14 is a partially enlarged schematic diagram of the metal wire provided in an embodiment of this disclosure;

[0053] Figure 15 is a partially enlarged schematic diagram of the metal wire provided in an embodiment of this disclosure;

[0054] Figure 16 is a partially enlarged schematic diagram of the metal wire provided in an embodiment of this disclosure;

[0055] Figure 17 is a partial enlarged schematic diagram of Figure 6;

[0056] Figure 18 is a schematic diagram of another layout corresponding to some sub-pixels in Figure 1, provided by an embodiment of this disclosure;

[0057] Figure 19 is a partially enlarged schematic diagram of Figure 18;

[0058] Figure 20 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0061] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] As used in this disclosure, "parallel," "perpendicular," and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 10% of either one.

[0063] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0064] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, for clarity, the thickness of layers and the area of ​​regions are enlarged. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] In this disclosure, circles, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate circles, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances may exist, and chamfers, curved edges, and other deformations may exist.

[0066] LCD display panels generally include an array substrate and a counter substrate (i.e., a color filter substrate) arranged opposite each other, and a liquid crystal layer located between the array substrate and the counter substrate. A liquid crystal alignment layer is provided on the side of the array substrate facing the liquid crystal layer and on the side of the counter substrate facing the liquid crystal layer. The liquid crystal alignment layer can be a polyimide film, or PI film for short.

[0067] With the continuous maturation of liquid crystal display technology, LCD array substrates have gradually developed towards lower cost and lower power consumption. Currently, array substrates reduce the number of data signal channels by adding gate drive circuits (GOA) and gate lines for time-division driving, thereby reducing the number of driver chips (ICs). However, the increase in gate lines inevitably reduces the pixel aperture ratio. Therefore, in order to reduce costs without sacrificing too much aperture ratio, the commonly used pixel architecture is Dual Gate (each row of pixel units is driven by two rows of gate lines). As shown in Figure 1, Figure 1 is a schematic diagram of a Dual Gate pixel architecture of an LCD array substrate. The array substrate includes multiple gate lines (G1, G2, ...) and multiple data lines (D1, D2, ...). The gate lines and data lines are insulated and cross each other to define multiple pixel units distributed in an array. Each pixel unit includes multiple sub-pixels with different color resist colors. Optionally, each pixel unit includes three sub-pixels with color resist colors of red (R), green (G), and blue (B). Red, green, and blue are the basic colors in the display field. Various colors are obtained by changing the red, green, and blue color channels and superimposing them, thereby achieving full-color display.

[0068] Specifically, as shown in Figures 2 and 3, Figure 2 is a schematic diagram of the layout of some sub-pixels in Figure 1, and Figure 3 is a partially enlarged schematic diagram of Figure 2. The array substrate includes a substrate 1, a gate metal layer (G, denoted by G), a gate insulating layer (GI), an active layer (Act), a source / drain metal layer (SD), a passivation layer (PVX), and a double-layer ITO electrode layer, where one ITO electrode layer serves as the pixel electrode layer and the other ITO electrode layer serves as the common electrode layer. To reduce the number of masks required to fabricate the array substrate, the lower ITO electrode layer (hereinafter referred to as 1ITO) can be fabricated in one mask process with the gate metal layer (Gate), for example, using halftone mask (HTM) technology, with 1ITO directly below the gate metal layer (Gate); the active layer (Act) and the source / drain metal layer (SD) can also be fabricated in one mask process, for example, using halftone mask (HTM) technology, with the active layer (Act) directly below the source / drain metal layer (SD). Specifically, 1ITO can serve as the pixel electrode layer, and the upper ITO electrode layer (hereinafter referred to as 2ITO) serves as the common electrode layer. The common electrode layer is located above the source and drain metal layers. The pixel electrode layer includes multiple independent pixel electrodes P, and the common electrode layer includes multiple independent common electrodes com. Pixel electrodes P correspond one-to-one with sub-pixels, and common electrodes com correspond one-to-one with sub-pixels. To ensure the uniformity of the common signal (com uniformity) of the entire LCD display panel, adjacent common electrodes com in the row direction are generally connected together using 2ITO, and adjacent common electrodes com in the column direction are connected together using 2ITO to improve the uniformity of the common signal. Because ITO has a relatively high resistance (sheet resistivity Rs = 31Ω), if adjacent common electrodes com in the row / column direction are only connected through 2ITO, the uniformity of the common signal is poor, and the panel display will exhibit a greenish tint.

[0069] Specifically, as shown in Figures 1-3, since this pixel architecture uses a Dual Gate, it can reduce the number of data lines by half compared to the traditional Single Gate pixel architecture. This allows for the placement of metal lines (D1', D2', ...) on the same layer as the data lines (D1, D2...) between adjacent sub-pixels that do not have data lines. The 2ITO, which is electrically connected to the adjacent common electrode com in the column direction, is electrically connected to the metal lines (D1', D2', ...) through the first via V1 that passes through the PVX. Since the material of the data line is generally Cu, which has low resistance (sheet resistivity Rs = 0.075Ω), electrically connecting the common electrode layer to the metal lines can reduce the resistance of the common electrode com, which is beneficial to improving the uniformity of the common signal and preventing the panel display from turning green.

[0070] As shown in Figure 4, which is an enlarged schematic diagram of the location of the first via V1 in Figure 3, the common electrode layer (2ITO) is electrically connected to the underlying metal lines (D1', D2', etc.) through the first via V1. Since there is one first via V1 between every two sub-pixels in the column direction, multiple first via V1s are arrayed in the display area. In actual production, the inventors of this disclosure found that the first via V1 of PVX is not conducive to the diffusion of PI liquid. As shown in Figure 5, which is a cross-sectional schematic diagram of a portion of the film layer along the AA' direction in Figure 4, due to the surface tension of the PI liquid itself, the PI liquid will accumulate around the first via V1. The PI closer to the first via V1 is thicker, and the PI farther away from the first via V1 is thinner. This will cause display problems such as pixel display unevenness (mura), resulting in product yield loss.

[0071] This disclosure provides an array substrate, as shown in Figures 1 and 6-12. Figure 6 is a schematic diagram of the layout of some sub-pixels in Figure 1, Figure 7 is a partially enlarged schematic diagram of Figure 6, Figure 8 is a partially enlarged schematic diagram of Figure 7, Figure 9 is a cross-sectional schematic diagram along the CC' direction in Figure 8, Figure 10 is a cross-sectional schematic diagram along the FF' direction in Figure 8, Figure 11 is an enlarged schematic diagram of the position of the first via V1 in Figure 8, and Figure 12 is a cross-sectional schematic diagram along the AA' direction in Figure 11. The array substrate has a plurality of sub-pixels P arranged in an array. The array substrate includes:

[0072] Substrate 1;

[0073] The first metal layer 2 is located on one side of the substrate 1. The first metal layer 2 includes metal lines (D1', D2'...) located between adjacent sub-pixels. The extension direction of the metal lines (D1', D2'...) is the first direction Y, and the direction intersecting the first direction Y is the second direction X.

[0074] The first insulating layer 3 is located on the side of the first metal layer 2 that is away from the substrate 1;

[0075] The first transparent electrode layer 4 is located on the side of the first insulating layer 3 facing away from the substrate 1. The first transparent electrode layer 4 includes a first transparent electrode 41 located in each sub-pixel and includes a first connection portion 42 and a second connection portion 43. Two adjacent first transparent electrodes 41 arranged along the second direction X are electrically connected through the first connection portion 42, and two adjacent first transparent electrodes 41 arranged along the first direction Y are electrically connected through the second connection portion 43. The second connection portion 43 is electrically connected to the metal lines (D1', D2'...) through a first via V1 penetrating the first insulating layer 3. The metal lines (D1', D2'...) have a first notch H1 corresponding to the position of the first via V1. The orthogonal projection of the first notch H1 on the substrate 1 covers part of the orthogonal projection of the first via V1 on the substrate 1.

[0076] Specifically, the first metal layer 2 is a source / drain metal layer (SD), the first transparent electrode layer 4 is a common electrode layer (2ITO), that is, the first transparent electrode 41 is a common electrode com, and the first insulating layer 3 can be a passivation layer (PVX).

[0077] The array substrate provided in this embodiment of the present disclosure, by setting a first notch on the metal line and overlapping a portion of the first via for connecting the first transparent electrode layer and the metal line with the first notch and the other portion with the metal line, that is, forming the first via on the metal line in a semi-overlapping manner, can form multiple stepped buffer structures at the first notch. When PI liquid is coated, when the PI liquid passes through the first via, the terrain at the location of the first via is relatively flat, which guides the flow of the PI liquid, making the PI flow better and facilitating the diffusion of the PI liquid toward the first via, thereby preventing the PI liquid from accumulating at the first via, improving the problem of uneven PI diffusion, thereby avoiding the problem of pixel display unevenness (mura), and improving the product yield of the array substrate.

[0078] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 6-8, 11, and 12, the metal lines (D1', D2', ...) include a first portion 21 corresponding to the position of the first via V1 and a second portion 22 corresponding to the position of a non-first via V1. The width of the first portion along the second direction X of 21 is greater than the width of the second portion 22 along the second direction X. The first portion 21 has a first notch H1. Specifically, the size of the second connection portion 43 corresponding to the position of the first via V1 is approximately the same as the size of the first portion 21, which ensures that the second connection portion 43 is electrically connected to the first portion along 21 through the first via V1. The width of the second portion 22 is greater than the width of the second connection portion 43 corresponding to the position of a non-first via V1. For example, if the width of the second connection portion 43 corresponding to the position of a non-first via V1 is 5.5 μm, the width of the second portion 22 is 8 μm. A larger line width results in lower resistance. A larger width of the second portion 22 helps to reduce the resistance of the common electrode com, improve the uniformity of the common signal, and prevent the panel display from showing a green tint.

[0079] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 6-12, it further includes: a second metal layer 5 located between the substrate 1 and the first metal layer 2, a second transparent electrode layer 6 located between the second metal layer 5 and the substrate 1, a second insulating layer 7 located between the second metal layer 5 and the first metal layer 2, and an active layer 8 (Act) located between the second insulating layer 7 and the first metal layer 2; specifically, the second metal layer 5 is a gate metal layer (Gate), the second transparent electrode layer 6 is a pixel electrode layer (ITO), and the second insulating layer 7 is a gate insulating layer (GI).

[0080] Specifically, in order to save on mask and reduce manufacturing costs, the second transparent electrode layer 6 and the second metal layer 5 can be fabricated using a single mask process, that is, the second transparent electrode layer 6 and the second metal layer 5 can be fabricated using halftone mask (HTM) technology.

[0081] Specifically, in order to save on mask and reduce manufacturing costs, the first metal layer 2 and the active layer 8 can be fabricated using a single mask process, that is, the first metal layer 2 and the active layer 8 can be fabricated using halftone mask (HTM) technology.

[0082] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 6-8, 11, 13 and 14, Figure 13 is a partially enlarged schematic diagram of Figure 11, and Figure 14 is another partially enlarged schematic diagram of the metal line provided in the embodiments of this disclosure. If the area of ​​the first gap H1 is too small, it is easy for the first gap H1 to not cover the first via V1. If the area of ​​the first gap H1 is too large, it is easy for the metal line to break. Therefore, in this disclosure, the area of ​​the first gap H1 is set to be less than 1 / 4 of the sum of the areas of the first part 21 and the first gap H1. Specifically, the sum of the areas of the first part 21 and the first gap H1 is equal to the area of ​​the square pattern of the metal line corresponding to the first via V1 in Figure 4. In this disclosure, the square pattern of the metal line corresponding to the first via V1 in Figure 4 with less than 1 / 4 of its area is removed to form the first gap H1. The orthographic projection of the first gap H1 on the substrate 1 covers the orthographic projection of a corner of the first via V1 on the substrate 1. This allows the PI liquid to flow under a relatively gentle elevation difference, which can better solve the problem of PI liquid accumulation at the first via V1.

[0083] In the array substrates provided in some embodiments of this disclosure, as shown in Figures 6-8, 11 and 13, the orthographic projection of the inner wall of the first notch H1 onto the substrate 1 can be a polygonal shape; as shown in Figure 14, the orthographic projection of the inner wall of the first notch H1 onto the substrate 1 can be an arc shape; of course, it is not limited to this.

[0084] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 11 and 12, the first via V1 is divided into four first sub-vias V11 along the first direction Y and the second direction X. The orthographic projection of the first notch H1 on the substrate 1 at least covers a portion of the orthographic projection of one of the first sub-vias V11 on the substrate 1. Optionally, the shape of the first via V1 can be square, circular, elliptical, etc. In this embodiment, a square hole is used as an example. The orthographic projection of the first notch H1 on the substrate 1 covers the orthographic projection of the upper right corner of the first via V1 on the substrate 1. This allows the PI liquid to flow under a relatively gentle elevation difference, which can better solve the problem of PI liquid accumulation at the first via V1. Specifically, the film cross-sectional structure at positions ①, ②, ③, ④, ⑤, ⑥, and ⑦ in Figure 11 is shown in Figure 12. The specific film cross-sectional structure is as follows:

[0085] ① The location has a substrate 1 / 1ITO / Gate / GI / Act / SD / PVX / 2ITO, and the terrain is relatively high;

[0086] ②The substrate 1 / GI / Act / SD / PVX / 2ITO is located at a slightly lower elevation than ①;

[0087] ③ The substrate 1 / GI / PVX / 2ITO is located at a lower elevation than ②.

[0088] ④ The substrate 1 / GI / 2ITO is located at position ④, and its terrain is lower than that of ③;

[0089] ⑤ The substrate 1 / GI / Act / SD / 2ITO is located at position ⑤, and its terrain is higher than that of ④;

[0090] Location ⑥ contains substrate 1 / GI / Act / SD / PVX / 2ITO, and its terrain is higher than that of location ⑤;

[0091] ⑦ The substrate 1 / 1ITO / Gate / GI / Act / SD / PVX / 2ITO is located at a relatively high elevation.

[0092] As can be seen from the terrain at positions ①, ②, ③, ④, ⑤, ⑥, and ⑦ above, the PI (pixel permeable) is buffered and guided by multiple steps when passing through the first via V1. The PI flows downhill and then uphill due to the alternating high and low terrain. Because the terrain is relatively flat and slopes gently, it guides the flow of the PI, improving its fluidity and preventing it from accumulating at the first via V1, which could cause pixel inhomogeneity (mura). This, in turn, improves the product yield of the array substrate.

[0093] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 15 and 16, the first portion 21 may also have a second notch H2. The orthographic projection of the second notch H2 onto the substrate 1 at least covers a portion of the area of ​​another first sub-via V11 (e.g., the upper left corner or lower left corner of a square hole) onto the substrate 1. By forming two notches on the first portion 21 of the metal lines (D1', D2'...), a large area of ​​high and low buffering terrain can be formed at the location of the first via V1, which improves the flowability of PI and forms a uniform PI film.

[0094] In the array substrate provided in some embodiments of this disclosure, as shown in FIG15, the first notch H1 and the second notch H2 can be arranged opposite to each other, that is, the orthographic projection of the second notch H2 on the substrate 1 covers the orthographic projection of the lower left corner of the first via V1 on the substrate 1; optionally, the first portion 21 has a center point A, and the first notch H1 and the second notch H2 are centrally symmetrical about the center point A. This embodiment takes the orthographic projection of the inner wall of the first notch H1 and the second notch H2 on the substrate 1 as a broken line shape as an example. Of course, the orthographic projection of the inner wall of the first notch H1 and the second notch H2 on the substrate 1 can also be an arc or other shapes.

[0095] In the array substrate provided in some embodiments of this disclosure, as shown in FIG16, the first notch H1 and the second notch H2 can be arranged adjacent to each other, that is, the orthographic projection of the second notch H2 on the substrate 1 covers the orthographic projection of the upper left corner of the first via V1 on the substrate 1; optionally, the metal lines (D1', D2'...) have a center line L extending along the first direction Y, and the first notch H1 and the second notch H2 can be symmetrically arranged about the center line L. This embodiment takes the orthographic projection of the inner wall of the first notch H1 and the second notch H2 on the substrate 1 as an example of being arc-shaped. Of course, the orthographic projection of the inner wall of the first notch H1 and the second notch H2 on the substrate 1 can also be a polygonal shape or other shapes.

[0096] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 15 and 16, the area of ​​the second notch H2 and the area of ​​the first notch H1 can be the same; of course, they can also be different, as long as the orthogonal projections of the first notch H1 and the second notch H2 on the substrate 1 respectively cover the orthogonal projection of a corner of the first via V1 on the substrate 1.

[0097] It should be noted that the embodiments disclosed herein take the first part 21 of the metal wire having one or two gaps as an example. Of course, the first part 21 can also have three or four gaps, as long as the metal retained between two adjacent gaps does not cause the metal wire to break. The principle of improving the flow of PI liquid with three or four gaps is similar to that with one or two gaps, and a gentler terrain can be achieved from different directions.

[0098] It should be noted that, in the above-described array substrate provided in some embodiments of this disclosure, the first via V1 is square in shape as an example. When the first via V1 is circular or elliptical, when the first part 21 only includes the first notch H1, the orthogonal projection of the first notch H1 on the substrate 1 can cover the orthogonal projection of 1 / 4 of the circular or elliptical hole on the substrate 1. When the first part 21 includes the first notch H1 and the second notch H2, the orthogonal projection of the first notch H1 on the substrate 1 can cover the orthogonal projection of one of the areas smaller than 1 / 4 of the circular or elliptical hole on the substrate 1, and the orthogonal projection of the second notch H2 on the substrate 1 can cover the orthogonal projection of the other area smaller than 1 / 4 of the circular or elliptical hole on the substrate 1.

[0099] In the array substrate provided in some embodiments of this disclosure, as shown in FIG1 and FIG6-8, the second metal layer 5 includes a plurality of gate lines (G1, G2...) extending along the second direction X and arranged along the first direction Y, and the first metal layer 2 also includes a plurality of data lines (D1, D2...) extending along the first direction Y and arranged along the second direction X. The data lines (D1, D2...) and metal lines (D1', D2'...) are alternately disposed between sub-pixels in adjacent columns.

[0100] Multiple gate lines (G1, G2...) and multiple data lines (D1, D2...) intersect to define multiple sub-pixels. Sub-pixels in the same row have different colors (e.g., arranged in RGBRGBRGB... in the same row), while sub-pixels in the same column have the same color. Each row of sub-pixels is electrically connected to two gate lines. That is, the pixel architecture of this embodiment is a Dual Gate. Dual gate driving can reduce power consumption and cost. Compared to array substrates using Single Gate technology, array substrates employing Dual Gate technology can save half the number of data lines. This allows for the placement of metal lines (D1', D2', ...) on the same layer as the data lines (D1, D2, ...) between adjacent columns of sub-pixels that do not have data lines (D1, D2, ...). The second connection portion 43, which connects to the adjacent first transparent electrode 41 in the first direction Y, is electrically connected to the metal lines (D1', D2', ...) through the first via V1 penetrating the PVX. Since the material of the data lines is generally Cu, which has low resistance (sheet resistivity Rs = 0.075Ω), electrically connecting the common electrode layer to the metal lines can reduce the resistance of the common electrode com, which is beneficial for improving the uniformity of the common signal, preventing the panel display from turning green, and effectively preventing display defects such as panel flicker.

[0101] In the array substrate provided in some embodiments of this disclosure, as shown in FIG1 and FIG6-8, two gate lines (G3 and G4) electrically connected to the same row of sub-pixels (e.g., the second row of sub-pixels) are respectively located on both sides of the sub-pixel (the second row of sub-pixels), and there are two gate lines (G2 and G3) between adjacent rows of sub-pixels (e.g., the first row of sub-pixels and the second row of sub-pixels).

[0102] The orthographic projection of the first via V1 on the substrate 1 is located between the orthographic projections of the two gate lines (G4 and G5) between adjacent sub-pixels (e.g., the second and third rows of sub-pixels) on the substrate 1. The orthographic projection of the first part 21 on the substrate 1 is located between the orthographic projections of the two gate lines (G4 and G5) between adjacent sub-pixels (e.g., the second and third rows of sub-pixels) on the substrate 1. This is beneficial for forming the high and low buffer terrain shown in Figure 12 as ①, ②, ③, ④, ⑤, ⑥, and ⑦, which is conducive to the flow of PI liquid and the formation of a uniform PI film.

[0103] In the array substrate provided in some embodiments of this disclosure, as shown in FIG17 (a partially enlarged schematic diagram of FIG6), the width W2 of the region overlapping with the gate line (e.g., G4) of the second part 22 is greater than the width W1 of the region of the second part 22 that does not overlap with the gate line (e.g., G4). This is because the film thickness in the region with the gate line is higher, and the second part 22 needs to climb a slope when crossing the gate line. In order to prevent the risk of line breakage during the climbing of the second part 22, the width W2 of the region overlapping with the gate line (e.g., G4) of the second part 22 can be set to be greater than the width W1 of the region of the second part 22 that does not overlap with the gate line (e.g., G4).

[0104] Specifically, as shown in Figure 17, the width W4 of the non-notch position of the first part 21 is greater than the width W3 of the notch position, and W3 can be set to be greater than W2, which can also prevent the metal wire from climbing and breaking at the grid position.

[0105] In the array substrate provided in some embodiments of this disclosure, as shown in FIG1 and FIG6, the first transparent electrode 41 and the second connection portion 43 of the two columns (second column and third column) between two adjacent data lines (e.g., D1 and D2) can be an integral structure. This is because no data lines are provided between the two columns of first transparent electrodes 41 between two adjacent data lines (e.g., D1 and D2). Therefore, the two columns of first transparent electrodes 41 of the integral structure will not have the problem of overlapping capacitance with the data lines, and the integral structure can further improve the uniformity of the common signal.

[0106] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 18 and 19 (Figure 19 is a partially enlarged schematic diagram of Figure 18), the first transparent electrode layer 4 further includes a third connecting portion 44, and two adjacent second connecting portions 43 along the second direction X are electrically connected through the third connecting portion 44. This connection of the second connecting portions 43 via the third connecting portion 44 in the horizontal direction further increases the uniformity of the common signal.

[0107] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 6-8, 10, and 18, the first metal layer 2 further includes a source electrode S and a drain electrode D. The second transparent electrode layer 6 includes a second transparent electrode 61 (i.e., a pixel electrode) located in each sub-pixel. The first transparent electrode layer 4 further includes a fourth connection portion 45, which is electrically connected to the drain electrode D and the second transparent electrode 61 respectively through a second via V2 penetrating the first insulating layer 3 and the second insulating layer 7. Data lines (D1, D2, ...) are electrically connected to the source electrode S. In addition, the second metal layer 5 also includes a gate electrode G electrically connected to the gate line. The gate electrode G, the source electrode S, the drain electrode D, and the active layer (Act) constitute a thin-film transistor. In this way, the drain electrode D and the second transparent electrode 61 are electrically connected through the fourth connection portion 45, realizing independent driving of each sub-pixel.

[0108] In the array substrate provided in some embodiments of this disclosure, as shown in Figures 6, 9, 12, and 18, the active layer 8 includes a channel portion 81 electrically connected to the source electrode S and the drain electrode D, and a dummy portion 82 located between the metal lines (D1', D2'...) and the second insulating layer 7. The pattern of the dummy portion 82 is the same as that of the metal lines (D1', D2'...), and the dummy portion 82 has a third notch corresponding to the position of the first notch H1. Specifically, since the active layer 8 and the first metal layer 2 are fabricated using the HTM process, the first metal layer 2 and the active layer 8 can be etched using the same mask to form the dummy portion 82 and the metal lines (D1', D2'...) with the same pattern.

[0109] In the array substrate provided in some embodiments of this disclosure, as shown in FIG6 and FIG18, the first transparent electrode 41 is a common electrode and may include a plurality of slits; the second transparent electrode 61 is a pixel electrode and may be a planar electrode.

[0110] Alternatively, the active layer can be made of amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (such as indium gallium zinc oxide IGZO), etc.

[0111] Specifically, as shown in Figures 6 and 18, multiple sub-pixels emit different colors. For example, these sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel emits red (R), the second sub-pixel emits green (G), and the third sub-pixel emits blue (B). RGB is the fundamental color spectrum in the display field. By varying the R, G, and B color channels and superimposing them, various colors are obtained, thus achieving full-color display.

[0112] Optionally, the materials of the first insulating layer and the second insulating layer can be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0113] Optionally, the materials of the first transparent electrode layer and the second transparent electrode layer include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0114] Optionally, the material of the first metal layer may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The first metal layer may be a single-layer structure or a stacked structure. For example, the first metal layer may be a stacked structure composed of a titanium metal layer, an aluminum metal layer, and a titanium metal layer.

[0115] Optionally, the material of the second metal layer may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The second metal layer may be a single-layer structure or a stacked structure. For example, the second metal layer may be a single-layer structure composed of a molybdenum metal layer.

[0116] It should be noted that other essential components in the array substrate are all known to those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0117] Based on the same inventive concept, this disclosure also provides a display panel, including: the array substrate provided in this disclosure, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

[0118] Specifically, in this embodiment, the opposing substrate can be a color filter substrate, on which a black matrix (BM) and multiple filters are disposed. The BM is disposed in the gap between adjacent sub-pixels. On the one hand, the BM is used to define multiple sub-pixels to avoid light crosstalk between adjacent sub-pixels. On the other hand, the BM is used to block metal signal lines, such as gate lines and data lines, to prevent metal signal lines from reflecting and reduce the reflectivity of the display area. Specifically, the BM includes an opening corresponding to each sub-pixel, and each filter is disposed in the corresponding opening. The multiple filters may include a red filter (e.g., a red color filter), a green filter (e.g., a green color filter), and a blue filter (e.g., a blue color filter).

[0119] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of the display device provided in this disclosure can refer to the implementation of the display panel described above, and repeated details will not be elaborated further.

[0120] In some embodiments, the display device provided in this disclosure further includes a backlight module located on the light-incident side of the array substrate.

[0121] In some embodiments, the backlight module in the display device provided in this disclosure can be a direct-lit backlight module or an edge-lit backlight module. Optionally, an edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. A direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).

[0122] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0123] In specific implementation, the display device provided in the embodiments of this disclosure is a liquid crystal display device. The liquid crystal display device also includes other necessary components and parts, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here and should not be regarded as a limitation of this disclosure.

[0124] In specific implementation, the display device provided in the embodiments of this disclosure may be a full-screen display device or a flexible display device, etc., and is not limited thereto.

[0125] In specific implementations, the display device provided in this disclosure embodiment can be a full-screen mobile phone as shown in FIG20. Of course, the display device provided in this disclosure embodiment can also be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure. This display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this disclosure embodiment. In other words, the display device provided in this disclosure embodiment can include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0126] This disclosure provides an array substrate, display panel, and display device. By providing a first notch on a metal line and overlapping a portion of a first via for connecting a first transparent electrode layer and the metal line with the first notch and the other portion with the metal line, the first via is formed on the metal line in a semi-overlapping manner. This creates multiple stepped buffer structures at the first notch. During PI liquid coating, the PI liquid flows through the first via because the terrain at the location of the first via is relatively flat, which guides the flow of the PI liquid, improves PI fluidity, and facilitates the diffusion of the PI liquid toward the first via. This prevents the PI liquid from accumulating at the first via, improves the problem of uneven PI diffusion, avoids pixel display inhomogeneity (mura), and improves the product yield of the array substrate.

[0127] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0128] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate having a plurality of sub-pixels arranged in an array, wherein, The array substrate includes: Substrate; A first metal layer is located on one side of the substrate. The first metal layer includes metal lines located between adjacent sub-pixels. The extending direction of the metal lines is a first direction, and the direction intersecting the first direction is a second direction. A first insulating layer is located on the side of the first metal layer that faces away from the substrate. A first transparent electrode layer is located on the side of the first insulating layer facing away from the substrate. The first transparent electrode layer includes a first transparent electrode located in each sub-pixel and includes a first connection portion and a second connection portion. Two adjacent first transparent electrodes arranged along the second direction are electrically connected through the first connection portion, and two adjacent first transparent electrodes arranged along the first direction are electrically connected through the second connection portion. The second connection portion is electrically connected to the metal line through a first via penetrating the first insulating layer. The metal line has a first notch corresponding to the position of the first via, and the orthographic projection of the first notch on the substrate covers part of the orthographic projection of the first via on the substrate.

2. The array substrate as claimed in claim 1, wherein, The metal wire includes a first portion corresponding to the first via location and a second portion corresponding to a location other than the first via location. The width of the first portion along the second direction is greater than the width of the second portion along the second direction, and the first portion has the first notch.

3. The array substrate as described in claim 2, wherein, The area of ​​the first gap is less than 1 / 4 of the sum of the areas of the first part and the first gap.

4. The array substrate as claimed in claim 3, wherein, The inner wall of the first notch has a polygonal projection on the substrate.

5. The array substrate as claimed in claim 3, wherein, The inner wall of the first notch has an arc shape when projected onto the substrate.

6. The array substrate according to any one of claims 2-5, wherein, The first via is divided into four first sub-vias along the first direction and the second direction, and the orthogonal projection of the first notch on the substrate covers at least a portion of the orthogonal projection of one of the first sub-vias on the substrate.

7. The array substrate as claimed in claim 6, wherein, The first portion also has a second notch, the orthographic projection of which on the substrate at least covers the orthographic projection of a portion of another first sub-via on the substrate.

8. The array substrate as claimed in claim 7, wherein, The first gap and the second gap are positioned opposite each other.

9. The array substrate as claimed in claim 8, wherein, The first part has a center point, and the first gap and the second gap are centrally symmetrical about the center point.

10. The array substrate as claimed in claim 7, wherein, The first gap and the second gap are arranged adjacent to each other.

11. The array substrate as claimed in claim 10, wherein, The metal wire has a center line extending along the first direction, and the first gap and the second gap are symmetrically arranged about the center line.

12. The array substrate according to any one of claims 7-11, wherein, The area of ​​the second gap is the same as the area of ​​the first gap.

13. The array substrate according to any one of claims 2-12, wherein, It also includes a second metal layer located between the substrate and the first metal layer. The second metal layer includes a plurality of gate lines extending along the second direction and arranged along the first direction. The first metal layer also includes a plurality of data lines extending along the first direction and arranged along the second direction. The data lines and the metal lines are alternately disposed between the sub-pixels in adjacent columns. The multiple gate lines and the multiple data lines intersect to define the multiple sub-pixels. The sub-pixels in the same row have different colors, while the sub-pixels in the same column have the same color. Each row of sub-pixels is electrically connected to two corresponding gate lines.

14. The array substrate as claimed in claim 13, wherein, The two gate lines electrically connected to the sub-pixels in the same row are located on both sides of the sub-pixel, and there are two gate lines between two adjacent rows of sub-pixels; The orthographic projection of the first via on the substrate is located between the orthographic projections of the two gate lines between adjacent sub-pixels on the substrate.

15. The array substrate as claimed in claim 14, wherein, The orthographic projection of the first portion on the substrate lies between the orthographic projections of the two gate lines between adjacent sub-pixels on the substrate.

16. The array substrate as claimed in claim 15, wherein, The width of the area of ​​the second part that overlaps with the gate line is greater than the width of the area of ​​the second part that does not overlap with the gate line.

17. The array substrate according to any one of claims 13-16, wherein, The two columns of the first transparent electrodes and the second connection portion between two adjacent data lines are an integral structure.

18. The array substrate according to any one of claims 1-17, wherein, The first transparent electrode layer further includes a third connection portion, and two adjacent second connection portions along the second direction are electrically connected through the third connection portion.

19. The array substrate according to any one of claims 13-17, wherein, Also includes: A second transparent electrode layer located between the second metal layer and the substrate, a second insulating layer located between the second metal layer and the first metal layer, and an active layer located between the second insulating layer and the first metal layer; wherein, The first metal layer further includes a source and a drain, the second transparent electrode layer includes a second transparent electrode located in each of the sub-pixels, the first transparent electrode layer further includes a fourth connection portion, the fourth connection portion is electrically connected to the drain and the second transparent electrode respectively through a second via penetrating the first insulating layer and the second insulating layer, and the data line is electrically connected to the source.

20. The array substrate as claimed in claim 19, wherein, The active layer includes a channel portion that is electrically connected to the source and the drain, and a dummy portion located between the metal wire and the second insulating layer. The pattern of the dummy portion is the same as that of the metal wire, and the dummy portion has a third notch corresponding to the position of the first notch.

21. The array substrate as claimed in claim 19, wherein, The first transparent electrode is a common electrode, and the first transparent electrode includes multiple slits; The second transparent electrode is a pixel electrode, and the second transparent electrode is a planar electrode.

22. A display panel, wherein, include: The array substrate as described in any one of claims 1-21, the opposing substrate disposed opposite to the array substrate, and the liquid crystal layer located between the array substrate and the opposing substrate.

23. A display device, wherein, Includes the display panel as described in claim 22.

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