Power semiconductor module and method for creating a current bypass in the power semiconductor module

Abstract

A power semiconductor module (100), comprising a to p plate (10) extending along an extension area (A1), having a first main surface (11) and a second main surface (12) opposite the first main surface (11) in a stacking direction (S1 ). The power semiconductor module (100) further comprises a substrate (20), having a third main surface (21) and a fourth main surface (22) opposite the third main surface ( 21) in the stacking direction (S1), wherein the second main surface (12) faces the third main surface (21). A chip (30) with at least one top side contact (31), arranged on the third ma in surface (21), wherein the at least one top side contact (31 ) faces the second main surface (12). The power semiconductor module (100) further comprises a pressure contact (50) arranged in the stacking direction (S1) between the top plate ( 10) and the chip (30), wherein the at least one top side contact (31) of the chip (30) is electrically connected to the t op plate (10) by the pressure contact (50), and wherein the pressure contact (50) comprises a contact layer (60) configured to melt due to elevated temperatures generated by high current in case of a short-circuit situation, and to flow a cross the chip (30), such that a current bypass over the chip (30) to the substrate (20) is created. Meanwhile the pressure contact (50) maintains a pressure on the chip (30) due to a spring force of the pressure contact (50) and maintains an electrical connection to the chip (30).

Description

[0001] P2024,0627 WO N / P240029WO01 August27,2025 -1 - Description POWER SEMICONDUCTOR MODULE AND METHOD FOR CREATIANCGURRENT BYPASS IN THE POWER SEMICONDUCTOR MODULEThe present disclosure relates to a power semicondu ctormodule. The present disclosure further relates to a methodfor creating a current bypass in the power semicond uctormodule.Power semiconductor modules with multiple individua lswitching elementsare a widelyused type ofpowersemiconductor module, for example in high-voltage d irectcurrent (HVDC) applications, where multiple power m odules arearranged in a stack providing a serial connection o f thepower modules. On a submodule of a power semiconduc tor modulewith pressure contactsmultiple chipsare soldered to abaseplate and are individually connected with a top plate bythe pressure contacts.It is an object to provide a power semiconductor mo dule withan enhanced short-circuitcapability.This object is solved by the features of the indepe ndentclaims. Advantageous embodiments are indicated in t hedependentclaims.Embodiments of the disclosure, for instance as clai med in theindependentclaims,addressthe above shortcomings in the artin whole or in part. Further embodiments of the pow ersemiconductor module and of the method for creating a currentbypass in the power semiconductor module are subjec t matterofthe furtherclaims. P2024,0627 WO N / P240029WO01 August27,2025 -2 -There is provided a power semiconductor module. The powersemiconductor module comprises a top plate extendin g along anextension area. The extension area has a first main surfaceand a second main surface opposite the first main s urface ina stacking direction. The power semiconductor modul e furthercomprises a substrate. The substrate has a third ma in surfaceand a fourth main surface.The fourth main surface isopposite the third main surface in the stacking dir ection.The second main surface faces the third main surfac e. Thesubstrate may be a simple metal base plate , an insulatedmetal substrate, comprising a metal plate, an isola tingsheet, and a circuit metallization, or a ceramic su bstrateconsisting of an isolating ceramic sheet with top a nd bottommetallization. A chip is arranged on the third main surface.The chip has at least one top side contact. The num ber of topside contacts is not limited to one and the chip ca n havemore than one top side contact. The at least one to p sidecontactfacesthe second main surface.A pressure contact is arranged in the stacking dire ctionbetween the top plate and the chip. The at least on e top sidecontact of the chip is electrically connected to th e topplate bythe pressure contact.The pressure contact comprises a contact layer, whi ch isconfigured to melt in case of a short-circuit situa tion, inparticular due to elevated temperatures generated b y a highcurrentthrough the powersemiconductormodule,in particulara terminal, and in particular the chip. The materia l of thecontactlayerflowsin itsmolten state acrossthe chip,creating a current bypass over the chip to the subs trate. P2024,0627 WO N / P240029WO01 August27,2025 -3 -In a short-circuit situation accompanied by high te mperaturegeneration, the material of the contact layer is me lting andflowing down towardsthe chip.The materialofthe contactlayer provides a conductive coating of the chip andconsequently an electrical short or bypass across t he chipbetween the pressure contact and the substrate, e.g .baseplate. In this manner a low-Ohmic electrical co nnectionis created between a terminal of the pressure conta ct and thesubstrate.Thus,a powersemiconductormodule with asignificantly enhanced current rating in normal ope ration anda significantly enhanced short-circuit capability o f up to5,000 A isprovided.The additional body of the conductive material of t he contactlayer also acts as a heat buffer, which prevents th e pressurecontact from melting, until the current bypass over the chipis formed. This enhances the endurance of the powersemiconductor module in the short-circuit situation .In the meantime, the pressure contact maintains a p ressure onthe chip due to a spring force of the pressure cont act. Dueto the exerted pressure, the pressure contact maint ains anelectrical connection to the chip, both in normal o peration,i.e., prior to melting of the material of the conta ct layer,and in the short-circuit situation, i.e., after mel ting ofthe materialofthe contactlayer.The pressure contact comprises for example a pressp in bodyand a spring. The presspin body has a first thickne ss in thestacking direction and is electrically connected to the chip.The spring is configured to apply pressure on the p resspinbody in the stacking direction towards the chip. Op tionally,the spring carries the current. The spring is elect rically P2024,0627 WO N / P240029WO01 August27,2025 -4 -contacted to the top plate. The presspin body is fo r exampleformed as a kind of a stamp, which is pressed again st thechip surface. The presspin body has for example a f irst thickportion,e.g.,forproviding an electricalcontact with thechip or contact layer, and a second thinner pin-sha pedportion, where the spring is arranged in a surround ingmanner. The structure of the pressure contact is no t limitedto the described example. Other setups of the press urecontactare also possible.According to an embodiment, the pressure contact co mprisesthe presspin body with the first thickness in the s tackingdirection. The first thickness is for example the l ength ofthe presspin body which extends in the stacking dir ection.The presspin bodyiselectricallyconnected to the chip.Thepressure contact further comprises a bracket. The b racketcomprises for example two leaves mainly extending i n thestacking direction. The bracket is arranged besides thespring and / orpresspin bodyin the extension area. Thebracket is configured to be used as current conduct or, whichiselectricallyconnected to the presspin bodyand the topplate. The pressure contact further comprises the s pring forapplying pressure on the presspin body in the stack ingdirection towardsthe chip.The pressure contact may incorporate more parts lik e washersor spacers and is not limited to the mentioned part s.According to an embodiment a first part of the cont act layeris arranged between the chip and the presspin body.The contact layer is for example arranged in the cu rrentpath, e.g. between the chip surface and the presspi n body. In P2024,0627 WO N / P240029WO01 August27,2025 -5 -case of a short-circuit, the body of the low meltin g materialof the contact layer is molten. Due to the strong s pringforce of 700-800 N, the molten material is squeezed out ofthe terminal structure and flows over the chip surf ace andthe sidewalls of the chip forming a current path. T hesidewalls of the chip are extending in the stackingdirection.According to a further embodiment the value of a se condthickness of the first part of the contact layer in thestacking direction is in the range between 0.5 mm a nd 15 mm.The second thickness of the contact layer is for ex ample thelength of the contact layer, which extends in the s tackingdirection. The contact layer needs sufficient mater ial, whichcan be melted due to the high temperatures generate d by thehigh currentsduring a short-circuitsituation.On the otherhand, due to space saving requirements, height limi tationsand / or a maximum spring path of the pressure contac t thesecond thicknessshould notbe too large.Preferably, the dimensions of the contact layer alo ng theextension area are equal to the dimensions of the p resspinbody along the extension area. Alternatively, the d imensionsof the contact layer along the extension area are l arger thanthe dimensions of the presspin body along the exten sion area,such that, for example, the contact layer may protr ude fromthe perimeter of the presspin body or even from the perimeterof the chip. Alternatively, the dimensions of the c ontactlayer along the extension area are smaller than thedimensions of the presspin body along the extension area. P2024,0627 WO N / P240029WO01 August27,2025 -6 - The shape ofthe contactlayer,when viewed in the stackingdirection can be circular or rectangular. Other sha pes mayalso be possible. The contact layer has for example a shape,when viewed in the stacking direction, which corres ponds tothe cross-sectional shape of the presspin body, whe n viewedin the stacking direction. Alternatively, the conta ct layerhas for example a shape, when viewed in the stackin gdirection,which correspondsto the shape orouter dimensionsof the chip, when viewed in the stacking direction.According to a further embodiment, alternatively or inaddition, a second part of the contact layer is arr angedalong the extension area in a circumferential manne r aroundthe presspin body. The term “second part” is merely used tofacilitate reference to a specific part of the cont act layerand doesnotnecessarilyrequire the presence ofa firstpart ofthe contactlayer.The contact layer is for example arranged around th e presspinbody, e.g. covering an outer surface, such as a cyl indricalsurface of the presspin. In other words, the contac t layerextends along the extension area beyond the perimet er of thepresspin body and / or outside the perimeter of the c hip. Forexample, a part of the contact layer may be arrange d in anouter part of the at least one top side contact and / or chipnot covered by the presspin body, i.e., be laterall y orhorizontally offset with respect to the center of t hepresspin body. This part may also extend in the lat eraldirection beyond the perimeter of the chip, i.e., b eoverhanging. For example, said part may extend beyo nd thelateral dimensions of the top side contact. Optiona lly, afurther, potentially thinner part of the contact la yer may bearranged between the chip and the presspin bodyas described P2024,0627 WO N / P240029WO01 August27,2025 -7 -above with respect to the first part. These arrange ments useadditional space along the extension area and may a llow tosave space in the stacking direction for a more com pactstructure.Additionally,theygive the opportunity to arrangemore material if desired to guarantee the electrica l short.The second part of the contact layer has for exampl e anoverhanging portion with respectto the chip.When viewed inthe stacking direction the contact layer extends fo r examplebeyond the boundaries of the chip. Alternatively, t o savemore space along the extension area, the second par t of thecontact layer extends along the extension area with in theboundariesofthe chip when viewed in the stacking direction.Depending on the needed amount of material of the c ontactlayer, the dimensions of the second part of the con tact layeralong the extension area and in the stacking direct ion can bevaried, while meeting space saving requirements, an d / ormaintaining desired distances to neighbored termina ls and / orto sidewallsofsubmodule.According to a further embodiment the value of a th irdthickness of the second part of the contact layer i n thestacking direction issmallerthan orequalto the value of the firstthickness.The third thicknesses of the contact layer may be s imilar tothe first thickness of the presspin body. The conta ct layerextends for example of up to 20 mm along the extens ion area.Thisfacilitatesthe use ofa largeramountoflow meltingmaterial from the contact layer compared with an ar rangementin the current path. In case of a short-circuit sit uation,the low melting conductive materialofthe contact layermelts and flows down to the chip, such that the con ductivematerial is spreading over the chip surface and the sidewalls P2024,0627 WO N / P240029WO01 August27,2025 -8 - ofthe chip forming an electricalshortorcurrent bypass.Additionally, the comparably high amount of materia l isworking like a phase-change heat sink, which preven ts thepresspin body from melting until a current bypass o ver thechip isformed.Alternatively, the third thickness is larger than t he firstthickness. For example, in case that the contact la yer is U-shaped, like a cup. The sidewalls of the U-shape ex tend inthe stacking direction and the bottom of the U-shap e extendsalong the extension area.According to a further embodiment the melting point of thecontact layer is lower than the melting point of an y part ofthe pressure contact. The melting point of the cont act layerislowerthan the melting pointofanypartofthe pressure contact.The melting pointofthe contactlayeris lowerthanthe melting point of the presspin body, the spring, thebracketoranyotherpartofthe pressure contact.According to a further embodiment the melting point of thecontact layer is lower than the melting point of th e chip.According to a further embodiment the melting point of thecontact layer is above the maximum process temperat ure, towhich the pressure contact is exposed during an ass emblyprocess. The melting point of the contact layer dep ends onthe temperature of the assembly process to which th e pressurecontact is exposed, i.e., while the contact layer i s present.The pressure contact is arranged after chip solderi ng, whichis done at a comparably high melting temperature. T hus, it isavoided to expose the contactlayerto unnecessary high temperaturesduring assembly. P2024,0627 WO N / P240029WO01 August27,2025 -9 -According to a further embodiment the power semicon ductormodule comprises a confinement structure. The confi nementstructure is arranged on the third surface. The con finementstructure extends in the stacking direction. The co nfinementstructure surrounds the chip at least partially alo ng theextension area. A currentbypassprovided bythe molten conductive materialof the contact layer is formed across the top surfa ce and oneor more sidewalls of the chip in a short-circuit si tuation.The confinement structure avoids that the molten ma terial isnot only flowing over the chip, but also further sp readingover the third main surface of the substrate surfac e. Theconfinement structure facilitates that there is a s ufficientamount of material from the contact layer remaining on thechip to form a current bypass, which avoids unrelia ble short-circuitconditions.The confinement structure may be realized by a fram e, bondwires, or by a coating with a material, which is no t wettedby the molten conductive material of the contact la yer.Alternatively, the confinement structure can be a r ecess, ora machined region,forexample a laserirradiation ofa metal surface providesa solderstop.According to a further embodiment the power semicon ductormodule has a short-circuit capability for electrica l currentsofup to 5000 A.According to a further embodiment the contact layer comprisesmetal,metalalloys,orconductive polymers. P2024,0627 WO N / P240029WO01 August27,2025 -10 - The materialofthe contactlayerisforexample a metal,a metalalloy,oranotherconductive materiallike a conductivepolymer. The material of the contact layer is for e xample,aluminum oraluminum alloyorlead.Alternatively, thematerial of the contact layer is solder or a brazin gmaterial.According to a further embodiment the power semicon ductormodule comprises a preform. The preform is arranged betweenthe pressure contactand the chip.The materialof thepreform is, for example, aluminum or molybdenum. In thisembodiment, the contact layer may have, for example , a shape,when viewed in the stacking direction, which corres ponds tothe shape orouterdimensionsofthe preform.There is also provided a method for creating a curr ent bypassin the power semiconductor module. The method compr ises thesteps of melting the contact layer due to a short-c ircuitsituation, for example due to elevated temperatures generatedby a high current in the short-circuit situation, a ndexerting a gravitational force in the stacking dire ctiontowards the chip on the molten contact layer. Conse quently,the molten contact layer flows over the chip. Thus, a currentbypass over the chip to the substrate is created wi th themolten contactlayer.According to a further embodiment the method for cr eating acurrent bypass in the power semiconductor module co mprisesthe steps of exerting with the pressure contact a p ressure inthe stacking direction towards the chip. Melting th e contactlayer due to a short-circuit situation, for example due toelevated temperatures generated by a high current i n the P2024,0627 WO N / P240029WO01 August27,2025 -11 -short-circuit situation. Then, squeezing the contac t layer ina molten state out due to the exerted pressure. Con sequently,the molten contact layer flows over the chip. Thus, a currentbypass over the chip to the substrate is created wi th themolten contact layer. Meanwhile, the pressure on th e chip ismaintained due to a spring force of the pressure co ntact. Andan electrical connection between the pressure conta ct and thechip ismaintained.The present disclosure comprises several aspects of a powersemiconductor module and of a method for creating a currentbypass in the power semiconductor module on the bas is oftheir embodiments and examples. Every feature descr ibed withrespect to one of the aspects is also disclosed her ein withrespect to the other aspect, even if the respective featureis not explicitly mentioned in the context of the s pecificaspect. For example, the method described in this d isclosureis directed to a method for creating a current bypa ss in apower semiconductor module. Thus, features and adva ntagesdescribed in connection with the power semiconducto r modulecan be used forthe method,and vice versa.While the disclosure is amenable to various modific ations andalternative forms, specifics thereof are shown by w ay ofexample in the figures and will be described in det ail. Itshould be understood, however, that the intention i s not tolimit the disclosure to the particular described em bodimentsand examples.On the contrary,the intention isto coverallmodifications, equivalents, and alternatives fallin g withinthe scope of the disclosure defined by the appended claims.The accompanying figuresare included to provide a furtherunderstanding. In the figures, elements of the same structure P2024,0627 WO N / P240029WO01 August27,2025 -12 - and / orfunctionalitymaybe referenced bythe same reference signs.Itisto be understood thatthe embodiments shown inthe figures are illustrative representations and ar e notnecessarilydrawn to scale. Figure 1 to 2 schematiccross-sectionalviewsofa power semiconductormodule, Figure 3 to 6 schematiccross-sectionalviewsofa power semiconductormodule according to embodiments, Figure 7 to 8 schematiccross-sectionalviewsofa power semiconductormodule according to embodiments with the contactlayerin a melted state,Figure 9 to 12schematic cross-sectional views of a powersemiconductormodule according to embodiments. Figure 1 showsa schematiccross-sectionalview of a powersemiconductor module 100. The power semiconductor m odule 100comprisesa top plate 10.The top plate 10 extends along anextension area A1. The top plate 10 has a first mai n surface11 and a second main surface 12. The second main su rface 12is opposite the first main surface 11 in (or along) astacking direction S1, which is typically perpendic ular tothe main surfaces 11 and 12 of the extension area A 1. Thepowersemiconductormodule 100 furthercomprisesa substrate20. The substrate 20 has a third main surface 21 an d a fourthmain surface 22. The fourth main surface 22 is oppo site thethird main surface 21 in the stacking direction S1. Thesecond main surface 12 faces the third main surface 21. Achip 30 is arranged on the third main surface 21. A pressurecontact 50 is arranged in the stacking direction S1 between P2024,0627 WO N / P240029WO01 August27,2025 -13 - the top plate 10 and the chip 30.In figure 1 four chips30 and fourpressure contacts50 are shown.The powersemiconductor module 100 is not limited to these nu mbers. Thepower semiconductor module 100 can comprise less th an four ormore than four chips 30 and pressure contacts 50. E ach of thechips 30 is electrically connected to the top plate 10 by thecorresponding pressure contact50. Figure 2 showsa schematiccross-sectionalview of the powersemiconductor module 100 of a further embodiment. T he powersemiconductor module 100 differs from the power sem iconductormodule 100 shown in figure 1 in that the power semi conductormodule 100 comprises a preform 40. The preform 40 i s arrangedbetween the pressure contact50 and the chip 30. Figure 3 showsa schematiccross-sectionalview of the powersemiconductor module 100 of an embodiment in a more detailedview.The pressure contact50 comprisesa presspin body51with a first thickness d1 in the stacking direction S1. Thepresspin body 51 is electrically connected to the c hip 30.The pressure contact 50 further comprises a bracket 52 usedas current conductor. The bracket 52 is electricall yconnected to the presspin body 51 and the top plate 10. Thepressure contact50 furthercomprisesa spring 53. The spring 53 appliespressure on the presspin body51 in the stacking direction S1 towardsthe chip 30.The pressure contact 50 comprises a contact layer 6 0. Thecontact layer 60 is arranged between the chip 30 an d thepresspin body 51. The contact layer 60 is configure d to meltdue to elevated temperatures generated by high curr ent incase of a short-circuit situation. Thus, the materi al of thecontact layer 60 is configured to flow across the c hip 30 P2024,0627 WO N / P240029WO01 August27,2025 -14 - towardsthe third main surface 21 ofthe substrate 20,suchthat a current bypass over the chip 30 to the subst rate 20 iscreated. Alternatively, at least the contact area o n top ofthe high-ohmic chip 30 is significantly increased b y themolten materialofthe contactlayer60,such that theresistance provided by the chip is at least reduced .Meanwhile, the pressure contact 50 maintains a pres sure onthe chip 30 due to a spring force of the pressure c ontact 50and maintainsan electricalconnection to the chip 30.The spring 53 providesthe necessaryspring force.The chip 30 has at least one top side contact 31. T he topside contact 31 faces the second main surface 12. T he topside contact 31 of the chip 30 is electrically conn ected tothe top plate 10 by the pressure contact 50. Sidewa lls of the32 extend in the stacking direction S1.The contact layer 60 has a second thickness d2 in t hestacking direction S1 in a non-melted state. The va lue of thesecond thickness d2 is in the range between 5 mm an d 20 mm.Figure 4 showsa schematiccross-sectionalview of the powersemiconductor module 100 according to a further emb odiment.The power semiconductor module 100 differs from the powersemiconductormodule 100 shown in figure 3 in that the power semiconductormodule 100 comprisesthe preform 40. Thepreform 40 is arranged between the contact layer 60 and thechip 30. The preform 40 isforexample a metalpreform,for example amolybdenum preform, which is arranged on the top si de contact31 of the chip 30. The preform 40 is in contact wit h thepresspin body 51. It may serve, for example, for st ress P2024,0627 WO N / P240029WO01 August27,2025 -15 -compensation between the chip 30 and the presspin b ody 51and / or to compensate a possible tilt of the presspi n body 51.In case of fail, a high temperature is generated by theshort-circuit current in the affected chip 30 and t erminal.Under certain conditions and for certain materials, thepreform 40 mayform a eutecticalloytogetherwith the chipmaterial, such that the chip 30 is getting conducti ve. Underdifferentcondition orfordifferentmaterials,no eutecticalloy is formed. This is not limited by the disclos ure,provided thatthe materialofthe contactlayer60 issufficiently heated in a short-circuit situation to melt. Thechip 30 may be, for example, a silicon-based chip 3 0.Figure 5 showsa schematiccross-sectionalview of the powersemiconductor module 100. The contact layer 60 is a rrangedalong the extension area A1 in a circumferential ma nneraround the presspin body 51. The contact layer 60 h as a thirdthickness d3 in the stacking direction S1 in a non- meltedstate. The value of the third thickness d3 is small er than orequal to the value of the first thickness d1. For e xample,the value ofthe third thicknessd3 maybe 5 to 20 mm.Moreover, the contact layer 60 may extend horizonta lly, i.e.,along the extension area A1, up to a given radius o r wallthickness.Forexample,the contactlayermayhave the shapeof a hollow cylinder (i.e., a cylindrical shell) wi th a(horizontal) wall thickness of up to 15 mm. This ar rangementofthe contactlayer60 usesavailable space along theextension area A1, e.g., space available in a housi ng frameorto a neighboring contact,and allowsto arrange morematerial in the contact layer compared with the pre viouslydescribed embodiment. It may also allow to save spa ce in thestacking direction S1 fora more compactstructure and / orto correspond to a given heightlimitation. P2024,0627 WO N / P240029WO01 August27,2025 -16 -The contact layer 60 extends along the extension ar ea A1within the boundaries of the chip 30 when viewed in thestacking direction S1 to allow to arrange more mate rial inthe contact layer. Depending on the needed amount o f materialof the contact layer 60, the dimensions of the cont act layer60 along the extension area A1 and in the stacking directionS1 can be varied, while meeting space saving requir ements.Alternatively, the contact layer 60 has for example anoverhanging portion with respect to the chip 30. Wh en viewedin the stacking direction S1 the contact layer 60 e xtends forexample beyond the boundariesofthe chip 30. Figure 6 showsa schematiccross-sectionalview of a furtherembodiment of the power semiconductor module 100. T he powersemiconductor module 100 differs from the power sem iconductormodule 100 shown in figure 5 in that the power semi conductormodule 100 comprisesthe preform 40. Figure 7 showsa schematiccross-sectionalview of the powersemiconductor module 100 according to figures 3 and 5 with amolten contact layer 60. The material of the contac t layer 60flows in its molten state across the chip 30, creat ing acurrent bypass over the chip 30 to the substrate 20 . In theembodiment shown in Figure 3, due to the strong spr ing forceof the spring 53, the molten material of the contac t layer 60issqueezed outofthe terminalstructure.In bothembodiments, the molten material of the contact lay er 60flows over the chip 30 surface and the sidewalls of the chip32 forming a current path, for example due to gravi tationalforces.In case ofthe embodimentshown in Fig.3, thismayalso be achieved, at least in part, by squeezing th e moltenmaterial of the contact layer 60 out of the termina l P2024,0627 WO N / P240029WO01 August27,2025 -17 -structure and guiding the molten material in a suit able way,such as a hollow channel formed in the power semico nductormodule. Figure 8 showsa schematiccross-sectionalview of the powersemiconductor module 100 with an additional preform 40according to figures4 and 6 with a molten contact layer60.The material of the contact layer 60 flows in its m oltenstate across the preform 40 and the chip 30, creati ng acurrent bypass over the chip 30 to the substrate 20 .Figure 9 showsa schematiccross-sectionalview of the powersemiconductor module 100 according to a further emb odiment.The power semiconductor module 100 comprises a conf inementstructure 70.The confinementstructure 70 extends in the stacking direction S1 and surroundsthe chip 30 at leastpartially along the extension area A1. The confinem entstructure 70 is mainly arranged on the third surfac e 21 ofthe substrate 20.The confinementstructure 70 may berealized by a frame, bondwires, or by a coating wit h amaterial, which is not wetted by the molten conduct ivematerial.Alternatively,the confinementstructure 70 can bea recess, or a machined region, for example a laserirradiation of a metal surface provides a solder st op.Figure 10 shows a schematic cross-sectional view of the powersemiconductor module 100 according to a further emb odiment.The power semiconductor module 100 differs from the powersemiconductormodule 100 shown in figure 9 in that the power semiconductormodule 100 comprisesthe preform 40.Figure 11 shows a schematic cross-sectional view of the powersemiconductor module 100 of a further embodiment. T he contact P2024,0627 WO N / P240029WO01 August27,2025 -18 -layer 60 has a U-shaped cross section, in which the presspinbody 51 is embodied. That is to say, the contact la yer 60comprises a first part arranged between the presspi n body 51and the top surface contact31,asdescribed above withrespect to Figures 3 and 4, and a second part surro unding thepresspin body 51, as described above with respect t o Figures5 and 6.In the described embodiment, the two parts of the c ontactlayer 60 effectively form a cup-like structure, wit h acylindrical sidewall 61 connected by a circular bot tom 62.The sidewall 61 extend vertically in the stacking d irectionS1, and the bottom 62 extends along the extension a rea A1. Infigure 11, the third thickness d3, i.e. a height of thesidewall 61, can be larger, equal or smaller than t he firstthickness d1. For example, the sidewall(s) 61 of th e U-shapedcontact layer 60 extend in the stacking direction S 1 for 5 to20 mm.The sidewall(s)61 maybe up to 15 mm thick in thehorizontal direction. The thickness of the bottom 6 2 in thestacking direction S1, may be, for example, up to 1 5 mm. Itmay correspond to the thicknessofthe sidewall(s) 61 in the horizontaldirection.Figure 12 shows a schematic cross-sectional view of the powersemiconductor module 100 of a further embodiment. T he powersemiconductor module 100 differs from the power sem iconductormodule 100 shown in figure 11 in that the power sem iconductormodule 100 comprisesthe preform 40.The embodiments shown in the Figures 1 to 12 as sta tedrepresent exemplary embodiments of the power semico nductormodule 100; therefore, they do not constitute a com plete listof all embodiments according to the power semicondu ctor P2024,0627 WO N / P240029WO01 August27,2025 -19 -module 100. Actual arrangements and methods may var y from theembodiments shown in terms of arrangements, devices andmethodsforexample.

[0002] P2024,0627 WO N / P240029WO01 August27,2025 -20 - Reference Signs 100 powersemiconductormodule 10 top plate 11 firstmain surface 12 second main surface 20 substrate 21 third main surface 22 second main surface 30 chip 31 top surface contacts 32 sidewallsofchip 40 preform 50 pressure contact 51 presspin body 52 bracket 53 spring 60 contactlayer 61 sidewall 62 bottom 70 confinementstructure S1 stacking direction A1 extension area

Claims

P2024,0627 WO N / P240029WO01 August27,2025 -21 - Claims 1.Powersemiconductormodule (100),comprising- a top plate (10) extending along an extension area (A1),having a firstmain surface (11)and a second main surface (12) opposite the first main surface (11) in a stac kingdirection (S1),- a substrate (20), having a third main surface (21) and afourth main surface (22) opposite the third main su rface(21) in the stacking direction (S1), wherein the se condmain surface (12) faces the third main surface (21) ,- a chip (30) with at least one top side contact (31) ,arranged on the third main surface (21), wherein th e atleast one top side contact (31) faces the second ma insurface (12),- a pressure contact (50) arranged in the stacking di rection(S1)between the top plate (10)and the chip (30), wherein the atleastone top side contact(31)ofthe chip (30)is electrically connected to the top plate (10) by thepressure contact(50),and wherein- the pressure contact (50) comprises a contact layer (60)configured to melt in case of a short-circuit situa tion,and to flow across the chip (30), such that a curre ntbypassoverthe chip (30)to the substrate (20)is created,while the pressure contact(50)maintains a pressure on the chip (30)due to a spring force of the pressure contact(50)and maintainsan electrical connection to the chip (30),and wherein- the pressure contact (50) comprises a presspin body (51)with a first thickness (d1) in the stacking directi on (S1)electrically connected to the chip (30), and a spri ng (53)forapplying pressure on the presspin body(51)in the stacking direction (S1) towards the chip (30), wher ein aP2024,0627 WO N / P240029WO01 August27,2025 -22 - second part of the contact layer (60) is arranged i n acircumferential manner around the presspin body (51 ).

2. Power semiconductor module (100) according to cl aim 1,wherein the pressure contact (50) further comprises a bracket(52) used as current conductor, which is electrical lyconnected to the presspin body (51) and the top pla te (10).

3. Power semiconductor module (100) according to cl aim 1 or2, wherein a first part of the contact layer (60) i s arrangedbetween the chip (30)and the presspin body(51).

4. Power semiconductor module (100) according to an y of thepreceding claims, wherein the value of a second thi ckness(d2) of the first part of the contact layer (60) in thestacking direction (S1) is in the range between 0.5 mm and 15mm.

5. Power semiconductor module (100) according to an y of thepreceding claims, wherein the value of a third thic kness (d3)of the second part of the contact layer (60) in the stackingdirection (S1) is smaller than or equal to the valu e of thefirstthickness(d1).

6. Power semiconductor module (100) according to an y of thepreceding claims,wherein the melting pointofthe contactlayer (60) is lower than the melting point of any p art of thepressure contact (50) and / or lower than the melting point ofthe chip (30).

7. Power semiconductor module (100) according to an y of thepreceding claims,wherein the melting pointofthe contactlayer (60) is above the maximum process temperature , to whichP2024,0627 WO N / P240029WO01 August27,2025 -23 -the pressure contact (50) is exposed during an asse mblyprocess.

8. Power semiconductor module (100) according to an y of thepreceding claims, comprising a confinement structur e (70)arranged on the third surface (21), wherein the con finementstructure (70) extends in the stacking direction (S 1), andsurrounds the chip (30) at least partially along th eextension area (A1).

9. Power semiconductor module (100) according to an y of thepreceding claims, wherein the power semiconductor m odule(100) has a short-circuit capability for electrical currentsofup to 5000 A.

10. Power semiconductor module (100) according to a ny of thepreceding claims, wherein the contact layer (60) co mprisesmetal,metalalloys,orconductive polymers.

11. Power semiconductor module (100) according to a ny of thepreceding claims, comprising a preform (40) arrange d betweenthe pressure contact(50)and the chip (30).

12. Method for creating a current bypass in the pow ersemiconductormodule (100)according to anyofthe preceding claims,comprising- melting the contact layer (60) due to a short-circu itsituation,- exerting a gravitational force in the stacking dire ction(S1) towards the chip (30) on the molten contact la yer(60), such that the molten contact layer (60) flows overthe chip (30),andP2024,0627 WO N / P240029WO01 August27,2025 -24 -- creating a current bypass over the chip (30) to thesubstrate (20)with the molten contactlayer(60).

13. Method for creating a current bypass in the pow ersemiconductormodule (100)according to anyofthe claims1 to 11,comprising- exerting with the pressure contact (50) a pressure in thestacking direction (S1)towardsthe chip (30),- melting the contact layer (60) due to a short-circu itsituation,- squeezing out the contact layer (60) in a molten st ate,such thatthe molten contactlayer(60)flowsover the chip (30),and- creating a current bypass over the chip (30) to thesubstrate (20)with the molten contactlayer(60), while- maintaining the pressure on the chip (30) due to a springforce ofthe pressure contact(50),and- maintaining an electrical connection to the chip (3 0).

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