Semiconductor device

Abstract

Provided is a semiconductor device having a novel configuration. This semiconductor device includes: a state control unit; a register unit having a first storage circuit; and a cache unit having a second storage circuit. The first storage circuit includes a flip-flop circuit and a first data holding circuit. The second storage circuit includes an inverter loop circuit and a second data holding circuit. The first storage circuit has a function of holding, in the first data holding circuit, first data output by the flip-flop circuit, in response to a first signal supplied from the state control unit, and a function of outputting the first data held in the first data holding circuit to the flip-flop circuit in response to a second signal supplied from the state control unit. The second storage circuit has a function of holding, in the second data holding circuit, second data output by the inverter loop circuit, in response to the first signal, and a function of outputting the second data held in the second data holding circuit to the inverter loop circuit in response to the second signal.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] Technological development of a semiconductor device that can hold charge according to data by combining a transistor using an oxide semiconductor for a channel formation region (also called an OS transistor) and a transistor using silicon for a channel formation region (also called a Si transistor) is underway.

[0004] The semiconductor device can achieve low power consumption by power gating or the like by configuring the semiconductor device to save (also referred to as evacuation, storage, or backup) or load (also referred to as restoration, restoration, or recovery) a program or data held in a flip-flop or the like. For this reason, application of the semiconductor device to semiconductor devices such as CPUs (Central Processing Units) is progressing (see, for example, Patent Document 1).

[0005] In a semiconductor device such as a CPU, a series of processes (tasks) are executed by sequentially performing processes according to a program or data. When multiple tasks are executed, each task is divided into small processing units, and the processing units of each task are executed sequentially, making it appear as if multiple tasks are being executed simultaneously. To execute the processes, multiple register banks (sets of general-purpose registers) are prepared, and the register banks are switched corresponding to each task to execute the task.

[0006] Also, when a program transitions from its main routine to a subroutine, the register bank is switched before the subroutine is processed, and after the subroutine processing is completed, the register bank is switched back to the original register bank before the main routine is processed.

[0007] JP 2013-9297 A

[0008] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] In semiconductor devices such as CPUs, when register banks are insufficient to handle complex processing, data in registers corresponding to a suspended task must be temporarily written to external memory, and then, when the task is executed again, the data must be written back from the external memory to the register. In this case, a large amount of power is consumed writing and restoring data between the external memory and the register. While providing a large number of register banks reduces the frequency of access to the external memory and the register and reduces power consumption related to communication, it also increases the circuit layout area.

[0010] Furthermore, from the viewpoint of high-speed operation, CPU memory is mainly made of static random access memory (SRAM), which is used as cache memory, but the circuit scale of SRAM is large, which leads to an increase in the circuit layout area. Furthermore, when data for each task is stored in external memory, power consumption increases for communication between the external memory and SRAM.

[0011] An object of one embodiment of the present invention is to provide a novel semiconductor device or the like.An object of one embodiment of the present invention is to provide a semiconductor device or the like in which an increase in a circuit layout area is suppressed.An object of one embodiment of the present invention is to provide a semiconductor device or the like that is excellent in reducing power consumption.

[0012] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems.

[0013] (1) One embodiment of the present invention includes a state control unit, a register unit having a first memory circuit, and a cache unit having a second memory circuit. The first memory circuit includes a flip-flop circuit and a first data retention circuit. The second memory circuit includes an inverter loop circuit and a second data retention circuit. The flip-flop circuit includes a first transistor including silicon in a semiconductor layer in which a channel is formed. The first data retention circuit includes a second transistor including an oxide semiconductor in the semiconductor layer in which a channel is formed. The inverter loop circuit includes a third transistor including silicon in the semiconductor layer in which a channel is formed. The second data retention circuit includes a fourth transistor including an oxide semiconductor in the semiconductor layer in which a channel is formed. a first memory circuit having a function of holding, in one of the first data holding circuits, first data output by the flip-flop circuit in response to a first signal supplied from the state control unit, and a function of outputting, to the flip-flop circuit, the first data held in one of the first data holding circuits in response to a second signal supplied from the state control unit; and a second memory circuit having a function of holding, in one of the second data holding circuits, second data output by the inverter loop circuit in response to the first signal supplied from the state control unit, and a function of outputting, to the inverter loop circuit, the second data held in one of the second data holding circuits in response to a second signal supplied from the state control unit.

[0014] In addition, in (1), it is preferable that the flip-flop circuit and the first data holding circuit have an overlapping area.

[0015] In addition, in (1), it is preferable that the inverter loop circuit and the second data holding circuit have an overlapping region.

[0016] In the above (1), the oxide semiconductor included in one or both of the second transistor and the fourth transistor preferably contains indium.

[0017] (2) One embodiment of the present invention includes a state control unit, a register unit having a plurality of first memory circuits, and a cache unit having a plurality of second memory circuits, each of the plurality of first memory circuits including a flip-flop circuit and a plurality of first data retention circuits, and each of the plurality of second memory circuits including an inverter loop circuit and a plurality of second data retention circuits, the flip-flop circuit including a first transistor including silicon in a semiconductor layer in which a channel is formed, each of the plurality of first data retention circuits including a second transistor including a first oxide semiconductor in the semiconductor layer in which a channel is formed, the inverter loop circuit including a third transistor including silicon in the semiconductor layer in which a channel is formed, and each of the plurality of second data retention circuits including a second oxide semiconductor in the semiconductor layer in which a channel is formed. The semiconductor device has a fourth transistor including a semiconductor, and each of the plurality of first memory circuits has a function of holding first data output by the flip-flop circuit in one of the plurality of first data holding circuits in response to a first signal supplied from the state control unit, and a function of outputting the first data held in one of the plurality of first data holding circuits to the flip-flop circuit in response to a second signal supplied from the state control unit, and each of the plurality of second memory circuits has a function of holding second data output by the inverter loop circuit in one of the plurality of second data holding circuits in response to the first signal supplied from the state control unit, and a function of outputting the second data held in one of the plurality of second data holding circuits to the inverter loop circuit in response to a second signal supplied from the state control unit.

[0018] In addition, in (2), it is preferable that the flip-flop circuit and at least one of the plurality of first data retention circuits have an overlapping area.

[0019] In addition, in (2), it is preferable that the inverter loop circuit and at least one of the plurality of second data holding circuits have an overlapping region.

[0020] In the above (2), the oxide semiconductor included in one or both of the second transistor and the fourth transistor preferably contains indium.

[0021] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like in which an increase in the circuit layout area is suppressed can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like which is excellent in low power consumption can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be found by a person skilled in the art from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 2A and 2B are diagrams illustrating a configuration example of a semiconductor device. FIG. 3 is a diagram illustrating a configuration example of a semiconductor device. FIG. 4A is a diagram illustrating a configuration example of a semiconductor device. FIG. 4B is a timing chart illustrating an operation example of a semiconductor device. FIGS. 5A, 5B, 5C, 5D, and 5E are diagrams illustrating configuration examples of a semiconductor device. FIG. 6 is a timing chart illustrating an operation example of a semiconductor device. FIGS. 7A and 7B are diagrams illustrating an example of a configuration of a semiconductor device. FIG. 8 is a diagram illustrating an example of a configuration of a semiconductor device. FIG. 9 is a diagram illustrating an example of a configuration of a semiconductor device. FIGS. 10A, 10B, 10C, and 10D are timing charts illustrating an operation example of a semiconductor device. FIGS. 11A, 11B, 11C, and 11D are timing charts illustrating an operation example of a semiconductor device. FIGS. 12A, 12B, 12C, 12D, and 12E are diagrams illustrating configuration examples of a semiconductor device. FIG. 13 is a timing chart illustrating an operation example of a semiconductor device. 14A and 14B are diagrams illustrating a configuration example of a semiconductor device. FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. FIG. 16 is a diagram illustrating a configuration example of a semiconductor device. FIGS. 17A, 17B, 17C, and 17D are timing charts illustrating an operation example of a semiconductor device. FIGS. 18A, 18B, 18C, 18D, and 18E are diagrams illustrating a configuration example of a semiconductor device. FIG. 19 is a diagram illustrating a configuration example of a semiconductor device. FIGS. 20A, 20B, and 20C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 21A and 21B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 22A, 22B, 22C, 22D, 22E, and 22F are diagrams illustrating a configuration example of an electronic device. FIGS. 23A and 23B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 23C is a cross-sectional view illustrating an indium oxide film. 24A1, 24A2, 24A3, 24A4, 24A5, 24A6, 24A7 and 24B1, 24B2, 24B3, 24B4, 24B5, and 24B6 are circuit diagrams for explaining electrical connections.

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings.

[0026] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vg is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0027] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like.

[0028] Embodiment 1 In this embodiment, a structural example of a semiconductor device 100 of one embodiment of the present invention will be described.

[0029] Fig. 1A is a block diagram showing a semiconductor device 100. Fig. 1B is a perspective schematic diagram showing the layer structure of the semiconductor device 100.

[0030] In the drawings shown in FIGS. 1A and 1B, the elements constituting the semiconductor device 100 are shown separated from one another to make the arrangement of the elements easier to understand.

[0031] The semiconductor device 100 has a state control unit 101, a processor core 102, and a cache unit 113. The processor core 102 has a register unit 103 and an arithmetic unit 104. The register unit 103 has a plurality of register banks 105. The register bank 105 has a plurality of registers 106. The register 106 has a plurality of first storage circuits 110. The first storage circuit 110 has a scan flip-flop 120 and a first data retention circuit 131. The first data retention circuit 131 is provided on the scan flip-flop 120. Note that a set of the plurality of first data retention circuits 131 is also referred to as a first data retention circuit group 130. Therefore, it can also be said that the first data retention circuit group 130 has a plurality of first data retention circuits 131.

[0032] The cache unit 113 has a plurality of second memory circuits 114a. The second memory circuits 114a have an inverter loop circuit 115 and a second data retention circuit 141. The second data retention circuit 141 is provided on the inverter loop circuit 115. A set of the plurality of second data retention circuits 141 is also referred to as a second data retention circuit group 140. Therefore, it can also be said that the second data retention circuit group 140 has a plurality of second data retention circuits 141.

[0033] The inverter loop circuit 115 can function as a memory cell that constitutes an SRAM.

[0034] FIG. 2A is a diagram for explaining a configuration example of the first memory circuit 110 shown in FIG. 1A.

[0035] The first memory circuit 110 has a scan flip-flop 120 (volatile register). The scan flip-flop 120 has a selector 121 and a flip-flop circuit 122. The scan flip-flop 120 is connected to one or more first data retention circuits 131. FIG. 2A shows an example in which the scan flip-flop 120 is connected to k first data retention circuits 131 (k is a natural number equal to or greater than 1). The first memory circuit 110 also has a transistor 132.

[0036] The state control unit 101 shown in FIG. 1A is a circuit that outputs control signals for switching between and processing multiple tasks in response to interrupt signals (Interrupts) input from outside the semiconductor device 100, sleep signals generated by the processor core 102, and the like. The state control unit 101 may also be simply referred to as a circuit. The state control unit 101 generates a clock signal CLK and various signals (signal BK[0], signal BK[k:1], signal RE[k:1], signal SE) shown in FIG. 2A. The clock signal CLK and various signals are input to the processor core 102. The state control unit 101 may be configured to output a signal for controlling power gating of the processor core 102.

[0037] The signal BK[k:1] is a signal that controls saving of data held in the flip-flop circuit 122 in the scan flip-flop 120. By saving the data, the data held in the flip-flop circuit 122 is held in any one of the plurality of first data hold circuits 131 in the first data hold circuit group 130. Note that the signal BK[k:1] may also be expressed as the signals BK[1] to BK[k].

[0038] The signal RE[k:1] is a circuit that controls the loading of data held in any one of the plurality of first data hold circuits 131 in the first data hold circuit group 130. By loading the data, the data held in any one of the plurality of first data hold circuits 131 is written back to the flip-flop circuit 122 in the scan flip-flop 120. Note that the signal RE[k:1] may also be expressed as the signals RE[1] to RE[k].

[0039] The signal SE is a switching signal for the selector 121. The clock signal CLK is a signal for controlling the operation of the flip-flop circuit 122. The flip-flop circuit 122 has a function of holding input data when the clock signal CLK changes, for example, from low level to high level, and a function of outputting a signal corresponding to the held data.

[0040] 1A , the processor core 102 is a circuit for performing arithmetic processing in the arithmetic unit 104 in accordance with program data held in the register unit 103. The processor core 102 may also be referred to as a CPU core. The semiconductor device 100 may have a configuration in which there is one processor core 102 (single-core), or two or more processor cores 102 (multi-core such as dual-core or many-core).

[0041] 1A, the register unit 103 includes a plurality of register banks 105, which may be provided in a pipeline register, a register file, or the like. The register unit 103 may also be referred to as an L1 (level 1) cache memory. The register unit 103 has a function of temporarily storing frequently used data.

[0042] 1A, the arithmetic unit 104 has the function of performing various arithmetic processes such as arithmetic operations and logical operations based on the data stored in the register unit 103. The arithmetic unit 104 is also called an ALU (arithmetic logic unit). In addition to the register unit 103 and the arithmetic unit 104, the processor core 102 may also have circuits such as a program counter or a control circuit.

[0043] 1A , each of the multiple register banks 105 is assigned one of multiple tasks executed by processing according to a program. When the state control unit 101 controls switching between multiple tasks, the state control unit 101 switches to the register bank 105 corresponding to each task, thereby improving computational performance. The register 106 has a function of storing program data for executing tasks and data obtained by computational processing. The first memory circuit 110 corresponds to a 1-bit memory circuit constituting the register 106.

[0044] The first memory circuit 110 holds data input from terminal D or data input from terminal SD in a flip-flop circuit 122 within the scan flip-flop 120 in response to a clock signal CLK, and outputs the held data from a terminal Q. The data output from terminal Q is saved in one of a plurality of first data hold circuits 131 connected to the scan flip-flop 120 in response to a signal BK[k:1]. The data held in one of the plurality of first data hold circuits 131 is loaded into the flip-flop circuit 122 within the scan flip-flop 120 in response to a signal RE[k:1].

[0045] The selector 121 has a function of transmitting a signal from terminal D or terminal SD to the flip-flop circuit 122 in response to signal SE. Terminal D is a terminal that provides data input from outside the first memory circuit 110 to the scan flip-flop 120. Terminal SD is a terminal that provides data input from the first data hold circuit group 130 or scan test data input from terminal SD_IN to the scan flip-flop 120. The scan test data input from terminal SD_IN is provided via a transistor 132 that controls switching between a conductive state and a non-conductive state by signal BK[0].

[0046] 2A and other figures illustrate a D flip-flop as the flip-flop circuit 122, but one embodiment of the present invention is not limited to this. A flip-flop circuit provided in a standard circuit library can be applied to the flip-flop circuit 122. The flip-flop circuit 122 can hold 1-bit data. The flip-flop circuit 122 has a function of holding data supplied to an input terminal DF when the clock signal CLK changes from a potential "L" to a potential "H" or from a potential "H" to a potential "L" and a function of outputting the held data to a terminal Q via an output terminal QF.

[0047] The flip-flop circuit 122 included in the first memory circuit 110 may include, for example, Si transistors. The flip-flop circuit 122 may also include a silicon CMOS (Complementary Metal Oxide Semiconductor) circuit using Si transistors. The silicon CMOS circuit is a circuit formed on a silicon substrate, with a circuit structure that combines nMOSFETs and pMOSFETs.

[0048] For the Si transistor, it is preferable to use silicon with high crystallinity, such as single crystal silicon or polycrystalline silicon, since high field effect mobility can be achieved and higher speed operation is possible.

[0049] The Si transistor included in the flip-flop circuit 122 described above may be referred to as a first transistor.

[0050] The first data retention circuit 131 may include an OS transistor. An OS transistor has a characteristic of having a very low off-state current. Therefore, when an OS transistor is used as a transistor constituting the first data retention circuit 131 included in the first data retention circuit group 130, data written to the first data retention circuit 131 can be retained for a long period of time. By configuring the first data retention circuit 131 using an OS transistor, the first data retention circuit 131 can be provided overlapping with a circuit including a Si transistor, such as the scan flip-flop 120. In particular, in this specification, an oxide semiconductor including a channel formation region of the OS transistor used in the first data retention circuit 131 may be referred to as a first oxide semiconductor.

[0051] Note that the above-described transistor including the first oxide semiconductor may be referred to as a second transistor.

[0052] Each of the multiple first data retention circuits 131 included in the first data retention circuit group 130 can independently save or load data under the control of the signal BK[k:1] and the signal RE[k:1]. In other words, data held in the scan flip-flops 120 that need to be switched for each task can be stored in different first data retention circuits 131 in response to the task switching. The first data retention circuit group 130 may also be simply referred to as a circuit.

[0053] Each of the plurality of first data retention circuits 131 can be configured with an OS transistor and a capacitor. The first data retention circuit 131 may be simply referred to as a circuit. As described above, an OS transistor can be provided overlapping a circuit configured with a Si transistor. For example, the plurality of first data retention circuits 131 can be provided on Si transistors that constitute a circuit such as a scan flip-flop 120. By adding the first data retention circuit 131 configured with an OS transistor on the scan flip-flop 120 configured with a Si transistor, an increase in layout area due to the addition of the first data retention circuit 131 can be suppressed. Each of the plurality of first data retention circuits 131 can store charge in a capacitor by utilizing the very low off-state current of an OS transistor, and can retain a potential corresponding to written data for a long period of time.

[0054] 2B is a diagram showing an example of a circuit configuration of the first data retention circuit 131 included in the first data retention circuit group 130 of FIG. 2A. Note that FIG. 2B shows first data retention circuit 131[1] to first data retention circuit 131[k] as the multiple first data retention circuits 131. The first data retention circuits 131[1] to first data retention circuit 131[k] are connected to terminal Q and terminal SD, respectively. In each of the multiple first data retention circuits 131, the terminal (wiring) connected to terminal Q is called an input terminal, and the terminal (wiring) connected to terminal SD is called an output terminal. The output terminal QF of the above-mentioned flip-flop circuit 122 is connected to the input terminals of the first data retention circuits 131[1] to first data retention circuit 131[k], respectively, and the input terminal DF of the flip-flop circuit 122 is connected to the output terminals of the first data retention circuits 131[1] to first data retention circuit 131[k], respectively, via the selector 121.

[0055] Each of the multiple first data retention circuits 131 includes a transistor 133, a transistor 134, and a capacitor 135. One of the source or the drain of the transistor 133 is connected to the terminal Q and the output terminal QF. The other of the source or the drain of the transistor 133 is connected to one electrode of the capacitor 135 and one of the source or the drain of the transistor 134. The other of the source or the drain of the transistor 134 is connected to the terminal SD. The other electrode of the capacitor 135 is connected to a wiring CL. The transistor 133 is provided between the capacitor 135 and the terminal Q. The transistor 134 is provided between the capacitor 135 and the terminal SD. In each of the multiple first data retention circuits 131, one electrode of the capacitor 135 is illustrated as a node SN[1] to a node SN[k].

[0056] The wiring CL is preferably a wiring that applies a constant potential. The constant potential is preferably, for example, a ground potential. Alternatively, the constant potential can be a positive potential or a negative potential.

[0057] In the first data hold circuit 131[i] (i is an integer between 1 and k), a signal BK[i] is applied to the gate of the transistor 133, and a signal RE[i] is applied to the gate of the transistor 134. The signal BK[i] is a signal for saving data held in the flip-flop circuit 122 in the first data hold circuit 131[i]. The signal RE[i] is a signal for loading the data held in the first data hold circuit 131[i] into the flip-flop circuit 122.

[0058] In the plurality of first data retention circuits 131, the transistors 133 and 134 are preferably OS transistors. Note that FIG. 2B illustrates the transistors 133 and 134 as transistors having back gates. Providing back gates for the transistors 133 and 134 allows a constant voltage to be applied to the back gates, thereby controlling the transistor characteristics. Among the transistors included in the first memory circuit 110, at least the transistors 133 and 134 are preferably OS transistors. The OS transistors have an extremely low off-state current, which can suppress fluctuations in the voltages of the nodes SN[1] to SN[k] due to the off-state current. Furthermore, the first data retention circuit 131 consumes almost no power to retain data. Because the first data retention circuit 131 rewrites data by charging and discharging the capacitor 135, there is no limit to the number of rewrites, in principle, and data can be written and read with low power consumption.

[0059] Furthermore, by using OS transistors for all the transistors in the first data retention circuits 131, it is possible to stack a plurality of first data retention circuits 131. For example, as shown in FIG. 3 , the first data retention circuits 131[1] to 131[k] are stacked in order from the bottom up, and the plurality of first data retention circuits 131 can be stacked on the scan flip-flop 120 configured with a silicon CMOS circuit. In FIG. 3 , of the plurality of stacked first data retention circuits 131, the first data retention circuit 131 in the first layer is referred to as the first data retention circuit 131[1], the first data retention circuit 131 in the second layer is referred to as the first data retention circuit 131[2], and the first data retention circuit 131 in the kth layer is referred to as the first data retention circuit 131[k].

[0060] In the first data holding circuit 131, the OS transistor functions as a switch. In an OS transistor, which is an n-channel transistor, a signal applied to the gate is set to a high level (hereinafter also referred to as "H") to bring the source and drain into a conductive state (ON), and a signal applied to the gate is set to a low level (hereinafter also referred to as "L") to bring the source and drain into a non-conductive state (OFF). The selector 121 outputs a signal supplied to a terminal SD by setting a signal SE to "H" and outputs a signal supplied to a terminal D by setting the signal SE to "L."

[0061] For example, by setting the signal BK[1]="H" in the first data retention circuit 131[1], data held by the flip-flop circuit 122 can be written to the node SN[1] of the first data retention circuit 131[1]. Similarly, by setting the signal BK[k]="H", data from the flip-flop circuit 122 can be written to the node SN[k] of the first data retention circuit 131[k]. Furthermore, by setting the signal RE[1]="H" and the signal SE="H", data from the node SN[1] of the first data retention circuit 131[1] can be written back to the flip-flop circuit 122. Similarly, by setting the signal RE[k]="H" and the signal SE="H", data from the node SN[k] of the first data retention circuit 131[k] can be written back to the flip-flop circuit 122.

[0062] As an oxide semiconductor used in an OS transistor, for example, indium oxide (In oxide, indium oxide, also referred to as "IO") is preferably used. Indium oxide will be described in detail in Embodiment 6. As an oxide semiconductor used in an OS transistor, for example, gallium oxide (Ga oxide), zinc oxide (Zn oxide, zinc oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al—Zn oxide), Indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"), etc., can be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0063] The oxide semiconductor preferably contains at least indium (In). It may also contain indium and zinc. In addition to these, it may also contain an element M. The element M may be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, the element M is preferably one or more of aluminum, gallium, yttrium, and tin. It is even more preferable that the element M contains one or both of aluminum, gallium, yttrium, and tin.

[0064] Note that an oxide semiconductor used in an OS transistor preferably has crystallinity. Examples of crystalline oxide semiconductors include c-axis-aligned crystalline (CAAC)-OS and nanocrystalline (nc)-OS. When a crystalline oxide semiconductor is used, a highly reliable semiconductor device can be provided.

[0065] In FIG. 3, the transistor 132 is illustrated as a transistor provided in the same layer as the transistors 133 and 134 included in the first data holding circuit 131[1].

[0066] Note that the transistor 132 is not limited to an OS transistor, and a Si transistor can also be used.

[0067] The first data retention circuits 131 included in the first data retention circuit group 130 have a significantly smaller number of circuit elements than the scan flip-flops 120. Therefore, it is not necessary to change the circuit configuration and layout of the scan flip-flops 120 to form the first data retention circuit group 130. In other words, the first data retention circuits 131 included in the first data retention circuit group 130 can be said to be highly versatile circuits. Furthermore, as shown in FIG. 3 , multiple first data retention circuits 131 can be stacked in a direction perpendicular to the surface on which the scan flip-flops 120 are formed. Therefore, even if the number of first data retention circuits 131 stacked on the scan flip-flops 120 is increased, the area overhead occupied by the first data retention circuit group 130 can be reduced to zero. Furthermore, the first data retention circuits 131 included in the first data retention circuit group 130 consume little power to retain data.

[0068] By providing the first data retention circuit 131 in the first memory circuit 110, a parasitic capacitance due to the transistor 133 is added to the terminal Q. However, this parasitic capacitance is smaller than the parasitic capacitance due to the logic circuit connected to the terminal Q, and therefore has little effect on the operation of the scan flip-flop 120. In other words, even if a plurality of first data retention circuits 131 are provided, the performance of the first memory circuit 110 does not substantially deteriorate.

[0069] 4A illustrates the configuration of the first memory circuit 110 when the first data retention circuit group 130 includes four first data retention circuits 131 in order to explain the operation of the first memory circuit 110. Specifically, the first memory circuit 110 in FIG. 4A has a circuit configuration when k=4. FIG. 4A illustrates nodes SN[1] to SN[4] that retain data in the first data retention circuits 131 (first data retention circuits 131[1] to first data retention circuits 131[4]) included in the first data retention circuit group 130. FIG. 4A also illustrates signals BK[1] to BK[4] and signals RE[1] to RE[4] that control the first data retention circuits 131[1] to first data retention circuits 131[4].

[0070] 4B shows an example of a timing chart illustrating the operation of the first memory circuit 110 shown in FIG. 4A. FIG. 4B illustrates fluctuations in the potentials of the clock signal CLK, terminal D, terminal Q, signal BK[1], signal BK[2], signal RE[1], signal RE[2], node SN[1], node SN[2], and signal SE supplied to the selector 121. The flip-flop circuit 122 stores data supplied to the input terminal DF in synchronization with the rising edge (waveform switching from L to H) of the clock signal CLK. The flip-flop circuit 122 also outputs a potential corresponding to the data from the output terminal QF.

[0071] 5A to 5E are schematic diagrams of the first memory circuit 110 for explaining the operation in the timing chart of Fig. 4B. Fig. 5A illustrates the scan flip-flop 120 and the first data retention circuits 131[1] to 131[4] of the first data retention circuit group 130. Figs. 5B to 5E are diagrams illustrating data input / output to / from the scan flip-flop 120 and the first data retention circuits 131[1] to 131[4] of the first data retention circuit group 130 at times T1, T3, T5, and T7 in Fig. 4B, respectively.

[0072] At time T0, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores data D0 and outputs the data D0 from the output terminal QF.

[0073] At time T1, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores data D1 given to terminal D and outputs data D1 from output terminal QF. At time T1, by setting signal BK[1]="H", signal RE[1]="L", and signal SE="L", data D1 of the scan flip-flop 120 is held in node SN[1] of the first data hold circuit 131[1] (see FIG. 5B). Data D2 is given to terminal D.

[0074] At time T2, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D2 applied to the terminal D and outputs it from the output terminal QF.

[0075] At time T3, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores data D3 given to terminal D and outputs it from output terminal QF. At time T3, signal BK[2]="H", signal RE[2]="L", and signal SE="L", so that data D3 of the scan flip-flop 120 is held in node SN[2] of the first data hold circuit 131[2] (see FIG. 5C). Data D4 is given to terminal D.

[0076] At time T4, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D4 applied to the terminal D and outputs it from the output terminal QF.

[0077] At time T5, by setting the signal BK[1]="L", the signal RE[1]="H", and the signal SE="H", data D1 held in node SN[1] of the first data hold circuit 131[1] can be written back to the scan flip-flop 120 in synchronization with the rising edge of the clock signal CLK. Data D6 is provided to the terminal D (see FIG. 5D).

[0078] At time T6, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D6 applied to the terminal D and outputs it from the output terminal QF.

[0079] At time T7, by setting BK[2]="L", RE[2]="H", and SE="H", data D3 held in node SN[2] of the first data hold circuit 131[2] can be written back to the scan flip-flop 120 in synchronization with the rising edge of the clock signal CLK. Data D8 is provided to terminal D (see FIG. 5E).

[0080] As described with reference to Figures 4B and 5B to 5E, a configuration is possible in which data of an interrupted task is saved and data of a task to be resumed is loaded. In one embodiment of the present invention, data saved in association with task switching can be stored in the multiple first data retention circuits 131 included in the first data retention circuit group 130. With this configuration, program processing can be executed sequentially by saving and loading data in response to switching between multiple tasks at the timing when an interrupt signal is input. This makes it possible to process data more efficiently.

[0081] FIG. 6 is a timing chart of the task switching operation using the first storage circuit 110 shown in FIG. 4A and the operation of the first storage circuit 110 described with reference to FIG. 4B from time Ta to time Tc.

[0082] At time Ta, while the semiconductor device 100 is executing task 1, the data in the scan flip-flop 120 is stored in the first data retention circuit 131[1] (Save to 131[1]), and then the data in the first data retention circuit 131[2] is written back to the scan flip-flop 120 (Load from 131[2]). In this way, the state of task 1 is saved, and task 2 is made executable, and the semiconductor device 100 switches to task 2.

[0083] At time Tb, while the semiconductor device 100 is executing task 2, the data in the scan flip-flop 120 is stored in the first data retention circuit 131[2] (Save to 131[2]), and then the data in the first data retention circuit 131[3] is written back to the scan flip-flop 120 (Load from 131[3]). In this way, the state of task 2 is saved, and task 3 is placed in an executable state, and the semiconductor device 100 switches to task 3.

[0084] At time Tc, while the semiconductor device 100 is executing task 3, the data in the scan flip-flop 120 is stored in the first data retention circuit 131[3] (Save to 131[3]), and then the data in the first data retention circuit 131[1] is written back to the scan flip-flop 120 (Load from 131[1]). Here, the data written back to the scan flip-flop 120 from the first data retention circuit 131[1] is the data stored in the first data retention circuit 131[1] from the scan flip-flop 120 at time Ta. In other words, task 1, which was being executed up to time Ta, can be continued. In this way, the state of task 3 is saved, and task 1 is switched to task 3 as an executable state.

[0085] The above configuration makes it possible to provide a semiconductor device that can reduce power consumption while providing a large number of register banks.Furthermore, since processing can be resumed from where it left off when switching tasks, it is possible to provide a semiconductor device with improved computing performance.

[0086] Although the flip-flop circuit has a larger circuit scale than the inverter loop circuit, it allows high-speed access and is suitable for registers that require high-speed operation rather than storage capacity.

[0087] 7A is a diagram showing an example of the configuration of the second memory circuit 114a. As described above, the second memory circuit 114a has an inverter loop circuit 115 and a second data hold circuit 141. The inverter loop circuit 115 is connected to one or more second data hold circuits 141.

[0088] The inverter loop circuit 115 includes a first inverter 200, a second inverter 201, a transistor 142, a transistor 147, and a transistor 148. The second memory circuit 114a includes a transistor 150 connected to the second data retention circuit group 140, and a transistor 146 that controls switching between a conductive state and a non-conductive state between the inverter loop circuit 115 and the second data retention circuit group 140.

[0089] The first inverter 200 and the second inverter 201 are also called "NOT gate circuits" or "inverting circuits." Each inverter has the function of inverting the logic of input data and outputting it. For example, when a potential "H" is input as data "1," it outputs a potential "L" as data "0," and when a potential "L" is input as data "0," it outputs a potential "H" as data "1." Note that data "0" may be treated as a potential "H," and data "1" may be treated as a potential "L."

[0090] In the inverter loop circuit 115, one of the source and the drain of the transistor 147 is connected to the wiring BL, the gate of the transistor 147 is connected to the wiring WL, and the other of the source and the drain of the transistor 147 is connected to one of the source and the drain of the transistor 142, the input terminal of the first inverter 200, and one of the source and the drain of the transistor 146. One of the source and the drain of the transistor 148 is connected to the wiring BLB, the gate of the transistor 148 is connected to the wiring WL, and the other of the source and the drain of the transistor 148 is connected to the output terminal of the first inverter 200 and the input terminal of the second inverter 201. The output terminal of the second inverter 201 is connected to the other of the source and the drain of the transistor 142. The gate of the transistor 142 is connected to a wiring that provides a signal BK[0].

[0091] In the inverter loop circuit 115 of FIG. 7A, the connection point between the input terminal of the first inverter 200, one of the source or drain of the transistor 142, and one of the source or drain of the transistor 146 is referred to as a terminal TE1.

[0092] The wiring BL and the wiring BLB function as a bit line pair that can handle data complementarily. For example, when data with a logic value of "1" is applied to the wiring BL, data with a logic value of "0" is applied to the wiring BLB. Depending on the situation, data with the same logic value may be applied to the wiring BL and the wiring BLB. The wiring WL functions as a word line in the inverter loop circuit 115.

[0093] In the inverter loop circuit 115, when "H" is applied as the signal BK[0], electrical continuity is established between the input terminal of the first inverter 200 and the output terminal of the second inverter 201. At this time, by applying "H" to the wiring WL to turn on the transistors 147 and 148, data is applied from the wiring BL and the wiring BLB, and the data can be written to the inverter loop circuit 115. After the data is written, by applying "L" to the wiring WL to turn off the transistors 147 and 148, the data can be held by the first inverter 200 and the second inverter 201.

[0094] Furthermore, various signals (signal BK, signal RE, signal EN, signal PCB) generated by the state control unit 101 are input to the second storage circuit 114a. The state control unit 101 may be configured to output signals for controlling power gating of the second storage circuit 114a. Note that the various signals described above are different signals from those of the first data retention circuit group 130.

[0095] The signal BK[k:1] is a signal that controls saving of data held in the inverter loop circuit 115. By saving the data, the data held in the inverter loop circuit 115 is held in any one of the plurality of second data hold circuits 141 in the second data hold circuit group 140.

[0096] The signal RE[k:1] is a circuit that controls loading of data held in any one of the plurality of second data hold circuits 141 in the second data hold circuit group 140. By loading the data, the data held in any one of the plurality of second data hold circuits 141 in the second data hold circuit group 140 is held in the inverter loop circuit 115.

[0097] The signal EN is an enable signal that controls switching between the conductive state and the non-conductive state between the inverter loop circuit 115 and the second data hold circuit group 140 .

[0098] Note that a connection point between one of the source and the drain of the transistor 150, the second data holding circuit 141, and the other of the source and the drain of the transistor 146 is referred to as a node RO.

[0099] 7A, the inverter loop circuit 115 may include, for example, Si transistors, or may include a silicon CMOS circuit using Si transistors.

[0100] The Si transistor included in the inverter loop circuit 115 described above may be referred to as a third transistor.

[0101] The second data retention circuit 141 can include an OS transistor. OS transistors have a characteristic of extremely low off-state current. Therefore, when an OS transistor is used as a transistor constituting the second data retention circuit 141 included in the second data retention circuit group 140, data written to the second data retention circuit 141 can be retained for a long period of time. By using an OS transistor for the second data retention circuit 141, the second data retention circuit 141 can be provided overlapping with a circuit including a Si transistor, such as the inverter loop circuit 115. In particular, in this specification, an oxide semiconductor in a channel formation region of an OS transistor used in the second data retention circuit 141 may be referred to as a second oxide semiconductor.

[0102] Note that the above-described transistor including the second oxide semiconductor may be referred to as a fourth transistor.

[0103] Each of the multiple second data retention circuits 141 included in the second data retention circuit group 140 can independently save or load data under the control of the signal BK[k:1] and the signal RE[k:1]. In other words, the data retained in the inverter loop circuit 115, which needs to be switched for each task, can be stored in a different second data retention circuit 141 in response to the task switching. The second data retention circuit group 140 may also be simply referred to as a circuit.

[0104] Each of the second data retention circuits 141 can be configured with an OS transistor and a capacitor. The second data retention circuit 141 may be simply referred to as a circuit. As described above, an OS transistor can be provided overlapping a circuit configured with a Si transistor. For example, the second data retention circuits 141 can be provided on Si transistors that form a circuit such as the inverter loop circuit 115. By adding the second data retention circuit 141 configured with an OS transistor on the inverter loop circuit 115 configured with a Si transistor, an increase in layout area due to the addition of the second data retention circuit 141 can be suppressed. Each of the second data retention circuits 141 can store charge in a capacitor by utilizing the very low off-state current of an OS transistor and can retain a potential corresponding to written data for a long period of time.

[0105] 7B is a diagram showing an example of the circuit configuration of the second data retention circuit 141 included in the second data retention circuit group 140. Note that Fig. 7B shows second data retention circuit 141[1] to second data retention circuit 141[k] as the multiple second data retention circuits 141. Each of the second data retention circuit 141[1] to second data retention circuit 141[k] is connected to the inverter loop circuit 115 via a transistor 146.

[0106] In the inverter loop circuit 115, the terminal TE1 functions as an output terminal when outputting data to the second data retention circuit 141 of the second data retention circuit group 140, and also functions as an input terminal when writing back data from the second data retention circuit 141.

[0107] The second data retention circuits 141[1] to 141[k] each include a transistor 143, a transistor 144, and a capacitor 145. One of the source or the drain of the transistor 143 is connected to the other of the source or the drain of the transistor 146. The other of the source or the drain of the transistor 143 is connected to one of the source or the drain of the transistor 144 and one terminal of the capacitor 145. The other electrode of the capacitor 145 is connected to a wiring CL1. The other of the source or the drain of the transistor 144 is connected to the other of the source or the drain of the transistor 146 and one of the source or the drain of the transistor 150. The other of the source or the drain of the transistor 150 is connected to a wiring CL2.

[0108] Note that the wirings CL1 and CL2 are preferably wirings that apply the same constant potential. The constant potential is preferably, for example, ground potential. Alternatively, the constant potential may be a positive potential or a negative potential. Alternatively, the wirings CL1 and CL2 may be wirings that apply different potentials.

[0109] In each of the second data retention circuits 141[1] to 141[k], one electrode of the capacitor 145 is illustrated as a node SN[1] to a node SN[k].

[0110] In the second data holding circuit group 140, a connection point between one of the source and the drain of the transistor 143, the other of the source and the drain of the transistor 144, and one of the source and the drain of the transistor 146 is referred to as a terminal TE2.

[0111] In the second data retention circuits 141[1] to 141[k], the terminal TE2 functions as an output terminal when outputting data to the inverter loop circuit 115 and as an input terminal when inputting data from the inverter loop circuit 115.

[0112] The transistor 150 has a function of applying a precharge potential to a wiring connected to the transistor 150 in response to a signal PCB. For example, by setting the signal PCB to "H", the transistor 150 is turned on, and the precharge potential can be applied to a wiring connected to the terminal TE2. Note that the precharge potential is a read potential that is applied to a wiring connected to the terminal TE2 in advance when data is read from any one of the second data retention circuits 141[1] to 141[k].

[0113] In the second data hold circuit 141[i] (where i is an integer between 1 and k), a signal BK[i] is applied to the gate of the transistor 143, and a signal RE[i] is applied to the gate of the transistor 144. The signal BK[i] is a signal for saving data held by the inverter loop circuit 115 in the second data hold circuit 141[i]. The signal RE[i] is a signal for loading the data held in the second data hold circuit 141[i] into the inverter loop circuit 115.

[0114] The transistors 143 and 144 can be OS transistors. In FIG. 7B , the transistors 143 and 144 each have a back gate. By providing the back gates of the transistors 143 and 144 and supplying a constant voltage to the back gates, the transistor characteristics can be controlled. Among the transistors included in the second memory circuit 114a, at least the transistors 143 and 144 are preferably OS transistors. The OS transistors have an extremely low off-state current, which can suppress fluctuations in the voltages of the nodes SN[1] to SN[k] due to the off-state current. The second data retention circuit 141 consumes almost no power to retain data. Because the second data retention circuit 141 rewrites data by charging and discharging the capacitor 145, the number of rewrites is not limited in principle, and data can be written and read with low power consumption.

[0115] The OS transistor functions as a switch in the second data holding circuit 141. In an OS transistor, which is an n-channel transistor, when a signal applied to the gate is set to "H", conduction between the source and the drain can be brought about (ON), and when a signal applied to the gate is set to "L", conduction between the source and the drain can be brought about (OFF).

[0116] For example, by setting the signal BK[1]="H" and the signal EN="H" in the second data hold circuit 141, the data held by the inverter loop circuit 115 can be written to the node SN[1] of the second data hold circuit 141. Similarly, by setting the signal BK[k]="H" and the signal EN="H", the data of the inverter loop circuit 115 can be written to the node SN[k] of the second data hold circuit 141. Furthermore, by setting the signal RE[1]="H" and the signal EN="H", the data of the node SN[1] of the second data hold circuit 141 can be written back to the inverter loop circuit 115. Similarly, by setting the signal RE[k]="H" and the signal EN="H", the data of the node SN[k] of the second data hold circuit 141 can be written back to the inverter loop circuit 115.

[0117] It is highly preferable that all the transistors included in the second data retention circuits 141 in the second data retention circuit group 140 are OS transistors. By using OS transistors for all the transistors in the second data retention circuits 141, it is possible to stack a plurality of second data retention circuits 141. For example, as shown in FIG. 8 , the plurality of second data retention circuits 141 are stacked in order from the bottom up, and can be stacked on the inverter loop circuit 115 configured as a silicon CMOS circuit.

[0118] 8, the transistor 146 is illustrated as a transistor that connects the inverter loop circuit 115 and the second data retention circuit group 140. The transistor 146 is not limited to an OS transistor, and a Si transistor can also be used.

[0119] The second data retention circuits 141 included in the second data retention circuit group 140 have a significantly smaller number of circuit elements than the inverter loop circuits 115. Therefore, it is not necessary to change the circuit configuration and layout of the inverter loop circuits 115 to form the second data retention circuit group 140. In other words, the second data retention circuits 141 included in the second data retention circuit group 140 can be said to be highly versatile circuits. Furthermore, as shown in FIG. 3 , multiple second data retention circuits 141 can be stacked in a direction perpendicular to the surface on which the inverter loop circuits 115 are formed. Therefore, even if the number of second data retention circuits 141 stacked on the inverter loop circuits 115 is increased, the area overhead occupied by the second data retention circuit group 140 can be reduced to zero. Furthermore, the second data retention circuits 141 included in the second data retention circuit group 140 consume little power to retain data.

[0120] By providing the second data hold circuit 141, parasitic capacitance due to the transistors 143 and 144 is added to the terminal TE2. However, by providing the transistor 146 between the terminals TE2 and TE1, the effect of this parasitic capacitance is mitigated and has almost no effect on the operation of the inverter loop circuit 115. In other words, even if a plurality of second data hold circuits 141 are provided, the performance of the second memory circuit 114a does not substantially deteriorate.

[0121] 9 illustrates the configuration of the second memory circuit 114a when the second data retention circuit group 140 includes four second data retention circuits 141, in order to explain the operation of the second memory circuit 114a. Specifically, the second memory circuit 114a in FIG. 9 has a circuit configuration when k=4. FIG. 9 illustrates nodes SN[1] to SN[4] that retain data in the second data retention circuits 141 (second data retention circuits 141[1] to 141[4]) included in the second data retention circuit group 140. FIG. 9 also illustrates signals BK[1] to BK[4] and signals RE[1] to RE[4] that control the second data retention circuits 141[1] to 141[4].

[0122] Next, an example of the operation of the inverter loop circuit 115 included in the second memory circuit 114a will be described. 10A to 10D are timing charts illustrating an example of the operation of the inverter loop circuit 115.

[0123] 10A to 10D illustrate the fluctuations in the potentials of the signal DT, the signal DTB, the wiring WL, the wiring BL, the wiring BLB, the signal BK[0], the signal RE[4:1], the signal BK[4:1], the signal EN, and the signal PCB. Note that the signal DT is a signal output from the terminal TE1 of the inverter loop circuit 115, and the signal DTB is a signal output from the output terminal of the first inverter 200. The initial values ​​are set to the wiring WL="L", the wiring BL="H", the wiring BLB="H", and the signal BK[0]="H".

[0124] Also, in Figures 10A to 10D, the second data retention circuits 141[1] to 141[4] are not operating, so the signal RE[4:1] is given an "L", the signal BK[4:1] is given an "L", the signal EN is given an "L", and the signal PCB is given an "H".

[0125] FIG. 10A shows a timing chart of the operation of writing a logical value of "0" to the inverter loop circuit 115.

[0126] Before time T70, the potential of the signal DT output from the terminal TE1 of the inverter loop circuit 115 and the potential of the signal DTB output from the output terminal of the first inverter 200 are not particularly limited, and therefore, in Fig. 10A, hatching with diagonal lines indicates that the respective potentials are undefined. Note that in Fig. 10B, which will be described later, hatching with diagonal lines also indicates that the potentials are undefined.

[0127] Between time T70 and time T71, "H" is applied to the wiring WL. Furthermore, "L" is applied to the wiring BL and "H" is applied to the wiring BLB as the logical value "0" to be written to the inverter loop circuit 115. As a result, the inverter loop circuit 115 outputs "0" as the signal DT. Furthermore, the first inverter 200 outputs "1" as the signal DTB from the output terminal. Note that since the signal BK[0] is "L", the inverter loop circuit 115 does not hold the logical value "0" at this stage.

[0128] Between time T71 and time T72, "L" is applied to the wiring WL. Thereafter, by setting the signal BK[0] to "H", conduction is established between the input terminal of the first inverter 200 and the output terminal of the second inverter 201, so that "H" continues to be output to the output terminal of the first inverter 200 and "L" continues to be output to the output terminal of the second inverter 201. As a result, the inverter loop circuit 115 holds a logical value of "0". Note that in FIG. 10A, the potential of the wiring BL is set to "H" between time T71 and time T72.

[0129] FIG. 10B shows a timing chart of the operation of writing a logical value of "1" to the inverter loop circuit 115.

[0130] Between time T73 and time T74, "H" is applied to the wiring WL. Furthermore, as a logical value "1" to be written to the inverter loop circuit 115, "H" is applied to the wiring BL and "L" is applied to the wiring BLB. As a result, the inverter loop circuit 115 outputs "1" as the signal DT. Furthermore, the first inverter 200 outputs "0" as the signal DTB from the output terminal. Note that since the signal BK[0] is "L", the inverter loop circuit 115 does not hold the logical value "1" at this stage.

[0131] Between time T74 and time T75, "L" is applied to the wiring WL. Thereafter, by setting the signal BK[0] to "H", conduction is established between the input terminal of the first inverter 200 and the output terminal of the second inverter 201, so that "L" continues to be output to the output terminal of the first inverter 200 and "H" continues to be output to the output terminal of the second inverter 201. As a result, the inverter loop circuit 115 holds a logical value of "1". Note that in FIG. 10B, the potential of the wiring BLB is set to "H" between time T74 and time T75.

[0132] 10C shows a timing chart of an operation for reading out the logical value "1" stored in the inverter loop circuit 115. In addition, in FIG. 10C, the inverter loop circuit 115 outputs "1" as the signal DT from the terminal TE1, and outputs "0" as the signal DTB from the output terminal of the first inverter 200.

[0133] Before time T76, "H" is applied to the wiring BL and the wiring BLB. Also, before time T76, it is assumed that the wiring BL and the wiring BLB are in a floating state.

[0134] Between time T76 and time T77, "H" is applied to the wiring WL. As a result, conduction is established between the output terminal of the second inverter 201 and the wiring BL, and "H" output from the output terminal of the second inverter 201 is applied to the wiring BL. Conduction is also established between the output terminal of the first inverter 200 and the wiring BLB, and "L" output from the output terminal of the first inverter 200 is applied to the wiring BLB. As a result, the potential of the wiring BL is maintained at "H", and the potential of the wiring BLB drops from "H" to "L".

[0135] Between time T76 and time T77, the logical value "1" stored in the inverter loop circuit 115 can be read from the potentials of the wiring BL and the wiring BLB.

[0136] Between time T77 and time T78, the wiring WL is set to "L." In addition, in the timing chart of FIG. 10C, after the readout is completed, the potentials of the wiring BL and the wiring BLB are set to "H."

[0137] 10D shows a timing chart of an operation for reading out the logical value "0" stored in the inverter loop circuit 115. In addition, in Fig. 10D, the inverter loop circuit 115 outputs "0" as the signal DT from the terminal TE1, and outputs "1" as the signal DTB from the output terminal of the first inverter 200.

[0138] Before time T79, "H" is applied to each of the wiring BL and the wiring BLB. Also, before time T79, each of the wiring BL and the wiring BLB is assumed to be in a floating state.

[0139] Between time T79 and time T80, "H" is applied to the wiring WL. As a result, conduction is established between the output terminal of the second inverter 201 and the wiring BL, and "L" output from the output terminal of the second inverter 201 is applied to the wiring BL. Conduction is also established between the output terminal of the first inverter 200 and the wiring BLB, and "H" output from the output terminal of the first inverter 200 is applied to the wiring BLB. As a result, the potential of the wiring BLB remains "H", and the potential of the wiring BL drops from "H" to "L".

[0140] Between time T80 and time T81, the logical value "0" stored in the inverter loop circuit 115 can be read from the potentials of the wiring BL and the wiring BLB.

[0141] 11A to 11D are examples of timing charts illustrating the operation of the second memory circuit 114a shown in FIG.

[0142] 11A to 11D illustrate the fluctuations in the potentials of signal DT, signal DTB, wiring WL, wiring BL, wiring BLB, signal BK[1], signal BK[2], signal RE[1], signal RE[2], node SN[1], node SN[2], signal PCB, node RO, signal EN, and signal BK[0]. Initial values ​​are set as follows: signal DT="1", signal DTB="0", signal BK[1]="L", signal BK[2]="L", signal RE[1]="L", signal RE[2]="L", signal EN="L", wiring PCB="L", and signal BK[0]="H". In FIGS. 11A to 11D, U70 to U83 represent time.

[0143] 11A to 11D, the second data retention circuit 141[3] and the second data retention circuit 141[4] are not used, and therefore the potentials of the signals BK[3], BK[4], RE[3], and RE[4] are always set to L (not shown). The potentials of the nodes SN[3] and SN[4] are not particularly limited.

[0144] 11A to 11D, data is not written from the wiring BL and the wiring BLB to the inverter loop circuit 115, and data is not read from the inverter loop circuit 115 to the wiring BL and the wiring BLB. Therefore, "L" is always applied to the wiring WL. In addition, the potentials of the wiring BL, the wiring BLB, the node SN[1], the node SN[2], and the node RO are not particularly limited, and therefore, in FIGS. 11A to 11D, diagonal hatching is shown to indicate that the respective potentials are indefinite.

[0145] 12A to 12E are schematic diagrams of the second memory circuit 114a for explaining the operation in the timing charts of FIG. 11A to 11D. FIG. 12A illustrates the inverter loop circuit 115 and the second data retention circuits 141[1] to 141[4] of the second data retention circuit group 140. FIG. 12B to 12E respectively illustrate the inverter loop circuit 115 and the second data retention circuits 141[1] to 141[4] of the second data retention circuit group 140 at time U71 in FIG. 11A, time U74 in FIG. 11B, time U77 in FIG. 11C, and time U81 in FIG. 11D.

[0146] The timing chart of FIG. 11A shows an example of an operation in which the logical value "1" held in the inverter loop circuit 115 is stored in the second data holding circuit 141[1].

[0147] Also, from time U70 to time U72, the second memory circuit 114a is supplied with the signal PCB at "L." Therefore, the transistor 150 is turned off, and there is no conduction between the line CL2 and the node RO.

[0148] Furthermore, between time U70 and time U72, signals RE[1] to RE[4] are set to "L" to the second data retention circuits 141[1] to 141[4], respectively. As a result, between time U70 and time U72, the transistors 144 of the second data retention circuits 141[1] to 141[4] are turned off.

[0149] Furthermore, between time U70 and time U72, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, causing inverter loop circuit 115 to hold data. Note that in the timing chart of FIG. 11A, it is assumed that a logical value of "1" is being held as the data. Also, at this time, terminal TE1 of inverter loop circuit 115 outputs a logical value of "1" as signal DT, and the output terminal of first inverter 200 outputs a logical value of "0" as signal DTB.

[0150] Between time U70 and time U71, a signal EN of "L" is applied to the gate of the transistor 146, and the transistor 146 is in an OFF state.

[0151] Between time U71 and time U72, a signal EN of "H" is applied to the gate of the transistor 146, turning on the transistor 146. At this time, the signal DT output from the terminal TE1 of the inverter loop circuit 115 is input to the second data hold circuits 141[1] to 141[4] via the terminal TE2 (node ​​RO).

[0152] Furthermore, between time U71 and time U72, a signal BK[1] of "H" is provided to the second data retention circuit 141[1], and signals BK[2] to BK[4] of "L" are provided to each of the second data retention circuits 141[2] to 141[4]. This causes the transistor 143 of the second data retention circuit 141[1] to be turned on, and each of the transistors 143 of the second data retention circuits 141[2] to 141[4] to be turned off. Therefore, the signal DT output from the terminal TE1 of the inverter loop circuit 115 is stored in the second data retention circuit 141[1] (see FIG. 12B). Specifically, a logical value of "1" is stored in the node SN[1] of the second data retention circuit 141[1].

[0153] After time U72, a low level signal BK[1] is sent to the gate of the transistor 143 of the second data hold circuit 141[1], turning the transistor 143 off. This completes the storage of the logical value "1" in the node SN[1] of the second data hold circuit 141[1]. Furthermore, a low level signal EN is sent to the gate of the transistor 146, turning the transistor 146 off.

[0154] FIG. 12B shows an example in which data D1 is held in the second data holding circuit 141[1] as a logical value "1".

[0155] The timing chart of FIG. 11B shows an example of an operation in which the logical value "0" held in the inverter loop circuit 115 is stored in the second data holding circuit 141[2].

[0156] Also, from time U73 to time U75, the second memory circuit 114a is supplied with the signal PCB at "L." Therefore, the transistor 150 is turned off, and there is no conduction between the line CL2 and the node RO.

[0157] Furthermore, between time U73 and time U75, signals RE[1] to RE[4] are set to "L" to the second data retention circuits 141[1] to 141[4], respectively. As a result, between time U73 and time U75, the transistors 144 of the second data retention circuits 141[1] to 141[4] are turned off.

[0158] Furthermore, between time U73 and time U75, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, causing inverter loop circuit 115 to hold data. Note that in the timing chart of FIG. 11B, it is assumed that the data held is a logical "0." At this time, terminal TE1 of inverter loop circuit 115 outputs a logical "0" as signal DT, and the output terminal of first inverter 200 outputs a logical "1" as signal DTB.

[0159] Between time U73 and time U74, a signal EN of "L" is applied to the gate of the transistor 146, and the transistor 146 is in an OFF state.

[0160] Between time U74 and time U75, a signal EN of "H" is applied to the gate of the transistor 146, turning on the transistor 146. At this time, the signal DT output from the terminal TE1 of the inverter loop circuit 115 is input to the second data hold circuits 141[1] to 141[4] via the terminal TE2 (node ​​RO).

[0161] Furthermore, between time U74 and time U75, "H" is provided as the signal BK[2] to the second data hold circuit 141[2], and "L" is provided as the signals BK[1], BK[3], and BK[4] to the second data hold circuit 141[1], the second data hold circuit 141[3], and the second data hold circuit 141[4], respectively. As a result, the transistor 143 of the second data hold circuit 141[2] is turned on, and the transistors 143 of the second data hold circuit 141[1], the second data hold circuit 141[3], and the second data hold circuit 141[4] are turned off. Therefore, the signal DT output from the terminal TE1 of the inverter loop circuit 115 is stored in the second data hold circuit 141[2] (see FIG. 12C ). More specifically, the logical value "0" is stored in the node SN[2] of the second data holding circuit 141[2].

[0162] After time U75, a low level signal BK[2] is sent to the gate of the transistor 143 of the second data hold circuit 141[2], turning the transistor 143 off. This completes the storage of the logic value "0" in the node SN[2] of the second data hold circuit 141[2]. A low level signal EN is also sent to the gate of the transistor 146, turning the transistor 146 off.

[0163] FIG. 12C shows an example in which data D2 is held in the second data holding circuit 141[2] as a logical value "0".

[0164] The timing chart of FIG. 11C shows an example of an operation in which the logical value “1” held in the second data holding circuit 141[1] is restored to the inverter loop circuit 115.

[0165] Furthermore, between time U76 and time U79, signals BK[1] to BK[4] of "L" are provided to the second data retention circuits 141[1] to 141[4], respectively, so that the transistors 143 of the second data retention circuits 141[1] to 141[4] are turned off between time U76 and time U79.

[0166] Also, before time U76, the inverter loop circuit 115 is assumed to hold a logical value of "0." Specifically, "H" is provided to the gate of the transistor 142 as the signal BK[0], turning the transistor 142 on. As a result, conduction occurs between the input terminal of the first inverter 200 and the output terminal of the second inverter 201, and the inverter loop circuit 115 is in a state of holding data. Furthermore, the terminal TE1 of the inverter loop circuit 115 outputs a logical value of "0" as the signal DT, and the output terminal of the first inverter 200 outputs a logical value of "1" as the signal DTB.

[0167] Between time U76 and time U77, a signal EN of "L" is applied to the gate of the transistor 146, and the transistor 146 is in an OFF state.

[0168] Also, from time U76 to time U77, the second memory circuit 114a is supplied with a signal PCB of "H." This turns on the transistor 150, establishing electrical continuity between the line CL2 and the node RO. This causes a precharge potential of "L" from the line CL2 to be supplied to the node RO and the terminal TE2.

[0169] Thereafter, from time U77 to time U78, the second memory circuit 114a is supplied with the signal PCB at "L." Therefore, the transistor 150 is turned off, and there is no conduction between the line CL2 and the node RO. As a result, the node RO is in a floating state.

[0170] Furthermore, between time U77 and time U78, "L" is applied to the gate of the transistor 142 as the signal BK[0], turning off the transistor 142. This causes a non-conductive state between the input terminal of the first inverter 200 and the output terminal of the second inverter 201.

[0171] Between time U77 and time U78, a signal EN of "H" is applied to the gate of the transistor 146, turning on the transistor 146. This brings the terminal TE1 and the terminal TE2 (node ​​RO) into a conductive state.

[0172] Furthermore, between time U77 and time U78, "H" is provided as the signal RE[1] to the second data retention circuit 141[1], and "L" is provided as the signals RE[2] to RE[4] to each of the second data retention circuits 141[2] to 141[4]. As a result, the transistor 144 of the second data retention circuit 141[1] is turned on, and each of the transistors 144 of the second data retention circuits 141[2] to 141[4] is turned off. As a result, the node SN[1], the terminal TE1, and the terminal TE2 are mutually conductive.

[0173] Furthermore, since node SN[1], terminal TE1, and terminal TE2 are each in a floating state, node SN[1], terminal TE1, and terminal TE2 are each brought into a mutually conductive state, causing charge redistribution to occur between node SN[1], terminal TE1, and terminal TE2. As a result, the potential of the logical value "1" at node SN[1] drops, and the potentials of terminals TE1 and TE2 rise from "L."

[0174] Furthermore, in the inverter loop circuit 115, the potential of the input terminal (terminal TE1) of the first inverter 200 rises, and therefore "L" indicating a logical value "0" is output from the output terminal of the first inverter 200. Furthermore, the logical value "0" output from the output terminal of the first inverter 200 is input to the input terminal of the second inverter 201, and "H" indicating a logical value "1" is output from the output terminal of the second inverter 201.

[0175] Between time U78 and time U79, a signal EN of "L" is applied to the gate of the transistor 146, turning off the transistor 146. This causes a non-conduction state between the terminal TE1 and the terminal TE2 (node ​​RO).

[0176] Furthermore, between time U78 and time U79, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, and "H" indicating a logical value "1" output from the output terminal of second inverter 201 is input to the input terminal of first inverter 200. As a result, data with a logical value "1" from second data hold circuit 141[1] is restored to inverter loop circuit 115. Also, at this time, terminal TE1 of inverter loop circuit 115 outputs a logical value "1" as signal DT, and the output terminal of first inverter 200 outputs a logical value "0" as signal DTB.

[0177] Furthermore, between time U78 and time U79, "L" is provided as the signal RE[1] to the second data hold circuit 141[1], turning off the transistor 144 of the second data hold circuit 141[1]. This results in a non-conductive state between the node SN[1] and the terminal TE2. This completes the restoration of the data with a logical value of "1" from the second data hold circuit 141[1] to the inverter loop circuit 115.

[0178] 12D shows an example in which the data D1, which is the logical value “1” held in the second data holding circuit 141[1], is written back to the inverter loop circuit 115. In FIG.

[0179] The timing chart of FIG. 11D shows an example of an operation in which the logical value “0” held in the second data holding circuit 141[2] is restored to the inverter loop circuit 115.

[0180] Furthermore, between time U80 and time U83, signals BK[1] to BK[4] of "L" are provided to the second data retention circuits 141[1] to 141[4], respectively, so that the transistors 143 of the second data retention circuits 141[1] to 141[4] are turned off between time U80 and time U83.

[0181] Also, before time U80, the inverter loop circuit 115 is assumed to hold a logical value of "1." Specifically, "H" is provided to the gate of the transistor 142 as the signal BK[0], turning the transistor 142 on. As a result, conduction occurs between the input terminal of the first inverter 200 and the output terminal of the second inverter 201, and the inverter loop circuit 115 is in a state of holding data. Furthermore, the terminal TE1 of the inverter loop circuit 115 outputs a logical value of "1" as the signal DT, and the output terminal of the first inverter 200 outputs a logical value of "0" as the signal DTB.

[0182] Between time U80 and time U81, a signal EN of "L" is applied to the gate of the transistor 146, and the transistor 146 is in an OFF state.

[0183] Also, from time U80 to time U81, the second memory circuit 114a is supplied with a signal PCB of "H." This turns on the transistor 150, establishing a conductive state between the line CL2 and the node RO. As a result, a precharge potential of "L" is applied to the node RO and the terminal TE2 from the line CL2.

[0184] Thereafter, from time U81 to time U82, the second memory circuit 114a is supplied with a signal PCB of "L." Therefore, the transistor 150 is turned off, and a non-conductive state is established between the line CL2 and the node RO. As a result, the node RO is in a floating state.

[0185] Furthermore, between time U81 and time U82, "L" is applied to the gate of the transistor 142 as the signal BK[0], turning off the transistor 142. This causes a non-conductive state between the input terminal of the first inverter 200 and the output terminal of the second inverter 201.

[0186] Between time U81 and time U82, a signal EN of "H" is applied to the gate of the transistor 146, turning on the transistor 146. This brings the terminal TE1 and the terminal TE2 (node ​​RO) into a conductive state.

[0187] Furthermore, between time U81 and time U82, "H" is provided as the signal RE[2] to the second data retention circuit 141[2], and "L" is provided as the signals RE[1], RE[3], and RE[4] to the second data retention circuit 141[1], the second data retention circuit 141[3], and the second data retention circuit 141[4], respectively. As a result, the transistor 144 of the second data retention circuit 141[2] is turned on, and the transistors 144 of the second data retention circuit 141[1], the second data retention circuit 141[3], and the second data retention circuit 141[4] are turned off. As a result, the node SN[2], the terminal TE1, and the terminal TE2 are mutually conductive.

[0188] Furthermore, since node SN[2], terminal TE1, and terminal TE2 are each in a floating state, node SN[2], terminal TE1, and terminal TE2 are each brought into a mutually conductive state, causing charge redistribution to occur between node SN[2], terminal TE1, and terminal TE2. As a result, the potential of the logical value "0" at node SN[2] rises, and the potentials of terminals TE1 and TE2 rise from "L."

[0189] Furthermore, in the inverter loop circuit 115, the potential of the input terminal (terminal TE1) of the first inverter 200 rises, and therefore "H" indicating a logical value "1" is output from the output terminal of the first inverter 200. Furthermore, the logical value "1" output from the output terminal of the first inverter 200 is input to the input terminal of the second inverter 201, and "L" indicating a logical value "0" is output from the output terminal of the second inverter 201.

[0190] Between time U82 and time U83, a signal EN of "L" is applied to the gate of the transistor 146, turning off the transistor 146. This causes a non-conduction state between the terminal TE1 and the terminal TE2 (node ​​RO).

[0191] Furthermore, between time U82 and time U83, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, and "L" indicating a logical value "0" output from the output terminal of second inverter 201 is input to the input terminal of first inverter 200. As a result, data with a logical value "0" from second data hold circuit 141[2] is restored to inverter loop circuit 115. Also, at this time, terminal TE1 of inverter loop circuit 115 outputs a logical value "0" as signal DT, and the output terminal of first inverter 200 outputs a logical value "1" as signal DTB.

[0192] Furthermore, between time U82 and time U83, "L" is provided as the signal RE[2] to the second data hold circuit 141[2], turning off the transistor 144 of the second data hold circuit 141[2]. This results in a non-conductive state between the node SN[2] and the terminal TE2. This completes the restoration of the data with a logical value of "0" from the second data hold circuit 141[2] to the inverter loop circuit 115.

[0193] As described with reference to Figures 11 and 12B to 12D, a configuration is possible in which data of an interrupted task is saved and data of a task to be resumed is loaded. In one aspect of the present invention, data saved in association with task switching can be stored in the multiple second data retention circuits 141 included in the second data retention circuit group 140. With this configuration, program processing can be executed sequentially by saving and loading data in response to switching between multiple tasks at the timing when an interrupt signal is input. This allows data processing to be performed more efficiently.

[0194] The inverter loop circuit has a smaller circuit scale than the flip-flop circuit, and therefore can have a larger storage capacity, making it suitable for cache memories that require a larger storage capacity rather than a faster operation speed.

[0195] Figure 13 is a timing chart for explaining how task switching in the first memory circuit 110 described in Figures 4A and 4B and task switching in the second memory circuit 114a described in Figures 11A to 11D are performed simultaneously from time Ta to time Tc.

[0196] At time Ta, while the semiconductor device 100 is executing task 1, the data in the scan flip-flop 120 is stored in the first data retention circuit 131[1] (Save to 131[1]), and then the data in the first data retention circuit 131[2] is written back to the scan flip-flop 120 (Load from 131[2]). At the same time, the data in the inverter loop circuit 115 is stored in the second data retention circuit 141[1] (Save to 141[1]), and then the data in the second data retention circuit 141[2] is written back to the inverter loop circuit 115 (Load from 141[2]). In this way, the state of task 1 is saved, and task 2 is switched to as an executable state.

[0197] At time Tb, while the semiconductor device 100 is executing task 2, the data in the scan flip-flop 120 is stored in the first data hold circuit 131[2] (Save to 131[2]), and then the data in the first data hold circuit 131[3] is written back to the scan flip-flop 120 (Load from 131[3]). At the same time, the data in the inverter loop circuit 115 is stored in the second data hold circuit 141[2] (Save to 141[2]), and then the data in the second data hold circuit 141[3] is written back to the inverter loop circuit 115 (Load from 141[3]). In this way, the state of task 2 is saved, and task 3 is made executable and switched to task 3.

[0198] At time Tc, while the semiconductor device 100 is executing task 3, the data in the scan flip-flop 120 is stored in the first data hold circuit 131[3] (Save to 131[3]), and then the data in the first data hold circuit 131[1] is written back to the scan flip-flop 120 (Load from 131[1]). Here, the data written back to the scan flip-flop 120 from the first data hold circuit 131[1] is the data stored in the first data hold circuit 131[1] from the scan flip-flop 120 at time Ta. In other words, task 1, which was being executed up to time Ta, can be continued. At the same time, the data in the inverter loop circuit 115 is stored in the second data hold circuit 141[3] (Save to 141[3]), and then the data in the second data hold circuit 141[1] is written back to the inverter loop circuit 115 (Load from 141[1]). Here, the data written back to the inverter loop circuit 115 from the second data hold circuit 141[1] is the data stored in the second data hold circuit 141[1] from the inverter loop circuit 115 at time Ta. In this way, the state of task 3 is saved, and task 1 is switched to task 3 as an executable state.

[0199] As described above, the semiconductor device 100 of one embodiment of the present invention can provide a semiconductor device that can back up and restore tasks not only in the CPU but also in the cache memory at high speed.

[0200] As described above, by using the first memory circuit 110 according to one embodiment of the present invention for a register included in a semiconductor device, the frequency of access to an external memory during task switching can be reduced. Furthermore, by using the second memory circuit 114a according to one embodiment of the present invention for a cache memory included in a semiconductor device, the frequency of access to an external memory during task switching can be reduced. Therefore, task switching, such as interrupt processing, can be performed efficiently, quickly, and with low power consumption. Furthermore, by using the first memory circuit 110 for a register included in a semiconductor device and the second memory circuit 114a for a cache memory, the frequency of access to an external memory during task switching can be further reduced. Therefore, task switching, such as interrupt processing, can be performed efficiently, quickly, and with low power consumption.

[0201] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0202] Second Embodiment In the second embodiment, a configuration different from that of the second data retention circuit group 140 described above in the second memory circuit 114a described in the first embodiment will be described. Here, as an example, a second memory circuit 114b using NOSRAM (registered trademark) will be described. Note that the description of the first embodiment can be referred to for details of the inverter loop circuit 115.

[0203] NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory." NOSRAM refers to a memory in which a memory cell has a two-transistor (2T) or three-transistor (3T) gain cell, and the transistor included in the gain cell is an OS transistor using an oxide semiconductor for a channel formation region. OS transistors have a characteristic of extremely small leakage current, that is, a current flowing between a source and a drain in an off state. NOSRAM can retain charge corresponding to data in a memory cell using an OS transistor with extremely small leakage current. In particular, NOSRAM can read retained data without destroying it (nondestructive read), and is therefore suitable for arithmetic processing in which only data read operations are repeated a large number of times. NOSRAM can increase its data capacity by stacking gain cells, and therefore can improve the performance of semiconductor devices by using it as a large-scale cache memory, main memory, or storage memory.

[0204] FIG. 14A is a diagram for explaining the configuration of the second memory circuit 114b.

[0205] The second memory circuit 114b includes an inverter loop circuit 115 and a third data retention circuit 161. The inverter loop circuit 115 includes a first inverter 200, a second inverter 201, a transistor 142, a transistor 147, and a transistor 148. Note that for the connection configuration of the circuit elements included in the inverter loop circuit 115, the description of the inverter loop circuit 115 shown in FIG. 7A in Embodiment 1 can be referred to.

[0206] The third data hold circuit 161 is provided on the inverter loop circuit 115. A set of multiple third data hold circuits 161 is also referred to as a third data hold circuit group 160. Therefore, it can also be said that the third data hold circuit group 160 has multiple third data hold circuits 161. The inverter loop circuit 115 is connected to one or more third data hold circuits 161.

[0207] The second memory circuit 114 b also includes a transistor 166 connected to the third data hold circuit group 160 , and transistors 146 and 149 connecting the inverter loop circuit 115 and the third data hold circuit group 160 .

[0208] 14A (signal BK, signal RE, signal EN, signal PCB) can be generated by the state control unit 101 described in embodiment 1. The state control unit 101 may also be configured to output a signal for controlling power gating of the second memory circuit 114b.

[0209] The signal BK[k:1] is a signal that controls saving of data held in the inverter loop circuit 115. By saving the data, the data held in the inverter loop circuit 115 is held in any one of the plurality of third data hold circuits 161 in the third data hold circuit group 160. Note that the signal BK[k:1] may also be expressed as the signals BK[1] to BK[k].

[0210] The signal RE[k:1] is a circuit that controls loading of data held in any one of the plurality of third data hold circuits 161 in the third data hold circuit group 160. By loading the data, the data held in any one of the plurality of third data hold circuits 161 in the third data hold circuit group 160 is written back to the inverter loop circuit 115.

[0211] The signal EN is an enable signal that controls switching between the inverter loop circuit 115 and the third data holding circuit group 160 between a conductive state and a non-conductive state.

[0212] The third data retention circuit 161 can include an OS transistor having a very low off-state current, similar to the first data retention circuit 131 and the second data retention circuit 141 described in Embodiment 1. Therefore, the third data retention circuit 161 included in the third data retention circuit group 160 can retain a potential corresponding to data written to the third data retention circuit 161 for a long period of time, similar to the first data retention circuit 131 and the second data retention circuit 141 described in Embodiment 1. Furthermore, similar to the first data retention circuit 131 and the second data retention circuit 141 described in Embodiment 1, the third data retention circuit 161 can independently save or load data by controlling the signal BK[k:1] and the signal RE[k:1].

[0213] Furthermore, by providing the third data retention circuit 161 with an OS transistor, it is possible to obtain the same effect as that obtained by providing the first data retention circuit 131 and the second data retention circuit 141 with OS transistors, as described in Embodiment 1. For example, the third data retention circuit 161 can be formed so as to overlap with a region in which the inverter loop circuit 115 is formed.

[0214] 14A, a connection point between the output terminal of the first inverter 200, one of the source or drain of the transistor 149, and one of the source or drain of the transistor 148 is defined as a terminal TE3. A connection point between the input terminal of the first inverter 200, one of the source or drain of the transistor 142, one of the source or drain of the transistor 146, and one of the source or drain of the transistor 147 is defined as a terminal TE1.

[0215] 14B is a diagram showing an example of the circuit configuration of the plurality of third data retention circuits 161 included in the third data retention circuit group 160. Note that in FIG. 14B, the plurality of third data retention circuits 161 are shown as third data retention circuits 161[1] to third data retention circuit 161[k]. Each of the third data retention circuits 161[1] to third data retention circuit 161[k] is connected to the inverter loop circuit 115 via a transistor 146. Each of the third data retention circuits 161[1] to third data retention circuit 161[k] is connected to the inverter loop circuit 115 via a transistor 149.

[0216] In the inverter loop circuit 115, the terminal TE3 functions as an output terminal when outputting data to the third data retention circuit group 160. The terminal TE1 functions as an input terminal when writing back data from the third data retention circuit group 160. The terminal TE3 is configured to be connected to the input terminal of the third data retention circuit group 160 (third data retention circuit 161[1] to third data retention circuit 161[k]). The terminal TE1 is configured to be connected to the output terminal of the third data retention circuit group 160 (third data retention circuit 161[1] to third data retention circuit 161[k]).

[0217] The third data retention circuits 161[1] to 161[k] each include a transistor 162, a transistor 163, a transistor 164, and a capacitor 165. One of the source or the drain of the transistor 162 is connected to the other of the source or the drain of the transistor 149. The other of the source or the drain of the transistor 162 is connected to the gate of the transistor 163 and one electrode of the capacitor 165. The other electrode of the capacitor 165 is connected to a wiring CL1. One of the source or the drain of the transistor 163 is connected to a wiring CL3. The other of the source or the drain of the transistor 163 is connected to one of the source or the drain of the transistor 164. The other of the source or the drain of the transistor 164 is connected to the other of the source or the drain of the transistor 146 and one of the source or the drain of the transistor 166. The other of the source or the drain of the transistor 166 is connected to a wiring CL2.

[0218] Note that the wiring CL1 and the wiring CL3 are preferably wirings that apply the same constant potential. The constant potential is preferably, for example, ground potential. Alternatively, the constant potential can be a positive potential or a negative potential. Alternatively, the wiring CL1 and the wiring CL3 may be wirings that apply different potentials. Furthermore, the wiring CL2 is preferably a wiring that applies a constant potential. For example, the constant potential can be a positive potential.

[0219] In each of the third data retention circuits 161[1] to 161[k], one electrode of the capacitor 165 is illustrated as a node SN[1] to a node SN[k].

[0220] In the third data holding circuit group 160, a connection point between one of the source or drain of the transistor 162 and the other of the source or drain of the transistor 149 is referred to as a terminal TE4. A connection point between the other of the source or drain of the transistor 164 and the other of the source or drain of the transistor 146 and one of the source or drain of the transistor 166 is referred to as a terminal TE2.

[0221] In the plurality of third data hold circuits 161, the terminal TE3 functions as an output terminal when the inverter loop circuit 115 outputs data, and the terminal TE1 functions as an input terminal when writing data back to the inverter loop circuit 115.

[0222] The transistor 166 has a function of applying a precharge potential to a wiring connected to the transistor 166 in response to a signal PCB. For example, by setting the signal PCB to "L," the transistor 166 is turned on, and the precharge potential can be applied to a wiring connected to the terminal TE2. Note that the precharge potential is a read potential that is applied to a wiring connected to the terminal TE2 in advance when data is read from any one of the third data retention circuits 161[1] to 161[k]. Note that the transistor 166 is a p-channel type.

[0223] In the third data hold circuit 161[i] (where i is an integer between 1 and k), a signal BK[i] is applied to the gate of the transistor 162, and a signal RE[i] is applied to the gate of the transistor 164. The signal BK[i] is a signal for saving data held by the inverter loop circuit 115 in the third data hold circuit 161[i]. The signal RE[i] is a signal for loading the data held in the third data hold circuit 161[i] into the inverter loop circuit 115.

[0224] The transistors 162, 163, and 164 can be OS transistors. In FIG. 14B , the transistors 162, 163, and 164 are illustrated as transistors having back gates. By providing back gates to the transistors 162, 163, and 164 and supplying a constant voltage to the back gates, the transistor characteristics can be controlled. Among the transistors included in the second memory circuit 114b, at least the transistors 162, 163, and 164 are preferably OS transistors. OS transistors have an extremely low off-state current, which can suppress fluctuations in the voltages of the nodes SN[1] to SN[k] due to the off-state current. The third data retention circuit 161 consumes almost no power to retain data. The third data retention circuit 161 rewrites data by charging and discharging the capacitor 165. Therefore, in principle, there is no limit to the number of rewrite operations, and data can be written and read with low power consumption.

[0225] The OS transistor functions as a switch in the third data holding circuit 161. In an OS transistor, which is an n-channel transistor, a high-level signal “H” applied to the gate can bring the source and drain into a conductive state (ON), and a low-level signal “L” applied to the gate can bring the source and drain into a non-conductive state (OFF).

[0226] For example, by setting the signal BK[1]="H" and the signal EN="H" in the third data hold circuit 161[1], data held by the inverter loop circuit 115 can be written to the node SN[1] of the third data hold circuit 161[1]. Similarly, by setting the signal BK[k]="H" and the signal EN="H", data from the inverter loop circuit 115 can be written to the node SN[k] of the third data hold circuit 161[k]. Furthermore, by setting the signal RE[1]="H" and the signal EN="H", data from the node SN[1] of the third data hold circuit 161 can be written back to the inverter loop circuit 115. Similarly, by setting the signal RE[k]="H" and the signal EN="H", data from the node SN[k] of the third data hold circuit 161[k] can be written back to the inverter loop circuit 115.

[0227] It is highly preferable that all the transistors included in the plurality of third data retention circuits 161 in the third data retention circuit group 160 are OS transistors. By using OS transistors for all the transistors in the plurality of third data retention circuits 161, for example, as shown in FIG. 15 , the plurality of third data retention circuits 161 can be stacked on an inverter loop circuit 115 configured as a silicon CMOS circuit.

[0228] 15, the transistors 146 and 149 are illustrated as transistors that connect the inverter loop circuit 115 and the third data retention circuit group 160. The transistors 146 and 149 are not limited to OS transistors, and Si transistors can also be used.

[0229] The third data hold circuits 161 included in the third data hold circuit group 160 have a significantly smaller number of circuit elements than the inverter loop circuits 115. Therefore, it is not necessary to change the circuit configuration and layout of the inverter loop circuits 115 to form the third data hold circuit group 160. In other words, the third data hold circuits 161 included in the third data hold circuit group 160 can be said to be highly versatile. Furthermore, as shown in FIG. 15 , multiple third data hold circuits 161 can be stacked in a direction perpendicular to the surface on which the inverter loop circuits 115 are formed. Therefore, even if the number of third data hold circuits 161 stacked on the inverter loop circuits 115 is increased, the area overhead occupied by the third data hold circuit group 160 can be reduced to zero. Furthermore, the third data hold circuits 161 included in the third data hold circuit group 160 consume little power to hold data.

[0230] By providing the third data hold circuit 161, a parasitic capacitance due to the transistor 162 is added to the terminal TE4. However, by providing the transistor 149 between the terminal TE4 and the terminal TE3, the influence of this parasitic capacitance is reduced, and the operation of the inverter loop circuit 115 is hardly affected. Furthermore, by providing the third data hold circuit group 160, a parasitic capacitance due to the transistor 164 is added to the terminal TE2. However, by providing the transistor 146 between the terminal TE2 and the terminal TE1, the influence of this parasitic capacitance is reduced, and the operation of the inverter loop circuit 115 is hardly affected. In other words, even if a plurality of third data hold circuits 161 are provided, the performance of the second memory circuit 114b does not substantially deteriorate.

[0231] 16 illustrates the configuration of the second memory circuit 114b when the third data retention circuit group 160 includes four third data retention circuits 161, in order to explain the operation of the second memory circuit 114b. Specifically, the inverter loop circuit 115 in FIG. 16 has a circuit configuration similar to that of the inverter loop circuit 115 in FIG. 14B when k=4. FIG. 16 also illustrates nodes SN[1] to SN[4] that retain data in the third data retention circuits 161 (third data retention circuits 161[1] to third data retention circuits 161[4]) included in the third data retention circuit group 160. FIG. 16 also illustrates signals BK[1] to BK[4] and signals RE[1] to RE[4] that control the third data retention circuits 161[1] to third data retention circuits 161[4].

[0232] 17A to 17D are example timing charts illustrating the operation of the second memory circuit 114b illustrated in Fig. 16. Note that the contents described in Embodiment 1 can be referred to for the description of the operation of the inverter loop circuit 115 in the second memory circuit 114b.

[0233] 17A to 17D illustrate the fluctuations in the potentials of the signal DT, the signal DTB, the wiring WL, the wiring BL, the wiring BLB, the signal BK[1], the signal BK[2], the signal RE[1], the signal RE[2], the node SN[1], the node SN[2], the signal PCB, the node RO, the signal EN, and the signal BK[0]. The signal DT is a signal input to the terminal TE1 of the inverter loop circuit 115, and the signal DTB is a signal output from the terminal TE3 of the inverter loop circuit 115. Also, the initial values ​​are set as follows: signal DT="1", signal DTB="0", signal BK[1]="L", signal BK[2]="L", signal RE[1]="L", signal RE[2]="L", signal EN="L", wiring PCB="H", node RO="0", signal BK[0]="H". Note that in Figures 17A to 17D, V70 to V83 represent time.

[0234] 17A to 17D, the third data retention circuit 161[3] and the third data retention circuit 161[4] are not used, and therefore the potentials of the signals BK[3], BK[4], RE[3], and RE[4] are always set to L (not shown). The potentials of the nodes SN[3] and SN[4] are not particularly limited.

[0235] 17A to 17D, data is not written from the wirings BL and BLB to the inverter loop circuit 115, and data is not read from the inverter loop circuit 115 to the wirings BL and BLB, so that "L" is always applied to the wiring WL. In addition, the potentials of the wirings BL and BLB are not particularly limited, so that the potentials of the wirings BL and BLB are shown hatched with diagonal lines in FIGS. 17A to 17D to indicate that the respective potentials are indefinite.

[0236] Similarly, in the operation examples shown in each of Figures 17A to 17D, during the period when the potentials of nodes SN[1] and SN[2] are not limited, diagonal hatching is shown to indicate that the respective potentials are indefinite.

[0237] 18A to 18E are schematic diagrams of the second memory circuit 114b for explaining the operation in the timing charts of FIG. 17A to 17D. FIG. 18A illustrates the inverter loop circuit 115 and the third data retention circuits 161[1] to 161[4] of the third data retention circuit group 160. FIG. 18B to 18E illustrate the inverter loop circuit 115 and the third data retention circuits 161[1] to 161[4] of the third data retention circuit group 160 at time V81 in FIG. 17A, time V74 in FIG. 17B, time V77 in FIG. 17C, and time V81 in FIG. 17D.

[0238] The timing chart of FIG. 17A shows an example of an operation in which the logic of data with a logical value of “1” held in the inverter loop circuit 115 is inverted and stored in the third data holding circuit 161[1].

[0239] Also, assume that the signal PCB of “H” is applied to the second memory circuit 114b from time V70 to time V72, so that the transistor 166 is turned off, and there is no conduction between the line CL2 and the node RO.

[0240] Furthermore, between time V70 and time V72, signals RE[1] to RE[4] are set to "L" to the third data retention circuits 161[1] to 161[4], respectively. As a result, between time V70 and time V72, the transistors 164 of the third data retention circuits 161[1] to 161[4] are turned off.

[0241] Furthermore, between time V70 and time V72, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, causing inverter loop circuit 115 to hold data. Note that in the timing chart of FIG. 17A, it is assumed that the data held is a logical "1." At this time, terminal TE1 of inverter loop circuit 115 outputs a logical "1" as signal DT, and terminal TE3 of inverter loop circuit 115 outputs a logical "0" as signal DTB.

[0242] Between time V70 and time V71, a signal EN of "L" is applied to the gates of the transistors 146 and 149, and the transistors 146 and 149 are turned off.

[0243] Between time V71 and time V72, a signal EN of "H" is provided to the gates of the transistors 146 and 149, turning on the transistors 146 and 149. At this time, the signal DTB output from the terminal TE3 of the inverter loop circuit 115 is input to the third data hold circuits 161[1] to 161[4] via the terminal TE4. The signal DT output from the terminal TE1 of the inverter loop circuit 115 is input to the third data hold circuits 161[1] to 161[4] via the terminal TE2.

[0244] Furthermore, between time V71 and time V72, a signal BK[1] of "H" is provided to the third data retention circuit 161[1], and signals BK[2] to BK[4] of "L" are provided to the third data retention circuits 161[2] to 161[4]. This causes the transistor 162 of the third data retention circuit 161[1] to be turned on, and the transistors 162 of the third data retention circuits 161[2] to 161[4] to be turned off. Therefore, the signal DTB output from the terminal TE3 of the inverter loop circuit 115 is stored in the third data retention circuit 161[1] (see FIG. 18B). Specifically, a logical value of "0" is stored in the node SN[1] of the third data retention circuit 161[1]. At this time, it should be noted that the logical value of the data held by the inverter loop circuit 115 (data output from terminal TE1) and the logical value held at node SN[1] of the third data holding circuit 161[1] are inverted in logic to each other.

[0245] After time V72, a signal BK[1] of "L" is provided to the gate of the transistor 162 of the third data hold circuit 161[1], turning off the transistor 162 of the third data hold circuit 161[1]. This completes the storage of the logical value "0" in the node SN[1] of the third data hold circuit 161[1]. Furthermore, a signal EN of "L" is provided to the gates of the transistors 146 and 149, turning off the transistors 146 and 149.

[0246] 18B shows an example of an operation in which the logic of data with a logical value of "1" held in the inverter loop circuit 115 is inverted and stored in the third data hold circuit 161[1]. Also, FIG. 18B shows an example in which data D1 is held in the third data hold circuit 161[1] as a logical value of "0".

[0247] The timing chart of FIG. 17B shows an example of an operation in which the logical value “0” held in the inverter loop circuit 115 is stored in the third data holding circuit 161[2].

[0248] Also, assume that the signal PCB of “H” is supplied to the second memory circuit 114b from time V73 to time V75, so that the transistor 166 is turned off, and there is no conduction between the line CL2 and the node RO.

[0249] Furthermore, between time V73 and time V75, signals RE[1] to RE[4] are set to "L" to the third data retention circuits 161[1] to 161[4], respectively. As a result, between time V73 and time V75, the transistors 164 of the third data retention circuits 161[1] to 161[4] are turned off.

[0250] Furthermore, between time V73 and time V75, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, causing inverter loop circuit 115 to hold data. Note that in the timing chart of FIG. 17B, it is assumed that the logical value "0" is being held as the data. Also, at this time, terminal TE1 of inverter loop circuit 115 outputs a logical value "0" as signal DT, and terminal TE3 of inverter loop circuit 115 outputs a logical value "1" as signal DTB.

[0251] Between time V73 and time V74, a signal EN of "L" is applied to the gates of the transistors 146 and 149, and the transistors 146 and 149 are turned off.

[0252] Between time V74 and time V75, a signal EN of "H" is provided to the gates of the transistors 146 and 149, turning on the transistors 146 and 149. At this time, the signal DTB output from the terminal TE3 of the inverter loop circuit 115 is input to the third data hold circuits 161[1] to 161[4] via the terminal TE4. The signal DT output from the terminal TE1 of the inverter loop circuit 115 is input to the third data hold circuits 161[1] to 161[4] via the terminal TE2.

[0253] Furthermore, between time V74 and time V75, "H" is provided as the signal BK[2] to the third data hold circuit 161[2], and "L" is provided as the signals BK[1], BK[3], and BK[4] to the third data hold circuit 161[1], the third data hold circuit 161[3], and the third data hold circuit 161[4], respectively. As a result, the transistor 162 of the third data hold circuit 161[2] is turned on, and the transistors 162 of the third data hold circuit 161[1], the third data hold circuit 161[3], and the third data hold circuit 161[4] are turned off. Therefore, the signal DTB output from the terminal TE3 of the inverter loop circuit 115 is stored in the third data hold circuit 161[2] (see FIG. 18C ). Specifically, the logical value "1" is stored in the node SN[2] of the third data hold circuit 161[2]. At this time, it should be noted that the logical value of the data held by the inverter loop circuit 115 (the data output from the terminal TE1) and the logical value held in the node SN[2] of the third data hold circuit 161[2] are inverted in logic to each other.

[0254] After time V75, a signal BK[2] of "L" is provided to the gate of the transistor 162 of the third data hold circuit 161[2], turning off the transistor 162 of the third data hold circuit 161[2]. This completes the storage of the logical value "1" in the node SN[2] of the third data hold circuit 161[2]. Furthermore, a signal EN of "L" is provided to the gates of the transistors 146 and 149, turning off the transistors 146 and 149.

[0255] 18C shows an example of an operation in which the logic of data with a logical value of "0" held in the inverter loop circuit 115 is inverted and stored in the third data hold circuit 161[2]. Also, FIG. 18C shows an example in which data D2 is held in the third data hold circuit 161[2] as a logical value of "1".

[0256] The timing chart of FIG. 17C shows an example of an operation in which the logic of the data with a logical value of “0” held in the third data holding circuit 161[1] is inverted and restored to the inverter loop circuit 115.

[0257] Furthermore, between time V76 and time V79, signals BK[1] to BK[4] of "L" are provided to the third data retention circuits 161[1] to 161[4], respectively. As a result, between time V76 and time V79, the transistors 162 of the third data retention circuits 161[1] to 161[4] are turned off.

[0258] Also, before time V76, the inverter loop circuit 115 is assumed to hold a logical value of "0." Specifically, "H" is provided to the gate of the transistor 142 as the signal BK[0], turning the transistor 142 on. As a result, conduction occurs between the input terminal of the first inverter 200 and the output terminal of the second inverter 201, and the inverter loop circuit 115 is in a state of holding data. Furthermore, the terminal TE1 of the inverter loop circuit 115 outputs a logical value of "0" as the signal DT, and the terminal TE3 of the inverter loop circuit 115 outputs a logical value of "1" as the signal DTB.

[0259] Between time V76 and time V77, a signal EN of "L" is applied to the gates of the transistors 146 and 149, and the transistors 146 and 149 are turned off.

[0260] Also, from time V76 to time V77, it is assumed that "L" is applied to the gate of the transistor 166 as the signal PCB. Therefore, the transistor 166 is turned on, and conduction is established between the line CL2 and the node RO. As a result, "H" is applied to the node RO as a precharge potential from the line CL2.

[0261] Thereafter, from time V77 to time V78, it is assumed that a signal PCB of "H" is applied to the gate of the transistor 166. As a result, the transistor 166 is turned off, and a non-conductive state is established between the wiring CL2 and the node RO. As a result, the node RO is in a floating state.

[0262] Furthermore, between time V77 and time V78, a signal BK[0] of "L" is applied to the gate of the transistor 142, turning the transistor 142 off. This causes a non-conductive state between the input terminal of the first inverter 200 and the output terminal of the second inverter 201.

[0263] Between time V77 and time V78, a signal EN of "H" is applied to the gates of the transistors 146 and 149, turning on the transistors 146 and 149. This brings the terminal TE1 and the terminal TE2 (node ​​RO) into a conductive state.

[0264] Furthermore, between time V77 and time V78, "H" is provided as the signal RE[1] to the third data retention circuit 161[1], and "L" is provided as the signals BK[2] to BK[4] to the third data retention circuits 161[2] to 161[4]. As a result, the transistor 164 of the third data retention circuit 161[1] is turned on, and the transistors 164 of the third data retention circuits 161[2] to 161[4] are turned off. As a result, one of the source and the drain of the transistor 163 of the third data retention circuit 161[1] is brought into conduction with the terminal TE1 and the terminal TE2 (node ​​RO).

[0265] Furthermore, since the node SN[1] holds a potential of "L" corresponding to the logical value of "0", the transistor 163 is turned off. That is, there is no conduction between the node RO and the wiring CL3.

[0266] At this time, since terminal TE1 and terminal TE2 (node ​​RO) are both in a floating state, terminal TE1 and terminal TE2 (node ​​RO) become conductive to each other, and charge is redistributed between terminal TE1 and terminal TE2 (node ​​RO). As a result, the potential of terminal TE1 rises from "L". Also, the potential of terminal TE2 (node ​​RO) drops.

[0267] Furthermore, in the inverter loop circuit 115, the potential of the input terminal (terminal TE1) of the first inverter 200 rises, and therefore "L" indicating a logical value "0" is output from the output terminal of the first inverter 200. Furthermore, the logical value "0" output from the output terminal of the first inverter 200 is input to the input terminal of the second inverter 201, and "H" indicating a logical value "1" is output from the output terminal of the second inverter 201.

[0268] Between time V78 and time V79, a signal EN of "L" is applied to the gates of the transistors 146 and 149, turning off the transistors 146 and 149. This brings the state of non-conduction between the terminal TE1 and the terminal TE2 (node ​​RO).

[0269] Furthermore, between time V78 and time V79, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, and "H" indicating a logical value "1" output from the output terminal of second inverter 201 is input to the input terminal of first inverter 200. As a result, data obtained by inverting the logical value of the data of logical value "0" held by third data hold circuit 161[1] is restored to inverter loop circuit 115. Also, at this time, terminal TE1 of inverter loop circuit 115 outputs a logical value "1" as signal DT, and terminal TE3 of inverter loop circuit 115 outputs a logical value "0" as signal DTB.

[0270] Furthermore, between time V78 and time V79, "L" is provided as the signal RE[1] to the third data hold circuit 161[1], and the transistor 164 of the third data hold circuit 161[1] is turned off. As a result, one of the source and drain of the transistor 163 of the third data hold circuit 161[1] is not conductive with the node RO. This completes the restoration of data from the third data hold circuit 161[1] to the inverter loop circuit 115.

[0271] 18D shows an example in which the logic value of the data held by the third data holding circuit 161[1], which is "0", is inverted and written back to the inverter loop circuit 115.

[0272] The timing chart of FIG. 17D shows an example of an operation in which the logic of data D1 with a logical value of “1” held in the third data holding circuit 161[2] is inverted and restored to the inverter loop circuit 115.

[0273] Furthermore, between time V80 and time V83, signals BK[1] to BK[4] of "L" are provided to the third data retention circuits 161[1] to 161[4], respectively, so that the transistors 162 of the third data retention circuits 161[1] to 161[4] are turned off between time V80 and time V83.

[0274] Also, before time V80, the inverter loop circuit 115 is assumed to hold a logical value of "1." Specifically, "H" is provided to the gate of the transistor 142 as the signal BK[0], turning the transistor 142 on. As a result, conduction occurs between the input terminal of the first inverter 200 and the output terminal of the second inverter 201, and the inverter loop circuit 115 is in a state of holding data. Furthermore, the terminal TE1 of the inverter loop circuit 115 outputs a logical value of "1" as the signal DT, and the terminal TE3 of the inverter loop circuit 115 outputs a logical value of "0" as the signal DTB.

[0275] Between time V80 and time V81, a signal EN of "L" is applied to the gates of the transistors 146 and 149, and the transistors 146 and 149 are turned off.

[0276] Also, from time V80 to time V81, it is assumed that "L" is applied to the gate of the transistor 166 as the signal PCB. Therefore, the transistor 166 is turned on, and conduction is established between the line CL2 and the node RO. As a result, "H" is applied to the node RO as a precharge potential from the line CL2.

[0277] Thereafter, from time V81 to time V82, it is assumed that a signal PCB of "H" is applied to the gate of the transistor 166. As a result, the transistor 166 is turned off, and a non-conductive state is established between the wiring CL2 and the node RO. As a result, the node RO is in a floating state.

[0278] Between time V81 and time V82, a signal BK[0] of "L" is applied to the gate of the transistor 142, turning the transistor 142 off. This causes a non-conductive state between the input terminal of the first inverter 200 and the output terminal of the second inverter 201.

[0279] Between time V81 and time V82, a signal EN of "H" is applied to the gates of the transistors 146 and 149, turning on the transistors 146 and 149. This brings the terminal TE1 and the terminal TE2 (node ​​RO) into a conductive state.

[0280] Furthermore, between time V81 and time V82, "H" is provided as the signal RE[2] to the third data hold circuit 161[2], and "L" is provided as the signals BK[1], BK[3], and BK[4] to the third data hold circuit 161[1], the third data hold circuit 161[3], and the third data hold circuit 161[4], respectively. As a result, the transistor 164 of the third data hold circuit 161[2] is turned on, and the transistors 164 of the third data hold circuit 161[1], the third data hold circuit 161[3], and the third data hold circuit 161[4] are turned off. As a result, one of the source and the drain of the transistor 163 of the third data hold circuit 161[2] is electrically connected to the terminal TE1 and the terminal TE2 (node ​​RO).

[0281] Furthermore, since the node SN[2] holds a potential of "H" corresponding to the logical value "1", the transistor 163 is turned on. That is, conduction is established between the node RO and the wiring CL3.

[0282] As a result, the line CL3, the node RO (terminal TE2), and the terminal TE1 are electrically connected to each other. As a result, the charges stored in the node RO (terminal TE2) and the terminal TE1 flow to the line CL3. As a result, the potentials of the node RO (terminal TE2) and the terminal TE1 become L.

[0283] Furthermore, in the inverter loop circuit 115, the potential of the input terminal (terminal TE1) of the first inverter 200 drops, and therefore "H" indicating a logical value "1" is output from the output terminal of the first inverter 200. Furthermore, the logical value "1" output from the output terminal of the first inverter 200 is input to the input terminal of the second inverter 201, and "L" indicating a logical value "0" is output from the output terminal of the second inverter 201.

[0284] Between time V82 and time V83, a signal EN of "L" is applied to the gates of the transistors 146 and 149, turning off the transistors 146 and 149. This brings the terminal TE1 and the terminal TE2 (node ​​RO) into a non-conductive state.

[0285] Furthermore, between time V82 and time V83, "H" is applied to the gate of transistor 142 as signal BK[0], turning transistor 142 on. This establishes conduction between the input terminal of first inverter 200 and the output terminal of second inverter 201, and "L" indicating a logical value "0" output from the output terminal of second inverter 201 is input to the input terminal of first inverter 200. As a result, data obtained by inverting the logical value of the data of logical value "1" held by third data hold circuit 161[2] is restored to inverter loop circuit 115. Also, at this time, terminal TE1 of inverter loop circuit 115 outputs a logical value "0" as signal DT, and terminal TE3 of inverter loop circuit 115 outputs a logical value "1" as signal DTB.

[0286] Furthermore, between time V82 and time V83, "L" is provided as the signal RE[2] to the third data hold circuit 161[2], and the transistor 164 of the third data hold circuit 161[2] is turned off. As a result, one of the source and drain of the transistor 163 of the third data hold circuit 161[2] is not conductive with the node RO. This completes the restoration of data from the third data hold circuit 161[2] to the inverter loop circuit 115.

[0287] 18E shows an example in which the logic of data D2, which is held in the third data holding circuit 161[2] and has a logical value of “1”, is inverted and written back to the inverter loop circuit 115.

[0288] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0289] (Embodiment 3) In this embodiment, a structure of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0290] 19 shows a part of a cross-sectional structure of a semiconductor device. The semiconductor device shown in FIG. 19 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 20A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 20B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 20C is a cross-sectional view of the transistor 550 in the channel width direction. For example, the transistor 500 corresponds to the Si transistor described in the above embodiment, and the transistor 550 corresponds to an OS transistor.

[0291] In FIG. 19, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0292] The transistor 550 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions.

[0293] 20C , in the transistor 550, the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. By forming the transistor 550 as a Fin type in this manner, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0294] The transistor 550 may be either a p-channel type or an n-channel type.

[0295] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A structure using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0296] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0297] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0298] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0299] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0300] The SOI substrate may be a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have occurred in the surface layer, or an SOI substrate formed using a Smart Cut method or an ELTRAN method (registered trademark: Epitaxial Layer Transfer) that cleaves a semiconductor substrate by utilizing growth by heat treatment of microvoids formed by hydrogen ion implantation. A transistor formed using a single crystal substrate has a single crystal semiconductor in a channel formation region.

[0301] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order to cover the transistor 550 .

[0302] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0303] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0304] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0305] The insulator 324 is preferably a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 550 to a region where the transistor 500 is provided.

[0306] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0307] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, in the TDS analysis, the amount of desorption of hydrogen from the insulator 324 is calculated as 1×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. and the amount of desorption converted into hydrogen atoms is 1×10 １６ atoms / cm ２ Below 5 × 10, preferably １５ atoms / cm ２ It is preferable to do the following:

[0308] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0309] Furthermore, the insulators 320, 322, 324, and 326 are embedded with the capacitor 600 or the conductors 328 and 330 connected to the transistor 500. The conductors 328 and 330 function as plugs or wiring. Furthermore, a plurality of conductors functioning as plugs or wiring may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0310] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the plug and wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0311] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 19 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0312] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0313] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0314] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 19 , an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using the same material as the conductors 328 and 330.

[0315] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0316] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 19 , an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be formed using a material similar to that of the conductors 328 and 330.

[0317] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0318] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 19 , an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be formed using a material similar to that of the conductors 328 and 330.

[0319] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0320] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0321] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like.

[0322] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0323] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0324] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0325] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0326] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0327] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 described later), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that of the conductors 328 and 330.

[0328] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0329] Above the insulator 516, the transistor 500 is provided.

[0330] As shown in Figures 20A and 20B, the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping with the conductors 542a and 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the surface on which the insulator 545 is formed.

[0331] 20A and 20B, it is preferable that an insulator 544 be arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is also preferable that the conductor 560 have a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is also preferable that an insulator 574 be arranged on the insulator 580, the conductor 560, and the insulator 545, as shown in FIG.

[0332] In this specification and other places, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0333] Although the transistor 500 has a structure in which two layers of the oxide 530a and the oxide 530b are stacked in the region where a channel is formed and in the vicinity thereof, the present invention is not limited to this structure. For example, the oxide 530b may be a single layer or a stack of three or more layers.

[0334] Although the transistor 500 has a two-layer structure in which the conductor 560 is stacked, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 shown in FIGS. 19 and 20A is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0335] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The conductors 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0336] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0337] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0338] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0339] In this specification, etc., a transistor structure in which a channel formation region is electrically surrounded by the electric field of a first gate electrode is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification, etc., is different from a Fin structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc., can also be regarded as a type of Fin structure. In this specification, etc., a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of a channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0340] By forming the transistor in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore, can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be the entire bulk. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current of the transistor or the field-effect mobility of the transistor.

[0341] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inside. Note that although the transistor 500 shows a structure in which the conductors 503a and 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0342] Here, the conductor 503a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and the oxygen.

[0343] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, which can suppress the conductor 503b from being oxidized and causing a decrease in conductivity.

[0344] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated as a stack of the conductors 503a and 503b in this embodiment, the conductor 503 may have a single-layer structure.

[0345] The insulators 520, 522, and 524 function as a second gate insulating film.

[0346] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen." That is, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V Ｏ When hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V Ｏ H.) may function as a donor and generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. ＯIn order to obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygenation treatment"). Ｏ When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0347] Specifically, it is preferable to use an oxide material from which part of the oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen, converted into oxygen atoms, is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0348] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VoH bond, in other words, "V Ｏ H → V Ｏ The reaction "+H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time combines with oxygen to form H ２ As O, it may be removed from the oxide 530 or from an insulator near the oxide 530. Also, some of the hydrogen may be gettered to the conductor 542.

[0349] Furthermore, the microwave treatment is preferably performed using, for example, an apparatus having a power supply for generating high-density plasma or an apparatus having a power supply for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530. The microwave treatment may be performed under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. For example, oxygen and argon are used as gases to be introduced into the microwave treatment apparatus, and the oxygen flow ratio (O ２ / (O ２ +Ar)) is preferably 50% or less, and more preferably 10% or more and 30% or less.

[0350] Furthermore, in the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 530, thereby eliminating oxygen vacancies (V Ｏ ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0351] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, ＯFurthermore, the reaction of the supplied oxygen with the hydrogen remaining in the oxide 530 can be accelerated to convert the hydrogen into H ２ As a result, hydrogen remaining in the oxide 530 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed.

[0352] Furthermore, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (that is, the insulator 524 is less likely to transmit oxygen).

[0353] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524, the oxide 530, and the like can be suppressed.

[0354] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ It is preferable to use an insulator containing a so-called high-k material such as (BST) in a single layer or a laminated layer. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulating films. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0355] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., the oxygen is less likely to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0356] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0357] Furthermore, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0358] 20A and 20B , the second gate insulating film has a three-layer structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0359] The transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) can be used as the oxide 530.

[0360] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an atomic layer deposition (ALD) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0361] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap in this manner, the off-state current of the transistor can be reduced.

[0362] By having the oxide 530a below the oxide 530b, the oxide 530 can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0363] The oxide 530 preferably has a configuration of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to M in the metal oxide used for the oxide 530a.

[0364] The oxide 530a preferably has a conduction band minimum energy higher than that of the oxide 530b, or in other words, the oxide 530a preferably has a lower electron affinity than that of the oxide 530b.

[0365] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxide 530a and the oxide 530b. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0366] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, or a gallium oxide can be used as the oxide 530a.

[0367] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0368] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on the oxide 530b. The conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or alloys containing the above metal elements or alloys combining the above metal elements. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, or the like are preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0369] 20A shows the conductor 542a and the conductor 542b as a single layer, they may also be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may also be used.

[0370] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0371] 20A , regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source and drain regions, and the region 543b functions as the other of the source and drain regions. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0372] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0373] The insulator 544 is provided to cover the conductors 542 a and 542 b and suppresses oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0374] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0375] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than a hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later step. Note that if the conductors 542a and 542b are made of an oxidation-resistant material or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0376] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. Furthermore, the insulator 580 can prevent excess oxygen from oxidizing the conductor 542.

[0377] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0378] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0379] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0380] Furthermore, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0381] Note that the insulator 545 may have a stacked structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulating films. Therefore, by using a stacked structure of a high-k material and a thermally stable material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a stacked structure that is thermally stable and has a high dielectric constant can be achieved.

[0382] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 20A and 20B, but may have a single-layer structure or a stacked structure of three or more layers.

[0383] The conductor 560a is a material containing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms, etc., or that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). The conductor 560a has the function of suppressing oxygen diffusion, which can suppress the oxidation of the conductor 560b due to the oxygen contained in the insulator 545, thereby preventing a decrease in conductivity. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material that has the function of suppressing oxygen diffusion. Furthermore, an oxide semiconductor that can be used for the oxide 530 can be used as the conductor 560a. In this case, the electrical resistance of the conductor 560a can be reduced by forming the conductor 560b by a sputtering method, thereby making the conductor 560a a conductor. This can be called an oxide conductor (OC) electrode.

[0384] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0385] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because an excess oxygen region can be easily formed in a later step.

[0386] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0387] The opening of the insulator 580 is formed to overlap the region between the conductor 542 a and the conductor 542 b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542 a and the conductor 542 b.

[0388] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased for this purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, and therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0389] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0390] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium.

[0391] In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as an oxygen source and also as a barrier film against impurities such as hydrogen.

[0392] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0393] Furthermore, the conductor 540a and the conductor 540b are arranged in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same structure as the conductor 546 and the conductor 548, which will be described later.

[0394] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0395] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0396] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0397] In addition, in FIG. 19, conductors 546, conductors 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0398] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0399] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0400] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0401] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0402] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0403] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0404] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0405] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape below it.

[0406] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0407] Examples of a substrate that can be used for the semiconductor device of one embodiment of the present invention include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, etc.), a semiconductor substrate (e.g., a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), an SOI (Silicon on Insulator) substrate, and the like. A plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may also be used. Examples of a glass substrate include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Alternatively, crystallized glass or the like can be used.

[0408] Alternatively, a flexible substrate, a laminated film, paper containing a fibrous material, a base film, or the like can be used as the substrate. Examples of flexible substrates, laminated films, base films, and the like include the following: For example, plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) are available. Another example is synthetic resins such as acrylic. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Another example is polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, or paper. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, it is possible to manufacture transistors with small size, high current capability, and little variation in characteristics, size, or shape. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0409] Alternatively, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistors, resistors, and / or capacitors. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer it to another substrate. In this case, the transistors, resistors, and / or capacitors can be transferred to a substrate with poor heat resistance, a flexible substrate, or the like. The release layer may be, for example, a laminated structure of an inorganic film including a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0410] That is, the semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which the semiconductor device may be transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, and rubber substrates. By using these substrates, it is possible to manufacture semiconductor devices that are flexible, durable, heat-resistant, lightweight, or thin.

[0411] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0412] 20 is just an example and is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit structure, driving method, etc. For example, when the semiconductor device is a unipolar circuit including only OS transistors (meaning transistors with the same polarity, such as only n-channel transistors), the structure of the transistor 550 may be the same as that of the transistor 500.

[0413] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiment modes and examples.

[0414] Embodiment 4 In this embodiment, an example of a chip including a semiconductor device according to one embodiment of the present invention and an example of a module for an electronic device will be described.

[0415] FIG. 21A is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer.

[0416] 21A , a chip 751 corresponding to a semiconductor device according to one embodiment of the present invention is connected to terminals 752 on an interposer 750 by wire bonding. The terminals 752 are arranged on the surface of the interposer 750 on which the chip 751 is mounted. The chip 751 may be sealed with a mold resin 753, but the sealing is performed in a state where a portion of each terminal 752 is exposed.

[0417] The configuration of an electronic device module in which a package is mounted on a circuit board is shown in FIG. 21B.

[0418] 21B has a package 802 and a battery 804 mounted on a printed wiring board 801. The printed wiring board 801 is mounted by an FPC 803 on a panel 800 provided with a display element.

[0419] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0420] (Embodiment 5) A semiconductor device according to one embodiment of the present invention can be used in a display device, a personal computer, or an image playback device equipped with a recording medium (typically, a device having a display capable of playing back a recording medium such as a DVD (Digital Versatile Disc) and displaying the image). Other examples of electronic devices that can use a semiconductor device according to one embodiment of the present invention include mobile phones, game consoles including portable ones, personal digital assistants, e-book readers, video cameras, cameras such as digital still cameras, goggle displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 22 .

[0421] 22A illustrates a portable game console, which includes a housing 5001, a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, a speaker 5006, operation keys 5007, a stylus 5008, and the like. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the portable game console. Note that although the portable game console illustrated in FIG. 22A includes two display portions, 5003 and 5004, the number of display portions included in the portable game console is not limited to this.

[0422] 22B illustrates a portable information terminal including a first housing 5101, a second housing 5102, a first display portion 5103, a second display portion 5104, a connection portion 5105, operation keys 5106, and the like. The first display portion 5103 is provided in the first housing 5101, and the second display portion 5104 is provided in the second housing 5102. The first housing 5101 and the second housing 5102 are connected to each other by a connection portion 5105, and the angle between the first housing 5101 and the second housing 5102 can be changed by the connection portion 5105. An image displayed on the first display portion 5103 may be switched depending on the angle between the first housing 5101 and the second housing 5102 at the connection portion 5105. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the portable information terminal. A display device having a function as a position input device may be used for at least one of the first display portion 5103 and the second display portion 5104. The function as the position input device can be added by providing a touch panel to the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device.

[0423] 22C shows a laptop personal computer including a housing 5201, a display portion 5202, a keyboard 5203, a pointing device 5204, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the laptop personal computer.

[0424] 22D shows an automobile including a body 5301, wheels 5302, a dashboard 5303, and lights 5304. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the automobile.

[0425] 22E illustrates a video camera including a first housing 5401, a second housing 5402, a display portion 5403, operation keys 5404, a lens 5405, a connection portion 5406, and the like. The operation keys 5404 and the lens 5405 are provided in the first housing 5401, and the display portion 5403 is provided in the second housing 5402. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the video camera. The first housing 5401 and the second housing 5402 are connected by a connection portion 5406, and the angle between the first housing 5401 and the second housing 5402 can be changed by the connection portion 5406. An image on the display portion 5403 may be switched depending on the angle between the first housing 5401 and the second housing 5402 at the connection portion 5406.

[0426] 22F shows an electric refrigerator-freezer, which includes a housing 5501, a refrigerator door 5502, a freezer door 5503, and the like. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the electric refrigerator-freezer.

[0427] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiment modes and examples.

[0428] Embodiment 6 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0429] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0430] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0431] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 23A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 23B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0432] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 23B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 23A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 23A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 23A.

[0433] 23A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0434] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0435] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0436] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0437] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 23A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0438] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0439] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0440] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0441] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0442] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0443] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0444] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0445] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0446] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0447] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 23C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ In some cases, oxygen atoms are released as oxygen vacancies (Vo) in the film. If oxygen vacancies (Vo) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0448] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0449] Furthermore, as shown in FIG. 23C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0450] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0451] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0452]

[0453] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0454] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0455] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0456] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0457] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0458] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0459] [Additional Notes Regarding the Description of the Present Specification, etc.] The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0460] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0461] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0462] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0463] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0464] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0465] Furthermore, in this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0466] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0467] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0468] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0469] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0470] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0471] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0472] In this specification, the channel length refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a top view of a transistor, or a distance between a source and a drain in a region where a channel is formed.

[0473] In this specification and the like, the channel width refers to, for example, the length of a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is in an on-state) and a gate electrode overlap, or the length of a portion where a source and a drain face each other in a region where a channel is formed.

[0474] In this specification, "connection" includes, as an example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, as examples, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0475] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0476] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 24A1 and 24A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 24A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0477] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 24A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 24A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0478] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 24A6 and 24A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 24A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 24A6 and 24A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0479] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0480] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 24B1, 24B2, and 24B3. When A and B are connected to a power supply that supplies a constant potential V or GND without any circuit element between them, as shown in FIGS. 24B4 and 24B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 24B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0481] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0482] BK[0]: Signal, BK[1]: Signal, BK[2]: Signal, BK[3]: Signal, BK[4]: Signal, BK[i]: Signal, BK[k]: Signal, BK: Signal, BL: Wiring, BLB: Wiring, CL: Wiring, CLK: Clock signal, DF: Input terminal, DT: Signal, DTB: Signal, EN: Signal, QF: Output terminal, RE[1]: Signal, RE[2]: Signal, RE[3]: Signal, RE[4]: Signal, RE[i]: Signal, RE[k]: Signal, RE: Signal, RO: Node, SD: Terminal, SD_IN: Terminal, SE: Signal, SN[1]: Node, SN[2]: Node, SN[3]: Node, SN[4]: Node, SN[k]: Node, T70: Time, T71: Time, T72: Time, T73: Time, T74: Time, T75: Time, T76: Time, T77: Time, T78: Time, T79: Time, T80: Time, T81: Time, Ta: Time, Tb: Time, Tc: Time time, TrP: transistor, TrQ: transistor, U70: time, U71: time, U72: time, U73: time, U74: time, U75: time, U76: time, U77: time, U78: time, U79: time, U80: time, U81: time, U82: time, U83: time, V70 : time, V71: time, V72: time, V73: time, V74: time, V75: time, V76: time, V77: time, V78: time, V79: time, V80: time, V81: time, V82: time, V83: time, Vg: voltage, Vth: threshold voltage, WL: wiring, 100: semiconductor device, 101: state control unit, 102: processor core, 103: register unit, 104: arithmetic unit, 105: register bank, 106: register, 110: first memory circuit, 113: cache unit, 114a: second memory circuit, 114b: second memory circuit, 115: inverter loop circuit 120: scan flip-flop, 121: selector, 122: flip-flop circuit, 130: first data hold circuit group, 131[1]: first data hold circuit, 131[2]: first data hold circuit, 131[3]: first data hold circuit, 131[4]: first data hold circuit, 131[i]: first data hold circuit, 131[k]: first data hold circuit, 131: first data hold circuit, 132: transistor, 133: transistor, 134: transistor, 135: capacitor, 140: second data hold circuit group, 141[1]: second data hold circuit,141[2]: second data hold circuit, 141[3]: second data hold circuit, 141[4]: second data hold circuit, 141[i]: second data hold circuit, 141[k]: second data hold circuit, 141: second data hold circuit, 142: transistor, 143: transistor, 144: transistor, 145: capacitor, 146: transistor, 147: transistor, 148: transistor, 149: transistor, 150: transistor, 160: third data hold circuit group, 161[1]: third data hold circuit, 161[2]: third data hold circuit, 16 1[3]: third data retention circuit, 161[4]: third data retention circuit, 161[i]: third data retention circuit, 161[k]: third data retention circuit, 161: third data retention circuit, 162: transistor, 163: transistor, 164: transistor, 165: capacitor, 166: transistor, 200: first inverter, 201: second inverter, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 32 8: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 530: Acid oxide, 530a: oxide, 530b: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 545: insulator, 546: conductor, 548: conductor, 550: transistor, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitor, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 750: interposer,751: Chip, 752: Terminal, 753: Molding resin, 800: Panel, 801: Printed wiring board, 802: Package, 803: FPC, 804: Battery, 5001: Housing, 5002: Housing, 5003: Display unit, 5004: Display unit, 5005: Microphone, 5006: Speaker, 5007: Operation keys, 5008: Stylus, 5101: First housing, 5102: Second housing, 5103: First display unit, 5104: Table 2 display unit, 5105: connection unit, 5106: operation keys, 5201: housing, 5202: display unit, 5203: keyboard, 5204: pointing device, 5301: body, 5302: wheels, 5303: dashboard, 5304: lights, 5401: first housing, 5402: second housing, 5403: display unit, 5404: operation keys, 5405: lens, 5406: connection unit, 5501: housing, 5502: refrigerator compartment door, 5503: freezer compartment door,

Claims

a state control unit, a register unit having a first storage circuit, and a cache unit having a second storage circuit; the first memory circuit includes a flip-flop circuit and a first data retention circuit; the second memory circuit includes an inverter loop circuit and a second data holding circuit; the flip-flop circuit includes a first transistor including silicon in a semiconductor layer in which a channel is formed; the first data retention circuit includes a second transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed; the inverter loop circuit includes a third transistor including silicon in a semiconductor layer in which a channel is formed; the second data retention circuit includes a fourth transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed; the first memory circuit has a function of holding, in the first data holding circuit, first data output by the flip-flop circuit in response to a first signal supplied from the state control unit, and a function of outputting, to the flip-flop circuit, the first data held in the first data holding circuit in response to a second signal supplied from the state control unit; The second memory circuit has a function of holding, in the second data holding circuit, second data output by the inverter loop circuit in response to the first signal supplied from the state control unit, and a function of outputting, to the inverter loop circuit, the second data held in the second data holding circuit in response to the second signal supplied from the state control unit. 　 In claim 1, the flip-flop circuit and the first data retention circuit have overlapping regions; The inverter loop circuit and the second data holding circuit have overlapping regions. 　 In claim 1 or claim 2, The oxide semiconductor included in one or both of the second transistor and the fourth transistor contains indium. 　 a state control unit, a register unit having a plurality of first storage circuits, and a cache unit having a plurality of second storage circuits; each of the plurality of first memory circuits includes a flip-flop circuit and a plurality of first data retention circuits; each of the plurality of second memory circuits includes an inverter loop circuit and a plurality of second data retention circuits; the flip-flop circuit includes a first transistor including silicon in a semiconductor layer in which a channel is formed; each of the plurality of first data retention circuits includes a second transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed; the inverter loop circuit includes a third transistor including silicon in a semiconductor layer in which a channel is formed; each of the plurality of second data retention circuits includes a fourth transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed; each of the plurality of first memory circuits has a function of holding first data output by the flip-flop circuit in any one of the plurality of first data holding circuits in response to a first signal supplied from the state control unit, and a function of outputting the first data held in any one of the plurality of first data holding circuits to the flip-flop circuit in response to a second signal supplied from the state control unit; Each of the plurality of second memory circuits has a function of holding second data output by the inverter loop circuit in one of the plurality of second data holding circuits in response to the first signal supplied from the state control unit, and a function of outputting the second data held in one of the plurality of second data holding circuits to the inverter loop circuit in response to the second signal supplied from the state control unit. 　 In claim 4, the flip-flop circuit and at least one of the plurality of first data retention circuits have overlapping regions; The inverter loop circuit and at least one of the plurality of second data holding circuits have an overlapping region. 　 In claim 4 or claim 5, The oxide semiconductor included in one or both of the second transistor and the fourth transistor contains indium.

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