Drive circuit and imaging device

Abstract

The present invention makes it possible for a plurality of loads to be driven while suppressing the interference of potential fluctuations via a power supply line.　This drive circuit comprises: a plurality of drivers; and a switching unit capable of switching between isolation and connection of power supply potentials between the drivers. The drivers may be selectively connected to a first power supply potential or a second power supply potential. The switching unit may switch between the first power supply potential and the second power supply potential for each driver. A first power supply line for supplying the first power supply potential and a second power supply line for supplying the second power supply potential may be provided. The first power supply potential and the second power supply potential may be ground potentials of mutually isolated power supplies.

Description

Drive circuit and imaging device

[0001] The present technology relates to a drive circuit and an imaging device. More particularly, the present technology relates to a drive circuit and an imaging device capable of switching power supplies.

[0002] A drive circuit may be used to drive a plurality of loads. For example, a vertical drive circuit that simultaneously drives all of a plurality of sensor pixels in a pixel array portion has been disclosed (see, for example, Japanese Patent Application Laid-Open No. 2003-222294).

[0003] Japanese Patent Application Laid-Open No. 2015-195235

[0004] However, in the above-mentioned conventional technology, potential fluctuations in the output of one driver may interfere with the output of the other driver via the power supply line, which may cause malfunctions or the like.

[0005] This technology was developed in light of these circumstances, and aims to enable driving multiple loads while suppressing interference from potential fluctuations via power lines.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a drive circuit including a plurality of drivers and a switching unit capable of switching between connection and separation of a power supply potential between the drivers, thereby providing an effect of separating the power supply potentials that cause interference due to potential fluctuations in the driver outputs.

[0007] In the first aspect, the driver may be selectively connected to a first power supply potential or a second power supply potential, and the switching unit may switch between the first power supply potential and the second power supply potential for each driver, thereby providing an effect of switching the power supply potential so that potential fluctuations in the outputs do not interfere with each other between the drivers.

[0008] In the first aspect, the first power supply potential and the second power supply potential may be ground potentials that are separated from each other, thereby suppressing interference of potential fluctuations in the driver output via the ground potential.

[0009] In the first aspect, the power supply circuit may include a first power supply line that supplies the first power supply potential and a second power supply line that supplies the second power supply potential, and the switching unit may include a plurality of switches that selectively connect the plurality of drivers to the first power supply line or the second power supply line, thereby providing an effect of separating the power supply lines that mediate interference due to potential fluctuations in the driver outputs.

[0010] In the first aspect, the first power supply line and the second power supply line may be power-separated from each other, thereby suppressing interference of potential fluctuations in the driver output via the power supply lines.

[0011] In the first aspect, the device may further include a switching control unit that connects at least one of the plurality of drivers to the first power supply potential and connects the drivers that are not connected to the first power supply potential to the second power supply potential, thereby suppressing interference of potential fluctuations of the outputs of simultaneously driven drivers.

[0012] A second aspect of the present invention is an imaging device including a pixel array unit in which pixels are arranged in a matrix in row and column directions, and a drive circuit for driving the pixels, the drive circuit including a plurality of drivers for driving the pixels on a row-by-row basis, and a switching unit capable of switching between connection and disconnection of a power supply potential between the drivers, thereby providing the effect of separating the power supply potential that causes interference due to potential fluctuations in the driver outputs when the pixels are driven.

[0013] In the second aspect, the driver may be selectively connected to a first power supply potential or a second power supply potential, and the switching unit may switch between the first power supply potential and the second power supply potential for each driver, thereby achieving an effect of switching the power supply potential so that output potential fluctuations do not interfere with each other between drivers that drive pixels for each row.

[0014] In addition, in the second aspect, the pixel circuit may further include horizontal drive lines connecting the driver and the pixels for each row, and vertical signal lines transmitting pixel signals read from the pixels for each column, thereby achieving the effect of driving the pixels for each row while reading out pixel signals for each column.

[0015] In the second aspect, the display device may further include a switching control unit that connects the drivers for the shutter rows and the non-selected rows to the first power supply potential and the drivers for the read rows to the second power supply potential, thereby providing an effect of controlling the driver output of the read row so that potential fluctuations in the drivers for the shutter rows and the non-selected rows do not interfere with the output of the drivers for the read row.

[0016] In a second aspect, the switching control unit may connect the driver of the read row to the first power supply potential in a P-phase readout and connect the driver of the read row to the second power supply potential in a D-phase readout, thereby suppressing interference with the output of the driver of the read row during the D-phase readout.

[0017] In a second aspect, the pixel may include an imaging pixel and a phase-difference pixel, the drive circuit may include a first driver that drives the imaging pixel and a second driver that drives the phase-difference pixel, and the switching unit may include a power supply separation switch that separates a power supply for the first driver from a power supply for the second driver. This has the effect of suppressing potential fluctuations in the output of the driver when the imaging pixel is driven from interfering with potential fluctuations in the output of the driver for the phase-difference pixel via the power supply.

[0018] In a second aspect, the switching control unit may separate a power supply for the first driver from a power supply for the second driver during global operation of the imaging pixel or the phase difference pixel, thereby suppressing potential fluctuations in the output of the driver during global operation of the imaging pixel from interfering with potential fluctuations in the output of the driver of the phase difference pixel via the power supply.

[0019] 10 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. FIG. 11 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. FIG. 12 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 13 is a diagram showing waveforms of each part when a pixel signal is read out according to the first embodiment. FIG. 14 is a block diagram showing an example of the configuration of a drive circuit according to the first embodiment. FIG. 15 is a timing chart showing an example of a method for driving the drive circuit according to the first embodiment. FIG. 16 is a block diagram showing an example of the configuration of a drive circuit according to the second embodiment. FIG. 17 is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to a third embodiment. FIG. 18 is a plan view showing an example of the layout of a phase difference pixel according to the third embodiment. FIG. 19 is a timing chart showing waveforms of each part of a pixel during operation of a solid-state imaging device according to the third embodiment. FIG. 19 is a diagram showing an example of a schematic configuration of a drive circuit according to the third embodiment. FIG. 19 is a block diagram showing an example of the configuration of a drive circuit according to the third embodiment. FIG. 19 is a timing chart showing an example of a method for driving the drive circuit according to the third embodiment. FIG. 19 is a block diagram showing another example of the configuration of the drive circuit according to the third embodiment. FIG. 19 is a timing chart showing another example of the method for driving the drive circuit according to the third embodiment. FIG. 19 is a block diagram showing an example of the configuration of a drive circuit according to the fourth embodiment. FIG. 19 is a perspective view showing an example of a stack of layers in a solid-state imaging device according to a fifth embodiment. It is a block diagram showing a schematic configuration example of a vehicle control system.It is an explanatory diagram showing an example of an installation position of an imaging unit.

[0020] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which the power supply potential on the ground side can be switched for each driver depending on the active state) 2. Second embodiment (an example in which the power supply potential on the power supply side can be switched for each driver depending on the active state) 3. Third embodiment (an example in which the power supply potentials of drivers provided for each imaging pixel and phase difference pixel can be separated) 4. Fourth embodiment (an example in which the power supply potentials of drivers provided for each row of imaging pixels and phase difference pixels can be separated) 5. Fifth embodiment (an example in which semiconductor chips on which a solid-state imaging device is formed are stacked) 6. Application example to a moving body

[0021] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0022] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0023] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0024] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. Single-slope AD conversion may be used to digitize the electrical signal. In this case, the solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS (Dynamic Differential Sampling) readout. Each pixel may include a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a lateral overflow integration capacitor (LOFIC) image sensor.

[0025] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0026] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0027] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0028] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0029] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0030] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0031] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0032] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0033] The pixel array unit 111 includes a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX for each row when reading out a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read out from the pixels PX to the column signal processing unit 114 for each column.

[0034] Each pixel PX may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixel PX may also include an image plane phase difference pixel. Each pixel PX may support rolling shutter readout or global shutter readout. Each pixel PX may be an HDR (High Dynamic Range) pixel capable of outputting signals by switching conversion efficiency. The pixels PX may also be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0035] The vertical scanning circuit 112 scans the pixels PX to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, when reading out signals from each pixel PX, the vertical scanning circuit 112 can drive each pixel PX row by row via a horizontal drive line HSL. The vertical scanning circuit 112 includes a drive circuit 112A.

[0036] The drive circuit 112A drives each pixel PX for each row. The drive circuit 112A can switch between connection and disconnection of the power supply potential between the drivers provided for each row. The power supply potential may be a power supply potential on the ground side or a power supply potential on the power supply side. The power supply potential may include a positive potential, a ground potential, or a negative potential.

[0037] The column readout circuit 113 can form a source follower with each pixel PX when reading out a signal from the pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0038] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PX. For example, the column signal processing unit 114 can perform CDS (Correlated Double Sampling) processing based on the signals transmitted in the column direction from each pixel PX. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PX, and output an imaging signal Gout. The imaging signal Gout may include not only imaging data but also phase difference data. The column signal processing unit 114 includes a column ADC unit 114A.

[0039] The column ADC unit 114A can perform AD conversion processing for each column in parallel. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion.

[0040] The horizontal scanning circuit 115 scans the pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0041] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0042] FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0043] 1, a pixel PX includes a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS (Metal Oxide Semiconductor) transistors.

[0044] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to a power supply voltage VDD via a reset transistor 123. The power supply voltage VDD is connected to a vertical signal line VSL via a series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0045] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL in FIG. 2. At this time, the drive circuit 112A can output the transfer signal TGL, reset signal RST, and selection signal SEL to each pixel PX for each row.

[0046] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0047] 4 is a diagram showing waveforms at various parts when pixel signals are read out according to the first embodiment, and shows an example of waveforms within a 1H period (one horizontal synchronization period).

[0048] In the figure, the reset signal RST rises (t1), turning on the reset transistor 123 and resetting the floating diffusion FD. Also, the selection signal SEL rises, turning on the selection transistor 125. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the power supply voltage VDD is applied to the gate of the amplification transistor 124.

[0049] Next, the reset signal RST falls (t2), turning off the reset transistor 123. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0050] Next, the potential of the vertical signal line VSL corresponding to the P-phase level is compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of the vertical signal line VSL is output as the comparison result. At this time, the P-phase level read out from the pixel PX is AD converted for each column based on the count operation until the level of the reference signal REF matches the potential of the vertical signal line VSL.

[0051] Next, when the transfer signal TGL rises (t3), the transfer transistor 122 is turned on and the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.

[0052] Next, when the transfer signal TGL falls (t4), the transfer transistor 122 is turned off. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0053] Next, the potential of the vertical signal line VSL corresponding to the D-phase level is compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of the vertical signal line VSL is output as the comparison result. At this time, the D-phase level read out from the pixel PX is AD converted for each column based on the count operation until the level of the reference signal REF matches the potential of the vertical signal line VSL.

[0054] 5 is a block diagram showing an example of the configuration of a drive circuit according to the first embodiment. While vertical signal lines VSL1 and VSL2 for two columns are shown in the figure, the same can be applied to a case where there are more vertical signal lines. Furthermore, although drivers DV1 to DV3 for three rows are shown in the figure, the same can be applied to a case where there are more drivers DV1 to DV3.

[0055] In the figure, pixels PX are connected to the vertical signal lines VSL1 and VSL2, respectively. At this time, the amplification transistor 124 of each pixel PX is connected to the vertical signal lines VSL1 and VSL2 via the selection transistor 125, respectively.

[0056] The drive circuit 112A includes drivers DV1 to DV3, a switching unit SE, and a switching control unit SC.

[0057] Drivers DV1 to DV3 are provided for each row. Drivers DV1 to DV3 drive each pixel PX for each row. In the same figure, an example is shown in which the transfer transistor 122 is driven based on a transfer signal TGL. In addition to drivers DV1 to DV3 that drive the gate of the transfer transistor 122, a driver that drives the gate of the reset transistor 123 and a driver that drives the gate of the selection transistor 125 may also be provided.

[0058] The power supply sides of drivers DV1 to DV3 are connected to a power supply line VD3, and the ground sides of drivers DV1 to DV3 are selectively connected to power supply lines VD1 and VD2 via a switching unit SE. The power supply line VD3 is set to a high power supply potential, and the power supply lines VD1 and VD2 are set to a low power supply potential. The low power supply potential may be ground potential or a negative potential. The power supplies of the power supply lines VD1 and VD2 can be separated from each other.

[0059] The switching unit SE can switch between connection and disconnection of the power supply potential of the drivers DV1 to DV3. The power supply potential may be the potential on the ground side of the drivers DV1 to DV3, or the potential on the power supply side. For example, the switching unit SE can switch between the power supply lines VD1 and VD2 for each of the drivers DV1 to DV3. The switching unit SE includes switches SW1 to SW3. The input side of each of the switches SW1 to SW3 is switchably connected to the power supply lines VD1 and VD2, and the output side of each of the switches SW1 to SW3 is connected to the ground side of each of the drivers DV1 to DV3.

[0060] The switching control unit SC switches the switches SW1 to SW3 based on the switching signal PL1. At this time, the switching control unit SC can connect at least one of the drivers DV1 to DV3 to the power supply line VD2 via the switches SW1 to SW3, and can connect the drivers DV1 to DV3 that are not connected to the power supply line VD2 to the power supply line VD1 via the switches SW1 to SW3. For example, assume that the driver DV1 is in the shutter row, the driver DV2 is in the non-selected row, and the driver DV3 is in the read row. At this time, the switching control unit SC can connect the drivers DV1 and DV2 to the power supply line VD1 via the switches SW1 and SW2, respectively, and can connect the driver DV3 to the power supply line VD2 via the switch SW3.

[0061] Here, assume that parasitic capacitances C1 and C2 exist between the vertical signal line VSL1 and the outputs of the drivers DV1 and DV2, and that a parasitic capacitance C3 exists between the floating diffusion FD of the pixel PX connected to the vertical signal line VSL2 and the output of the driver DV3. If the amount of light from the pixel PX connected to the vertical signal line VSL1 is large, the amplitude of the potential VS1 of the vertical signal line VSL1 increases when reading from that pixel PX. At this time, noises Z1 and Z2 are superimposed on the outputs of the drivers DV1 and DV2 due to capacitive coupling with the vertical signal line VSL1 via the parasitic capacitances C1 and C2. Then, noise Z3 is generated on the power supply line VD1 connected to the drivers DV1 and DV2 due to the noises Z1 and Z2.

[0062] Here, because driver DV3 is connected to power supply line VD2 via switch SW3, noise Z3 generated on power supply line VD1 is not transmitted to driver DV3. Also, because power supplies of power supply lines VD1 and VD2 are separated from each other, potential VE1 of power supply line VD2 is not affected by noise Z3 generated on power supply line VD1. Therefore, potential VE2 of the output of driver DV3 is not affected by noise Z3 generated on power supply line VD1.

[0063] At this time, the potential of the floating diffusion FD of the pixel PX connected to the vertical signal line VSL2 may fluctuate due to capacitive coupling with the output of the driver DV3 via the parasitic capacitance C3. Here, if the amount of light of the pixel PX connected to the vertical signal line VSL2 is small, the amplitude of the potential VS2 of the vertical signal line VSL2 decreases when reading from that pixel PX. At this time, the potential VE2 of the output of the driver DV3 is not affected by the noise Z3 generated in the power supply line VD1, so the influence on the potential VS2 of the vertical signal line VSL2 can be suppressed, and the readout accuracy from the pixel PX with a small amount of light can be improved.

[0064] FIG. 6 is a timing chart showing an example of a driving method of the driving circuit according to the first embodiment.

[0065] In the figure, in the CDS, the state ST switches between P-phase readout and D-phase readout in accordance with the horizontal synchronization signal XHS. At this time, in the P-phase readout, even if a pixel PX with a large amount of light is connected, there is no fluctuation in the potential of the vertical signal line VSL connected to that pixel PX. Therefore, in the P-phase readout, the switching control unit SC connects each of the drivers DV1 to DV3 to the power supply line VD1, and does not need to switch to the power supply line VD2.

[0066] In this way, in the first embodiment described above, the power supply lines VD1 and VD2 on the ground side of the drivers DV1 to DV3 are separated from each other, and the power supply lines VD1 and VD2 are switched for each of the drivers DV1 to DV3. This makes it possible to suppress interference of potential fluctuations in the outputs of the drivers DV1 to DV3 via the ground potential, even when the parasitic capacitances C1 to C3 increase as the pixels PX become smaller.

[0067] 2. Second Embodiment In the first embodiment described above, the power supply lines VD1 and VD2 on the ground side of the drivers DV1 to DV3 are separated from each other, and the ground side power supply lines VD1 and VD2 are switched for each of the drivers DV1 to DV3. In this second embodiment, the power supply lines on the power supply side of the drivers DV1 to DV3 are separated from each other, and the power supply side power supply lines are switched for each of the drivers DV1 to DV3.

[0068] FIG. 7 is a block diagram showing an example of the configuration of a drive circuit according to the second embodiment.

[0069] In the figure, the drive circuit includes drivers DV1' to DV3', a switching unit SE', and a switching control unit SC'.

[0070] Drivers DV1' to DV3' are provided for each row. Drivers DV1' to DV3' drive each pixel PX for each row. The same figure shows an example in which the transfer transistor 122 is driven based on a transfer signal TGL. The ground sides of drivers DV1' to DV3' are connected to a power supply line VD1, and the power supply sides of drivers DV1' to DV3' are selectively connected to power supply lines VD2' and VD3 via a switching unit SE'. The power supply lines VD2' and VD3 are set to a high power supply potential, and the power supply line VD1 is set to a low power supply potential. The power supplies of the power supply lines VD2' and VD3 can be separated from each other.

[0071] The switching unit SE' switches between the power supply lines VD2' and VD3 for each of the drivers DV1 to DV3. The switching unit SE' includes switches SW1' to SW3'. The input sides of the switches SW1' to SW3' are switchably connected to the power supply lines VD2' and VD3, and the output sides of the switches SW1' to SW3' are connected to the power supply sides of the drivers DV1' to DV3'.

[0072] The switching control unit SC' switches the switches SW1' to SW3'. At this time, the switching control unit SC' can connect at least one of the drivers DV1' to DV3' to the power supply line VD2' via the switches SW1' to SW3', and can connect the drivers DV1' to DV3' that are not connected to the power supply line VD2' to the power supply line VD3 via the switches SW1' to SW3'. For example, it is assumed that the driver DV1' is in the shutter row, the driver DV2' is in the non-selected row, and the driver DV3' is in the read row. At this time, the switching control unit SC' can connect the drivers DV1' and DV2' to the power supply line VD3 via the switches SW1' and SW2', respectively, and can connect the driver DV3' to the power supply line VD2' via the switch SW3'.

[0073] In this way, in the second embodiment described above, the power supply lines VD2' and VD3 on the power supply side of the drivers DV1' to DV3' are separated from each other, and the power supply lines VD2' and VD3 on the power supply side are switched for each of the drivers DV1' to DV3'. This makes it possible to suppress interference of potential fluctuations in the outputs of the drivers DV1' to DV3' via the power supply potential, even when the parasitic capacitances C1 to C3 increase as the pixels PX are made smaller.

[0074] 3. Third Embodiment In the first embodiment described above, the power supply lines VD1 and VD2 on the ground side of the drivers DV1 to DV3 are separated from each other, and the power supply lines VD1 and VD2 on the ground side are switched for each of the drivers DV1 to DV3. In this third embodiment, the power supply potentials of the drivers provided for the imaging pixels and the phase difference pixels can be separated.

[0075] FIG. 8 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the third embodiment.

[0076] In the figure, each pixel PXD includes a photodiode PD, a floating diffusion FD, a capacitor CA, and an overflow control transistor 122A. Furthermore, each pixel PXD includes transfer transistors 122B and 122C, a reset transistor 123, an amplifier transistor 124, and a selection transistor 125. Each pixel PXD can support global operation. In this case, each pixel PXD can simultaneously sample and hold the charge photoelectrically converted by the photodiode PD for all pixels, and output a pixel signal corresponding to the sampled and held charge for each row.

[0077] The overflow control transistor 122A, the transfer transistors 122B and 122C, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 may be MOS transistors. The capacitor CA may be a MIM (Metal Insulation Metal) capacitor or a junction capacitor formed on a semiconductor substrate.

[0078] The photodiode PD performs photoelectric conversion, and each capacitor CA stores the photoelectrically converted charge. Charge transfer from the photodiode PD to the capacitor CA may be performed simultaneously for all pixels. The overflow control transistor 122A controls the overflow of charge from the photodiode PD.

[0079] The transfer transistor 122B transfers the charge accumulated in the photodiode PD to the capacitor CA. The transfer transistor 122C transfers the charge held in the capacitor CA to the floating diffusion FD. The reset transistor 123 resets the floating diffusion FD. The amplification transistor 124 outputs a signal according to the potential of the floating diffusion FD. The selection transistor 125 selects the output of the amplification transistor 124.

[0080] In pixel PXD, the amplification transistor 124 and selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to an overflow potential OFD via an overflow control transistor 122A. The cathode of the photodiode PD is also connected to a capacitor CA via a transfer transistor 122B. The capacitor CA is also connected to a floating diffusion FD via the transfer transistor 122B. The floating diffusion FD is also connected to a reset voltage VRS via a reset transistor 123. The series circuit of the amplification transistor 124 and selection transistor 125 is connected between a power supply voltage VDD and a vertical signal line VSL. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0081] An overflow control signal OFG is applied to the gate of the overflow control transistor 122A. Transfer signals TRX and TRG are applied to the gates of the transfer transistors 122B and 122C. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The overflow control signal OFG, transfer signals TRX and TRG, reset signal RST, and selection signal SEL can be transmitted to each pixel PXD via the horizontal drive line HSL in FIG. 2 .

[0082] FIG. 9 is a plan view illustrating an example of the layout of a phase difference pixel according to the third embodiment.

[0083] In the figure, pixels PXD are arranged in the row and column directions in the pixel array unit 111. In the figure, a Bayer array is used as an example of the arrangement of the pixels PXD. In this case, of the 2×2 pixels PX, green pixels Pg are arranged diagonally, and one blue pixel Pb and one red pixel Pr are arranged. The pixels PXD include imaging pixels PXG and phase difference pixels PXP.

[0084] The imaging pixels PXG are arranged in the row and column directions. The phase difference pixels PXP are arranged in pairs of a right phase difference pixel PXR and a left phase difference pixel PXL, which are discretely arranged in a Bayer array. The phase difference pixels PXP may be image plane phase difference pixels. The right phase difference pixel PXR and the left phase difference pixel PXL are arranged close to each other in the pixel array unit 111. One side of each of the right phase difference pixel PXR and the left phase difference pixel PXL is covered with a light-shielding film Sy1, Sy2, respectively. The light-shielding films Sy1, Sy2 are arranged at positions offset from each other in opposite directions. Phase difference data can be read from the right phase difference pixel PXR and the left phase difference pixel PXL. The phase difference data can be used for autofocus.

[0085] 10 is a timing chart showing waveforms at various parts of a pixel during operation of a solid-state imaging device according to the third embodiment. In the figure, "a" indicates a waveform during charge transmission from photodiode PD to capacitor CA. "b" indicates a waveform during shuttering of pixel PIX. "c" indicates a waveform during readout of a pixel signal from pixel PIX.

[0086] At "a" in the figure, when charge is transferred from the photodiode PD to the capacitor CA, the selection signal SEL is set to a low level, turning off the selection transistor 125. Then, the transfer signal TRG and the reset signal RST rise (t11), turning on the transfer transistor 122C and the reset transistor 123, thereby resetting the capacitor CA and the floating diffusion FD.

[0087] Next, the transfer signal TRG and the reset signal RST fall sequentially, and then the transfer signal TRX rises (t12). At this time, the transfer transistor 122B turns on while the transfer transistor 122C and the reset transistor 123 are off, and the charge accumulated in the photodiode PD is transferred to the capacitor CA. Then, after the transfer signal TRX falls, the overflow control signal OFG rises (t13).

[0088] At b in the figure, during shuttering, the transfer signals TRX and TRG, the reset signal RST, and the selection signal SEL are set to low level. Then, the overflow control signal OFG falls (t14), turning off the overflow control transistor 122A. This shuttering operation can be performed simultaneously for all pixels, and exposure can be started simultaneously for all pixels.

[0089] At c in the figure, in reading out pixel signals, the overflow control signal OFG is set to a high level, the transfer signal TRX is set to a low level, the overflow control transistor 122A is turned on, and the selection transistor 125 is turned off. Then, the reset signal RST and the selection signal SEL rise (t15), turning on the reset transistor 123 and the selection transistor 125. At this time, the floating diffusion FD is reset, and the P-phase level of the floating diffusion FD is transmitted via the vertical signal line VSL.

[0090] Next, the reset signal RST falls, and the transfer signal TRG rises while the reset transistor 123 is turned off, turning on the transfer transistor 122C (t16). At this time, the charge held in the capacitor CA is transferred to the floating diffusion FD, and the D-phase level of the floating diffusion FD is transmitted via the vertical signal line VSL.

[0091] 11 is a diagram showing a schematic configuration example of a drive circuit according to the third embodiment, which shows a schematic configuration example of a drive circuit for the layout of the pixel PXD in FIG.

[0092] In the figure, the drive circuit includes drivers DV11 to DV14, a switching unit SE3, and a switching control unit SC3.

[0093] Drivers DV11 to DV14 are provided for each row. In this case, drivers DV11 to DV13 are arranged in rows that do not include a phase difference pixel PXP and drive the imaging pixel PXG. Driver DV14 is arranged in a row that includes a phase difference pixel PXP and drives the phase difference pixel PXP. The ground sides of drivers DV11 to DV14 are connected to a power supply line VD31, and the power supply sides of drivers DV11 to DV14 are connected to a power supply line VD33. The power supply line VD33 is set to a high power supply potential, and the power supply line VD31 is set to a low power supply potential.

[0094] The switching unit SE3 can separate the power supply lines VD31 and VD33 between the drivers DV11 to DV13 and the driver DV14. The switching unit SE3 includes power supply separation switches SW11 and SW12. The power supply separation switch SW11 separates the power supply line VD31 between the drivers DV11 to DV13 and the driver DV14 on the ground side of each of the drivers DV11 to DV14. The power supply separation switch SW12 separates the power supply line VD33 between the drivers DV11 to DV13 and the driver DV14 on the power supply side of each of the drivers DV11 to DV14.

[0095] The switching control unit SC3 switches the power supply separation switches SW11 and SW12 based on the switching signal PL3. At this time, the switching control unit SC3 turns off the power supply separation switches SW11 and SW12 during global operation of the imaging pixels PXG or the phase difference pixels PXP, and can separate the power supply lines VD31 and VD33 between the drivers DV11 to DV13 and the driver DV14.

[0096] 12 is a block diagram showing an example of the configuration of a drive circuit according to the third embodiment, in which the driver DV11 and the driver DV14 shown in FIG.

[0097] In the figure, a driver DV11 drives the imaging pixel PXG. A driver DV14 drives the phase difference pixel PXP. In the figure, an example is shown in which the transfer transistor 122C is driven based on a transfer signal TRG. In addition to drivers DV1 to DV3 that drive the gate of the transfer transistor 122C, a driver that drives the gate of the overflow control transistor 122A, a driver that drives the gate of the transfer transistor 122B, a driver that drives the gate of the reset transistor 123, and a driver that drives the gate of the selection transistor 125 may also be provided.

[0098] When a falling edge E11 occurs in the transfer signal TRG of the imaging pixel PXG, a spike noise Z11 is generated in response to the falling edge E11 and sneaks into the power line VD31 (R11). At this time, the switching control unit SC3 turns off the power separation switches SW11 and SW12 to separate the power lines VD31 and VD33 between the drivers DV11 to DV13 and the driver DV14. This blocks the spike noise Z11 that sneaks into the power line VD31 from the driver DV11 at the position of the switch SW12. This prevents the potential of the output of the driver DV14 from fluctuating due to the spike noise Z11, and stabilizes the potential V11 of the transfer signal TRG of the phase difference pixel PXP. This prevents the transfer transistor 122C of the phase difference pixel PXP from being turned on due to the spike noise Z11, thereby preventing storage breakdown during global operation.

[0099] 13 is a timing chart showing an example of a driving method of the driving circuit according to the third embodiment. Note that this figure shows an example of a timing chart within a 2V period (two vertical synchronization periods).

[0100] In the figure, the vertical synchronization period is set in accordance with the vertical synchronization signal XVS. Within one vertical synchronization period, a phase difference global reset period AFR, a phase difference global transfer period AFT, a phase difference AD ​​conversion period AFD, an imaging global reset period PGR, an imaging global transfer period PGT, and an imaging AD conversion period PGD are provided as states ST.

[0101] Furthermore, an exposure period EXG and a global shutter period GSH are provided in the imaging pixel PXG. An exposure period EXA and a global shutter period ASH are provided in the phase difference pixel PXP. The exposure periods EXG, EXA and the global shutter periods GSH, ASH may differ for each vertical synchronization period.

[0102] At this time, the switching control unit SC3 can detect global operations of the imaging pixels PXG and the phase difference pixels PXP. The global operation of the imaging pixels PXG is performed during an imaging global reset period PGR, an imaging global transfer period PGT, and a global shutter period GSH. The global operation of the phase difference pixels PXP is performed during a phase difference global reset period AFR, a phase difference global transfer period AFT, and a global shutter period ASH. When the switching control unit SC3 detects the global operation, it sets the switching signal PL3 to a high level, thereby turning off the power supply separation switches SW11 and SW12 and isolating the power supply lines VD31 and VD33 between the drivers DV11 and DV14.

[0103] 14 is a block diagram showing another example of the configuration of the drive circuit according to the third embodiment, which shows an example of the arrangement of pixels PXD for two rows.

[0104] 14, this drive circuit includes drivers DV11', DV14', a switch unit SE3', and a switch control unit SC3' instead of the drivers DV11, DV14, switch unit SE3, and switch control unit SC3 of Fig. 12. Other configurations of the drive circuit of Fig. 14 are the same as those of the drive circuit of Fig. 12.

[0105] The power supply sides of the drivers DV11' and DV14' are connected to a power supply line VD33, and the ground sides of the drivers DV11' and DV14' are selectively connected to the power supply lines VD31 and VD32 via a switching unit SE3'. The power supply lines VD31 and VD32 are set to a low power supply potential. The low power supply potential may be a ground potential or a negative potential. The power supplies of the power supply lines VD31 and VD32 can be separated from each other.

[0106] The switching unit SE3' switches between the power supply lines VD31 and VD32 for each of the drivers DV11' and DV14'. The switching unit SE3' includes switches SW31 and SW34. The input sides of the switches SW31 and SW34 are switchably connected to the power supply lines VD31 and VD32, and the output sides of the switches SW31 and SW34 are connected to the ground sides of the drivers DV11' and DV14'.

[0107] The switching control unit SC3' switches the switches SW31 and SW34 based on the switching signal PL3'. At this time, the switching control unit SC3' can connect at least one of the drivers DV11' and DV14' to the power supply line VD32 via the switches SW31 and SW34, and can connect the drivers DV11' and DV14' that are not connected to the power supply line VD32 to the power supply line VD31 via the switches SW31 and SW34. Furthermore, the switching control unit SC3' can connect the drivers DV11' and DV14' used in global operation to the power supply line VD32 via the switches SW31 and SW34, and can connect the drivers DV11' and DV14' used in non-global operation to the power supply line VD31 via the switches SW31 and SW34.

[0108] 15 is a timing chart showing another example of the driving method of the driving circuit according to the third embodiment. Note that this figure shows an example of the timing chart within a 2V period (two vertical synchronization periods).

[0109] In the figure, a switching control unit SC3' can detect global operations of the imaging pixels PXG and the phase difference pixels PXP. The switching control unit SC3' can set a switching signal PL3' based on the logical sum of a switching signal PL3, which is set to a high level when global operations are detected, and a switching signal PL1, which switches the power supply potential of each driver DV11', DV14'. The switching control unit SC3' can switch switches SW31, SW34 based on the switching signal PL3', thereby isolating the power supplies of the ground sides of each driver DV11', DV14' from each other.

[0110] In this way, in the third embodiment described above, the power supply potential of the driver provided for each of the imaging pixels PXG and the phase difference pixels PXP can be switched, thereby realizing global operation of the imaging pixels PXG and the phase difference pixels PXP while suppressing interference between the outputs of the drivers for the imaging pixels PXG and the phase difference pixels PXP.

[0111] 4. Fourth Embodiment In the above-described third embodiment, the power supply potentials of the drivers provided for the imaging pixels PXG and the phase difference pixels PXP can be separated. In this fourth embodiment, the power supply potentials of the drivers provided for each row of the imaging pixels PXG and the phase difference pixels PXP can be separated.

[0112] 16 is a block diagram showing an example of the configuration of a drive circuit according to the fourth embodiment, which shows an example of the arrangement of pixels PXD for two rows.

[0113] 16, this drive circuit has drivers DV11' and DV14' added to the drive circuit of FIG. 12. Other configurations of the drive circuit of FIG. 16 are the same as those of the drive circuit of FIG.

[0114] The driver DV11' is connected in parallel to the driver DV11 with respect to the imaging pixel PXG. At this time, the output of the driver DV11' is connected to the output of the driver DV11. Here, when the imaging pixel PXG is driven, the pulse signal PS1 is input to the driver DV11 as the transfer signal TRG, and the input of the driver DV11' is set to low level L.

[0115] The driver DV14' is connected in parallel to the driver DV14 with respect to the phase difference pixel PXP. At this time, the output of the driver DV14' is connected to the output of the driver DV14. Here, when the phase difference pixel PXP is driven, a pulse signal PS4 is input to the driver DV14 as a transfer signal TRG, and the input of the driver DV14' is set to low level L.

[0116] As described above, in the fourth embodiment, the drivers DV11, DV11', DV14, and DV14' are provided for each row of the imaging pixels PXG and the phase difference pixels PXP, making it possible to separate the power supply potentials of the drivers DV11 and DV14' from the drivers DV11' and DV14. This makes it possible to achieve global operation of the imaging pixels PXG and the phase difference pixels PXP while suppressing interference between the outputs of the drivers DV11, DV11', DV14, and DV14' of the imaging pixels PXG and the phase difference pixels PXP, and makes it unnecessary to change the configuration of the drivers DV11, DV11', DV14, and DV14' depending on whether or not a phase difference pixel PXP is present.

[0117] 5. Fifth Embodiment In the first embodiment described above, the power supply lines VD1 and VD2 on the ground side of the drivers DV1 to DV3 are separated from each other, and the ground side power supply lines VD1 and VD2 are switched for each of the drivers DV1 to DV3. In this fifth embodiment, semiconductor chips each having a pixel array portion in which pixels are arranged in a matrix are stacked.

[0118] FIG. 17 is a perspective view showing an example of a stack of pixel array units according to the fifth embodiment.

[0119] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0120] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be pixels PX of FIG. 3 or pixels PXD of FIG. 8. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0121] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and a drive circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The drive circuit 928 can be provided with any of the configurations of the first to fourth embodiments described above.

[0122] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0123] As described above, in the fifth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0124] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0125] FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0126] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 86, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0127] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0128] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0129] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0130] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0131] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0132] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0133] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0134] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0135] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 18, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0136] FIG. 19 is a diagram showing an example of the installation position of the imaging unit 12031.

[0137] In FIG. 19, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0138] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0139] 19 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0140] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0141] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0142] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0143] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0144] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging device according to the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to improve the quality of images captured by the imaging unit 12031 and improve the autofocus accuracy of the imaging unit 12031.

[0145] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0146] The present technology may also be configured as follows: (1) A drive circuit including a plurality of drivers and a switching unit capable of switching between connection and separation of a power supply potential between the drivers. (2) The drive circuit according to (1), wherein the drivers are selectively connected to a first power supply potential or a second power supply potential, and the switching unit switches between the first power supply potential and the second power supply potential for each driver. (3) The drive circuit according to (2), wherein the first power supply potential and the second power supply potential are ground potentials that are power-source-separated from each other. (4) The drive circuit according to (2) or (3), including a first power supply line that supplies the first power supply potential and a second power supply line that supplies the second power supply potential, and wherein the switching unit includes a plurality of switches that selectively connect the plurality of drivers to the first power supply line or the second power supply line. (5) The drive circuit according to (4), wherein the first power supply line and the second power supply line are power-source-separated from each other. (6) The drive circuit according to any one of (2) to (5), further comprising a switching control unit that connects at least one of a plurality of drivers to the first power supply potential and connects a driver not connected to the first power supply potential to the second power supply potential. (7) An imaging device comprising: a pixel array unit in which pixels are arranged in a matrix in row and column directions; and a drive circuit that drives the pixels, the drive circuit comprising: a plurality of drivers that drive the pixels for each row; and a switching unit that can switch between connection and isolation of the power supply potential between the drivers. (8) The imaging device according to (7), wherein the drivers are selectively connected to a first power supply potential or a second power supply potential, and the switching unit switches between the first power supply potential and the second power supply potential for each driver. (9) The imaging device according to (8), further comprising: a horizontal drive line that connects the driver and the pixels for each row; and a vertical signal line that transmits pixel signals read out from the pixels for each column. (10) The imaging device according to (8) or (9), further comprising a switching control unit that connects the drivers of the shutter row and the non-selected row to the first power supply potential and connects the drivers of the read row to the second power supply potential.(11) The imaging device according to (10), wherein the switching control unit connects the driver of the read row to the first power supply potential in P-phase readout, and connects the driver of the read row to the second power supply potential in D-phase readout. (12) The imaging device according to (7), wherein the pixels include imaging pixels and phase difference pixels, the drive circuit includes a first driver that drives the imaging pixels and a second driver that drives the phase difference pixels, and the switching unit includes a power supply separation switch that separates the power supply of the first driver from the power supply of the second driver. (13) The imaging device according to (12), wherein the switching control unit separates the power supply of the first driver from the power supply of the second driver during global operation of the imaging pixels or the phase difference pixels.

[0147] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 112A Drive circuit 113 Column readout circuit 114 Column signal processing unit 114A Column ADC unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel HSL Horizontal drive line VSL Vertical signal line PD Photodiode FD Floating diffusion 122 Transfer transistor 123 Reset transistor 124 Amplification transistor 125 Selection transistor SE Switching unit SC Switching control unit DV1 to DV3 Drivers SW1 to SW3 Switches VD1 to VD3 Power supply lines

Claims

1. A drive circuit comprising a plurality of drivers and a switching unit capable of switching between isolation and connection of a power supply potential between the drivers.

2. The drive circuit according to claim 1, wherein the driver is selectively connected to a first power supply potential or a second power supply potential, and the switching section switches between the first power supply potential and the second power supply potential for each driver.

3. The drive circuit according to claim 2, wherein the first power supply potential and the second power supply potential are ground potentials that are power supplies separated from each other.

4. A drive circuit as described in claim 2, comprising: a first power supply line that supplies the first power supply potential; and a second power supply line that supplies the second power supply potential; and the switching unit comprising a plurality of switches that selectively connect the plurality of drivers to the first power supply line or the second power supply line.

5. The drive circuit according to claim 4, wherein the first power supply line and the second power supply line are separated from each other.

6. The drive circuit according to claim 2, further comprising a switching control section that connects at least one of the plurality of drivers to the first power supply potential and connects the drivers that are not connected to the first power supply potential to the second power supply potential.

7. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in row and column directions; and a drive circuit for driving the pixels, wherein the drive circuit comprises a plurality of drivers for driving the pixels row by row; and a switching section capable of switching between isolation and connection of power supply potential between the drivers.

8. The imaging device according to claim 7, wherein the driver is selectively connected to a first power supply potential or a second power supply potential, and the switching unit switches between the first power supply potential and the second power supply potential for each driver.

9. The imaging device according to claim 8, further comprising: horizontal drive lines connecting the driver and the pixels for each row; and vertical signal lines transmitting pixel signals read from the pixels for each column.

10. The imaging device according to claim 8, further comprising a switching control section that connects the drivers of the shutter rows and non-selected rows to the first power supply potential and that connects the drivers of the read rows to the second power supply potential.

11. The imaging device according to claim 10, wherein the switching control unit connects the driver of the read row to the first power supply potential in P-phase readout, and connects the driver of the read row to the second power supply potential in D-phase readout.

12. The imaging device described in claim 7, wherein the pixels include imaging pixels and phase difference pixels, the drive circuit includes a first driver that drives the imaging pixels and a second driver that drives the phase difference pixels, and the switching unit includes a power supply separation switch that separates the power supply of the first driver from the power supply of the second driver.

13. The imaging device according to claim 12, wherein the switching control unit separates the power supply of the first driver from the power supply of the second driver during global operation of the imaging pixels or the phase difference pixels.

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