Circuit board

Abstract

The present invention provides a circuit board that facilitates the implementation of a fine pitch in a structure in which multiple bonding parts are arranged for electrical connection. The circuit board according to the present embodiment comprises: an insulating layer; pad parts disposed on the insulating layer; and bonding parts disposed on the pad parts, wherein the bonding parts are arranged so as to surround respective pad parts.

Description

circuit board

[0001] This embodiment relates to a circuit board.

[0002]

[0003] Electronic components employed in electronic devices include various active and passive circuit elements, and these circuit elements may be integrated into semiconductor chips or dies. Furthermore, the semiconductor chips or dies may be provided in the form of electronic packages mounted on a substrate including circuit wiring, such as a printed circuit board (PCB).

[0004] Meanwhile, flip-chip connection structures, which utilize connection structures to mount and electrically connect semiconductor chips on printed circuit boards, are widely used in electronic packages. For example, flip-chip connection structures utilizing bumps are advantageous for implementing stacked structures of various semiconductor chips. Furthermore, flip-chip connection structures facilitate the use of multiple connection structures to secure a large number of input / output (I / O) terminals.

[0005] Among the methods for forming such connection structures, there is the Solder-On-Pad (SOP) method. The SOP method manufactures connection structures by printing metallic paste or mounting ball-shaped solder on the connection pads on the upper surface of a printed circuit board exposed by a solder mask pattern, and then reflowing to form a spherical solder portion through the surface tension effect. However, as the integration level of semiconductor chips increases and their size decreases, there is a problem that the SOP method has limitations in implementing connection members with fine pitches.

[0006] Recently, a method of introducing a post-shaped bump as a connecting member has been proposed, but as the spacing between multiple pads is increasingly reduced for integration, the short-circuit defect rate between adjacent pads is increasing.

[0007]

[0008] The present invention provides a circuit board that is easy to implement in a fine pitch in a structure where a plurality of bonding portions are arranged to form an electrical connection.

[0009]

[0010] A circuit board according to the present embodiment includes an insulating layer; a pad portion disposed on the insulating layer; and a bonding portion disposed on the pad portion, wherein the bonding portion is disposed to surround the pad portion.

[0011] The above bonding portion can be arranged to surround the upper surface and side surfaces of the above pad portion.

[0012] It may include a seed layer disposed between the insulating layer and the bonding portion.

[0013] In the horizontal direction, the seed layer may have a width wider than the width of the pad portion.

[0014] In the horizontal direction, the seed layer may have a width equal to or smaller than the width of the bonding portion.

[0015] The seed layer may include a first portion in contact with the pad portion and a second portion in contact with the bonding portion.

[0016] A second insulating layer is disposed on the above insulating layer, and the bonding portion can be wrapped with the second insulating layer.

[0017] The second insulating layer may be a material different from the material of the insulating layer.

[0018] A semiconductor element is disposed on the insulating layer, and the bonding portion is provided in multiple numbers and spaced apart in a horizontal direction, and the multiple bonding portions can be disposed around the semiconductor element.

[0019] The horizontal central axis of the above bonding portion may be misaligned with the horizontal central axis of the above pad portion.

[0020]

[0021] Through this embodiment, the horizontal width of the pad portion can be reduced to be less than the horizontal width of the bonding portion, thereby ensuring sufficient horizontal spacing between adjacent pad portions.

[0022] In addition, by arranging the bonding portion to wrap around the upper and side surfaces of the pad portion, it is possible to compensate for the decrease in bonding strength with the bonding portion due to reduction in the size of the pad portion.

[0023]

[0024] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0025] FIG. 2 is an enlarged cross-sectional view showing the bonding structure of a pad portion and a bonding portion on an insulating layer according to an embodiment of the present invention.

[0026] Figures 3 to 10 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0027] FIG. 11 is a drawing showing the arrangement structure of semiconductor elements in a circuit board according to an embodiment of the present invention.

[0028]

[0029] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0030] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0031] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0032] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0033] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0034] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0035] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0036] Furthermore, when a component is described as being "exposed," it should not only mean that it is exposed to the exterior of the invention as defined in the present invention, but also that it is exposed to another component other than that component. That is, when it is described that B contained in A is exposed from A, it should not only mean that B is exposed to the exterior of the invention as defined in the present invention, but also that it is covered by another component, C, unless there are special circumstances.

[0037] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0038] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0039] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0040] Furthermore, with respect to a single component, the terms "one side" and "the other side" should refer to the upper and lower surfaces, respectively, or should include the side surfaces between the upper and lower surfaces. Furthermore, when "one side" refers to a side surface, unless otherwise specified, it should be understood that there are multiple sides. For example, if a rectangular solid has four sides between the upper and lower surfaces, for convenience of explanation, "one side" and / or "the other side" should be understood to refer to one of the four sides.

[0041] Fig. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, and Fig. 2 is an enlarged cross-sectional view showing the bonding structure of a pad portion and a bonding portion on an insulating layer according to an embodiment of the present invention.

[0042] Referring to FIGS. 1 and 2, a circuit board (10) according to an embodiment of the present invention may include an insulating layer, a pad portion (130), and a bonding portion (140).

[0043] The circuit board (10) may include an insulating layer. The insulating layers may be provided in multiple numbers and arranged in a vertical direction. For example, the multiple insulating layers may include a first insulating layer (101), a second insulating layer (102), a third insulating layer (103), a fourth insulating layer (104), a fifth insulating layer (105), a sixth insulating layer (106), a seventh insulating layer (107), and an eighth insulating layer (108).

[0044] The seventh insulating layer (107) may be disposed on the eighth insulating layer (108). The sixth insulating layer (106) may be disposed on the seventh insulating layer (107). The fifth insulating layer (105) may be disposed on the sixth insulating layer (106). The fourth insulating layer (104) may be disposed on the fifth insulating layer (105). The third insulating layer (103) may be disposed on the fourth insulating layer (104). The second insulating layer (102) may be disposed on the third insulating layer (103). The first insulating layer (101) may be disposed on the second insulating layer (102). The first to eighth insulating layers (101, 102, 103, 104, 105, 106, 107, 108) can be laminated along the vertical direction.

[0045] The first to eighth insulating layers (101, 102, 103, 104, 105, 106, 107, 108) may each be any insulator, such as photocurable and / or thermosetting. As the thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a prepreg (PPG) including glass fibers in a resin may be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic fillers may be provided with a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material provided with glass fibers or aramid fibers may be included. When the first to eighth insulating layers (101, 102, 103, 104, 105, 106, 107, 108) are photocurable insulators, the first to eighth insulating layers (101, 102, 103, 104, 105, 106, 107, 108) may each be a PID (Photo Imageable Dielectric).

[0046] The plurality of insulating layers may be formed of the same material, but alternatively, the material of at least one insulating layer among the plurality of insulating layers may be different from the material of the other insulating layers. Here, the meaning of the material being different may include the meaning of the composition or the content of a specific material being different. In addition, although not illustrated, a core layer (not illustrated) may be provided at the vertical center of the plurality of insulating layers to form the basis of the circuit board (10). The core layer may be omitted.

[0047] A circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to electronic devices such as semiconductor chips. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0048] A plurality of wiring sections may be arranged on the surfaces of the plurality of insulating layers, respectively. Here, "arranged on the surface" may not only mean that the plurality of wiring sections are arranged on the surfaces of the plurality of insulating layers, but may also mean that at least a portion of the plurality of wiring sections are embedded within the plurality of insulating layers or protective layers and exposed to the outside from the surface. Since the wiring sections function to transmit electrical signals or power, they may also be referred to as conductive layers.

[0049] The meaning that the wiring portion is disposed on the surface means that the wiring portion is disposed on at least one of one surface, the other surface, or the side surface of the plurality of insulating layers. The wiring portion may be disposed on one surface and the other surface of some of the plurality of insulating layers, and the structure may also be such that the wiring portion is disposed on only one surface or the other surface of other portions of the plurality of insulating layers.

[0050] The plurality of wiring portions may include a first wiring portion (111) disposed on the upper surface of the second insulating layer (102), a second wiring portion (112) disposed on the upper surface of the third insulating layer (103), a third wiring portion (113) disposed on the upper surface of the fourth insulating layer (104), a fourth wiring portion (114) disposed on the upper surface of the fifth insulating layer (105), a fifth wiring portion (115) disposed on the lower surface of the fifth insulating layer (105), a sixth wiring portion (116) disposed on the lower surface of the sixth insulating layer (106), a seventh wiring portion (117) disposed on the lower surface of the seventh insulating layer (107), and an eighth wiring portion (118) disposed on the lower surface of the eighth insulating layer (108).

[0051] It may include an eighth wiring section (118) arranged on the lower surface of the insulating layer (108).

[0052] A plurality of wiring portions may include pad portions (130). The pad portions (130) may function to electrically connect between a configuration included in the circuit board (10) and a configuration not included in the circuit board (10). In addition, a via portion, which will be described later, may be arranged to connect the wiring portions arranged on one surface of each of the plurality of stacked insulating layers. In this case, the wiring portion connected to the via portion may be referred to as a pad portion (130, 111). At least one pad portion among the pad portions (130, 111) may be arranged on the upper surface of the first insulating layer (101). The pad portion (130) may be arranged to vertically overlap with at least one or more of the first to eighth wiring portions (111, 112, 113, 114, 115, 116, 117, 118).

[0053] The pad portion (130) may be arranged on the upper surface of the first insulating layer (101). The pad portion (130) may be arranged to overlap vertically with at least one of the first to eighth wiring portions (111, 112, 113, 114, 115, 116, 117, 118).

[0054] A plurality of pad portions (130) may be provided and arranged to be spaced apart from each other in a horizontal direction on one surface of the insulating layer. A pattern portion (138) may be arranged between the plurality of pad portions (130). The pattern portion (138) may be on the first insulating layer (101). The pattern portion (138) may be a circuit pattern arranged on the first insulating layer (101).

[0055] When the plurality of pad parts (130) arranged on both sides of the pattern part (138) are respectively named the first pad part and the second pad part, the horizontal distance between the first pad part and the pattern part (138) and the horizontal distance between the second pad part and the pattern part (138) may be the same.

[0056] The horizontal width of the pad section (130) may be shorter than the horizontal width of any one of the first to eighth wiring sections (111, 112, 113, 114, 115, 116, 117, 118), but is not limited thereto and may be longer.

[0057] The vias (121, 122, 123, 124, 125, 126, 127, 128) may be provided with a conductive material and arranged in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction and / or a wiring portion and a pad portion (130). Here, the via hole may vertically penetrate at least a portion of each of the plurality of insulating layers, and a via portion (121, 122, 123, 124, 125, 126, 127, 128) provided with a conductive material may be arranged within the via hole.

[0058] The vias (121, 122, 123, 124, 125, 126, 127, 128) include a first via (121) penetrating at least a part of the first insulating layer (101), a second via (122) penetrating at least a part of the second insulating layer (102), a third via (123) penetrating at least a part of the third insulating layer (103), a fourth via (124) penetrating at least a part of the fourth insulating layer (104), a fifth via (125) penetrating at least a part of the fifth insulating layer (105), a sixth via (126) penetrating at least a part of the sixth insulating layer (106), a seventh via (127) penetrating at least a part of the seventh insulating layer (107), and an eighth via (128) penetrating at least a part of the eighth insulating layer (108). It may include the 8th via (128).

[0059] The first via portion (121) can electrically connect the first wiring portion (111) and the pad portion (130). The second via portion (122) can electrically connect the first wiring portion (111) and the second wiring portion (112). The third via portion (123) can electrically connect the second wiring portion (112) and the third wiring portion (113). The fourth via portion (124) can electrically connect the third wiring portion (113) and the fourth wiring portion (114). The fifth via portion (125) can electrically connect the fourth wiring portion (114) and the fifth wiring portion (115). The sixth via portion (126) can electrically connect the fifth wiring portion (115) and the sixth wiring portion (116). The seventh via section (127) can electrically connect the sixth wiring section (116) and the seventh wiring section (117). The eighth via section (128) can electrically connect the seventh wiring section (117) and the eighth wiring section (118).

[0060] The first to fourth via sections (121, 122, 123, 124) may each have a shape in which the horizontal width decreases as they go downward. The fifth to eighth via sections (125, 126, 127, 128) may each have a shape in which the horizontal width increases as they go downward.

[0061] The circuit pattern includes a bonding portion (140). The bonding portion (140) may be arranged on the pad portion (130), as illustrated in FIG. 2. The bonding portion (140) is for electrical connection between the circuit board (10) and a semiconductor element and / or another circuit board via the pad portion (130), and may be arranged to surround the pad portion (130).

[0062] In detail, the bonding portion (140) may be arranged to surround the upper surface and side surfaces of the pad portion (130). The bonding portion (140) may include a lower region (144) that horizontally overlaps the pad portion (130), and an upper region (142) that is arranged on the lower region (144) and does not horizontally overlap the pad portion (130). At least a portion of the upper region (142) may be arranged to vertically overlap the pad portion (130).

[0063] In the past, when forming a bonding portion on a pad portion, the bonding portion was arranged on a portion of the upper surface of the pad portion, so that the horizontal width of the pad portion was required to be at least a certain amount larger than the horizontal width of the bonding portion for the purpose of positional alignment of the bonding portion and / or support of the bonding portion. Accordingly, it was not easy to adjust the pitch between multiple pad portions, and there was a problem of electrical short-circuiting between adjacent bonding portions and pad portions and / or between adjacent bonding portions.

[0064] However, according to the present embodiment, by arranging the horizontal width of the pad portion (130) to be smaller than the horizontal width of the bonding portion (140), a sufficient horizontal distance between adjacent pad portions (130) and bonding portions (140) and / or a horizontal distance between bonding portions (140) can be secured. In addition, by arranging the bonding portion (140) to surround the upper surface and side surface of the pad portion (130), a decrease in the bonding force between the bonding portion (140) and the pad portion (130) due to a reduction in the size of the pad portion (130) can be compensated for.

[0065] Meanwhile, the bonding portion (140) may be made of a metal material. For example, the material of the bonding portion (140) may include at least one of copper (Cu), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), or may be provided as a combination including at least one of these. The bonding portion (140) is for electrical connection between the circuit board (10) and other package substrates and / or semiconductor elements, and may be distinguished from solder, which is a bonding means.

[0066] As illustrated in FIG. 2, the pad portion (130) and the bonding portion (140) may be provided in multiple numbers and arranged along the vertical direction on one surface of the insulating layer. In this case, as in the case of the pad portion (130) and the bonding portion (140) arranged on the left, the horizontal center (O) of the bonding portion (140) and the horizontal center (l) of the pad portion (130) may be arranged to be misaligned. Accordingly, by arranging the bonding portion (140) to be eccentric in one or the other direction with respect to the pad portion (130), the separation distance from the adjacent pad portion or bonding portion may be variably adjusted. In addition, in order to control warpage of the circuit board (10), the eccentricity of the horizontal center (O) of the bonding portion (140) and the horizontal center (l) of the pad portion (130) may be arranged to become larger or smaller as they go outward.

[0067] However, as in the case of the pad portion (130) and the bonding portion (140) arranged on the right side of Fig. 2, the horizontal center (O) of the bonding portion (140) and the horizontal center (l) of the pad portion (130) may coincide. In this case, the bonding area between the pad portion (130) and the bonding portion (140) may be uniformly formed based on the center of the pad portion (130).

[0068] For example, referring to FIG. 2, the pad portion (130) and the bonding portion (140) positioned on the right side of FIG. 2 may be positioned in the horizontal central region of the circuit board, and the pad portion (130) and the bonding portion (140) positioned on the left side of FIG. 2 may be positioned on the outside of the circuit board. Accordingly, by controlling the position-specific density of the material constituting the bonding portion (140), warpage of the circuit board (10) may be alleviated.

[0069] The bonding portion (140) may include an overlapping portion that vertically overlaps the pad portion (130). The overlapping portion may form at least a portion of the upper region (142) of the aforementioned bonding portion (140). Here, the upper region (142) may be an area that is disposed on the pad portion (130) and does not horizontally overlap with the pad portion (130). The vertical thickness of the overlapping portion may be thicker than the vertical thickness of the pad portion (130). Accordingly, the vertical length of the bonding portion (140) is sufficiently secured, thereby securing a Z-height for mounting a semiconductor element and / or another package substrate.

[0070] A pad portion (130), a bonding portion (140), and a seed layer (150) for forming the via portion may be disposed on one surface of the insulating layer and within the via hole. At least a portion of the seed layer (150) may be disposed between the first insulating layer (101) and the bonding portion (140). The seed layer (150) may include a surface area (152) disposed on the surface of the insulating layer and a via area (154) disposed within the via hole of the insulating layer. The surface area (152) and the via area (154) may be connected. Accordingly, the horizontal width (l3) of the seed layer (150) may be longer than the horizontal width (l4) of the pad portion (130).

[0071] The horizontal width (l3) of the seed layer (150) may correspond to the horizontal width of the bonding portion (140) or may be formed to be smaller than that. That is, the horizontal width (l3) of the seed layer (150) may exceed the horizontal width of the pad portion (130) and may be less than or equal to the horizontal width of the bonding portion (140). When the horizontal width (l3) of the seed layer (150) is smaller than the horizontal width of the bonding portion (140), the side surface of the bonding portion (140) and the side surface of the seed layer (150) may be stepped along the horizontal direction, thereby forming a groove.

[0072] The seed layer (150) may include a first portion (155) that is in direct contact with the pad portion (130) and a second portion (156) that is in direct contact with the bonding portion (140). Accordingly, the production efficiency can be improved through the process of forming the pad portion (130) and the bonding portion (140) using a single seed layer (150). In addition, the bonding strength between multiple components can be increased through the combined structure of the seed layer (150), the pad portion (130), and the bonding portion (140).

[0073] Below, the process of forming the pad portion (130) and bonding portion (140) in the circuit board (10) according to an embodiment of the present invention will be described.

[0074] Figures 3 to 10 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0075] Referring to FIGS. 3 and 4, a first insulating layer (101) is disposed on a second insulating layer (102), and a via hole (200) may be formed on one surface of the first insulating layer (101). The via hole (200) is for forming a first via portion (121) penetrating the first insulating layer (101), and the via hole (200) may be formed by a laser drilling method.

[0076] Next, as illustrated in FIG. 5, a seed layer (150) may be plated on the surface of the insulating layer. The seed layer (150) may be formed along the upper surface of the first insulating layer (101) and the inner surface of the via hole (200).

[0077] Next, as illustrated in FIGS. 6 and 7, a pad portion (130) may be formed on the first insulating layer (101) on which the seed layer (150) is formed. In the process of forming the pad portion (130), a mask (300) for forming the pad portion (130) may be placed on the first insulating layer (101), and the mask (300) includes a hole pattern corresponding to the shapes of the plurality of pad portions (130, 138). Accordingly, the pad portion (130) may be formed through surface plating of the first insulating layer (101) to which the mask (300) is attached. Meanwhile, in the process of forming the pad portion (130), a first via portion (121) in the via hole (200) may also be formed through plating of the seed layer (150).

[0078] Next, as illustrated in FIGS. 8 and 9, a bonding portion (140) may be formed on the first insulating layer (101) on which the pad portion (130) is formed. During the process of forming the bonding portion (140), a mask (400) may be placed on the first insulating layer (101), and the mask (400) may include a hole pattern corresponding to the shape of the bonding portion (140). Here, the hole size of the mask (400) for forming the bonding portion (140) may be larger than the hole size of the pad portion (130), and when the mask (400) is attached on the first insulating layer (101), the pad portion (130) may be placed within the hole of the mask (400). Accordingly, the bonding portion (140) surrounding the pad portion (130) may be formed through surface plating of the first insulating layer (101) on which the mask (400) is attached.

[0079] Next, as illustrated in FIG. 10, a portion of the seed layer (150) may be removed through surface etching of the first insulating layer (101). In this case, the seed layer (150) within the circuit board (10) may remain between the first insulating layer (101) and the bonding portion (140), and between the first insulating layer (101) and the pad portion (130).

[0080] FIG. 11 is a drawing showing the arrangement structure of semiconductor elements in a circuit board according to an embodiment of the present invention.

[0081] Referring to Fig. 11, semiconductor elements may be arranged on a circuit board (10). For example, the semiconductor elements may include a first semiconductor element (1000), a second semiconductor element (200), a third semiconductor element (3000), and a fourth semiconductor element (4000). Among these, the first semiconductor element (1000) may be arranged on one surface of an insulating layer on which a pad portion (130) and a bonding portion (140) are arranged, and the second to fourth semiconductor elements (2000, 3000, 4000) may be arranged on the other surface of the insulating layer. At least one of the second to fourth semiconductor elements (2000, 3000, 4000) arranged on the other surface of the insulating layer may have a region that vertically overlaps with the pad portion (130) or the bonding portion (140).

[0082] The first semiconductor element (1000) may be coupled to a connection pad (170) disposed on one surface of an insulating layer. The first semiconductor element (1000) may be coupled to the connection pad (170) through a connecting member such as a solder ball. In this case, a plurality of bonding portions (140) disposed on one surface of the insulating layer may be disposed around the first semiconductor element (1000). For example, the first semiconductor element (1000) may be disposed between the plurality of bonding portions (140) and may be disposed such that at least a portion of the first semiconductor element (1000) overlaps the bonding portions (140) along a horizontal direction.

[0083] Molding parts (191, 192) may be arranged on one side and the other side of the insulating layer, respectively. The molding parts (191, 192) may be made of a different material from the insulating layer.

[0084] The molding portion (191, 192) may include a first molding portion (191) disposed on the upper surface of the first insulating layer (101) and a second molding portion (192) disposed on the lower surface of the eighth insulating layer (108). The first molding portion (191) has a predetermined thickness in the vertical direction, and the bonding portion (140) and the first semiconductor element (1000) may be wrapped by the first molding portion (191). The second molding portion (192) has a predetermined thickness in the vertical direction, and the second to fourth semiconductor elements (2000, 3000, 4000) may be wrapped by the second molding portion (192).

[0085] Meanwhile, when the first to eighth insulating layers (101, 102, 103, 104, 105, 106, 107, 108) are all named as the first insulating layer, the second molding part (192) can be named as the second insulating layer.

[0086] In addition, the cavity formation structure using a single insulating layer has the advantage of making it easier to secure cavity space and preventing eccentricity from occurring in the cavity formation process between different insulating layers.

[0087] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present invention.

[0088] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

[0089] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0090] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Insulating layer; A pad portion disposed on the insulating layer; and Including a bonding portion arranged on the above pad portion, The above bonding portion is a circuit board arranged to surround the above pad portion.

2. In paragraph 1, A circuit board in which the above bonding portion is arranged to surround the upper surface and side surfaces of the above pad portion.

3. In paragraph 1, A circuit board including a seed layer disposed between the insulating layer and the bonding portion.

4. In paragraph 3, A circuit board in which the seed layer has a width wider than the width of the pad portion, based on the horizontal direction.

5. In paragraph 3, A circuit board in which, with respect to the horizontal direction, the seed layer has a width equal to or smaller than the width of the bonding portion.

6. In paragraph 3, A circuit board including a first portion in contact with the pad portion and a second portion in contact with the bonding portion, wherein the seed layer is a first portion in contact with the pad portion.

7. In paragraph 1, A second insulating layer is disposed on the insulating layer, A circuit board in which the above bonding portion is wrapped with the second insulating layer.

8. In paragraph 7, A circuit board in which the second insulating layer is made of a different material from the material of the insulating layer.

9. In paragraph 1, It includes a semiconductor element disposed on the above insulating layer, The above bonding portion is provided in multiple numbers and is spaced apart along the horizontal direction, A circuit board in which the above plurality of bonding portions are arranged around the semiconductor element.

10. In paragraph 1, A circuit board in which the horizontal central axis of the bonding portion is misaligned with the horizontal central axis of the pad portion.

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