TGV substrate having thermal durability and manufacturing method thereof

Abstract

A through glass via (TGV) substrate according to an embodiment of the present invention may comprise: a glass substrate comprising a TGV; an alloy coating layer which comprises an alloy containing a first metal material and a second metal material and which is coated on the inner wall of the TGV; and a conductive material disposed on the alloy coating layer and filling the TGV.

Description

Heat-resistant TGV substrate and manufacturing method thereof

[0001] The present invention relates to a TGV substrate and a method for manufacturing the same, and is a TGV substrate technology that improves thermal durability by positioning a thermal expansion stress relief material between conductive material substrates in a TGV.

[0002] With the advancement of 2.5D and 3D stacking technologies in the semiconductor packaging field, interposer technology that meets the demands of high integration, low power, and miniaturization is attracting attention. Interposers have a structure that forms penetrating electrodes inside a substrate to implement electrical connections between dies, and the representative method for implementing this is Through Silicon Via (TSV) technology. Existing TSV technology has limitations in electrical loss and process cost because it uses a silicon substrate. In contrast, Through Glass Via (TGV) technology, which uses a glass substrate instead of silicon, is emerging as a next-generation packaging technology due to its advantages of excellent insulation properties, low dielectric loss, and low-cost mass production.

[0003] In the TGV structure, the interior of the vias in the glass substrate are filled with a metal material for electrical connection. However, if the coefficient of thermal expansion between the glass substrate and the filling metal is large, problems such as interface delamination, cracks, and mechanical damage may occur during high-temperature processes or repeated thermal shock environments. Various technologies are being studied to alleviate these problems in the existing TSV structure. However, these technologies are optimized for silicon substrate-based structures and have limitations in directly applying them to alleviate the thermal stress of TGVs. Therefore, a new structure and manufacturing method that can alleviate the mismatch in the coefficient of thermal expansion between the glass and the filling metal are required.

[0004] In order to solve the above-mentioned problem, the present invention provides a TGV substrate and a method for manufacturing the same, which can alleviate thermal stress due to a mismatch in thermal expansion coefficient between a glass substrate and a conductive material by providing an alloy coating layer on the inner wall of a glass substrate having a glass penetration via formed thereon.

[0005] A TGV substrate according to one embodiment of the present invention may include a glass substrate including a Through Glass Via (TGV), an alloy coating layer including an alloy composed of a first metal material and a second metal material and coated on an inner wall of the Through Glass Via, and a conductive material positioned on the alloy coating layer to fill the Through Glass Via.

[0006] Additionally, according to one embodiment, the coefficient of thermal expansion of the alloy coating layer may be characterized as being between the coefficients of thermal expansion of the conductive material and the glass substrate.

[0007] Additionally, according to one embodiment, the challenge material may be characterized as being Cu.

[0008] Additionally, according to one embodiment, the first metal material may be characterized as being Ni.

[0009] Additionally, according to one embodiment, the second metal material may be characterized as being Fe.

[0010] Additionally, according to one embodiment, the alloy coating layer may be characterized in that the atomic ratio of the first metal material and the second metal material is within a range of 1:3 to 1:0.5.

[0011] Additionally, according to one embodiment, the coefficient of thermal expansion of the alloy coating layer may be characterized as being 8.5 to 15.5 ppm / ℃.

[0012] Additionally, according to one embodiment, the thickness of the alloy coating layer may be characterized as being 6 to 30 μm.

[0013] Additionally, according to one embodiment, the alloy coating layer may be formed from a seed coating layer formed on the inner wall of the glass through-via, including a first metal material, and the seed coating layer may be characterized in that it is deposited by electroless deposition.

[0014] Additionally, according to one embodiment, the alloy coating layer may be characterized by being deposited by electro-deposition.

[0015] A method for manufacturing a TGV substrate according to one embodiment of the present invention may include a step of preparing a glass substrate, a step of forming a through glass via (TGV) in the glass substrate, a step of coating a seed coating layer including a first metal material on an inner wall of the TGV, a step of coating an alloy coating layer including an alloy of a first metal material and a second metal material based on the seed coating layer, and a step of filling a conductive material on the alloy coating layer to fill the TGV.

[0016] Additionally, according to one embodiment, the coefficient of thermal expansion of the alloy coating layer may be characterized as being between the coefficients of thermal expansion of the conductive material and the glass substrate.

[0017] Additionally, according to one embodiment, the challenge material may be characterized as being Cu.

[0018] Additionally, according to one embodiment, the first metal material may be characterized as being Ni.

[0019] Additionally, according to one embodiment, the second metal material may be characterized as being Fe.

[0020] Additionally, according to one embodiment, the alloy coating layer may be characterized in that the atomic ratio of the first metal material and the second metal material is within a range of 1:3 to 1:0.5.

[0021] Additionally, according to one embodiment, the coefficient of thermal expansion of the alloy coating layer may be characterized as being 8.5 to 15.5 ppm / ℃.

[0022] In addition, according to one embodiment, the step of coating the alloy coating layer on the seed coating layer may be characterized by coating the alloy coating layer to a thickness in the range of 6 to 30 μm.

[0023] Additionally, according to one embodiment, the step of coating the seed coating layer on the inner wall of the glass through-via may be characterized by depositing the seed coating layer by electroless deposition.

[0024] Additionally, according to one embodiment, the step of coating the alloy coating layer on the seed coating layer may be characterized by depositing the alloy coating layer by electro-deposition.

[0025] According to the TGV substrate of the present invention and the method for manufacturing the same, an alloy coating layer is provided on the inner wall of a glass substrate on which a glass through via is formed, thereby alleviating thermal stress due to a mismatch in thermal expansion coefficient between the glass substrate and the conductive material.

[0026] Fig. 1 is a cross-sectional view of a TGV substrate according to one embodiment of the present invention.

[0027] Fig. 2 is a cross-sectional view of a TGV substrate of the present invention according to another embodiment.

[0028] Figure 3 is a flowchart of a method for manufacturing a TGV substrate according to one embodiment of the present invention.

[0029] Fig. 4 is a SEM (Scanning electron microscopy) image of a TGV substrate of the present invention according to one embodiment, and Fig. 5 is an EDS (Energy Dispersive Spectroscopy) analysis result of the same TGV substrate.

[0030] Figures 6 to 8 are SEM and EDS images of TGV substrates according to various embodiments.

[0031] Figures 9 to 11 are graphs showing the results of XRD (X-ray Diffraction) analysis of alloy coating layers according to various embodiments, and Figure 12 is a graph showing the change in thermal expansion coefficient according to the alloy composition ratio according to each embodiment.

[0032] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0033] The terms used in this specification will be briefly explained, and the present invention will be described in detail.

[0034] The terms used in this invention have been selected from widely used, current terms, taking into account the functions of the invention. However, these terms may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc. Furthermore, in certain cases, terms may be arbitrarily selected by the applicant, in which case their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should not be defined simply as names, but rather based on their inherent meanings and the overall content of the invention.

[0035] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily practice them. Furthermore, in order to clearly explain the present invention, portions irrelevant to the description are omitted in the drawings.

[0036] When a part of the specification is said to "include" a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated. Furthermore, terms such as "part," "module," and "unit" used in the specification may refer to a unit that processes at least one function or operation.

[0037] Terms including ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, the first component could be referred to as the second component, and similarly, the second component could also be referred to as the first component. The term "and / or" includes any combination of multiple related items or any one of multiple related items.

[0038]

[0039] The present invention relates to a TGV substrate. TGV (Through Glass Via) technology is a next-generation semiconductor packaging technology that implements electrical connections between dies by filling the interior of microscopic via holes penetrating a glass substrate with metal. TGV has advantages over Through Silicon Via (TSV), such as superior insulation properties, low dielectric loss, cost competitiveness in mass production, and the possibility of special applications utilizing transparent substrates, and can be applied to various fields such as 3D stacked structures, high-frequency circuits, sensors, and wearable devices.

[0040] However, in TGV structures, the coefficient of thermal expansion between the glass substrate and the metal filling the vias can differ significantly. This mismatch can generate significant thermal stress between the substrate and the metal during high-temperature processing or repeated thermal shock environments, potentially leading to deteriorated mechanical reliability issues such as interface delamination, cracks, and substrate damage. Existing TSV-related thermal stress relief technologies are optimized for silicon substrates, making them difficult to apply directly to TGVs using glass substrates.

[0041] To address these issues, the present invention proposes a TGV structure that mitigates thermal stress by forming a metal alloy layer with a controlled coefficient of thermal expansion between the glass substrate and the filling metal as a buffer layer. This buffer layer configuration allows the TGV substrate of the present invention to maintain interface stability even in high-temperature environments and repeated thermal shocks, and ensures long-term mechanical reliability, enabling stable application in high-performance and high-density semiconductor packaging.

[0042]

[0043] Hereinafter, the TGV substrate (1) of the present invention will be described.

[0044] Fig. 1 is a cross-sectional view of a TGV substrate (1) of the present invention according to one embodiment.

[0045] Referring to FIG. 1, the TGV substrate (1) of the present invention may include a glass substrate (10), an alloy coating layer (20), and a conductive material (30).

[0046] The glass substrate (10) is a substrate forming the base of the TGV substrate (1) of the present invention, and may be formed of a material having excellent insulating properties and low dielectric loss characteristics. A plurality of through glass vias (TGVs, 15) for electrical connection may be formed on the glass substrate (10), and these vias (15) may be implemented through a processing method such as laser processing, sapphire drilling, injection molding, or chemical etching. The glass substrate (10) may have an appropriate thickness so as to maintain mechanical strength even after the TGV is formed, and the diameter, depth, and aspect ratio of the vias (15) may vary depending on the requirements of the metal filling process and packaging structure.

[0047] A glass penetration via (15) is an opening penetrating a glass substrate (10) and can serve as a passage for electrically connecting both sides of the substrate. The glass penetration via (15) can be processed so that its internal surface condition for subsequent metal filling is maintained in good condition, and its diameter, depth, aspect ratio, etc. can be adjusted according to design specifications and electrical and mechanical requirements. In addition, the internal surface of the via (15) can undergo a pretreatment process such as cleaning and activation to ensure uniform deposition of a seed coating layer (25) described below and stable formation of an alloy coating layer (20).

[0048] The alloy coating layer (20) may be formed on the inner wall of the glass penetration via (15) by including an alloy composed of a first metal material and a second metal material different from the first metal material. The alloy coating layer (20) may be a buffer layer for alleviating the difference in thermal expansion coefficient between the glass substrate (10) and the conductive material (30) and preventing interface delamination. The alloy coating layer (20) is a key component of the present invention and can effectively alleviate thermal shock caused by repeated thermal expansion and contraction between the glass substrate (10) and the conductive material (30). The alloy coating layer (20) can disperse stress concentrated at the interface during the thermal cycling process by buffering the difference in thermal expansion coefficient between the two materials (substrate and conductive material (30)) with the alloy included therein. This stress dispersing effect can suppress the progression of microcracks that may occur in a long-term use environment and prevent interface delamination or substrate damage, thereby significantly improving the reliability of the entire packaging structure. The alloy coating layer (20) can be continuously formed on the inner wall of the glass penetration via (15), and the thickness can be in a range that can simultaneously secure a thermal stress relief effect and plating uniformity.

[0049] In addition, the alloy coating layer (20) of the present invention can freely set the coefficient of thermal expansion within the design range, thereby alleviating thermal stress caused by the difference in the coefficient of thermal expansion between the glass substrate (10) and the conductive material (30). For example, the alloy coating layer (20) can control the coefficient of thermal expansion by adjusting the composition ratio of the first metal material and the second metal material. Through these characteristics, the TGV substrate (1) of the present invention can be stably applied in various design conditions and usage environments in which the diameter, depth, and aspect ratio of the glass through via (15) are different.

[0050] The alloy coating layer (20) can be formed by a metal deposition method using power, such as electroplating, and detailed process conditions can be controlled so that the composition ratio and thickness of the alloy are maintained uniformly. At this time, the composition of the alloy can be adjusted to be located between the thermal expansion coefficient ranges of the glass substrate (10) and the conductive material (30), so that stable interface characteristics can be maintained even in a repetitive thermal shock environment. However, the method of forming the alloy coating layer (20) is not limited to the above-described method.

[0051] According to one embodiment, the alloy coating layer (20) may be formed by first forming a seed coating layer (25) made of a first metal material on the inner wall of a glass penetration via (15), and then forming an alloy of the first metal material and the second metal material through a plating process including a second metal material. This stepwise forming method increases the initial adhesive strength of the alloy layer, ensures uniformity of the alloy composition, and ultimately enables more stable relief of stress due to a difference in thermal expansion coefficient between the glass substrate (10) and the conductive material (30).

[0052] Here, the first metal material can be applied without limitation as long as it has excellent conductivity and adhesion and is a metal that can be electroless plated, and may include, for example, Ni, Cu, Co, Pd, Pt, etc. In one embodiment, the first metal material may be Ni. Ni has excellent adhesion to the glass substrate (10), stable metallurgical bonding with the Ni-Fe alloy coating layer (20) described below, and excellent electrical conductivity and corrosion resistance, and thus may be preferable as a metal material included in the seed coating layer (25) and the alloy coating layer (30).

[0053] In addition, the second metal material can be alloyed with the first metal material, and any metal capable of controlling the thermal expansion coefficient of the alloy can be applied without limitation. For example, the second metal material can include Fe, Co, W, Mo, Cr, etc. In one embodiment, when the first metal material is Ni, the second metal material can be Fe. Fe can be utilized to control the thermal expansion coefficient to an intermediate value between the glass substrate (10) and the conductive material (30) through alloy formation with Ni, and can be preferable as a metal material included in the alloy coating layer (20) because it has the effect of improving the mechanical strength and heat resistance of the alloy layer.

[0054] The conductive material (30) can be positioned on the alloy coating layer (20) and fill the glass through via (15). The conductive material (30) can electrically connect both sides of the substrate by filling the glass through via (15), and any metal that can provide low electrical resistance and excellent reliability can be applied without limitation. The conductive material (30) can include, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), etc. Among these, copper has high electrical conductivity and excellent price competitiveness, and can be applied to an electrolytic plating process suitable for mass production, so it can be used as the most preferable conductive material (30).

[0055] The conductive material (30) can be formed on the alloy coating layer (20) by electrolytic plating, electroless plating, deposition, or other methods, and the process conditions can be controlled so that the interior of the via (15) is filled without any gaps. In addition, the conductive material (30) forms a stable metallurgical bond with the alloy coating layer (20), thereby minimizing interface resistance and stably maintaining an electrical connection even in high temperature, high humidity, and thermal shock environments.

[0056]

[0057] Fig. 2 is a cross-sectional view of a TGV substrate (1) of the present invention according to another embodiment.

[0058] Referring to FIG. 2, the TGV substrate (1) may further include a seed coating layer (25).

[0059] According to one embodiment, the alloy coating layer (20) of the present invention may be prepared by first forming a seed coating layer (25) and then performing a separate plating process to form an alloy of a first metal material and a second metal material thereon. In this case, the seed coating layer (25) formed in the initial stage is not removed even after the subsequent alloy coating layer (20) is formed, but remains inside the substrate, and can be included as a structural part of the final TGV substrate (1).

[0060] The seed coating layer (25) can be formed on the inner wall of the glass through via (15) including the first metal material, and can serve as a base layer for uniform growth of the subsequent alloy coating layer (20) and stable filling of the conductive material (30). The seed coating layer (25) can be continuously formed on the entire inner wall of the glass through via (15), and the thickness can be in a range that can secure the adhesion stability and plating uniformity of the subsequent alloy coating layer (20). The seed coating layer (25) forms a continuous metal film structure interposed between the substrate surface and the alloy coating layer (20), and can function as a part of an electrical connection path and a mechanical support layer.

[0061] The seed coating layer (25) can be formed by a deposition method utilizing a chemical reaction without a power supply, such as electroless deposition, and detailed process conditions can be controlled so that it is uniformly coated on the entire inner wall of the glass through-via (15). However, the method of forming the seed coating layer (25) is not limited to the above-described method.

[0062]

[0063] Hereinafter, a method for manufacturing a TGV substrate (1) of the present invention will be described.

[0064] Fig. 3 is a flowchart of a method for manufacturing a TGV substrate (1) of the present invention according to one embodiment.

[0065] Referring to FIG. 3, a method for manufacturing a TGV substrate (1) may include a step of preparing a glass substrate (10) (S110), a step of forming a glass penetration via (15) in the glass substrate (10) (S120), a step of coating a seed coating layer (25) including a first metal material on the inner wall of the glass penetration via (15) (S130), a step of coating an alloy coating layer (20) including an alloy of a first metal material and a second metal material based on the seed coating layer (25) (S140), and a step of filling a conductive material (30) on the alloy coating layer (20) to fill the glass penetration via (15) (S150).

[0066] According to one embodiment, the step (S120) of forming a glass through-via (15) is a process of processing a through-hole for electrically connecting both sides of a substrate, and may be performed through various methods such as laser drilling, sapphire drilling, mechanical drilling, sandblasting, chemical etching, etc. The formed glass through-via (15) is designed to be suitable for the deposition and filling processes of the seed coating layer (25), the alloy coating layer (20), and the conductive material (30), and the diameter, depth, and aspect ratio may be set in consideration of the required electrical characteristics and mechanical stability. In addition, after the formation of the via (15), a cleaning and pretreatment process may be performed to remove roughness or contaminants on the internal surface.

[0067] The step (S130) of coating the seed coating layer (25) on the inner wall of the glass penetration via (15) is a process of forming a base metal film so that the subsequent alloy coating layer (20) can grow uniformly and the conductive material (30) can be stably filled. According to one embodiment, in this step, a metal layer including a first metal material can be uniformly formed on the entire inner wall of the via (15) by a deposition method using a chemical reaction without a power supply, such as electroless deposition. The formed seed coating layer (25) can improve the adhesive strength between the glass substrate (10) and the metal layer, and provide a current path in the subsequent electrolytic plating process to ensure the adhesion and uniformity of the alloy coating layer (20).

[0068] The step (S140) of coating the alloy coating layer (20) on the seed coating layer (25) is a process of forming an alloy layer composed of a first metal material and a second metal material. According to one embodiment, the step of coating the alloy coating layer (20) may be performed by depositing the alloy layer by electroplating using the seed coating layer (25) formed on the inner wall of the glass through-via (15) as a current supply path. In this step, the first metal ions and the second metal ions are simultaneously supplied in the electrolyte so that an alloy is formed on the surface of the seed coating layer (25), and the composition ratio of the alloy is adjusted so that it is positioned between the thermal expansion coefficient ranges of the glass substrate (10) and the conductive material (30), thereby forming an alloy coating layer (20) that can relieve thermal stress and prevent interfacial peeling. In addition, by controlling the electroplating conditions in the step of coating the alloy coating layer (20), the thickness of the alloy coating layer (20) can be freely controlled within the required range, and by controlling detailed process conditions such as current density, plating time, and electrolyte composition so that the thickness of the alloy coating layer (20) is maintained uniformly, a buffer layer with excellent mechanical and thermal stability can be implemented.

[0069]

[0070] Hereinafter, an experimental example of a TGV substrate (1) according to one embodiment of the present invention will be described. In this experimental example, an experiment was conducted on a TGV substrate (1) in which a Ni-Fe alloy coating layer (20) was formed using Ni as a first metal material and Fe as a second metal material, and Cu was filled as a conductive material (30).

[0071] Fig. 4 is a SEM (Scanning electron microscopy) image of a TGV substrate (1) of the present invention according to one embodiment. In addition, Fig. 5 is an EDS (Energy Dispersive Spectroscopy) analysis result of the same TGV substrate (1).

[0072] Referring to FIGS. 4 and 5, it can be seen that a plurality of glass penetration vias (15) formed on a glass substrate (10) are coated with an alloy coating layer (20) and filled with a conductive material (30). Specifically, Cu is uniformly distributed in the internal filling portion of the via (15), and Ni and Fe are uniformly distributed along the wall surface of the via (15). Referring to the element composition of the analysis portion and the respective mass ratio (Mass %) and atomic ratio (Atom %), it can be confirmed that Fe is measured to be approximately 31.66 at% and Ni is measured to be approximately 66.23 at%, and thus the Ni-Fe alloy coating layer (20) is uniformly formed on the interface.

[0073] Figures 6 to 8 are SEM and EDS images of TGV substrates (1) according to various embodiments.

[0074] FIGS. 6 to 8 show cases where the alloy coating layer (20) is formed to have a thickness of about 5.83 μm, 18 μm, and 30 μm, respectively, and it can be confirmed from the element mapping results that Fe and Ni are uniformly distributed along the wall surface of the via (15). Oxygen (O) and silicon (Si) are clearly detected in the glass substrate (10) region, and Fe and Ni are clearly detected in the alloy coating layer (20), so it can be visually confirmed that the internal structure of the via (15) is stably formed according to the change in the thickness of the alloy coating layer (20). The TGV substrate (1) of the present invention and its manufacturing method can control the thickness of the alloy coating layer (20) in this way, and thereby flexibly respond to cases where the thickness of the appropriate alloy coating layer (20) changes according to the diameter of the glass through-via (15).

[0075] Figures 9 to 11 are graphs showing the results of XRD (X-ray Diffraction) analysis of an alloy coating layer (20) according to various embodiments, and Figure 12 is a graph showing the change in thermal expansion coefficient according to the alloy composition ratio according to each embodiment.

[0076] Figures 9 to 11 are the analysis results for cases where the atomic ratio of Ni:Fe is 1:3, 1:1, and 2:1, respectively, and each graph shows the diffraction pattern measured while changing the temperature from 25°C to 400°C. The measurement results show that the thermal expansion coefficient (α) is 15.45X10, respectively, depending on the alloy composition. -6 / ℃, 8.67Х10 -6 / ℃, 10.48Х10 -6It can be confirmed that the difference in thermal expansion coefficient between the glass substrate (10) and the conductive material (30) is / ℃, which indicates that the difference in thermal expansion coefficient between the glass substrate (10) and the conductive material (30) can be controlled by adjusting the alloy composition ratio. In addition, referring to FIG. 12, it can be confirmed that the lowest thermal expansion coefficient value is shown when the composition ratio is adjusted to 1:1, which suggests that the most advantageous thermal expansion coefficient between the glass substrate (10) and the conductive material (30) can be confirmed, and the composition ratio can be adjusted accordingly to coat with a material having the corresponding thermal expansion coefficient.

[0077]

[0078] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

[0079]

[0080] The TGV substrate of the present invention and its manufacturing method have high industrial applicability because they can alleviate thermal stress due to thermal expansion coefficient mismatch between the glass substrate and the conductive material by providing an alloy coating layer on the inner wall of the glass substrate on which a glass through-via is formed.

Claims

1. A glass substrate including a through glass via (TGV); An alloy coating layer coated on the inner wall of the glass through-via, including an alloy composed of a first metal material and a second metal material; and A conductive material positioned on the alloy coating layer and filling the glass through-via; TGV board.

2. In paragraph 1, The coefficient of thermal expansion of the above alloy coating layer is Characterized in that the coefficient of thermal expansion of the above-mentioned challenging material and the above-mentioned glass substrate is between TGV board.

3. In paragraph 2, The above challenge material is, Characterized by Cu TGV board.

4. In paragraph 3, The above first metal material is, Characterized by Ni TGV board.

5. In paragraph 4, The above second metal material is, characterized by being Fe TGV board.

6. In paragraph 5, The above alloy coating layer is, Characterized in that the atomic ratio of the first metal material and the second metal material is within the range of 1:3 to 1:0.

5. TGV board.

7. In paragraph 3, The coefficient of thermal expansion of the above alloy coating layer is Characterized by 8.5 to 15.5 ppm / ℃ TGV board.

8. In paragraph 1, The thickness of the above alloy coating layer is: Characterized by being 6 to 30 μm TGV board.

9. In paragraph 1, The above alloy coating layer is, It is formed from a seed coating layer formed on the inner wall of a glass through-via, including a first metal material, The above seed coating layer, characterized by being deposited by electroless deposition TGV board.

10. In paragraph 9, The above alloy coating layer is, Characterized by being deposited by electro-deposition TGV board.

11. Step of preparing a glass substrate; A step of forming a through glass via (TGV) in the above glass substrate; A step of coating a seed coating layer including a first metal material on the inner wall of the glass through-via; A step of coating an alloy coating layer including an alloy made of the first metal material and the second metal material based on the seed coating layer; and A step of filling the glass through-via by filling a conductive material on the alloy coating layer; TGV substrate manufacturing method.

12. In paragraph 11, The coefficient of thermal expansion of the above alloy coating layer is Characterized in that the coefficient of thermal expansion of the above-mentioned challenging material and the above-mentioned glass substrate is between TGV substrate manufacturing method.

13. In paragraph 12, The above challenge material is, Characterized by Cu TGV substrate manufacturing method.

14. In paragraph 13, The above first metal material is, Characterized by Ni TGV substrate manufacturing method.

15. In paragraph 14, The above second metal material is, characterized by being Fe TGV substrate manufacturing method.

16. In paragraph 15, The above alloy coating layer is, Characterized in that the atomic ratio of the first metal material and the second metal material is within the range of 1:3 to 1:0.

5. TGV substrate manufacturing method.

17. In paragraph 13, The coefficient of thermal expansion of the above alloy coating layer is Characterized by 8.5 to 15.5 ppm / ℃ TGV substrate manufacturing method.

18. In paragraph 11, The step of coating the above alloy coating layer on the seed coating layer is: Characterized in that the thickness of the alloy coating layer is coated within the range of 6 to 30 μm. TGV substrate manufacturing method.

19. In paragraph 11, The step of coating the seed coating layer on the inner wall of the glass through-via is as follows: characterized in that the seed coating layer is deposited by electroless deposition. TGV substrate manufacturing method.

20. In paragraph 19, The step of coating the above alloy coating layer on the seed coating layer is: Characterized in that the alloy coating layer is deposited by electro-deposition. TGV substrate manufacturing method.

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