Method and system for change-aware circuit design verifications

Abstract

A system and a method for circuit design verification. The system and a method may reuse data generated in a verification iteration of a previous IC layout, thereby skipping one or more respective steps and / or reducing computation in the verification iteration for the current IC layout, thereby reducing the runtime for verifying the current IC layout. The method includes storing first IC layout data for a first IC layout; identifying one or more modifications between the first IC layout and a second IC layout; analyzing the one or more modifications; and based on the analysis of the one or more modifications, performing one or more of skipping a respective step of the plurality of steps, performing less computation for the respective step, or re-performing the respective step.

Description

202408140METHOD AND SYSTEM FOR CHANGE-AWARE CIRCUIT DESIGN VERIFICATIONSFIELD

[0001] The disclosed technology relates to the field of circuit design and circuit manufacturing, and specifically relates to circuit design verification.BACKGROUND

[0002] Electronic circuits, such as integrated circuits (ICs), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating an IC typically involves many steps, sometimes referred to as a “design flow.” The particular steps of the design flow often are dependent upon the type of integrated circuit, its complexity, the design team, and the integrated circuit fabricator or foundry that will manufacture the IC. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and / or hardware emulators. These steps aid in the discovery of errors in the design and allow the designers and engineers to correct or otherwise improve the design.

[0003] Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, such as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”

[0004] After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. The relationships between the electronic devices are then analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.

[0005] Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are202408140 polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing IC components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices.

[0006] Circuit layout descriptions can be provided in many different formats. These various industry formats are used to define the geometrical information in design layouts that are employed to manufacture integrated circuits.

[0007] Physical verification may validate that the physical layout of the IC complies with design rules including constraints imposed by the manufacturing process. Physical verification may include checking for compliance with manufacture rules regarding geometric constraints that are essential for manufacturability or performance. For example, a circuit design modeler typically will analyze (e.g., verify) a design to ensure that each circuit feature described in the design complies with design rules specified by the foundry that will manufacture microcircuits from the design. As IC designs became more complex, advanced electronic design automation tools like Calibre™ PERC were developed.

[0008] After determining a physical layout of the IC design, in general, designers perform tight iteration of “fix and verify.” In other words, when the physical verification tool identifies that the IC layout does not comply with the design rules, designers may modify or revise the IC layout to fix a potential problem, and then may execute the physical verification for the modified design. This “fix and verify” iteration may generally be repeated until the designer finds the IC layout that complies with all design rules, after which, the IC layout may be used to manufacture electronics, such as integrated circuits. Depending on the size of IC layout and the number of the rules that need to be checked, runtime of the tool to perform the physical verification can vary. Due to explosion in the combined impact of design size and the number of rules that need to be checked, the runtime of the tool to perform the physical verification may increase and a number of repetitions of “fix and verify” may cause delay in layout design.SUMMARY

[0009] In one embodiment, a computer-implemented method is disclosed. The method includes: storing first IC layout data generated by performing a plurality of steps to verify a first IC layout; identifying one or more modifications between the first IC layout and a second IC layout; analyzing the one or more modifications; and based on the analysis of the one or more202408140 modifications, verifying the second IC layout by performing one or more of: skipping a respective step of the plurality of steps by accessing at least a part of the first IC layout data; performing less computation for the respective step than performed for the respective step in verifying the first IC layout by performing the respective step on only a portion of the second IC layout and accessing the first IC layout data for part or all of a remaining portion of the second IC layout; or re-performing the respective step.

[0010] In another embodiment, a system is disclosed. The system includes at least one processor and at least one memory storing computer-executable instructions is disclosed. The computer-executable instructions, when executed by at least one processor, cause the system to: store first IC layout data generated by performing a plurality of steps to verify a first IC layout; identify one or more modifications between the first IC layout and a second IC layout; analyze the one or more modifications; and based on the analysis of the one or more modifications, verify the second IC layout by performing one or more of: skipping a respective step of the plurality of steps by accessing at least a part of the first IC layout data; performing less computation for the respective step than performed for the respective step in verifying the first IC layout by performing the respective step on only a portion of the second IC layout and accessing the first IC layout data for part or all of a remaining portion of the second IC layout; or re-performing the respective step.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of the invention and together with the description, serve to explain its principles. Wherever convenient, the same reference numbers will be used throughout the drawings to refer to the same or like elements.

[0012] FIG. 1 illustrates an example of a computing system that may be used to implement various embodiments of the disclosed technology.

[0013] FIG. 2 illustrates an example of a multi-core processor unit that may be used to implement various embodiments of the disclosed technology.

[0014] FIG. 3 is a block diagram illustrating a verification tool according to an embodiment of the disclosed technology.

[0015] FIG. 4A illustrates a flow chart illustrating full verification of a first IC layout.

[0016] FIG. 4B illustrates a flow chart illustrating full verification of a second IC layout.

[0017] FIG. 5 illustrate application of the verification method to example layout.DETAILED DESCRIPTION OF EMBODIMENTSGeneral Considerations202408140

[0018] Various aspects of the present disclosed technology relate to techniques for IC layout verification which may reuse data of a previous IC layout in a verification iteration (e.g., the plurality of steps performed in verifying a respective IC layout) with a modified IC layout, thereby reducing the runtime for IC layout verification. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present disclosed technology.

[0019] Some of the techniques described herein can be implemented in software instructions stored on one or more non-transitory machine-readable media, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0020] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the disclosed flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods. Additionally, the detailed description sometimes uses terms like “perform”, “generate,” “access,” “determine,” “decide,” “select,” and “identify” to describe the disclosed methods. Such terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0021] Also, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device, however, such as a portion of an integrated circuit device. Still further, the term “design” also is intended to encompass data describing more than one micro device, such as data to be used to form multiple micro devices on a single wafer.Illustrative Operating Environment

[0022] The execution of various electronic design automation processes according to embodiments of the disclosed technology may be implemented using computer-executable202408140 software instructions executed by one or more programmable computing devices. Because these embodiments of the disclosed technology may be implemented using software instructions, the components and operation of a generic programmable computer system on which various embodiments of the disclosed technology may be employed will first be described. Further, because of the complexity of some electronic design automation processes and the large size of many circuit design models, various electronic design automation tools are configured to operate on a computing system capable of simultaneously running multiple processing threads. The components and operation of a computer network having a host or master computer and one or more remote or servant computers therefore will be described with reference to FIG. 1. This operating environment is only one example of a suitable operating environment, however, and is not intended to suggest any limitation as to the scope of use or functionality of the disclosed technology.

[0023] In FIG. 1 , the computer network 101 includes a master computer 103. In the illustrated example, the master computer 103 is a multi-processor computer that includes a plurality of input / output devices 105 and a memory 107. The input / output devices 105 may include any device for receiving input data from or providing output data to a user. The input devices may include, for example, a keyboard, microphone, scanner or pointing device for receiving input from a user. The output devices may then include a display monitor, speaker, printer or tactile feedback device. These devices and their connections are well known in the art, and thus will not be discussed at length here.

[0024] The memory 107 may similarly be implemented using any combination of machine readable media, such as computer readable media that can be accessed by the master computer 103. The computer readable media may include, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable media may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, punched media, holographic storage devices, or any other medium that can be used to store desired information.

[0025] As will be discussed in detail below, the master computer 103 runs a software application for performing one or more operations according to various examples of the disclosed technology. Accordingly, the memory 107 stores software instructions 109A that, when executed, will implement a software application for performing one or more operations, such as the operations disclosed herein. The memory 107 also stores data 109B to be used with the software202408140 application. In the illustrated embodiment, the data 109B contains process data that the software application uses to perform the operations, at least some of which may be parallel.

[0026] The master computer 103 also includes a plurality of processor units 111 and an interface device 113. The processor units 111 may be any type of processor device that can be programmed to execute the software instructions 109A, but will conventionally be a microprocessor device. For example, one or more of the processor units 111 may be a commercially generic programmable microprocessor, such as Intel® Pentium® or Xeon™ microprocessors, Advanced Micro Devices Athlon™ microprocessors or Motorola 68K / Coldfire® microprocessors. Alternately or additionally, one or more of the processor units 111 may be a custom-manufactured processor, such as a microprocessor designed to optimally perform specific types of mathematical operations. The interface device 113, the processor units 111 , the memory 107 and the input / output devices 105 are connected together by a bus 115.

[0027] With some implementations of the disclosed technology, the master computer 103 may employ one or more processing units 111 having more than one processor core. Accordingly, FIG. 2 illustrates an example of a multi-core processor unit 111 that may be employed with various embodiments of the disclosed technology. As seen in this figure, the processor unit 111 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As known to those of ordinary skill in the art, a computing engine contains logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203 may then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0028] Each processor core 201 is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 111. With some processor cores 201 , such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 111 , however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, Calif., the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201 communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface between the processor unit 111 and the bus 115. Similarly, the202408140 memory controller 210 controls the exchange of information between the processor unit 111 and the system memory 107. With some implementations of the disclosed technology, the processor units 111 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201.

[0029] While FIG. 2 shows one illustration of a processor unit 111 that may be employed by some embodiments of the disclosed technology, it should be appreciated that this illustration is representative only, and is not intended to be limiting. Also, with some implementations, a multicore processor unit 111 can be used in lieu of multiple, separate processor units 111. For example, rather than employing six separate processor units 111 , an alternate implementation of the disclosed technology may employ a single processor unit 111 having six cores, two multi-core processor units each having three cores, a multi-core processor unit 111 with four cores together with two separate single-core processor units 111 , etc.

[0030] Returning now to FIG. 1 , the interface device 113 allows the master computer 103 to communicate with the servant computers 117A, 117B, 117C . . . 117x through a communication interface. The communication interface may be any suitable type of interface including, for example, a conventional wired network connection or an optically transmissive wired network connection. The communication interface may also be a wireless connection, such as a wireless optical connection, a radio frequency connection, an infrared connection, or even an acoustic connection. The interface device 113 translates data and control signals from the master computer 103 and each of the servant computers 117 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP), the user datagram protocol (UDP), and the Internet protocol (IP). These and other conventional communication protocols are well known in the art, and thus will not be discussed here in more detail.

[0031] Each servant computer 117 may include a memory 119, a processor unit 121 , an interface device 123, and, optionally, one more input / output devices 125 connected together by a system bus 127. As with the master computer 103, the optional input / output devices 125 for the servant computers 117 may include any conventional input or output devices, such as keyboards, pointing devices, microphones, display monitors, speakers, and printers. Similarly, the processor units 121 may be any type of conventional or custom-manufactured programmable processor device. For example, one or more of the processor units 121 may be commercially generic programmable microprocessors, such as Intel® Pentium® or Xeon™ microprocessors, Advanced Micro Devices Athlon™ microprocessors or Motorola 68K / Coldfire® microprocessors. Alternately, one or more of the processor units 121 may be custom-manufactured processors, such as202408140 microprocessors designed to optimally perform specific types of mathematical operations. Still further, one or more of the processor units 121 may have more than one core, as described with reference to FIG. 2 above. For example, with some implementations of the disclosed technology, one or more of the processor units 121 may be a Cell processor. The memory 119 then may be implemented using any combination of the computer readable media discussed above. Like the interface device 113, the interface devices 123 allow the servant computers 117 to communicate with the master computer 103 over the communication interface.

[0032] In the illustrated example, the master computer 103 is a multi-processor unit computer with multiple processor units 111 , while each servant computer 117 has a single processor unit 121. It should be noted, however, that alternate implementations of the disclosed technology may employ a master computer having single processor unit 111. Further, one or more of the servant computers 117 may have multiple processor units 121 , depending upon their intended use, as previously discussed. Also, while only a single interface device 113 or 123 is illustrated for both the master computer 103 and the servant computers, it should be noted that, with alternate embodiments of the disclosed technology, either the computer 103, one or more of the servant computers 117, or some combination of both may use two or more different interface devices 113 or 123 for communicating over multiple communication interfaces.

[0033] With various examples of the disclosed technology, the master computer 103 may be connected to one or more external data storage devices. These external data storage devices may be implemented using any combination of computer readable media that can be accessed by the master computer 103. The computer readable media may include, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable media may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, punched media, holographic storage devices, or any other medium that can be used to store desired information. According to some implementations of the disclosed technology, one or more of the servant computers 117 may alternately or additionally be connected to one or more external data storage devices. Typically, these external data storage devices will include data storage devices that also are connected to the master computer 103, but they also may be different from any data storage devices accessible by the master computer 103.202408140

[0034] It also should be appreciated that the description of the computer network illustrated in FIG. 1 and FIG. 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments of the disclosed technology.Verification Tools and Methods

[0035] FIG. 3 is a block diagram illustrating a verification tool according to an embodiment of the disclosed technology. In some embodiments, the verification tool may perform a PERC (Physical EDA Rules Checking). Referring to FIG. 3, the verification tool 300 may include a plurality of steps, including steps performed respective by: a layout extraction unit 310 (performing a layout extraction step); a netlist analysis unit 312 (performing a netlist analysis step); a probe generation unit 314 (performing a probe generation step); a layout data selection unit 316 (performing a layout data selection step); a parasitic extraction unit 318 (performing a parasitic extraction step); a control file generation unit 320 (performing a control file generation step); a simulation unit 322 (performing a simulation step); and a change analysis unit 330 (performing a change analysis step). The verification tool 300 may cooperate with (or incorporate) a database 340 and a rule base 342. The verification tool 300 may communicatively connect to the database 340 and the rule base 342. The database 340 may include input data input by a user (e.g., a designer) including IC layouts and / or modifications to the IC layouts and output database including data generated by one or more units 310-330 of the verification tool 300 during the verification iteration (e.g., the plurality of steps performed in verifying a respective IC layout). The rule base 342 may include rules for checking. The rules may include one or more design rules and / or one or more manufacturing rules.

[0036] The layout extraction unit 310 may extract information from an IC layout. The layout extraction unit 310 may convert the user designed layout into a layout dataset from which all circuit elements and the connectivity of all circuit elements can be identified. The layout extraction unit 310 may also convert the user designed layout into a graphical representation. In some embodiments, the layout extraction unit 310 may extract the layout dataset including connectivity, devices, properties, and netlist view (e.g., a netlist representation) along with coordinates, layers, geometry information from an input IC layout in Graphic Data System II (GDSII) or Open Artwork System Interchange Standard (OASIS) format. The netlist view may refer to a representation of a netlist in a hierarchical format.

[0037] The netlist analysis unit 312 may perform a netlist analysis. A netlist may comprise a textual representation of electrical connectivity and devices in the IC layout with their properties. The netlist representation may describe how the electronic components are electrically202408140 connected. Netlist analysis may analyze the netlist representation of the IC layout. In the netlist analysis, the netlist analysis unit 312 may identify nets, devices, and pads of the IC layout. For example, the netlist analysis unit 312 may identify presence and absence of electrostatic discharge (ESD) protection circuits and the protection devices along with their nets, device pins, and pads.

[0038] The probe generation unit 314 may determine the number of probes and select physical location of probes based on the netlist analysis. For example, the probe generation unit 314 may locate the physical location (e.g., x, y coordinates, a layer, a net) of the devices, pins, and pads identified as part of the netlist analysis. Those physical locations may become sources and sinks for performing point to point resistance checks and current density checks.

[0039] The layout data selection unit 316 may determine and select layout data of interest. In particular, the layout data selection unit 316 may select layout geometric elements of the IC layout based on the graphical representation that are of interest. For example, the layout geometric elements of interest may relate to (e.g., be involved in) the measurement of the IC layout for verification. For example, for ESD protection verification, the layout geometric elements of interest may include the layout geometric elements within the cells of interest that include portions of power supply grids on top metal layers. Embodiments of layout data selection are disclosed in US Patent No. 9,785,736 which is incorporated by reference herein in its entirety.

[0040] The parasitic extraction unit 318 may extract, based on the graphical representation of the IC layout, the parasitic elements of the IC layout. The parasitic elements may include, but not be limited to, parasitic resistance, parasitic inductance, parasitic capacitance, and the like.

[0041] The control file generation unit 320 may generate a control file (e.g., run-set file, or setup file) that sets up and provides instructions for execution of a simulation (e.g., execution of rule checks). For example, the control file may specify how the simulation unit 322 should perform rules checks on the IC layout.

[0042] The simulation unit 322 may perform, using the generated control file and data of the IC layout, the specified checks on the design for verification. For example, the simulation unit may measure the point-to-point resistance, a current density, and the like. The simulation unit 322 may further generate, after the simulation, a report describing the results of the simulation.

[0043] As discussed in more detail below, the change analysis unit 330 may analyze the changes between at least two IC layouts and determine whether the data of the previous IC layout may be used in verification of an IC layout which is modified (e.g., updated, or fixed) from the previous design model.202408140

[0044] As previously noted, various embodiments of the disclosed technology may be implemented by a multiprocessor computing system, such as the computing system illustrated in FIGS. 1 and 2. Accordingly, any one, any combination, or all of the circuit elements of the layout extraction unit 310, the netlist analysis unit 312, the probe generation unit 314, the layout data selection unit 316, the parasitic extraction unit 318, the control file generation unit 320, the simulation unit 322, and the change analysis unit 330 may be implemented by executing programming instructions on one or more processors in a computing system such as the computing system illustrated in FIG. 1 and FIG. 2. Correspondingly, some other embodiments of the disclosed technology may be implemented by software instructions, stored on a non-transitory computer-readable medium, for instructing one or more programmable computers / computer systems to perform the functions of any one, any combination, or all of the circuit elements of the layout extraction unit 310, the netlist analysis unit 312, the probe generation unit 314, the layout data selection unit 316, the parasitic extraction unit 318, the control file generation unit 320, the simulation unit 322, and the change analysis unit 330. As used herein, the term “non-transitory computer-readable medium” refers to computer-readable medium that are capable of storing data for future retrieval, and not propagating electro-magnetic waves. The non-transitory computer- readable medium may be, for example, a magnetic storage device, an optical storage device, a “punched” surface type device, or a solid state storage device.

[0045] It also should be appreciated that, while the layout extraction unit 310, the netlist analysis unit 312, the probe generation unit 314, the layout data selection unit 316, the parasitic extraction unit 318, the control file generation unit 320, the simulation unit 322, and the change analysis unit 330 are shown as separate units in FIG. 3, a single servant computer (or a single processor within a master computer) may be used to implement two or more of these units at different times, or components of two or more of these units at different times.

[0046] With various embodiments of the disclosed technology, the database 340 and the rule base 342 may be implemented using any suitable computer readable storage device. In other words, either of the database 340 and the rule base 342 may be implemented using any combination of computer readable storage devices including, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable storage devices may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, punched media, holographic storage devices, or any other non-transitory storage medium that can be used to store desired information. While the database 340 and the rule base202408140342 are shown as separate units in FIG. 3, a single data storage medium may be used to implement some or all of data of the database 340 and the rule base 342.

[0047] FIGS. 4A and 4B are flow charts illustrating an IC layout verification process that may be implemented according to embodiments of the disclosed technology. Methods for verifying the IC layout may be employed according to various embodiments of the disclosed technology and are described with reference to the verification tool 300 illustrated in FIG. 3 and the flow charts 400, 450 in FIGS. 4A and 4B. It should be appreciated, however, that alternate configurations of a verification tool may be used to perform the IC layout verification method in the flow charts 400, 450 according to various embodiments of the disclosed technology. In addition, it should be appreciated that implementations of verification tool 300 may be employed to implement methods for verification according to different embodiments of the disclosed technology other than those illustrated by the flow charts 400, 450 in FIGS. 4A and 4B.

[0048] FIG. 4A illustrates a flow chart 400 of verifying a first IC layout. In this regard, FIG. 4A may illustrate a first verification (e.g., a first verification iteration) or a previous verification (e.g., previous verification iteration) to the verification (e.g., verification iteration) described in FIG. 4B. Throughout the specification, the terms such as “first”, “second” and the like may be used in describing various elements, but the elements should not be limited by the terms. These terms are only for distinguishing the elements from other elements, and the nature or the sequence or order of the elements should not be limited by the terms unless a particular ordering is required by specific language set forth below.

[0049] Referring to FIG. 4A, at 408, the verification tool 300 may receive as input the first IC layout from a user (e.g., a designer), the database 340, and / or another unit or tool (e.g., an IC layout generation tool).

[0050] At 410, the layout extraction unit 310 may perform the layout extraction for the first IC layout. In performing the layout extraction, the layout extraction unit may extract a layout dataset from the first IC layout. In first layout verification (i.e., in verifying a first IC layout according to the flow charts 400), the layout extraction unit 310 may extract all layout geometries in the first IC layout. The layout dataset may include netlist representation and layout data including a graphical representation of the first IC layout. In some embodiments, the layout dataset extracted at 410 may include connectivity, devices, properties, and netlist view (e.g., a netlist representation) along with coordinates, layers, geometry information of the first IC layout. The extracted layout dataset corresponding to the first IC layout may be stored in the database 340.

[0051] At 412, the netlist analysis unit 312 may perform a netlist analysis for the first IC layout based on the netlist representation of the first IC layout. In performing the netlist analysis, the202408140 netlist analysis unit 312 may identify nets, devices, and pads of the IC layout. For example, the netlist analysis unit 312 may identify presence and absence of electrostatic discharge (ESD) protection circuits and the protection devices along with their nets, device pins, and pads. The result of the netlist analysis may be stored in the database 340.

[0052] At 414, the probe generation unit 314 may perform the probe generation for the first IC layout. In performing the probe generation, the probe generation unit 314 may generate, based on the netlist analysis , probes and their location on the first IC layout. Generating probes may include determining the number of probes for measurement and the physical locations of the probes for the first IC layout. For example, the probe generation unit 314 may locate the physical location (e.g., a (x, y) coordination, a layer, a net) of the devices, pins, and pads identified as part of the netlist analysis at 414. Those physical locations may be sources and sinks for performing point to point resistance checks and current density checks. The generated probe data, including the physical locations of the probes on the first IC layout, may be stored in the database 340.

[0053] At 416, the layout data selection unit 316 may perform the layout data selection for the first IC layout. In performing the layout data selection, the layout data selection unit 316 may determine and select layout data of interest from the entire layout data of the first IC layout. In some embodiments, at 416, the layout data selection unit 316 may identify circuit elements of interest in the first IC layout, and then determine nets of interest and cells of interest based at least on the circuit elements of interest, pins for the circuit elements of interest, or both. Then, at 416, the layout data selection unit 316 may select layout geometric elements of interest in the first IC layout based on the nets of interest and the cells of interest. The layout geometric elements of interest may be layout geometric elements that are related to measurement for the verification of the first IC layout. Again, embodiments of selection of layout data of interest are disclosed in US Patent No. 9,785,736 which is incorporated by reference in its entirety.

[0054] At 418, the parasitic extraction unit 318 may perform the parasitic extraction for the first IC layout. In performing the parasitic extraction, the parasitic extraction unit 318 may extract, based on the layout representation of the first IC layout, the parasitic elements in the first IC layout. In some embodiments, the parasitic extraction unit 318 may extract the parasitic elements (e.g., parasitic resistance, parasitic inductance, parasitic capacitance, and the like) based on the selected layout geometric elements. For example, the parasitic extraction unit 318 may extract parasitic resistance within the selected layout geometric elements of the first IC layout. The data of the parasitic elements extracted at 418 (e.g., the parasitic data) may be stored in the database 340.202408140

[0055] At 420, the control file generation unit 320 may perform the control file generation to generate a control file for simulation of the first IC layout. The control file may be generated based at least on the probes for the first IC layout generated in step 414. The data of the control file generated in step 420, i.e. , the control file data, may be stored in the database 340.

[0056] At 422, the simulation unit 322 may perform the simulation for the first IC layout. For example, the simulation unit 322 may run the verification simulation by performing, using the generated control file and the data of the first IC layout (e.g., the parasitic data), measurements on the first IC layout to check predetermined rules. For example, the simulation unit 322 may measure the point-to-point resistance, a current density, and the like on the first IC layout. The result of the verification simulation of the first IC layout may be stored in the database 340.

[0057] At 424, the simulation unit 322 may further generate, after the simulation, a report describing the result of the simulation. The simulation report for the first IC layout may be stored in the database 340.

[0058] When an IC layout for verifying is an initial IC layout (e.g., when there is no previous verification iteration or when data for the previous IC layout) and / or when data of the previous verification with the previous IC layout are not stored in the database 340, verifying the IC layout may be performed according to the flow chart 400.

[0059] When an IC layout is an IC layout modified based on a previous verification (e.g., previous verification iteration) and the previous IC layout data (including the data generated during the previous verification iteration with the previous IC layout) has been stored in the database 340, the verification tool 300 may identify and analyze the modifications, for example, using the change analysis unit 330, and determining, based on the analysis of the modifications, access and reuse of part or all of the previous IC layout data to skip one or more respective steps of the verification iteration or to repeat performing respective step(s) from a previous verification iteration but reducing computation for the respective step(s) of the verification iteration in verifying the modified IC layout (as compared to the computation performed in the previous iteration) by accessing part or all of the previous IC layout data and / or by determining that, due to lack of changes from the previous IC layout, as discussed in further detail below.

[0060] FIG. 4B illustrates a flow chart 450 illustrating verifying a second IC layout (e.g., a modified IC layout based on modifications of the first IC layout) according to an embodiment of the disclosed technology. In some embodiments, the verification iteration with the second IC layout may be after or later in time to the verification iteration with the first IC layout. In some embodiments, if there is no pertinent change between the first and second IC layouts, no verification needs to be performed for the second IC layout.202408140

[0061] Thus, the second IC layout may be an IC layout modified, revised, edited, and / or changed from the first IC layout. After verifying the first IC layout, a designer may design the second IC layout based on the first IC layout. For example, the designer may design the second IC layout by modifying at least portion of the first IC layout in attempt to address issues in the first IC layout (e.g., in an attempt to generate a new IC layout design complying with the rules that fixes the errors identified as part of the first layout verification executed). The second IC layout may include one or more modifications from the first IC layout. The one or more modifications may be any types of modifications that can be made on an IC layout, including, but not limited to, removal or addition of a device, a physical path, a geometric element, a pad, and a change of any aspect of a circuit element such as a shape, property, or location of the circuit element. In one or some embodiments, the IC layout may be iteratively modified for a plurality of iterations, such as until the IC layout is verified for use in manufacturing integrated circuits. After which, the IC layout may be used in order to manufacture integrated circuits.

[0062] In some embodiments, in verifying the second IC layout, the verification tool 300 may use, based on the modifications from the first IC layout and / or the analysis of the modifications from the first IC layout, at least a part of the first IC layout data stored in the database 340, and may skip or perform less computation for one or more steps of the verification iteration in verifying the second IC layout. As such, verification of the second IC layout may be a change-aware verification in that the differences between the first IC layout and second IC layout may impact which specific steps and computations are performed in verification of the second IC layout. For example, in verifying the second IC layout, the verification tool 300 may skip one or more respective step of a plurality of steps of the verification iteration. As described above with the flow chart 400, the plurality of steps for the verification iteration may include receiving an IC layout to run the verification iteration as 408, performing the layout extraction as 410, performing the netlist analysis as 412, performing the probe generation as 414, performing the layout data selection as 416, performing the parasitic extraction as 418, performing the control file generation as 420, performing the simulation as 422, and reporting the simulation result as 424.

[0063] As noted herein, the verification tool 300 may skip or perform less computations for any combination of the steps of a verification iteration for verifying the second IC layout, including as illustrative examples layout extraction and parasitic extraction. In that regard, verification of the second IC layout may be “change-aware” in that changes between the first IC layout and the second IC layout can be accounted for in the verification of the second IC layout. In some embodiments, in verifying the second IC layout, the verification tool 300 may access and use the at least a part of parasitic data of the first IC layout such that the verification tool 300 may perform202408140 less computation in performing the parasitic extraction for the second IC layout than the computations in performing the parasitic extraction for the first IC layout, as discussed in further detail below. In other words, the scope or extent of performing the parasitic extraction for the second IC layout may be narrower than the scope of performing the parasitic extraction for the first IC layout. In this regard, the parasitic extraction step may be re-performed in verifying the second IC layout; however, the respective step is only performed on a portion (or subpart) of the second IC layout (that may have changed) but the parasitic extraction step is not perform on part or all of a remaining portion of the second IC layout, instead using the results in performing the parasitic extraction step in verifying the first IC layout by accessing part or all of the first IC layout data that was generated in performing the parasitic extraction step in verifying the first IC layout.

[0064] The first IC layout data may include, but not be limited to, input data related to the first IC layout and / or the data generated during the verification iteration with the first IC layout. To determine the first IC layout data that may be used in verifying the second IC layout and / or the steps that need not be performed in verifying the second IC layout, the change analysis unit 330 may identify and analyze the modifications / changes from the first IC layout (e.g., the differences between the first IC layout and the second IC layout).

[0065] At 452, the verification tool 300 may receive as input the second IC layout from a user (e.g., a designer), the database 340, and / or another unit or tool (e.g., the IC layout generation tool). The input for the second IC layout may be the entirety of the second IC layout and one or both of the entirety of the first IC layout or only a modification of the first IC layout. At 454, the layout extraction unit 310 may extract a layout dataset from the second IC layout. The layout dataset may include a netlist representation and layout data including a graphical representation of the second IC layout. In some embodiments, the layout dataset extracted at 454 may include connectivity, devices, properties, and netlist view (e.g., a netlist representation) along with coordinates, layers, geometry information of the second IC layout. By performing the layout extraction, the verification tool 300 may draw a full picture of second IC layout. The extracted layout dataset corresponding to the second IC layout may be stored in the database 340.

[0066] At 456, the change analysis unit 330 may identify the one or more modifications on the second IC layout made from the first IC layout. Various ways are contemplated to identify the one or more modifications. As one example, the change analysis unit 330 may identify the one or more modification by comparing the extracted dataset for the first IC layout and the extracted dataset for the second IC layout.

[0067] At 458, the change analysis unit 330 may determine whether the one or more modifications cause a connectivity change between the first IC layout and the second IC layout.202408140To determine the occurrence of the connectivity change, the change analysis unit 330 may compare any one, any combination, or all of a netlist structure, the source / sink / device connections, and properties of interest of the first IC layout and the second IC layout to determine if there are connectivity changes between the two.

[0068] The change analysis unit 330 may determine that the connectivity has been changed from the first IC layout to the second IC layout, for example, when the change analysis unit 330 determines that there exists any one, any combination, or all of the following in the second IC layout compared to the first IC layout: addition of a net in the netlist representation; addition of a pad location in the netlist representation; addition of a device in the netlist representation; removal of a net in the netlist representation; removal of a pad location in the netlist representation; removal of a device in the netlist representation; change in at least one of width, length, or property of a device; and change in a name of a net.

[0069] When the change analysis unit 330 determines that a connectivity change does not occur between the first IC layout and the second IC layout (decision of No at 458), the flow may continue to 460. Otherwise, when the change analysis unit 330 determines that a connectivity change occurs between the first IC layout and the second IC layout (decision of Yes at 458), the flow may continue to 464.

[0070] At 460 (e.g., when the change analysis unit 330 determines that a connectivity change does not occur between the first IC layout and the second IC layout), the verification tool 300 may access the netlist analysis data of the first IC layout stored in the database 340 and use the netlist analysis data of the first IC layout in verifying the second IC layout instead of performing the netlist analysis for the second IC layout (e.g., netlist analysis at 412 need not be re-performed and may be skipped). When the verification tool 300 uses the netlist analysis data of the first IC layout in verifying the second IC layout (e.g., effectively re-using the results of the netlist analysis in the verification of the first IC layout), the verification tool 300 may store the netlist analysis result of the first IC layout as the netlist analysis result of the second IC layout in the database 340 without performing the netlist analysis for the second IC layout.

[0071] At 462, the verification tool 300 may further access the probe data of the first IC layout instead of generating probes for the second IC layout in response to the determination of absence of the connectivity change between the first IC layout and the second IC layout. In other words,202408140 when the verification tool 300 accesses and uses the netlist analysis data of the first IC layout in verifying the second IC layout (e.g., performing the plurality of steps in the verification iteration for the second IC layout) instead of performing the netlist analysis for the second IC layout (i.e., when the verification tool 300 skips the netlist analysis for the second IC layout), the verification tool 300 may access the probe data of the first IC layout and use the locations of one or more probes generated for the first IC layout in verifying the second IC layout. When the verification tool 300 uses the probe data of the first IC layout in verifying the second IC layout, the verification tool 300 may skip the probe generation in verifying the second IC layout and store the one or more probes and the locations of them generated for the first IC layout as the probe(s) and the location of the probe(s) for the second IC layout in the database 340 without re-performing the probe generation for the second IC layout. The probe data may include generated probes and selected location of the probes.

[0072] At 464 (i.e., when the change analysis unit 330 determines that a connectivity change occurs between the first IC layout and the second IC layout), the netlist analysis unit 312 may reperform the netlist analysis for the second IC layout. The netlist analysis for the second IC layout at 464 may be performed in the same way as the netlist analysis for the first IC layout at 412. The result of the netlist analysis for the second IC layout may be stored in the database 340. The flow may continue to 466.

[0073] At 466 (i.e., when the netlist analysis is performed for the second IC layout at 464), the change analysis unit 330 may determine an absence or a presence of a probe-impacting change between the first IC layout and the second IC layout. The absence or the presence of the probeimpacting change may be determined based on the results of the netlist analysis at 464, The probe-impacting change may include, but not be limited to, any one, any combination, or all of an addition of a device, a removal of a device, a relocation of a device, an addition of a pad, a removal of a pad, a relocation of a pad, or a change to design hierarchy due to addition and / or removal of cells and / or properties.

[0074] When the change analysis unit 330 determines that the probe-impacting changes does not exist between the first IC layout and the second IC layout, i.e., the absence of the probeimpacting change (decision of No at 466), the flow may continue to 462. In other words, the verification tool 300 may access the probe data of the first IC layout and use the probe data for the first IC layout in verifying the second IC layout when the verification tool 300 accesses and uses the netlist analysis data of the first IC layout in verifying the second IC layout instead of reperforming the netlist analysis for the second IC layout (i.e., in response to performing 460) or when the change analysis unit 330 determines that the probe-impacting changes does not exist202408140 between the first IC layout and the second IC layout mode (decision of No in 466). Then, the verification tool 300 may skip the probe generation in verifying the second IC layout and store the one or more probes and the locations of them generated for the first IC layout as the probe(s) and the location of the probe(s) for the second IC layout in the database 340 without re-performing the probe generation for the second IC layout.

[0075] Otherwise, when the change analysis unit 330 determines that the probe-impacting change exists between the first IC layout and the second IC layout (decision of Yes in 466), the flow may continue to 468.

[0076] At 468, the probe generation unit 314 may re-perform the probe generation for the second IC layout. The probe generation unit 314 may generate, based at least on the netlist analysis of the second IC layout, probes and their location on the second IC layout. The probe generation for the second IC layout at 468 may be performed in the same way as the probe generation for the first IC layout at 414. The generated probe data for the second IC layout may be stored in the database 340.

[0077] At 470, the layout data selection unit 316 may re-perform the layout data selection for the second IC layout. The layout data selection unit 316 may determine and select layout data of interest from the entire layout data of the second IC layout. In this regard, one of the functions that the layout data selection module may perform is to reduce (or select the geometries) that are necessary / pertinent for the analysis. It is contemplated that, based on change analysis unit 330, not to perform the work of selecting geometries in the second IC layout and instead use the selected geometries from first IC layout. In some embodiments, at 470, the layout data selection unit 316 may identify circuit elements of interest in the second IC layout, and then determine nets of interest and cells of interest based at least on the circuit elements of interest, pins for the circuit elements of interest, or both. Then, at 470, the layout data selection unit 316 may select layout geometric elements of interest in the second IC layout based on the nets of interest and the cells of interest. The layout geometric elements may be layout geometric elements related to measurement for the verification of the second IC layout. The layout data selection for the second IC layout in 470 may be performed in the same way as the layout data selection for the first IC layout in 416. The result of the layout data selection for the second IC layout may be stored in the database 340. In some embodiments, the layout selection step at 470 may be skipped or the computation for the layout selection step may be reduced. For example, based on the analysis done by the change analysis unit 330, the verification tool 300 may use the layout geometric elements of interest selected in verifying the first IC layout (e.g., the layout geometric elements of202408140 the interest selected at 416 of FIG. 4A) and skip the layout selection step in verifying the second IO layout.

[0078] At 472, the change analysis unit 330 may determine whether a measurement-related modification exists among the one or more identified modifications (e.g., may determine an absence or a present of the measurement-related modification among the one or more identified modification). The measurement-related modification may comprise a modification belonging to the one or more layout geometric element of interest in the second IO layout selected in 470. When the change analysis unit 330 determines that the measurement-related modification does not exist in the second IO layout (decision of No in 472), the flow may continue to 474. On the other hand, when the change analysis unit 330 determines that the measurement-related modification exists in the second IC layout (decision of Yes in 472), the flow may continue to 476.

[0079] at 474, the verification tool 300 may access, in response to determining the absence of the measurement-related modification, parasitic extraction data of the first IC layout. The verification tool 300 may, then, skip the parasitic extraction in verifying the second IC layout and store the parasitic elements extracted from the first IC layout in 418 of FIG. 4A as the parasitic elements of the second IC layout and may re-use the parasitic elements extracted from the first IC layout in verifying the second IC layout.

[0080] At 476, the change analysis unit 330 may determine whether the measurement-related modification includes a parasitic related modification. The parasitic related modification may be a modification that may impact the parasitic elements in an IC layout. The parasitic related modification may include, but not be limited to, any one, any combination, or all of a location change of at least one of a pin, a pad, or a probe, a geometry change belonging to a net involved in the measurement, a geometry change impacting a density computation, or a property change.

[0081] When the change analysis unit 330 determines that the measurement-related modification does not include the parasitic related modification (decision of No in 476), the flow may continue to 474. In other words, 474 may be performed in response to determining the absence of the measurement-related modification and / or in response to determining the absence of the parasitic related modification included in the measurement-related modification. On the other hand, when the change analysis unit 330 determines that the measurement-related modification includes a parasitic related modification (decision of Yes in 476), the flow may continue to 478.

[0082] At 478, the layout data selection unit 316 may select one or more cells and one or more layers related to (e.g., impacted by) the parasitic related modification included in the measurement-related modification. Then, at 480, if the one or more cells and the one or more202408140 layers selected in 478 cover all the layout geometric elements selected in 470 (e.g., the entirety of the layout geometric elements selected in 470), the parasitic extraction unit 318 may re-perform the parasitic extraction for the one or more cells and the one or more layers to extract parasitic elements from the one or more cells and the one or more layers related to the parasitic related modification selected in 478. The parasitic elements extracted in 480 may be stored in the database 340. The verification tool 300 may store, in the database 340, the parasitic elements obtained from the one or more cells and the one or more layers where the parasitic extraction is re-performed as the parasitic elements of the second IC layout.

[0083] Further, at 480, if the one or more cells and the one or more layers selected in 478 do not cover all the layout geometric elements selected in 470 (e.g., the entirety of the layout geometric elements selected in 470), the verification tool 300 may access and re-reuse only a part of the parasitic extraction data of the first IC layout corresponding to the remaining portion of the one or more layout geometric elements selected in 470 (e.g., the portion that is not covered by the one or more cells and the one or more layers selected in 478), and the parasitic extraction unit 318 may perform less computation for the parasitic extraction for the second IC layout by reperforming the parasitic extraction only for the layout geometric elements covered by the one or more cells and the one or more layers (e.g., on only a subpart ora portion of the second IC layout) and re-use the part of the parasitic extraction data of the first IC layout for the remaining portion of the one or more layout geometric elements. The verification tool 300 may store, in the database 340, the parasitic elements obtained from the one or more cells and the one or more layers where the parasitic extraction is re-performed and the parasitic elements of the first IC layout data for the remaining portion as the parasitic elements of the second IC layout (e.g., use data from reperforming the parasitic extraction step on the subpart and re-use part of the data from the parasitic extraction step in verifying the first IC layout, effectively mirroring the entire data set had the parasitic extraction step been re-performed for the entirety of the second IC layout) and use this data (e.g., re-performing the parasitic extraction step on the subpart and the re-used part of the data from the parasitic extraction step in verifying the first IC layout) in verifying the second IC layout.

[0084] At 482, the change analysis unit 330 may determine whether there exists a change in the probes between the first IC layout and the second IC layout, i.e., a probe change. The change in the probes may include a change of the number of the probes and / or a change of the probe location. When the verification tool 300 accesses, in response to determining the absence of the probe-impacting change, the probe data of the first IC layout and / or skipping the probe generation for the second IC layout in 462, the change analysis unit 330 may automatically determine that202408140 there is no change in the probes between the first IC layout and the second IC layout. When the probe generation unit 314 re-performs the probe generation for the second IC layout to generate probes for the second IC layout in 468, the change analysis unit 330 may automatically compare the probe data generated from the probe generation for the first IC layout and the probe data generated from the probe generation for the second IC layout, and then automatically determine whether there are one or more changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for second IC layout in 482. When the change analysis unit 330 automatically determines that there are no changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for second IC layout (e.g., probes have not been changed between the first IC layout and the second IC layout) (decision of No in 482), the flow may continue to 484. On the other hand, when the change analysis unit 330 automatically determines that there are the one or more changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for second IC layout (e.g., the change in the probes exist between the first IC layout and the second IC layout) (decision of Yes in 482), the flow may continue to step 486.

[0085] At 484, the verification tool 300 may access, in response to determining there are no changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for second IC layout (e.g., determining the absence of the probe change) and / or in response to accessing and re-using the probe data of the first IC layout and / or skipping the probe generation for the second IC layout), the control file data of the first IC layout to skip the control file generation for the second IC layout. The verification tool 300 may skip the control file generation for the second IC layout and store the control file of the first IC layout data as the control file of the second IC layout and may use the control file of the first IC layout in verifying the second IC layout.

[0086] At 486, responsive to determining there are the one or more changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for second IC layout, the control file generation unit 320 may re-perform the control file generation for the second IC layout to generate a control file for the simulation of the second IC layout. The control file may be generated based at least on the probes for the second IC layout. The control file for the second IC layout may be generated in the same way as the control file generation for the first IC layout in step 420 of FIG. 4A. The control file for the second IC layout may be stored in the database 340.202408140

[0087] At 488, the change analysis unit 330 may determine whether the simulation needs to be performed for the second IC layout. Responsive to the change analysis unit 330 identifying any changes that may cause different simulation results, the change analysis unit 330 may automatically determine that the simulation for the second IC layout is to be performed. For example, the change analysis unit 330 may automatically determine the necessity of the simulation for the second IC layout based at least on any one, any combination, or all of a change in the probes, the control files and / or the parasitic elements between the first IC layout and the second IC layout. When the change analysis unit 330 automatically determines that the simulation for the second IC layout is necessary (decision of Yes in 488), the flow may continue to 490. When the change analysis unit automatically determines that the simulation for the second IC layout is not necessary (decision of No in 488), the flow may continue to step 492.

[0088] At 490, the simulation unit 322 may run a verification simulation for the second IC layout. For example, the simulation unit 322 may run the verification simulation by performing, using the data of the second IC layout, the measurements on the second IC layout to check predetermined rules. For example, the simulation unit may measure the point-to-point resistance, a current density, and the like on the second IC layout. The scope of the simulation may be determined based on the one or more identified modifications and the impacts of the one or more identified modifications such as parasitic element changes according to the one or more identified modifications. In some embodiments, the simulation may be performed on the second IC layout on all nets or subset of nets based on control file and parasitic changes. In some embodiments, the simulation may be run on the second IC layout based on the one or more cells and the one or more layers of interest selected in step 478. The result of the verification simulation of the second IC layout may be stored in the database 340.

[0089] At 492, the simulation unit 322 may further generate, when the simulation is performed in 490, a report describing the results of the simulation. The simulation report for the second IC layout may be stored in the database 340. When the simulation is not performed based on the determination in 488, the simulation unit 322 may indicate, at 492, no change in the simulation result in various manners. For example, the simulation unit 322 may report the simulation result for the second IC layout is the same as the simulation report for the first IC layout or report that the simulation for the second IC layout has not been conducted.

[0090] The steps conducted by the change analysis unit 330, for example, 456, 458, 466, 472, 476, 482, and 488 may be collectively referred to as a step of analyzing the one or more modifications between the two IC layouts (e.g., the first IC layout and the second IC layout).202408140

[0091] In some embodiments, verifying (e.g., performing the plurality of steps for the verification iteration) may be repeated as many times as needed. After verifying the second IC layout, a designer may design the third IC layout by modifying the second IC layout based on the verification iteration result with the second IC layout. Then, the verification tool 300 may reperform the verification iteration with the third IC layout in which the change analysis unit 330 may analyze the modifications (e.g., changes) between the second IC layout and the third IC layout, and the verification tool 300 may access and use the data of the second IC layout based on the result of the change analysis. Change-aware verifications according to the present disclosure may thus be performed or supported across any number of design versions of an IC layout. In some embodiments, when the third IC layout is designed by modifying the first IC layout design instead of modifying the second IC layout design, the data of the first IC layout may be used in verification of the third IC layout. For example, rather than a single sequence of incremental refinements of an IC layout design, there may be exploratory refinements on the part of the user. For example, when there are two different ways of resolving an issue and the user wants to explore both ways before deciding on the IC layout design. In this example, both the second IC layout and the third layout may be directly derived from the first IC layout that is completely analyzed. Both the second and third IC layouts may be directly derived from the first IC layout, but distinct from each other. In this example, the analyses of both the second IC layout and the third IC layout may benefit from the re-use of data of the first IC layout, but exactly which data is re-used may differ between the second IC layout and the third IC layout. If a fourth IC layout is generated by modifying the second IC layout, then the verification tool 300 may re-use the data of the second IC layout based on the change between the second IC layout and the fourth IC layout.

[0092] Systems and methods according to some embodiments of the disclosed technology, may improve the function of the verification tool 300 and the technology of the circuit designing (e.g., IC layout designing). For example, the verification tool 300 may reuse the data of the previous IC layout, and thus, the verification tool may reduce the runtime for each of the subsequent verification (e.g., a subsequent verification iteration that performs the plurality of steps). Therefore, the systems and methods according to some embodiments of the disclosed technology may reduce the total time to determine the final IC layout according to the reduced runtime of verification iterations for each of the revised designs.

[0093] In some embodiments, the system for circuit design verification (e.g., IC layout verification) may delete the data of the previous IC layout (including the data generated during the verification iteration with the previous IC layout) after completing the verification iteration with the IC layout modified from the previous IC layout. This may reduce or prevent a potential data202408140 storage issue. In some embodiments, at least part of the data of the previous IC layout may be deleted even before completing the respective verification iteration with the modified IC layout. As discussed above, each verification iteration may include multiple internal analysis steps. When one of those analysis steps reads its input and generates its output, the output may be generated when the input is read. If that analysis step is the last one within the current verification iteration that reads (e.g., consumes) its input data, then, as the data is read, the algorithm may “move” the memory that held part of the input data (effectively deleting the input data), and instead hold part of the output data, thereby saving significant amounts of memory (e.g., disk space).

[0094] FIG. 5 illustrates application of the circuit design (e.g., IC layout) verification method to circuitry 500.

[0095] The circuitry 500 may represent an IC layout modified based on a previous IC layout with which the previous verification iteration has been performed. Referring to FIG. 5, wires 502, 504, 506, 508, 510 connected to power pads 542, 544 represent a power net. Wires 512, 514, 516, 518, respectively connected to I / O pads 534, 536, 538, 540, represent an I / O net. Wires 520, 522, 524, 528 connected to ground pads 546, 548 represent a ground net. The circuit elements 550, 552, 554 represent Metal-Oxide-Semiconductor (MOS) devices. In FIG. 5, pins for the circuit elements related to the measurement are represented by small solid squares. In FIG. 5, each of square boundaries with dotted lines represent a cell in a hierarchy of structures.

[0096] Example 1

[0097] The verification tool 300 receives input for modifications that edit polygons in areas 570, 572, 574;. The layout extraction unit 310 extracts a dataset from the modified IC layout necessary to run verification iteration with the modified IC layout (e.g., netlist representation and layout data including a graphical representation of the modified IC layout). The change analysis unit 330 identifies that the modifications are changes of polygons in the areas 570, 572, 574, and determines that the modifications do not cause a change in the nets, devices, and pads. The change analysis unit 330 also determines that the polygon change in area 570 is in the power net, the polygon change in area 572 in the I / O net, the change in area 574 is in the ground net.

[0098] Because the change analysis unit 330 determines that the modifications do not cause a change in the nets, devices, and pads, the change analysis unit 330 determines that there is no change in the connectivity. Based on the change analysis’s determination of absence of the connectivity change, the verification tool 300 skips the netlist analysis for the modified IC layout and accesses the netlist analysis data of the previous iteration to use it as the netlist analysis data of the modified IC layout. Further, when the netlist analysis is skipped for the modified IC layout, verification tool 300 may access the probe data of the previous iteration and use it as the probe202408140 data for the modified IC layout because the netlist analysis need not read the modified IC layout since there is no probe-impacting change (e.g., the power pads have not changed, the ground pads have not changed, and the device connection has not changed).

[0099] The layout data selection unit 316 selects layout geometric elements 502-510, 520-528, 542-548, and 550-554, which are related to the measurement. Then layout data selection unit 316 determines that the polygon change in areas 570, 574 are in the selected layout geometric element, but the polygon change in area 572 is not in the selected layout geometric elements. The change analysis unit 330 further determines that the polygon changes in the selected layout geometric elements (e.g., the polygon changes in areas 570, 574) are parasitic related modification related to the parasitic elements, and selects cells 582, 584 and layers (e.g., M3, M4) related to (e.g., including or impacted by) the polygon changes in the areas 570, 574.

[0100] Then, the parasitic extraction unit 318 extracts the parasitic elements of the selected cells 582, 584 and layers (e.g., M3, M4) and accesses the parasitic extraction data of the previous iteration for the remaining portion of selected layout geometric elements.

[0101] The change analysis unit 330 determines that a probe change does not exist because the verification tool 300 accesses and uses the probe data of the previous iteration instead of regenerating probes for the modified IC layout, and thus, the verification tool 300 accesses the control file of the previous IC layout instead of generating the control file for the modified IC layout.

[0102] The change analysis unit 330 further determines that the simulation is to be performed forthe modified IC layout in response to the determination that power parasitic has been changed. Therefore, the simulation unit 322 simulates the power change and generates a report for the new result of the simulation.

[0103] Example 2

[0104] The verification tool 300 receives input for modifications that add polygons 530 and I / O pad 532 which did not exist in the previous IC layout and assigns a property for the addition as a signal net 2. The layout extraction unit 310 extracts a dataset from the modified IC layout necessary to run verification iteration with the modified IC layout (e.g., netlist representation and layout data including a graphical representation of the modified IC layout). The change analysis unit 330 identifies that the modifications are the addition of polygons that add an I / O net 576. Because a new net 576 has been added, the change analysis unit 330 automatically determines that the modification causes a connectivity change. Based on the determination of presence of the connectivity change, the netlist analysis unit 312 performs the netlist analysis for the modified IC layout. The change analysis unit 330 also determines, based on the netlist representation, that there is a probe-impacting change because of the I / O pad 532 has been newly added. According202408140 to the determination of presence of the probe-impacting change, the probe generation unit 314 generates the probes for the modified IC layout.

[0105] The layout data selection unit 316 selects layout geometric elements of interest 502- 510, 520-528, 542-548, and 550-554, which are related to the measurement. Then layout data selection unit 316 determines that the addition of the I / O net 576 is not in the selected layout geometric elements. In response to the determination that the addition of the I / O net 576 is not in the selected layout geometric elements, the verification tool 300 accesses the parasitic data of the previous iteration to use it in verifying the modified IC layout.

[0106] The change analysis unit 330 also determines that the none of the probes have been changed, and thus, the verification tool 300 accesses and uses the control file of the previous iteration instead of generating the control file for the modified IC layout.

[0107] The change analysis unit 330 further determines that simulation does not need to be redone for the modified IC layout in response to the determination that power parasitic has not been changed and the control file has not been changed. Therefore, the simulation unit 322 reports that there is no change in the simulation result.

[0108] The above disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the description. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

202408140CLAIMS1 . A computer-implemented method comprising: storing first IC layout data generated by performing a plurality of steps to verify a first IC layout; identifying one or more modifications between the first IC layout and a second IC layout; analyzing the one or more modifications; and based on the analysis of the one or more modifications, verifying the second IC layout by performing one or more of: skipping a respective step of the plurality of steps by accessing at least a part of the first IC layout data; performing less computation for the respective step than performed for the respective step in verifying the first IC layout by performing the respective step on only a portion of the second IC layout and accessing the first IC layout data for part or all of a remaining portion of the second IC layout; or re-performing the respective step.

2. The method of claim 1 , wherein the plurality of steps of verifying include: a layout extraction step; a netlist analysis step; a probe generation step; a layout data selection step; a parasitic extraction step; a control file generation step; and a simulation step, wherein one or more of the layout extraction step, the netlist analysis step, the probe generation step, the layout data selection step, the parasitic extraction step, the control file generation step, and the simulation step are skipped or are performed with less computation in verifying the second IC layout than performed in verifying the first IC layout.

3. The method of claim 2, wherein performing less computation for the respective step includes performing less computation, by accessing at least a part of parasitic data of the first IC layout, for the parasitic extraction step in verifying the second IC layout than performed for the parasitic extraction step in verifying the first IC layout.2024081404. The method of claim 1 , wherein analyzing the one or more modifications includes determining whether the one or more modifications cause a connectivity change between the first IC layout and the second IC layout.

5. The method of claim 4 further comprising: accessing, in response to determining an absence of the connectivity change between the first IC layout and the second IC layout, skipping a netlist analysis step and accessing netlist analysis data of the first IC layout in verifying the second IC layout.

6. The method of claim 5 further comprising: accessing, in response to skipping the netlist analysis step in verifying the second IC layout, skipping a probe generation step and accessing probe data of the first IC layout in verifying the second IC layout.

7. The method of claim 4 further comprising: re-performing, in response to determining an occurrence of the connectivity change between the first IC layout and the second IC layout, a netlist analysis step for the second IC layout in verifying the second IC layout.

8. The method of claim 1 further comprising: determining an absence or a presence of a probe-impacting change between the first IC layout and the second IC layout, wherein the probe-impacting change includes an addition of a device, a removal of a device, a relocation of a device, an addition of a pad, a removal of a pad, a relocation of a pad, a change to design hierarchy due to addition and / or removal of cells and / or properties, or a combination thereof; responsive to determining that there is the presence of the probe-impacting change between the first IC layout and the second IC layout, re-performing a probe generation step for the second IC layout in verifying the second IC layout; and responsive to determining that there is the absence of the probe-impacting change between the first IC layout and the second IC layout, skipping the probe generation step and accessing probe data of the first IC layout in verifying the second IC layout.

9. The method of claim 8 further comprising:202408140 in response to skipping the probe generation in verifying the second IC layout, accessing control file data of the first IC layout to skip a control file generation step in verifying the second IC layout.

10. The method of claim 8 further comprising: in response to re-performing the probe generation step for the second IC layout in verifying the second IC layout, comparing data generated from the probe generation step for the first IC layout with data generated from the probe generation step for the second IC layout; determining whether there are one or more changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for the second IC layout; responsive to determining there are the one or more changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for the second IC layout, re-performing a control file generation step in verifying the second IC layout; and responsive to determining there are no changes between the data generated from the probe generation step for the first IC layout and the data generated from the probe generation step for the second IC layout, skipping the control file generation step in verifying the second IC layout.11 . The method of claim 1 further comprising: re-performing a layout data selection step in verifying the second IC layout to select one or more layout geometric elements of the second IC layout, wherein the one or more layout geometric elements are related to measurement of the second IC layout.

12. The method of claim 11 further comprising: determining an absence or a presence of a measurement-related modification among the one or more modifications, wherein the measurement-related modification belong to the one or more layout geometric elements related to measurement of the second IC layout.

13. The method of claim 12 further comprising: in response to determining the absence of the measurement-related modification, skipping a parasitic extraction step and accessing parasitic extraction data of the first IC layout to in verifying the second IC layout.20240814014. The method of claim 12 further comprising: in response to determining the presence of the measurement-related modification, determining whether the measurement-related modification includes a parasitic related modification, wherein the parasitic related modification includes at least one of: a location change of at least one of a pin, a pad, or a probe; a geometry change belonging to a net involved in measurement; a geometry change impacting a density computation; or a property change; responsive to determining that the measurement-related modification does not include the parasitic related modification, skipping a parasitic extraction step and accessing parasitic extraction data of the first IC layout in verifying the second IC layout; responsive to determining that the measurement-related modification includes the parasitic related modification and one or more cells and one or more layers related to the parasitic related modification do not cover an entirety of the one or more layout geometric elements, accessing only a part of the parasitic extraction data of the first IC layout to perform less computation for the parasitic extraction step in verifying the second IC layout; and responsive to determining that the measurement-related modification includes the parasitic related modification and the one or more cells and the one or more layers related to the parasitic related modification cover the entirety of the one or more layout geometric elements selected from the second IC layout, re-performing the parasitic extraction step in verifying the second IC layout.

15. The method of claim 14, wherein the part of the parasitic extraction data of the first IC layout corresponds to a portion of the one or more layout geometric elements not covered by the one or more cells and the one or more layers.

16. The method of claim 14 further comprising selecting the one or more cells and one or more layers related to the parasitic related modification.

17. The method of claim 1 further comprising extracting a layout data set of the second IC layout in verifying the second IC layout, and wherein identifying the one or more modifications between the first IC layout and the second IC layout is based on the extracted layout data set.20240814018. A system comprising: at least one processor; and at least one memory storing computer-executable instructions that, when executed by the at least one processor, cause the system to: store first IC layout data generated by performing a plurality of steps to verify a first IC layout; identify one or more modifications between the first IC layout and a second IC layout; analyze the one or more modifications; and based on the analysis of the one or more modifications, verify the second IC layout by performing one or more of: skipping a respective step of the plurality of steps by accessing at least a part of the first IC layout data; performing less computation for the respective step than performed for the respective step in verifying the first IC layout by accessing at least a part of the first IC layout data; or re-performing the respective step.

19. The system of claim 18, wherein the plurality of steps of verifying include: a layout extraction step; a netlist analysis step; a probe generation step; a layout data selection step; a parasitic extraction step; a control file generation step; and a simulation step, wherein the at least one memory storing computer-executable instructions that, when executed by the at least one processor, cause the system to, in verifying the first IC layout: skip or perform with less computation with one or more of the layout extraction step, the netlist analysis step, the probe generation step, the layout data selection step, the parasitic extraction step, the control file generation step, and the simulation step.20240814020. The system of claim 19, wherein the at least one memory storing computer-executable instructions that, when executed by the at least one processor, further cause the system to perform less computation for the parasitic extraction step in verifying the second IC layout than performed for the parasitic extraction step in verifying the first IC layout by accessing at least a part of parasitic data of the first IC layout.

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