Capacitive pressure sensor

Abstract

In one example, a method includes forming a dielectric layer (102) over a semiconductor substrate (101). A first conductive member (1002) is formed over the dielectric layer (102). The first conductive member (1002) includes a first metal layer (104). A second conductive member (1000) is formed over the first conductive member (1002). The second conductive member (1000) includes a second metal layer (110). A plurality of openings (116) extended through the second metal layer (110) are formed. A cavity (118) is formed between the first and second conductive members (1002,1000) through the plurality of openings (116).

Description

CAPACITIVE PRESSURE SENSORBACKGROUND

[0001] A MEMS (Microelectromechanical Systems) pressure sensor is a device that measures pressure and that is fabricated using microfabrication techniques, sometimes measured in microns (pm). Such sensors are composed of tiny mechanical structures, often made of materials like silicon, that can deform or move in response to changes in pressure. When pressure is applied to the sensor, its deformable structure deflects, thereby causing changes in electrical properties. These changes in electrical properties can then be measured and converted into pressure readings. One type of pressure sensor is a piezoresistive pressure sensor, which senses a change in resistance corresponding to deflection of a membrane when it is subjected to a pressure. Another type of pressure sensor is a capacitive pressure sensor, which senses changes in capacitance corresponding to deflection of a membrane when it is subjected to a pressure.SUMMARY

[0002] In one example, a capacitive pressure sensor includes a semiconductor substrate, a first dielectric layer, a first conductive member, and a second conductive member. The first dielectric layer is over the semiconductor substrate. The first conductive member is over the first dielectric layer. The first conductive member includes a first metal layer and is coupled to a first terminal of a capacitor of the capacitive pressure sensor. The second conductive member is over the first conductive member. The second conductive member includes a second metal layer and is coupled to a second terminal of the capacitor. A cavity is between the first and second conductive members.

[0003] In another example, a capacitive pressure sensor includes a semiconductor substrate, a first dielectric layer, a first conductive member, a second conductive member, and a third conductive member. The first dielectric layer is over the semiconductor substrate. The first conductive member is over the first dielectric layer. The first conductive member includes a first metal layer and is coupled to a first terminal of a capacitor of the capacitive pressure sensor. The second conductive member is over the first conductive member. The second conductive member includes a second metal layer and is coupled to a second terminal of the capacitor. A cavity is between thefirst and second conductive members. The third conductive member is located within the cavity. The third conductive member includes a third metal layer and is coupled to the second conductive member by a first conductive via within the cavity.

[0004] In another example, a method includes forming a dielectric layer over a semiconductor substrate. A first conductive member is formed over the dielectric layer. The first conductive member includes a first metal layer. A second conductive member is formed over the first conductive member. The second conductive member includes a second metal layer. A plurality of openings extended through the second metal layer are formed. A cavity is formed between the first and second conductive members through the plurality of openings.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIGS. 1 through 10 are respective cross-sectional views of a portion of a capacitive pressure sensor in intermediate stages of manufacturing according to some examples.

[0006] FIG. 11 illustrates example operation of the capacitive pressure sensor shown in FIGS. 1 through 10.

[0007] FIG. 12 is a top-down view of a portion of the capacitive pressure sensor shown in FIGS.1 through 11.

[0008] FIG. 13 illustrates a capacitive pressure sensor according to an alternative example.

[0009] The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and / or structurally) features. The figures are not necessarily drawn to scale.DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0010] Various features are described hereinafter with reference to the figures. Other examples may include any permutation of including or excluding aspects or features that are described. An illustrated example may not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described. Further, methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders (e.g., including different serial or parallel performance of various operations) with more or fewer operations.

[0011] The present disclosure relates generally, but not exclusively, to MEMS pressure sensors and their fabrication. MEMS pressure sensors use a variety of technologies to sense changes inelectrical properties resulting from deflection of a deformable structure caused by change in external pressure. Although a variety of MEMS pressure sensors exist, aspects of certain examples are described herein by comparing piezoresi stive pressure sensors and capacitive pressure sensors. In general, piezoresi stive pressure sensors measure pressure by changes in electrical resistance due to mechanical deformation of a deformable structure, while capacitive sensors measure pressure by changes in capacitance due to displacement of a deformable structure.

[0012] Piezoresi stive pressure sensors rely on the piezoresistive effect, which is a change in the electrical resistance of a material when it is subjected to mechanical stress. Piezoresistive pressure sensors often use a semiconductor material e.g., silicon) that changes resistance when pressure is applied. They often include a diaphragm made from a material that deforms under pressure. Strain gauges or resistors are attached to the diaphragm. When pressure is applied, the diaphragm deforms, causing a measurable change in resistance. The output is often an electrical resistance change, which is then converted to a voltage signal. The relationship between pressure and resistance change is usually linear over a range of pressures. Certain piezoresistive pressure sensors are known for high accuracy and sensitivity. They can detect very small changes in pressure. Piezoresistive pressure sensors are commonly used in medical devices, automotive systems, and industrial applications where high accuracy and sensitivity are critical.

[0013] Notwithstanding the above general characteristics of piezoresistive pressure sensors, they can have a variety of technical challenges and disadvantages. For example, piezoresistive pressure sensors can be relatively expensive to manufacture. A factor contributing to the manufacturing cost may be the use of a relatively large membrane that is deformable under the pressures of interest. Larger membranes can require a corresponding larger die size, thereby increasing cost and complexity. Some piezoresistive pressure sensors require back-end MEMS micromachining with front-to-backside wafer alignment, which can be difficult and expensive to implement. Certain piezoresistive pressure sensors provide a limited signal-to-noise ratio, which may result from difficulty in achieving sufficiently low doping in the resistor to create enough resistance to measure, while also combating noise from the resistor. Certain piezoresistive pressure sensors also have limited reliability and performance capabilities. For example, the use of certain resistors can have a higher temperature coefficient of resistance, which can result in degraded performance at higher temperatures. Some piezoresistive pressure sensors can have fabrication integration issues. For example, piezoresistive pressure sensors often require a back-side MEMS release,which is not always a viable monolithic solution (e.g., where underlying circuitry would potentially be removed during the back-side MEMS release). In addition, the fabrication of some piezoresistive pressure sensors can require wafer bonding within a vacuum to control the pressure of the cavity, thereby adding cost and complexity.

[0014] Certain capacitive pressure sensors described herein address various technical challenges and disadvantages of certain other types of MEMs pressure sensors, including those described above generally concerning piezoresistive pressure sensors. Capacitive pressure sensors generally operate based on changes in electrical capacitance. They structurally include at least two conductive electrodes separated by one or more dielectric materials. When pressure is applied, at least one of the conductive electrodes moves, altering the distance between the conductive electrodes and thus changing the capacitance. More specifically, a capacitive pressure sensor often includes a deformable structure and a fixed electrode. The deformable structure moves in response to pressure changes, causing variations in the capacitance between the deformable structure and the fixed electrode. The output is a change in capacitance, which can be converted into a voltage or frequency signal. This change in capacitance is related to e.g., proportional to) the applied pressure. Capacitive pressure sensors can achieve high accuracy and can provide very precise pressure sensing measurements. They can be used in applications where high resolution and stability are required. For example, capacitive pressure sensors can be used in automotive, aerospace, consumer electronics, industrial process control, and a variety of other applications. They are particularly useful in applications requiring a high degree of stability and long-term reliability.

[0015] Certain capacitive pressure sensors described herein can have any of a variety of technical benefits and advantages. Some examples facilitate forming a capacitive pressure sensor over a substrate (e.g., silicon) without necessarily requiring any backside etch of that substrate, which can eliminate the need for frontside-to-backside alignment of the substrate. Certain examples facilitate forming a capacitive sensor on the same substrate as analog circuitry coupled to the capacitive sensor, which may reduce manufacturing cost and complexity. Some examples employ a thin film that functions as a deflecting membrane layer, which may be beneficial in reducing the ratio of surface area to deflection distance. The thin film may be configured to achieve the same deflection distance as a silicon membrane of piezoresistive pressure sensor, for example, even though the thin film has a relatively smaller surface area than the silicon membrane of the piezoresistivepressure sensor. Reducing the surface area (e.g, a footprint) of a deflecting membrane layer for a capacitive pressure sensor can result in a reduction in die size, which is desirable for cost savings and manufacturing simplification. Some examples do not require silicon micromachining. In addition, in some examples, all process steps used to form the capacitive pressure sensor can be implemented using the same equipment that is used to create accompanying analog circuitry, which may result in cost savings, and which may eliminate the need for process equipment unique to sensor fabrication. In terms of performance, certain examples achieve low noise while providing a sufficient electrical signal. As a result, the signal-to-noise ratio of the capacitive pressure sensor may be superior, particularly relative to certain pi ezoresi stive approaches. In terms of reliability, certain capacitive pressure sensors can achieve consistent electrical signal output over a relatively large temperature range.

[0016] Various examples are described subsequently. Although the specific examples may illustrate various aspects of the above generally described features, examples may incorporate any combination of the above generally described features (which are described in more detail in examples below).

[0017] FIGS. 1 through 10 are respective cross-sectional views of a portion of a capacitive pressure sensor 100 in intermediate stages of manufacturing according to some examples. Referring to FIG. 1, a semiconductor substrate 101 is received in a processing chamber. Semiconductor substrate 101 may be or include a bulk semiconductor substrate, a semiconductor- on-insulator (SOI) substrate, or any other appropriate substrate. Semiconductor substrate 101 may also include a support (or handle) substrate and an epitaxial layer grown on the support substrate. In some examples, semiconductor substrate 101 is or includes a silicon substrate (which may be singulated from a bulk silicon wafer at the conclusion of semiconductor processing). In further examples, semiconductor substrate 101 includes a silicon substrate with an epitaxial silicon layer grown thereon. Semiconductor substrate 101 is or includes a semiconductor material in and / or on which circuitry (e.g, analog circuitry) can be formed. In some examples, the semiconductor material is or includes silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), the like, or a combination thereof.

[0018] A dielectric layer 102 has been formed over substrate 101 in an earlier process step. Dielectric layer 102 may include, for example, silicon dioxide (SiCh), or other dielectric material. Any suitable formation technique may be used. For example, dielectric layer 102 can be formedby thermal process, Low-Pressure Chemical Vapor Deposition (LPCVD) process, or Plasma- Enhanced Chemical Vapor Deposition (PECVD) process. In some examples, tetraethyl orthosilicate (TEOS) or silane (SiHi) may be used as silicon-based chemical precursors in the chemical vapor deposition processes. Dielectric layer 102 may have any suitable thickness. In some examples, dielectric layer has a thickness within the range of 0.5 to 8 pmor within the range of 1 to 2 pm. A thicker dielectric layer 102 can reduce parasitic capacitance to underlying semiconductor substrate 101, which can help improve signal levels.

[0019] A conductive layer 104 has been formed over dielectric layer 102 in an earlier process step. In addition, conductive layer 104 has been selectively patterned (e.g., etched) in earlier process steps to form opening 105 extending therethrough. Conductive layer 104 may include a stack of multiple conductive layers. For example, conductive layer 104 may include an aluminum (Al) layer between titanium (Ti) or titanium nitride (TiN) layers, optionally with titanium aluminum oxynitride (TiAlON) and Iridium (Ir) layers formed over the outmost Ti or TiN layer (e.g., as shown in FIG. 13). Using a noble metal (e.g., iridium or platinum) as an outermost layer may reduce the formation of oxide thereon and may decrease the possibility of a reaction creating a dielectric at the surface of conductive layer 104. Reducing the likelihood of forming nonconductive material on an outer surface of conductive layer 104 may improve the capacitance signal. In addition, it may improve the repeatability of manufacturing processes used to form capacitive pressure sensor 100 while reducing manufacturing variations. Conductive layer 104 may have a cumulative thickness within the range of 0.5 to 1 pm. For example, conductive layer may include 50 nanometers (nm) of TiN, 30 nm of Ti formed thereon, 500 nm of Al with Cu alloy formed thereon, 30 nm of Ti formed thereon, 50 nm of TiN formed thereon, 50 nm of titanium aluminum nitride (TiAlN) formed thereon, and 50 nm of Ir formed thereon. However, conductive layer 104 may include any suitable conductive material having any suitable respective thickness. Conductive layer 104 may be formed using physical deposition processing (e.g., evaporation or sputter deposition). However, any suitable processing may be used.

[0020] Any suitable processing may be used to form opening 105 extending through conductive layer 104. In one example, conductive layer 104 is patterned to define opening 105 and potentially other features (e.g., with a maximum width within the range of 0.25 to 1 pm). Conductive layer 104 is then etched. The etch may be performed, for example, using reactive ion etching (RIE) that involves one or more reactive gases (e.g., Ch, BCh, Ar, N2, O2, etc.), which may also be referredto as high-density plasma etching process. Ash processing may be used to remove any photoresist or other organic residues that can remain after the etching processing. One or more additional wet clean steps may be used to further clean exposed surfaces and to help remove any remaining residue at the edge of patterned features.

[0021] In another example, a hardmask may be used to form opening 105 extending through conductive layer 104. Use of a hardmask may facilitate etching through portions of conductive layer 104 (e.g., portions including a noble metal, such as iridium or platinum). An example hardmask process flow can include at least the following example process steps. The hardmask is deposited on conductive layer 104. The hardmask may include silicon nitride (SiN) deposited to a thickness within the range of 200 nm to 400 nm, for example. However, the hardmask may include any suitable material deposited to any suitable thickness. The hardmask can be used to pattern conductive layer 104 to define opening 105 and potentially other features. After patterning is complete, the hardmask can be etched with the etch stopping at the outer surface of conductive layer 104. Ash processing may be used to remove any residue that remains after the etching processing. One or more additional wet clean steps may be used to further clean exposed surfaces and to help remove any remaining residue at the edge of patterned features.

[0022] FIG. 2 illustrates a portion of capacitive pressure sensor 100 after the formation of dielectric layer 106 over conductive layer 104 and within opening 105 of conductive layer 104, such that the portion of dielectric layer 106 within opening 105 is in contact with an outer surface of dielectric layer 102. In some examples, only a single deposition of SiN may be used (e. ., using PECVD) to form dielectric layer 106 to the desired thickness (as measured from an outermost surface of conductive layer 104). The single deposition may form dielectric layer 106 with a thickness approximately equivalent to 1.5 times the thickness of conductive layer 104, plus a desired gap width. For example, if the cumulative thickness of conductive layer 104 is 0.75 pm, and the desired gap width is 1 pm, then the SiN thickness (formed using PECVD) may be (1.5 x 0.75 + 1) pm= ~2.1 pm. However, any suitable thickness may be used.

[0023] In some examples, multiple depositions may be used in sequence to form dielectric layer 106 to a desired thickness (as measured from an outermost surface of conductive layer 104). For example, SiN can be deposited to a first thickness using high-density plasma (HDP) deposition process and to a second thickness using PECVD. The first thickness may be substantially equivalent to the cumulative thickness of conductive layer 104, while the second thickness may behalf that amount plus the thickness of a desired gap width. For example, if the cumulative thickness of conductive layer 104 is 0.75 pm, and the desired gap width is 1 pm, then the first SiN thickness (formed using HDP deposition) may be 0.75 pmand the second SiN thickness (formed using PECVD) may be 0.75 / 2 pm+ 1 pm= (0.75 + 0.375 + 1) pm= total thickness of -2.1 pm. Among other advantages, use of multiple depositions to form dielectric layer 106 may facilitate larger feature sizes in certain applications.

[0024] Dielectric layer 106, once fully deposited, may be subjected to chemical mechanical polishing (CMP). The CMP may be used, for example, to planarize or flatten an outer surface of dielectric layer 106, while also fine tuning a desired final thickness. In some examples, a desired final thickness for dielectric layer 106 may be within the range of 0.5 to 2.5 pm (e.g., 1 pm).

[0025] FIG. 3 illustrates a portion of capacitive pressure sensor 100 after the formation of vias 108a-b within dielectric layer 106. Vias 108a and 108b are electrically isolated from one another to avoid shorting the capacitor of capacitive pressure sensor 100. In this example, via 108b is a portion of a contiguous trench forming at least a partial perimeter around a deformable structure 1000 of capacitive pressure sensor 100, as shown more clearly in FIG. 12. The formation of vias 108a-b may include patterning, etching, and cleaning dielectric layer 106 to form trenches (e.g., trenches extending in and out of the page) and then filling those trenches with conductive material (e.g., using a Damascene process). In some examples, the etch processing may involves reactive ion etching with fluorine-based chemistry e.g., CF4, CF3H, C2F6, . .. + N2, Ar, etc.).

[0026] The trenches extending through dielectric layer 106 are filled within one or more layers of conductive material to form vias 108a-b. For example, a first conductive material 107 may be used to line the sidewalls and base of the trenches. The first conductive material may include, for example, a first layer of Ti and a second layer of TiN formed thereon. The Ti layer may be sputtered deposited to a thickness of 30 nm and the TiN layer (formed over the Ti layer) may be deposited to a thickness of 30 nm using CVD. However, any suitable material, respective thickness, and formation techniques may be used. The remainder of the trenches may be filled or “plugged” with a second conductive material 109. For example, tungsten (W) may be deposited over dielectric layer 106 with sufficient thickness to fill the remainder of the trenches.

[0027] After the conductive material is deposited to fill the trenches, the conductive material may be subjected to a CMP. As a result, as shown in FIG. 3, all material used to form vias 108a-b remains only within dielectric layer 106, without any of that material remaining on an outer surfaceof dielectric layer 106. Vias 108a-b may have a minimum width that is approximately 0.2 to 1 times the thickness (e.g., height) of via 108a-b. For example, if vias 108a-b have a thickness of 1 pm, then the minimum width of vias 108a-b may be within the range of 0.2 to 1 pm (e.g., 0.5 pm).

[0028] FIG. 4 illustrates a portion of capacitive pressure sensor 100 after the formation of a conductive layer 110 over dielectric layer 106 and vias 108a-b. In some examples, conductive layer 110 may be substantially similar (if not identical) in its formation and resultant structure to conductive layer 104. In some examples, the conductive layer includes Al, Cu, TiW, W, Ti, TiN, or any other suitable conductive metal(s), including any suitable combination thereof. Some of these example metals have a high melting temperature and hence are more stable thermally, mechanically, or electrically than metals having lower melting temperatures (e.g., Al). After its formation, conductive layer 110 is patterned, etched, and cleaned, as described further with reference to FIG. 5.

[0029] FIG. 5 illustrates a portion of capacitive pressure sensor 100 after the selective patterning, etching, and cleaning of conductive layer 110 to form openings 112a-d. Openings 112a-d can be positioned laterally inward from a perimeter defined by vias 108a-b (e.g., as shown more clearly in FIG. 11). In some examples, openings 112a and 112d facilitate electrically isolating first and second terminals of capacitive pressure sensor, as described further below. As such, openings 112a,d may have dimensions that differ from those of openings 112b-c. For example, a respective minimum width of openings 112a, d may be larger than a respective minimum width of openings 112b-c. Openings 112b-c may each be patterned such that, once etched, each has a minimum width dimension substantially similar to that of vias 108a-b. In some examples, each opening 112b-c is formed using a pattern having minimum width within the range of 0.2 to 1 pm (e.g., 0.5 pm).

[0030] The patterning, etching, and cleaning of conductive layer 110 may be substantially similar to that described with reference to conductive layer 104. In some examples, conductive layer 110 may be etched using an RIE process that involves one or more reactive gases (e.g., Ch, BCI3, Ar, N2, O2, etc.). However, any suitable etching process may be used. The etching of conductive layer 110 may be followed with an ash resist process, and then by a wet clean, as described previously with reference to conductive layer 104. However, any suitable cleaning steps may be used.

[0031] FIG. 6 illustrates a portion of capacitive pressure sensor 100 after the formation of a dielectric layer 114 on conductive layer 110, including within openings 112a-d. In some examples,a single layer of SiCh is deposited to a desired thickness (e.g., using PECVD techniques). In some examples, a first layer of SiCh is deposited (e.g., using a HDP deposition techniques) with a thickness sufficient to fill openings 112a-d and, thereafter, a second layer of SiCh is deposited (e.g. , using PECVD techniques), such that a desired cumulative thickness of both the first and second SiChlayers is achieved. Once formed, the dielectric layer 114 can be subjected to CMP. The CMP may be used, for example, to planarize an outer surface of dielectric layer 114 and to fine-tune a desired thickness (e.g., 1 pm) of dielectric layer 114 over conductive layer 110.

[0032] FIG. 7 illustrates a portion of capacitive pressure sensor 100 after the selective pattern and etch of dielectric layer 114 to form openings 116a-d extending through respective portions of dielectric layer 114 and conductive layer 110. The openings 116a-d may each be patterned with width dimensions that are at least as wide as (filled) openings 112b-c, which were formed previously in conductive layer 110 and subsequently filled by dielectric layer 114. In some examples, openings 116a-d are patterned to have a minimum width that is approximately 20-50% of the maximum thickness of dielectric layer 114 (i.e., as measured where dielectric layer 114 contacts dielectric layer 106. After patterning of dielectric layer 114 is complete, the etching of dielectric layer 114 may involve an RIE process with fluorine-based chemistry (e.g., CF4, CF3H, C2F6, . .. + N2, Ar, etc.). In some examples, the etch processing may be followed by an ash resist process and wet clean process, using processing similar to that described above.

[0033] FIG. 8 illustrates a portion of capacitive pressure sensor 100 after the undercutting of dielectric layer 106 between vias 108a-b. In some examples, the undercutting involves a process (e.g., an ash process) that uses any fluorine plus oxygen gas mixture (e.g., CF4 + O2, SFe + O2, NF3 + O2, C2F6 + O2, etc.). Some examples may additionally, or alternatively, include N2, Ar, or other gas(es) that may be used in etching dielectric layer 106 (e.g., in conjunction with the gas mixture including fluorine and oxygen). The undercutting is performed in a manner that removes the portion of dielectric layer 106 exposed by openings 116a-d, which includes the volume at least partially defined by a perimeter including vias 108a-b. Vias 108a-b may operate to block further progression of the undercut of dielectrically layer 106. The undercut processing may be performed at a controlled temperature, such as ~40°C, for example. However, any suitable temperature may be used. The undercut processing may be followed by processing configured to condition the exposed surfaces shown. For example, an O2 ash or an anneal using vacuum or inert gas may be performed.

[0034] FIG. 9 illustrates a portion of capacitive pressure sensor 100 after the formation of a dielectric layer 120 on dielectric layer 114. In some examples, dielectric layer 120 includes hermetically-sealing material that provides a protective overcoat on the outermost surface. In some examples, dielectric layer 120 may include material configured to prevent the intrusion of certain gases, such as hydrogen and helium. In some examples, dielectric layer 120 is formed by depositing SiON (e.g., using CVD techniques, such as PECVD). In some examples, dielectric layer 120 is formed by depositing A1O, AIN, or other metallic compounds that have high stability and a relatively high melting temperature. However, any suitable material may be deposited using any suitable deposition techniques.

[0035] As shown in FIG. 9, the formation of dielectric layer 120 results in the creation of a sealed cavity 118. In addition, the formation of dielectric layer 120 over openings 116a-d may result in coating a portion of respective underlying surfaces of conductive layer 104 and dielectric layer 102. The coated portions are shown in FIG. 9 as mounds 117a-d, with each mound 117a-d corresponding to respective one of the openings 116a-d.

[0036] FIG. 10 illustrates a portion of capacitive pressure sensor 100 after the selective patterning and etching of dielectric layer 120 and dielectric layer 114 to form openings 122a-b. In some examples, the etching of dielectric layers 114 and 120 may involve an RIE process with fluorinebased chemistry (e.g., CF4, CF3H, C2F6, . . . + N2, Ar, etc.). In some examples, the etch processing may be followed by an ash resist process and a wet clean process, using processing similar to that described above. Openings 112a-b expose respective outer surface of conductive layer 110. Openings 112a-b may each be sufficiently wide to facilitate forming an electrical connection (e.g., using wire-bonding) to the exposed surfaces of conductive layer 110.

[0037] As shown in FIG. 10, the processing described with reference to FIGS. 1-10 may result in the formation of a thin-film deformable structure 1000 over cavity 118. Cavity 118 is located between, and electrically isolates, respective opposing portions of conductive layers 104 and 110. Vias 108a-b each has at least one respective sidewall defining at least part of a boundary or perimeter of cavity 118, where dimension 1060 represents the distance between those sidewalls along a line orthogonal to each via. In some examples, dimension 1060 may be 70 pm. However, dimension 1060 may have any suitable length. Cavity 118 may be sealed and filled with a gas (e.g., as a result of the example processing described with reference to FIG. 9). As noted above, conductive layer 104 may include a noble metal (e.g., iridium or platinum) as an outermost layerfacing cavity 118. Similarly, conductive layer 110 may include a noble metal (e.g, iridium or platinum) as an innermost layer facing cavity 118. Openings 116a-d are each in fluid communication with cavity 118.

[0038] FIG. 11 illustrates example operation of capacitive pressure sensor 100, in which an applied external pressure 1100 causes deformable structure 1000 to displace inwardly. The pressure- induced displacement decreases a minimum distance between deformable structure 1000 and an opposing face of conductive layer 104, thereby causing a change in capacitance. As shown in FIG. 11, the change in capacitance resulting from the illustrated deformation of deformable structure 1000 may be represented as AC = Co— C1;where Corepresents the capacitance in the absence of deformation and where Ci represents the capacitance where an inward surface of deformable structure 1000 is displaced along the dotted concave curve 1110.

[0039] In some examples, the change in capacitance (AC) is measured using a first terminal 1120 and a second terminal 1130. The first terminal 1120 is electrically coupled to conductive layer 110 at opening 122a. The second terminal 1130 is electrically coupled to conductive layer 110 at opening 122b. Via 108a electrically couples the first terminal 1120 to a first portion 1002 of conductive layer 104. The first portion 1002 of conductive layer 104 is referred to herein as a first conductive member (e.g., a conductive plate) of the capacitive pressure sensor 100. The first conductive member 1002 remains fixed in place during operation and extends along the majority of cavity 118. Via 108b electrically couples the second terminal 1130 to a second portion 1003 of conductive layer 104. The second portion 1003 is located at an end of cavity 118 and is electrically isolated from the first conductive member 1002 (and hence the first terminal 1120) by the gap created when forming opening 105 (as described above with reference to FIG. 1).

[0040] The portion of conductive layer 110 included within deformable structure 1000 provides a second conductive member (e.g., a conductive plate) for the capacitive pressure sensor 100, where the second conductive member is sufficiently thin to deform with the remainder of the deformable structure 1000. The deformable structure 1000 (including the second conductive member) is over the first conductive member 1002 and cavity 118 is therebetween. As noted above, the first conductive member 1002 is electrically coupled to first terminal 1120, and the second conductive member included within deformable structure 1000 is electrically coupled to second terminal 1130. Capacitive pressure sensor 100 has a capacitance that varies as a function of a distance between the first conductive member 1002 (formed in conductive layer 104) and the second conductivemember (formed in layer 110) of deformable structure 1000. The distance therebetween changes in response to a pressure 1100 external to deformable structure 1000.

[0041] FIG. 12 is a top-down view of a portion of capacitive pressure sensor 100, which can be formed using the example processing described with reference to FIGS. 1 through 10. On the left of FIG. 12 (in conjunction with FIG. 10), opening 122a (extending through dielectric layers 114 and 120) exposes a conductive surface area or “pad” 1210 of an underlying portion of conductive layer 110. On the right of FIG. 12 (in conjunction with FIG. 10), opening 122b (extending through dielectric layers 114 and 120) exposes a pad 1220 of an underling portion of conductive layer 110. Pads 1210 and 1220 each provide a respective conductive surface to which electrical connections can be made (e.g., through wire bonding). Pads 1210 and 1220 are not electrically interconnected to one another, thereby enabling the creation of an electric field between opposing conductive members of the capacitive pressure sensor 100.

[0042] Pad 1210 may be electrically configured as, or may be electrically coupled to, a first terminal 1120 of the capacitive pressure sensor 100. As shown in FIG. 12 (in conjunction with FIG. 10), for example, conductive routing within conductive layer 104 electrically interconnects pad 1210 (e.g., through via 108a) with a centralized portion of capacitive pressure sensor 100, including the first conductive member 1002 fixed in place.

[0043] Pad 1220 may be electrically configured as, or may be electrically coupled to, a second terminal 1130 of the capacitive pressure sensor 100. As shown in FIG. 12 (in conjunction with FIG. 10), for example, conductive routing within conductive layer 110 electrically interconnects pad 1220 to deformable structure 1000, which includes a portion of conductive layer 110 patterned to operate as a second conductive member for capacitive sensor 100. The second conductive member is configured to displace with deformable structure 1000 responsive to an external pressure applied thereto.

[0044] As shown in the centralized portion of FIG. 12 (in conjunction with FIG. 10), at least one of the via(s) (e.g., via 108b) forms a nearly complete perimeter around a region corresponding to cavity 118. In other words, via 108b shown in FIGS. 3 through 10 may be a cross section of the same contiguous via (e.g, via 108b) having a nearly closed shape (e.g., enclosing most of a rectangle or square). In this example, a gap in via 108b (shown in FIG. 12 on the left-hand side) avoids electrically shorting via 108b with an underlying conductive line of conductive layer 104. An array of openings (e.g., openings 116a-d) are arranged laterally within the perimeter at leastpartially enclosed by via (e. ., via 108b) and are distributed in amanner that facilitates the undercut processing described above with reference to FIG. 8.

[0045] As shown in FIG. 11, the deformation of deformable structure 1000 may result in a displacement of deformable structure 1000, in which a corresponding outer surface of conductive layer 110 deforms or bends in a manner conforming to the concave curve 1110. The greater the displacement of deformable structure 1000, the less parallel opposing surfaces of conductive layers 104 and 110 may become. As described further below, the example shown in FIG. 13 includes a deformable structure 1390 formed using at least two distinct conductive layers 1350 and 1310. When an external pressure is applied, one of the conductive layers (e.g., conductive layer 1310) is configured to deform or bend (e.g., in a manner similar to the conductive layer 110 of FIG. 11 deforms), while the other conductive layer (e.g, conductive layer 1335) maintains its flat, linear shape. Thus, even at a maximum displacement of deformable structure 1390, the respective opposing surfaces of conductive members 1330 and 1335 remain substantially parallel to one another. This aspect of the design of FIG. 13 may improve the capacitive sensitivity and capacitance dynamic range of capacitive pressure sensor 1300.

[0046] FIG. 13 illustrates a capacitive pressure sensor 1300 according to an alternative example. The capacitive pressure sensor 1300 shown in FIG. 13 includes certain features similar to those of capacitive pressure sensor 100 described with reference to FIGS. 1 through 12. However, the example of FIG. 13 differs at least in that a capacitor component of capacitive pressure sensor 1300 includes at least three conductive members 1330, 1335, and 1340. At least two of the conductive members (e.g., 1330 and 1335) may each include linear lateral surfaces that remain substantially parallel to one another during operation. The first and second conductive members (1330 and 1340, respectively) are on opposite ends (e.g., top and bottom ends) of a cavity 1318. The third conductive member 1335 is located within cavity 1318 between the first and second members 1330,1340. The third conductive member 1335 is electrically and structurally coupled to the second conductive member 1340 by one or more vias 1311 within cavity 1318. The third conductive member 1335 is formed from one or more conductive layers 1350.

[0047] A process flow that can be used to form the illustrated portion of capacitive pressure sensor 1300 may include at least the following process steps. A semiconductor substrate 1301 is received in a processing chamber. The semiconductor substrate 1301 may be substantially similar to semiconductor substrate 101 described above with reference to FIGS. 1 through 11. A dielectriclayer 1302 is formed over semiconductor substate 1301 (e.g., in a manner substantially similar to the formation of dielectric layer 102 described above with reference to FIG. 1). A conductive layer 1304 is formed over dielectric layer 1302 (e.g., in a manner substantially similar to the formation of conductive layer 104 of FIG. 1). The conductive layer 1304 is patterned, etched and cleaned (e.g., in a manner substantially similar to that described above with reference to FIG. 2). A dielectric layer 1306 is formed over conductive layer 1304 (e.g., in a manner substantially similar to that described above with reference to FIG. 2).

[0048] Multiple vias 1308a-c are formed within dielectric layer 1306 (e.g., in a manner substantially similar to that described above with reference to FIG. 3). Each via 1308a-c may include a first conductive layer 1307 lining sidewalls thereof and may be filled with a second conductive layer 1309 (e.g., in a manner substantially similar to that described above with reference to FIG. 3). At least one of the vias 1308c has an elongated filled-trench pattern that forms a nearly complete perimeter around a region that will ultimately correspond to cavity 1318 (which is not yet formed at this stage of the process). In other words, via 1308c shown in FIG. 13 may be a respective cross section of a single, contiguous, elongated via.

[0049] One or more conductive layer(s) 1350 are formed over dielectric layer 1306 and vias 1308. In one example, conductive layer 1350 has multiple layers stacked on one another, such as, for example, a TiAlN layer on another TiAlN layer on an Ir layer. In other examples, one or more of the TiAlN layers can be replaced with TiN, TaN, TiON, TaON, or with any other suitable conductive material. In some examples, the Ir layer can be replaced with other noble metals (e.g., Pt, Rh, Ru, etc.). Some examples may not include a noble metal as a base layer for conductive layer 1350, though use of a noble metal as a base layer for conductive layer 1350 may provide certain performance improvements.

[0050] Conductive layer 1350 is patterned, etched, and cleaned (e.g., in a manner substantially similar to that described above with reference to FIG. 1 or 5). In some examples, conductive layer 1350 may be patterned such that dimension 1360 as a width of 70 pm and dimension 1365 has a width of 40 pm. Dimension 1365 represents a length of the third conductive member 1330 along (or parallel to) a line orthogonal to respective opposing sidewalls of vias 1308b and 1308c.

[0051] A dielectric layer 1355 is formed over conductive layer 1350 (e.g., in a manner substantially similar to that described above with reference to FIG. 2). Multiple vias 131 la-d are formed within dielectric layer 1355 (e.g., in a manner substantially similar to that described abovewith reference to FIG. 3). Via 1311c structurally and electrically couples conductive member 1335 to conductive member 1340. At least one via 1311a may be in direct contact with an underlying via 1308a. In some examples, the direct physical contact between vias 1311a and 1308a may provide enhanced electrical conductivity or a reduced electrical resistance of an electrical path between conductive layers 1310 and 1304 (e.g., as compared to an electrical path between conductive layers 1304 and 1310 in which conductive layer 1350 electrically couples via 131 lb to via 1308b). At least one of the vias (e.g., via 131 Id) has an elongated filled-trench pattern that forms a nearly complete perimeter around a region that will ultimately correspond to cavity 1318 (which is not yet formed at this stage of the process). In other words, via 131 Id shown in FIG. 13 may be a respective cross section of a single, contiguous, elongated via.

[0052] The remaining process steps used to form conductive layer 1310, dielectric layers 1314 and 1320, openings 1322a-b and 1316a-d, deformable structure 1390, and sealed cavity 1318 may be substantially similar to those described above with reference to FIGS. 3 through 11, in describing like features.

[0053] Herein, “or” is inclusive and not exclusive, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, “A or B” means “A, B, or both,” unless expressly indicated otherwise or indicated otherwise by context. Moreover, “and” is both joint and several, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, “A and B” means “A and B, jointly or severally,” unless expressly indicated otherwise or indicated otherwise by context. To aid the Patent Office, and any readers of any patent issued on this application, in interpreting the claims appended hereto, applicant notes that there is no intention that any of the appended claims invoke 35 U.S.C. § 112(f) as it exists on the date of filing hereof unless the words “means for” or “step for” are explicitly used in the claim language.

[0054] In the foregoing descriptions, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of one or more examples. However, this disclosure may be practiced without some or all these specific details, as will be evident to one having ordinary skill in the art. In other instances, well-known process steps or structures have not been described in detail in order not to unnecessarily obscure this disclosure. In addition, the foregoing description is not intended to limit the disclosure to the described examples. To the contrary, the description is intended to cover alterations, modifications, substitutions, and equivalents as may be included without departing from the scope defined by the appended claims.

Claims

CLAIMSWhat is claimed is:

1. A capacitive pressure sensor, comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a first conductive member over the first dielectric layer, the first conductive member including a first metal layer and coupled to a first terminal of a capacitor of the capacitive pressure sensor; and a second conductive member over the first conductive member, the second conductive member including a second metal layer and coupled to a second terminal of the capacitor; and a cavity between the first and second conductive members.

2. The capacitive pressure sensor of claim 1, wherein the cavity is sealed and is filled with a gas.

3. The capacitive pressure sensor of claim 1, wherein the capacitor has a capacitance that varies as a function of a distance between the first and second conductive members, the distance changing in response to a pressure external to the second conductive member.

4. The capacitive pressure sensor of claim 1, wherein the first metal layer includes an aluminum layer.

5. The capacitive pressure sensor of claim 4, wherein the first conductive member includes an iridium layer over the aluminum layer, the iridium layer facing the cavity.

6. The capacitive pressure sensor of claim 1, further comprising: a conductive via connected to the second conductive member and a portion of the first metal layer separate from the first conductive member, the conductive via having a sidewall defining at least a part of a boundary of the cavity.

7. The capacitive pressure sensor of claim 1, further comprising: a plurality of mounds of a dielectric material over a surface of the first conductive member facing the cavity, each mound of the plurality of mounds corresponding to an opening in the second conductive member.

8. The capacitive pressure sensor of claim 1, further comprising: a second dielectric layer over the second metal layer; anda plurality of openings that each extends through the second metal layer and the second dielectric layer, each opening of the plurality of openings being in fluid communication with the cavity.

9. The capacitive pressure sensor of claim 8, further comprising: a third dielectric layer over the second dielectric layer, wherein individual openings of the plurality of openings partially extend into the third dielectric layer.

10. The capacitive pressure sensor of claim 1, further comprising: a third conductive member inside the cavity, the third conductive member including a third metal layer; and a conductive via inside the cavity, the conductive via connected to the second and third metal layers.

11. The capacitive pressure sensor of claim 10, further comprising: an iridium layer over a surface of the third conductive member, the surface facing the first conductive member.

12. A capacitive pressure sensor, comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a first conductive member over the first dielectric layer, the first conductive member including a first metal layer and coupled to a first terminal of a capacitor of the capacitive pressure sensor; a second conductive member over the first conductive member, the second conductive member including a second metal layer and coupled to a second terminal of the capacitor; a cavity between the first and second conductive members; and a third conductive member located within the cavity, the third conductive member including a third metal layer and coupled to the second conductive member by a first conductive via within the cavity.

13. The capacitive pressure sensor of claim 12, wherein the capacitor has a capacitance that varies as a function of a distance between the first and third conductive members, the distance changing in response to a pressure external to the second conductive member.

14. The capacitive pressure sensor of claim 12, wherein: the first conductive member includes a first iridium layer facing the cavity; andthe third conductive member includes a second iridium layer facing the first conductive member.

15. The capacitive pressure sensor of claim 12, further comprising: a second conductive via connected to a first portion of the first metal layer separate from the first conductive member and a second portion of the third metal layer separate from the third conductive member; and a third conductive vias connected to the second portion of the third metal layer and the second conductive member, wherein sidewalls of the second and third conductive vias collectively define at least a part of a boundary of the cavity.

16. The capacitive pressure sensor of claim 12, further comprising: an encapsulation layer over the second conductive member, the encapsulation layer including an encapsulation material; and a plurality of mounds of the encapsulation material over a surface of the first conductive member facing the cavity, each mound of the plurality of mounds corresponding to an opening in the second conductive member.

17. The capacitive pressure sensor of claim 12, further comprising: a second dielectric layer over the second metal layer; and a plurality of openings that each extends through the second metal layer and the second dielectric layer, each opening of the plurality of openings being in fluid communication with the cavity.

18. A method, comprising: forming a dielectric layer over a semiconductor substrate; forming a first conductive member over the dielectric layer, the first conductive member including a first metal layer; forming a second conductive member over the first conductive member, the second conductive member including a second metal layer; forming a plurality of openings extended through the second metal layer; and forming a cavity between the first and second conductive members through the plurality of openings.

19. The method of claim 18, further comprising: forming a third conductive member prior to forming the second conductive member and prior to forming the cavity, wherein the second conductive member is formed over the third conductive member and is coupled to the third conductive member by a conductive via therebetween.

20. The method of claim 19, wherein forming the cavity results in the conductive via suspending the third conductive member over the first conductive member.

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