Lamp panel and display device

Abstract

The present application relates to the technical field of display, and discloses a lamp panel and a display device. The lamp panel comprises a driving substrate, a driving chip, and a light-emitting unit. The arrangement direction of a plurality of driving pins of the driving chip is consistent with the arrangement direction of a plurality of types of signal lines comprised in the driving substrate; thus, the design ensures that the signal lines in the driving substrate and the driving pins of the driving chip that need to be correspondingly connected are relatively close to each other. In the case that the plurality of types of signal lines comprised in the driving substrate are all arranged in a first conductive layer, only a relatively small number of connection signal lines need to be arranged in a second conductive layer. In this way, the number of signal lines, requiring layer transition between the first conductive layer and the second conductive layer to achieve connection, among the plurality of types of signal lines comprised in the driving substrate can be reduced, improving the reliability and dependability of the lamp panel.

Description

Light panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a light panel and a display device. BACKGROUND

[0002] The light-emitting diode (LED) light panel can realize local dimming, thereby greatly improving the display quality of the display device. The light-emitting diode can be a mini LED or a micro LED.

[0003] SUMMARY

[0004] The present application provides a light panel and a display device, and the technical solutions are as follows:

[0005] In one aspect, a light panel is provided, the light panel has a light-emitting area and a peripheral area surrounding the light-emitting area; the light panel comprises:

[0006] a driving substrate, the driving substrate comprises a substrate, a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer which are stacked on one side of the substrate; the first conductive layer comprises a plurality of types of signal lines which are insulated from each other, the plurality of types of signal lines extend along a first direction, and signal lines of different types are arranged at intervals in a second direction, the second direction intersects the first direction; the plurality of types of signal lines comprise light-emitting driving signal lines;

[0007] a driving chip, the driving chip is connected through a via hole in the second insulating layer and a conductive layer in the driving substrate, the driving chip comprises a plurality of driving pins arranged in the first direction and in the second direction, the number of driving pins arranged in the second direction is greater than the number of driving pins arranged in the first direction; the plurality of driving pins comprise light-emitting control pins;

[0008] and a light-emitting unit located in the light-emitting area, the second conductive layer comprises first connection signal lines and second connection signal lines, the first connection signal lines are used to connect the light-emitting unit and the light-emitting driving signal lines, and the second connection signal lines are used to connect the light-emitting unit and the light-emitting control pins.

[0009] Optionally, the plurality of types of signal lines further comprise: ground signal lines, clock signal lines, control signal lines and chip driving signal lines; the clock signal lines comprise clock input signal lines and clock output signal lines, and the control signal lines comprise control input signal lines and control output signal lines.

[0010] The plurality of driving pins further comprise a ground pin, a clock input pin, a clock output pin, a control input pin, a control output pin and a chip control pin;

[0011] The ground pin is connected with the ground signal line, the clock input pin is connected with the clock input signal line, the clock output pin is connected with the clock output signal line, the control input pin is connected with the control input signal line, the control output pin is connected with the control output signal line, and the chip control pin is connected with the chip driving signal line.

[0012] Optionally, the light-emitting region comprises a first column of light-emitting regions extending along the first direction; the first column of light-emitting regions comprises a plurality of first control light-emitting regions arranged along the first direction, each first control light-emitting region comprises a plurality of first sub light-emitting regions, the lamp panel comprises a plurality of light-emitting units located in the plurality of first sub light-emitting regions, the second conductive layer comprises a plurality of first connection signal lines corresponding to the plurality of first sub light-emitting regions and a plurality of second connection signal lines corresponding to the plurality of first sub light-emitting regions; the plurality of light-emitting units of each first sub light-emitting region are connected in series with each other, and a first light-emitting unit in the plurality of light-emitting units connected in series is connected to the light-emitting driving signal line through the corresponding first connection signal line;

[0013] The lamp panel comprises a plurality of driving chips, the plurality of driving chips comprise a plurality of first type driving chips arranged along the first direction, the plurality of first type driving chips are arranged correspondingly to the plurality of first control light-emitting regions, each first type driving chip comprises a plurality of first type light-emitting control pins corresponding to the plurality of first sub light-emitting regions, and each first type light-emitting control pin is connected to a last light-emitting unit in the plurality of light-emitting units connected in series of the corresponding first sub light-emitting region through the corresponding second connection signal line;

[0014] The second conductive layer further comprises a plurality of first type third connection signal line groups corresponding to the plurality of first sub light-emitting regions, and each first type third connection signal line group is used for connecting the plurality of light-emitting units in the corresponding first sub light-emitting region.

[0015] Optionally, in the first column of light-emitting regions, the first conductive layer comprises a first first type light-emitting driving signal line, a first first type ground signal line, a first type clock signal line, a first type control signal line, a first type chip driving signal line, a second first type ground signal line and a second first type light-emitting driving signal line arranged along the second direction;

[0016] The first light emitting unit of at least one of the first sub light emitting areas is connected with the first first-type light emitting driving signal line, and the first light emitting unit of each of the first sub light emitting areas is connected with the second first-type light emitting driving signal line;

[0017] The first first-type ground connection part of the second conductive layer is connected with the first first-type ground signal line through a via hole in the first insulating layer at one end and connected with the second first-type ground signal line through a via hole in the first insulating layer at the other end.

[0018] Optionally, each of the first control light emitting areas comprises at least four first sub light emitting areas; and the first-type driving chip comprises 12 driving pins arranged in two rows in the first direction.

[0019] The first row of driving pins in the 12 driving pins of the first-type driving chip are respectively a first first-type light emitting control pin, a second first-type ground pin, a third first-type light emitting control pin, a third first-type ground pin, a first-type clock input pin, and a first-type control input pin.

[0020] The second row of driving pins in the 12 driving pins of the first-type driving chip are respectively a second first-type light emitting control pin, a first first-type ground pin, a fourth first-type light emitting control pin, a first-type chip control pin, a first-type clock output pin, and a first-type control output pin.

[0021] The first first-type light emitting control pin corresponds to the first first sub light emitting area, the third first-type light emitting control pin corresponds to the third first sub light emitting area, the second first-type light emitting control pin corresponds to the second first sub light emitting area, and the fourth first-type light emitting control pin corresponds to the fourth first sub light emitting area.

[0022] Optionally, the first-type clock signal line comprises a first-type clock input signal line and a first-type clock output signal line which are arranged at intervals along the first direction and both extend along the first direction. One end of the first-type clock input signal line close to the first-type clock output signal line is directly connected with the first-type clock input pin, and one end of the first-type clock output signal line close to the first-type clock input signal line is directly connected with the first-type clock output pin.

[0023] The first type of control signal lines include first type of control input signal lines and first type of control output signal lines which are arranged along the first direction and extend along the first direction, and one end of the first type of control input signal lines is directly connected to the first type of control input pin, and one end of the first type of control output signal lines is directly connected to the first type of control output pin.

[0024] Optionally, the first first type of ground signal line includes a first type of ground main part and a first type of second ground connecting part extending along the first direction, the first type of second ground connecting part is connected to the first type of ground main part at both ends in the first direction, the first type of ground main part and the first type of second ground connecting part form a first closed area, and the distance between the first type of second ground connecting part and the first type of clock signal line in the second direction is greater than the distance between the first type of ground main part and the first type of clock signal line in the second direction.

[0025] Optionally, the orthographic projection of the first first type of ground pin on the substrate substrate and the orthographic projection of the second first type of ground pin on the substrate substrate both overlap with the orthographic projection of the first type of second ground connecting part on the substrate substrate.

[0026] The first first type of ground pin and the second first type of ground pin are directly connected to the first type of second ground connecting part.

[0027] Optionally, the orthographic projection of the last light emitting unit of each of the two first sub light emitting areas in the plurality of first sub light emitting areas and the corresponding two first type of light emitting control pins on the substrate substrate are located in the first closed area.

[0028] The last light emitting unit of each of the two first sub light emitting areas in the plurality of first sub light emitting areas is connected to the corresponding first type of light emitting control pin through the corresponding second connecting signal line.

[0029] Optionally, the first first type of ground signal line further includes a first type of third ground connecting part extending along the first direction, one end of the first type of third ground connecting part is connected to the first type of ground main part.

[0030] The first type of third ground connection part is not overlapped with the first type of chip control pin in the substrate substrate, and the first type of third ground connection part is overlapped with the third first type of ground pin in the substrate substrate, and the other end of the first type of third ground connection part is directly connected with the third first type of ground pin.

[0031] Optionally, the first type of second ground connection part is close to the side of the first type of clock signal line and the first type of ground body part to form a first containing area.

[0032] The last light emitting unit of each first sub-light emitting area in two first sub-light emitting areas in the plurality of first sub-light emitting areas is overlapped with the first type of chip driving signal line and the second type of ground signal line in the substrate substrate.

[0033] The second connection signal line corresponding to one first sub-light emitting area in the plurality of first sub-light emitting areas is overlapped with the first type of chip driving signal line, the first type of control signal line, the first type of clock signal line and the first type of third ground connection part in the substrate substrate.

[0034] The second connection signal line corresponding to one first sub-light emitting area in the plurality of first sub-light emitting areas is overlapped with the first type of chip driving signal line, the first type of control signal line and the first type of clock signal line in the substrate substrate.

[0035] Optionally, the second conductive layer further comprises a first type of fourth connection signal line.

[0036] One end of the first type of fourth connection signal line is connected with the first type of chip driving signal line through the via in the first insulating layer, and the other end of the first type of fourth connection signal line is connected with the first type of chip control pin; wherein the first type of fourth connection signal line is overlapped with the first type of clock signal line and the first type of control signal line in the substrate substrate.

[0037] Optionally, the light-emitting region further comprises a second column of light-emitting regions extending along the first direction, the second column of light-emitting regions and the first column of light-emitting regions are arranged adjacent to each other along the second direction; the second column of light-emitting regions comprises a plurality of second control light-emitting regions arranged along the second direction, each of the second control light-emitting regions comprises a plurality of second sub-light-emitting regions, the light panel comprises a plurality of light-emitting units located in the plurality of second sub-light-emitting regions, the second conductive layer comprises a plurality of first connection signal lines corresponding to the plurality of second sub-light-emitting regions and a plurality of second connection signal lines corresponding to the plurality of second sub-light-emitting regions; the plurality of light-emitting units of each of the second sub-light-emitting regions are connected in series with each other, and a first light-emitting unit in the plurality of light-emitting units connected in series with each other is connected to the light-emitting driving signal line through the corresponding first connection signal line;

[0038] The plurality of driving chips further comprises a plurality of second type driving chips arranged along the first direction, the plurality of second type driving chips are arranged corresponding to the plurality of second control light-emitting regions, each of the second type driving chips comprises a plurality of second type light-emitting control pins corresponding to the plurality of second sub-light-emitting regions, and each of the second type light-emitting control pins is connected to a last light-emitting unit in the plurality of light-emitting units connected in series with each other of the corresponding second sub-light-emitting group through the corresponding second connection signal line;

[0039] The second conductive layer further comprises a plurality of second type third connection signal line groups corresponding to the plurality of second sub-light-emitting regions, each of the second type third connection signal line groups is used for connecting the plurality of light-emitting units in the corresponding second sub-light-emitting region, and the arrangement sequence of the plurality of types of signal lines in the second column of sub-light-emitting regions and the plurality of types of signal lines in the first column of sub-light-emitting regions in the second direction is opposite.

[0040] Optionally, in the second column of light-emitting regions, the first conductive layer comprises a first second type light-emitting driving signal line, a first second type ground signal line, a second type chip driving signal line, a second type control signal line, a second type clock signal line, a second second type ground signal line and a second second type light-emitting driving signal line arranged in sequence along the second direction; the second first type ground signal line and the first second type ground signal line are located between the first first type ground signal line and the second second type ground signal line;

[0041] The first conductive layer further comprises a third type ground signal line extending along the second direction and located at one end of the first first type ground signal line and the second second type ground signal line close to the peripheral region, and the third type ground signal line is directly connected to the first first type ground signal line and the second second type ground signal line.

[0042] Optionally, the third type of ground signal line and the second first type of ground signal line, the second first type of light-emitting driving signal line, the first second type of light-emitting driving signal line, and the first second type of ground signal line have a spacing in the first direction;

[0043] The first type of clock signal line includes a first type of clock output signal line, and the second type of clock signal line includes a second type of clock input signal line, which are connected as an integrated clock signal line, at least part of the integrated clock signal line being located in the spacing;

[0044] The first type of control signal line includes a first type of control output signal line, and the second type of control signal line includes a second type of control input signal line, which are connected as an integrated control signal line, at least part of the integrated control signal line being located in the spacing;

[0045] The part of the integrated control signal line located in the spacing is farther away from the third type of ground signal line than the part of the integrated clock signal line located in the spacing.

[0046] Optionally, the second conductive layer further includes a first type of fourth ground connection part and a second type of fourth ground connection part;

[0047] The orthogonal projection of the first type of fourth ground connection part on the substrate substrate crosses the orthogonal projection of the integrated control signal line and the integrated clock signal line on the substrate substrate, one end of the first type of fourth ground connection part is connected with the second first type of ground signal line, and the other end is connected with the third type of ground signal line.

[0048] The orthogonal projection of the second type of fourth ground connection part on the substrate substrate crosses the orthogonal projection of the integrated control signal line and the integrated clock signal line on the substrate substrate, one end of the first type of fourth ground connection part is connected with the first second type of ground signal line, and the other end is connected with the third type of ground signal line.

[0049] Optionally, the first light-emitting unit of at least one second sub-light-emitting area in the plurality of second sub-light-emitting areas is connected with the first second type of light-emitting driving signal line, and the first light-emitting unit of at least one second sub-light-emitting area in the plurality of second sub-light-emitting areas is connected with the second second type of light-emitting driving signal line;

[0050] The second type of ground signal line and the second type of ground pin of the second type of driving chip are directly connected, the second conductive layer further comprises a second type of first ground connecting part, a normal projection of the second type of first ground connecting part on the substrate substrate crosses a normal projection of the second type of clock signal line, the second type of control signal line, and the second type of chip driving signal line on the substrate substrate, one end of the second type of first ground connecting part is connected with the first second type of ground signal line through a via in the first insulating layer, and the other end is connected with the second second type of ground signal line through a via in the first insulating layer.

[0051] Optionally, each of the second control light-emitting areas comprises at least four second sub-light-emitting areas; and the second type of driving chip comprises 12 driving pins, and the 12 driving pins are arranged in two rows in the first direction.

[0052] The first row of driving pins in the 12 driving pins of the second type of driving chip are respectively a second type of control output pin, a second type of clock output pin, a second type of chip control pin, a first second type of light-emitting control pin, a first second type of ground pin, and a third second type of light-emitting control pin.

[0053] The second row of driving pins in the 12 driving pins of the second type of driving chip are respectively a second type of control input pin, a second type of clock input pin, a third second type of ground pin, a second second type of light-emitting control pin, a second second type of ground pin, and a fourth second type of light-emitting control pin.

[0054] The first second type of light-emitting control pin corresponds to the first second sub-light-emitting area, the third second type of light-emitting control pin corresponds to the third second sub-light-emitting area, the second second type of light-emitting control pin corresponds to the second second sub-light-emitting area, and the fourth second type of light-emitting control pin corresponds to the fourth second sub-light-emitting area.

[0055] Optionally, the second type of clock signal line comprises a second type of clock input signal line and a second type of clock output signal line, which are arranged at intervals along the first direction and both extend along the first direction, one end of the second type of clock input signal line close to the second type of clock output signal line is directly connected with the second type of clock input pin, and one end of the second type of clock output signal line close to the second type of clock input signal line is directly connected with the second type of clock output pin.

[0056] The second type of control signal lines include second type of control input signal lines and second type of control output signal lines which are arranged in the first direction and extend in the first direction. The second type of control input signal lines are directly connected to the second type of control input pins at one end close to the second type of control output signal lines. The second type of control output signal lines are directly connected to the second type of control output pins at one end close to the second type of control input signal lines.

[0057] Optionally, the light emitting region includes a plurality of the first column light emitting areas and a plurality of the second column light emitting areas, and the plurality of the first column light emitting areas and the plurality of the second column light emitting areas are staggered in the second direction.

[0058] In another aspect, a display device is provided, which includes a power supply component and a lamp panel as described in the above aspects.

[0059] The power supply component is connected to the lamp panel and is configured to supply power to the lamp panel. BRIEF DESCRIPTION OF DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0061] FIG. 1 is a schematic diagram of the arrangement of driving pins of a driving chip in the related art;

[0062] FIG. 2 is a schematic diagram of the partial structure of a driving substrate, a driving chip and a light emitting unit of a lamp panel in the related art;

[0063] FIG. 3 is an enlarged schematic diagram of area A in FIG. 2;

[0064] FIG. 4 is a schematic diagram of the partial structure of a driving substrate, a driving chip and a light emitting unit of another lamp panel in the related art;

[0065] FIG. 5 is a top view of a lamp panel according to an embodiment of the present application;

[0066] FIG. 6 is a partial top view of a light emitting region of a lamp panel according to an embodiment of the present application;

[0067] FIG. 7 is a partial cross-sectional schematic diagram of a light emitting region of a lamp panel according to an embodiment of the present application;

[0068] FIG. 8 is a schematic diagram of the arrangement of driving pins of a first type of driving chip according to an embodiment of the present application;

[0069] FIG. 9 is a partial top view of a first conductive layer in a first column of light emitting regions according to an embodiment of the present application;

[0070] FIG. 10 is a partial top view of a light emitting region of another light plate according to an embodiment of the present application;

[0071] FIG. 11 is a partial top view of a light emitting region of another light plate according to an embodiment of the present application;

[0072] FIG. 12 is a partial top view of a first conductive layer in a first column of light emitting regions and a second column of light emitting regions according to an embodiment of the present application;

[0073] FIG. 13 is a schematic diagram of an arrangement of drive pins of a second type of drive chip according to an embodiment of the present application;

[0074] FIG. 14 is a partial top view of a first conductive layer in a first column of light emitting regions and a second column of light emitting regions according to an embodiment of the present application;

[0075] FIG. 15 is a partial sectional view of a light emitting region of another light plate according to an embodiment of the present application;

[0076] FIG. 16 is a schematic diagram of a structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0077] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0078] In some embodiments, a light plate includes a drive substrate, a drive chip and a light emitting unit. The drive substrate includes a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer which are stacked in sequence. The first conductive layer and the second conductive layer can include a plurality of types of signal lines. The drive chip and the light emitting unit are connected, so that the drive chip controls the light emitting unit to emit light under the drive of the plurality of types of signal lines.

[0079] However, since a large number of signal lines need to be connected from the first conductive layer to the second conductive layer, the reliability of the light plate is poor.

[0080] FIG. 1 is a schematic diagram of an arrangement of pins of a drive chip in the related art. FIG. 2 is a schematic diagram of a partial structure of a drive substrate, a drive chip (IC) and a light emitting unit of a light plate in the related art. FIG. 3 is an enlarged schematic diagram of region A in FIG. 2. It can also be seen from FIGS. 1 to 3 that each signal line in the drive substrate extends along a first direction (a vertical direction), and the drive chip is also vertically arranged.

[0081] Referring to FIG. 2 and FIG. 3, the signal lines included in the first conductive layer of the driving substrate include light-emitting driving signal lines VLED, ground signal lines GND, chip driving signal lines VDD, clock input signal lines CI, clock output signal lines CO, control input signal lines DI, and control output signal lines DO.

[0082] Also, referring to FIG. 1, the driving chip includes four light-emitting control pins, three ground pins, one chip control pin, one clock input pin, one clock output pin, one control input pin, and one control output pin.

[0083] In combination with FIG. 1 to FIG. 3, the second conductive layer of the driving substrate needs to have multiple connection signal lines. For example, the second conductive layer includes connection signal lines m1 for connecting the light-emitting control pins and the light-emitting units, connection signal lines m2 for connecting the light-emitting units in series, connection signal lines m3 for connecting the light-emitting units and the light-emitting driving signal lines, connection signal lines m4 for connecting the ground pins and the ground signal lines, connection signal lines m5 for connecting the chip control pin and the chip driving signal lines, connection signal lines m6 for connecting the clock input pin and the clock input signal lines, connection signal lines m7 for connecting the clock output pin and the clock output signal lines, connection signal lines m8 for connecting the control input pin and the control input signal lines, and connection signal lines m9 for connecting the control input pin and the control output signal lines.

[0084] Further, referring to FIG. 4, if the clock signal lines of different and adjacent columns of light-emitting areas are connected in series (for example, the clock output signal lines of the first column of light-emitting areas and the clock input signal lines of the second column of light-emitting areas are connected in series), and the control signal lines are connected in series, the second conductive layer further needs to have clock connection signal lines m10 and control connection signal lines m11.

[0085] In the related art, because a large number of signal lines need to be connected by connection signal lines, the number of connection signal lines provided on the second conductive layer of the driving substrate is large. For example, referring to FIG. 3, there are many connection signal lines on the second conductive layer in the vicinity of the driving chip. In this case, if the moisture resistance of the second insulating layer above the second conductive layer is insufficient (the moisture resistance can be insufficient in that the internal water and oxygen content is relatively high), the connection signal lines or the via holes for signal connection on the second conductive layer are prone to be corroded, which can further cause abnormal performance of the lamp panel, and poor reliability and trustworthiness of the lamp panel.

[0086] For example, if the clock signal lines of the different and adjacent light emitting areas are connected in series (such as the clock output signal line of the first column of light emitting areas and the clock input signal line of the second column of light emitting areas are connected in series), the control signal lines are connected in series (such as the control output signal line of the first column of light emitting areas and the control input signal line of the second column of light emitting areas are connected in series), and the via hole at the junction of the clock signal line, the control signal line and the signal line of the first column of light emitting areas is corroded, the second column of light emitting areas cannot normally obtain the clock signal or the control signal, and the second column of light emitting areas cannot normally emit light.

[0087] Alternatively, since the connection signal line m4 for connecting the ground pin and the ground signal line and the connection signal line m1 for connecting the light emitting control pin and the light emitting unit are relatively close, if the two connection signal lines (m1 and m4) are short-circuited due to corrosion, the light emitting unit cannot be controlled to emit light by the driving chip, and the light emitting of the light emitting unit is not controlled.

[0088] Alternatively, if the connection signal line m4 for connecting the ground pin and the ground signal line and the connection signal line m5 for connecting the chip control pin and the chip driving signal line are short-circuited due to corrosion, the driving chip cannot normally work, and the light emitting of the light emitting unit is not controlled.

[0089] FIG. 5 is a top view of a lamp panel according to an embodiment of the present application. Referring to FIG. 5, the lamp panel 100 has a light emitting area 100a and a peripheral area 100b surrounding the light emitting area 100a. FIG. 6 is a partial top view of a light emitting area of a lamp panel according to an embodiment of the present application. FIG. 7 is a partial cross-sectional view of a light emitting area of a lamp panel according to an embodiment of the present application. As can be seen from FIGS. 6 and 7, the lamp panel 100 includes a driving substrate 101, a driving chip 102 and a light emitting unit 103.

[0090] The driving substrate 101 includes a substrate 1011, a first conductive layer 1012, a first insulating layer 1013, a second conductive layer 1014 and a second insulating layer 1015 which are stacked on one side of the substrate 1011. Optionally, the first insulating layer 1013 can have a via hole, and the second conductive layer 1014 can be connected to the first conductive layer 1012 through the via hole in the first insulating layer 1013, for example, FIG. 7 is a cross-sectional view of the driving substrate 101 at the via hole of the first insulating layer 1013.

[0091] Referring to FIG. 5, the first conductive layer 1012 includes a plurality of types of signal lines insulated from each other, the plurality of types of signal lines extending along a first direction X, and different types of signal lines being arranged at intervals in a second direction Y. The second direction Y and the first direction X intersect. For example, the second direction Y and the first direction X are perpendicular. The first direction X is a column direction of the light panel, and the second direction Y is a row direction of the light panel. The plurality of types of signal lines include light-emitting drive signal lines VLED (such as VLED1-1 and VLED1-2 in FIG. 5).

[0092] The driving chip 102 can be connected through a via in the second insulating layer 1015 and the driving substrate 101. The driving chip 102 includes a plurality of driving pins J arranged and disposed in the first direction X and the second direction Y. The number of driving pins J arranged in the second direction Y is greater than the number of driving pins J arranged in the first direction X. The plurality of driving pins J include light-emitting control pins (such as the first type of light-emitting control pin S1 in FIG. 5), such as the light-emitting control pins can be connected through a via in the second insulating layer 1015 and the light-emitting drive signal lines VLED of the driving substrate 101.

[0093] The second conductive layer 1014 includes a first connection signal line L1 and a second connection signal line L2, the first connection signal line L1 and the second connection signal line L2 being insulated from each other. The first connection signal line L1 is used to connect the light-emitting unit 103 and the light-emitting drive signal line VLED, and the first connection signal line L1 is used to transmit the light-emitting drive signal from the light-emitting drive signal line VLED to the light-emitting unit 103. The second connection signal line L2 is used to connect the light-emitting unit 103 and the light-emitting control pin S, and the second connection signal line L2 is used to transmit the light-emitting control signal from the driving chip 102 to the light-emitting unit 103. The light-emitting unit 103 is used to emit light under the control of the light-emitting drive signal and the light-emitting control signal. Moreover, since the first connection signal line L1 and the light-emitting drive signal line VLED are located in different conductive layers of the driving substrate 101, a via can be provided in the first insulating layer 1013 to realize the connection of the two.

[0094] In the embodiment of the present application, since the plurality of types of signal lines included in the driving substrate 101 extend along the first direction X, the number of the driving pins J of the driving chip 102 arranged along the second direction Y is greater than the number of the driving pins J arranged along the first direction X, the arrangement direction of the driving pins J in the driving chip 102 intersects with the extending direction of the plurality of types of signal lines and is consistent with the arrangement direction of the plurality of types of signal lines. For example, the extending direction of the plurality of types of signal lines is referred to as a vertical direction, and the driving pins J of the driving chip 102 can be arranged horizontally relative to the signal lines. In this embodiment, the first direction X can include a positive direction and a negative direction, the positive direction of the first direction X can be an upward direction, and the negative direction of the first direction X can be a downward direction. The second direction Y can include a positive direction and a negative direction, the positive direction of the second direction Y can be a rightward direction, and the negative direction of the second direction Y can be a leftward direction.

[0095] In the case where the driving chip 102 is arranged horizontally, the arrangement direction of the plurality of types of signal lines included in the driving substrate 101 can be consistent with the arrangement direction of the driving pins J in the driving chip 102. In this way, the distances between the signal lines in the driving substrate 101 and the driving pins J in the driving chip 102 that need to be connected can be made short by design, and thus the connection between the signal lines and the driving pins J can be achieved without using too many layer-changing connection lines based on the plurality of types of signal lines arranged in the first conductive layer 1012.

[0096] That is, by making the arrangement direction of the driving pins J of the driving chip 102 consistent with the arrangement direction of the plurality of types of signal lines, the plurality of types of signal lines included in the driving substrate 101 can be arranged in the first conductive layer 1012, and only a small number of layer-changing connection lines (for example, the first connection signal line L1 needs to be connected to the light-emitting driving signal line through a via in the first insulating layer 1013) are needed to achieve signal conduction. In this way, the number of signal lines included in the driving substrate 101 that need to be changed between the first conductive layer 1012 and the second conductive layer 1014 to achieve connection can be reduced, and the reliability and dependability of the lamp panel 100 can be improved.

[0097] In summary, the embodiment of the present application provides a lamp panel, which comprises a driving substrate, a driving chip and a light emitting unit. The arrangement direction of the plurality of driving pins of the driving chip is consistent with the arrangement direction of the plurality of types of signal lines included in the driving substrate, so that the distance between the signal lines in the driving substrate and the driving pins in the driving chip which need to be connected is designed to be close. In the case that the plurality of types of signal lines included in the driving substrate are all arranged in the first conductive layer, only a small number of connection signal lines need to be arranged in the second conductive layer. In this way, the number of signal lines which need to be switched between the first conductive layer and the second conductive layer to realize connection among the plurality of types of signal lines included in the driving substrate can be reduced, and the reliability and dependability of the lamp panel can be improved.

[0098] Optionally, the plurality of types of signal lines further comprise a ground signal line GND, a clock signal line (CI and CO), a control signal line (DI and DO) and a chip driving signal line VDD. The plurality of driving pins J further comprise a ground pin GND-J, a clock input pin CI-J, a clock output pin CO-J, a control input pin DI-J, a control output pin DO-J and a chip control pin VDD-J.

[0099] Correspondingly, the ground pin GND-J is connected with the ground signal line GND, the clock input pin CI-J is connected with the clock input signal line CI, and the clock output pin CO-J is connected with the clock output signal line CO. The control input pin DI-J is connected with the control input signal line DI, the control output pin DO-J is connected with the control output signal line DO, and the chip control pin VDD-J is connected with the chip driving signal line VDD.

[0100] Optionally, the ground signal line GND is configured to transmit a ground signal for the ground pin GND-J, and the driving chip 102 is configured to control the operation of the driving chip 102 or the light emitting unit 103 under the action of the ground signal transmitted by the ground signal line GND. The clock input signal line CI is configured to transmit a clock signal for the clock input pin CI-J, and the clock output pin CO-J is configured to output the clock signal through the clock output signal line CO. The clock input pin CI-J and the clock output pin CO-J of the driving chip 102 can generate accurate timing signals to accurately control various operations of the driving chip 102. The control input signal line DI is configured to transmit a control signal for the control input pin DI-J, and the control output pin DO-J is configured to output the control signal through the control output signal line DO. The control input pin DI-J and the control output pin DO-J of the driving chip 102 can transmit control instructions to the driving chip 102, so that the driving chip 102 adjusts the duty cycle of pulse width modulation (PWM) according to the instructions, and then controls the current size of the light emitting area 100a, thereby adjusting the brightness of the light emitting unit 103 in the series circuit. The chip driving signal line VDD is configured to transmit a chip driving signal for the chip driving pin J, and the driving chip 102 is configured to control the operation of the driving chip 102 under the action of the chip driving signal transmitted by the chip driving signal line VDD.

[0101] As shown in FIGS. 5 and 6, the light emitting area 100a includes a first column of light emitting areas 100a1 extending along the first direction X. The first column of light emitting areas 100a1 includes a plurality of first control light emitting areas 100a11 arranged along the first direction X. Each first control light emitting area 100a11 includes a plurality of first sub light emitting areas F1. The lamp panel 100 includes a plurality of light emitting units 103 located in the plurality of first sub light emitting areas F1. The second conductive layer 1014 includes a plurality of first connection signal lines L1 corresponding to the plurality of first sub light emitting areas F1 and a plurality of second connection signal lines L2 corresponding to the plurality of first sub light emitting areas F1. FIG. 5 schematically shows one first control light emitting area 100a11.

[0102] For example, for each first control light emitting area 100a11, the number of first sub light emitting areas F1 included in the first control light emitting area 100a11 can be equal to the number of first connection signal lines L1 of the second conductive layer 1014 located in the first control light emitting area 100a11, and can be equal to the number of second connection signal lines L2 of the second conductive layer 1014 located in the first control light emitting area 100a11.

[0103] Optionally, the plurality of light emitting units 103 in each first sub light emitting area F1 are connected in series with each other, and a first light emitting unit 103 in the plurality of light emitting units 103 connected in series with each other is connected through the corresponding first connection signal line L1 and the light emitting driving signal line VLED. That is, in the first sub light emitting area F1, the first light emitting unit 103 in the plurality of light emitting units 103 connected in series with each other can directly receive the light emitting driving signal provided by the light emitting driving signal line VLED through the first connection signal line L1.

[0104] The lamp panel 100 can include a plurality of driving chips 102, and the plurality of driving chips 102 can include a plurality of first type driving chips 102a arranged along the first direction X. The plurality of first type driving chips 102a and the plurality of first control light emitting areas 100a11 are correspondingly arranged, and each first type driving chip 102a is used for controlling the light emitting units 103 of the first sub light emitting area F1 in the corresponding first control light emitting area 100a11. Each first type driving chip 102a includes a plurality of first type light emitting control pins S1 corresponding to the plurality of first sub light emitting areas F1, and each first type light emitting control pin S1 is connected to the last light emitting unit 103 in the plurality of light emitting units 103 connected in series with each other in the corresponding first sub light emitting area F1 through the corresponding second connection signal line L2.

[0105] In addition, the second conductive layer 1014 further includes a plurality of third connection signal line groups L3z corresponding to the plurality of first sub light emitting areas F1, and each third connection signal line group L3z is used for connecting the plurality of light emitting units 103 in the corresponding first sub light emitting area F1, so as to realize the plurality of light emitting units 103 in each first sub light emitting area F1 connected in series with each other.

[0106] Optionally, the third connection signal line group L3z can include at least one third connection signal line L3. For example, in the case that the first sub light emitting area F1 is correspondingly arranged with four light emitting units 103, the third connection signal line group L3z can include three third connection signal lines L3. The first third connection signal line L3 can be used for connecting the first light emitting unit 103 and the second light emitting unit 103, the second third connection signal line L3 can be used for connecting the second light emitting unit 103 and the third light emitting unit 103, and the third third connection signal line L3 can be used for connecting the third light emitting unit 103 and the fourth light emitting unit 103.

[0107] In the embodiment of the present application, the light-emitting units 103 included in the lamp panel 100 each include a first light-emitting electrode and a second light-emitting electrode. The first light-emitting electrode can be a P-type electrode, and the second light-emitting electrode can be an N-type electrode. The series connection of the plurality of light-emitting units 103 can mean that the second light-emitting electrode of a previous light-emitting unit 103 is connected to the first light-emitting electrode of a subsequent light-emitting unit 103. For example, in the case where four light-emitting units 103 are provided corresponding to the first sub light-emitting area F1, the second light-emitting electrode of the first light-emitting unit 103 is connected to the first light-emitting electrode of the second light-emitting unit 103 through a third connection signal line L3, the second light-emitting electrode of the second light-emitting unit 103 is connected to the first light-emitting electrode of the third light-emitting unit 103 through a third connection signal line L3, and the second light-emitting electrode of the third light-emitting unit 103 is connected to the first light-emitting electrode of the fourth light-emitting unit 103 through a third connection signal line L3.

[0108] In the embodiment of the present application, since the first control light-emitting area 100a11 includes a plurality of first sub light-emitting areas F1, in order to facilitate the provision of light-emitting driving signals to the first light-emitting units 103 of the first sub light-emitting areas F1 at different positions in the first control light-emitting area 100a11, two light-emitting driving signal lines VLED and two ground signal lines GND can be provided. Referring to FIG. 5, in the first column light-emitting area 100a1, the first conductive layer 1012 includes, in the second direction Y, a first first-type light-emitting driving signal line VLED1-1, a first first-type ground signal line GND1-1, a first-type clock signal line (CI1 and CO1), a first-type control signal line (DI1 and DO1), a first-type chip driving signal line VDD1, a second first-type ground signal line GND1-2, and a second first-type light-emitting driving signal line VLED1-2.

[0109] The first light-emitting units 103 of at least one first sub light-emitting area F1 of the plurality of first sub light-emitting areas F1 are connected to the first first-type light-emitting driving signal line VLED1-1. The first light-emitting units 103 of at least one first sub light-emitting area F1 of the plurality of first sub light-emitting areas F1 are each connected to the second first-type light-emitting driving signal line VLED1-2. Thus, for the first light-emitting units 103 in each first sub light-emitting area F1, one light-emitting driving signal line close to the first sub light-emitting area F1 can be selected for connection, so as to avoid layer switching as much as possible and improve the reliability and dependability of the lamp panel 100.

[0110] As shown in FIG. 5, the first ground signal line GND1-1 is connected to the first ground pin GND-J1 of the first type of driving chip 102a. The second ground signal line GND1-2 is not directly connected to the ground pin GND-J of the first type of driving chip 102a. Thus, the second conductive layer 1014 further includes a first ground connection part GND-L1-1. The orthogonal projection of the first ground connection part GND-L1-1 on the substrate 1011 crosses the orthogonal projections of the first clock signal lines (CI1 and CO1), the first control signal lines (DI1 and DO1), and the first chip driving signal line VDD1 on the substrate 1011. One end of the first ground connection part GND-L1-1 is connected to the first ground signal line GND1-1 through a via in the first insulating layer 1013, and the other end is connected to the second ground signal line GND1-2 through a via in the first insulating layer 1013.

[0111] In the embodiments of the present application, the expression that one signal line crosses another signal line can mean that the one signal line and the other signal line are located in different conductive layers, and the orthogonal projection of the other signal line on the substrate 1011 and the orthogonal projection of the one signal line on the substrate 1011 overlap.

[0112] The first ground connection part GND-L1-1 can be used to connect the first ground signal line GND1-1 and the second ground signal line GND1-2. Since there are many signal lines around the driving chip 102, the orthogonal projection of the first ground connection part GND-L1-1 on the substrate 1011 and the orthogonal projection of the driving chip 102 on the substrate 1011 can be designed to be far apart, so that the first ground connection part GND-L1-1 does not cause the signal lines around the driving chip 102 to change layers, and the different types of signal lines are not short-circuited due to corrosion of the signal lines.

[0113] FIG. 8 is a schematic diagram of the arrangement of the driving pins of a first type of driving chip according to an embodiment of the present application. As shown in FIG. 8, when each first control light emitting region 100a11 includes four first sub-light emitting regions F1, the first type of driving chip 102a includes 12 driving pins. The 12 driving pins are arranged in two rows in the first direction X and six columns in the second direction Y.

[0114] The four first light emitting sub-regions F1 are arranged in two rows in the first direction X and two columns in the second direction Y. In subsequent embodiments, the first light emitting sub-region F1 in the first row and the first column of the four first light emitting sub-regions F1 is referred to as the first first light emitting sub-region F11, the first light emitting sub-region F1 in the second row and the first column of the four first light emitting sub-regions F1 is referred to as the second first light emitting sub-region F12, the first light emitting sub-region F1 in the first row and the second column of the four first light emitting sub-regions F1 is referred to as the third first light emitting sub-region F13, and the first light emitting sub-region F1 in the second row and the second column of the four first light emitting sub-regions F1 is referred to as the fourth first light emitting sub-region F14. The order of the rows is from top to bottom in the drawing, and the order of the columns is from left to right in the drawing.

[0115] The first row of the 12 driving pins in the first type of driving chip 102a is respectively: the first first light emitting control pin S1-1, the second first ground pin GND-J1-2, the third first light emitting control pin S1-3, the third first ground pin GND-J1-3, the first type of clock input pin CI-J1, and the first type of control input pin DI-J1.

[0116] The second row of the 12 driving pins in the first type of driving chip 102a is respectively: the second first light emitting control pin S1-2, the first first ground pin GND-J1-1, the fourth first light emitting control pin S1-4, the first type of chip control pin VDD-J1, the first type of clock output pin CO-J1, and the first type of control output pin DO-J1.

[0117] The first first light emitting control pin S1-1 corresponds to the first first light emitting sub-region F11, the third first light emitting control pin S1-3 corresponds to the third first light emitting sub-region F13, the second first light emitting control pin S1-2 corresponds to the second first light emitting sub-region F12, and the fourth first light emitting control pin S1-4 corresponds to the fourth first light emitting sub-region F14.

[0118] As shown in FIG. 8, the first first-type light-emitting control pin S1-1 and the second first-type light-emitting control pin S1-2 are arranged along the first direction X, and the second first-type ground pin GND-J1-2 and the first first-type ground pin GND-J1-1 are arranged along the first direction X. The third first-type light-emitting control pin S1-3 and the fourth first-type light-emitting control pin S1-4 are arranged along the first direction X. The third first-type ground pin GND-J1-3 and the first-type chip control pin VDD-J1 are arranged along the first direction X. The first-type clock input pin CI-J1 and the first-type clock output pin CO-J1 are arranged along the first direction X. The first-type control input pin DI-J1 and the first-type control output pin DO-J1 are arranged along the first direction X.

[0119] As shown in FIG. 8, the first first-type light-emitting control pin S1-1 and the second first-type light-emitting control pin S1-2 are arranged along the first direction X, and the second first-type ground pin GND-J1-2 and the first first-type ground pin GND-J1-1 are arranged along the first direction X. The third first-type light-emitting control pin S1-3 and the fourth first-type light-emitting control pin S1-4 are arranged along the first direction X. The third first-type ground pin GND-J1-3 and the first-type chip control pin VDD-J1 are arranged along the first direction X. The first-type clock input pin CI-J1 and the first-type clock output pin CO-J1 are arranged along the first direction X. The first-type control input pin DI-J1 and the first-type control output pin DO-J1 are arranged along the first direction X.

[0120] In the embodiment of the present application, referring to FIG. 9, the first-type clock signal lines (CI1 and CO1) include the first-type clock input signal line CI1 and the first-type clock output signal line CO1 which are arranged at intervals along the first direction X and both extend along the first direction X. The first-type clock input signal line CI1 is directly connected to the first-type clock input pin CI-J1 at one end close to the first-type clock output signal line CO1. The first-type clock output signal line CO1 is directly connected to the first-type clock output pin CO-J1 at one end close to the first-type clock input signal line CI1. Directly connected can mean not needing to be connected through layer changing.

[0121] Referring to FIG. 9, the first type of control signal lines (DI1 and DO1) include the first type of control input signal line DI1 and the first type of control output signal line DO1 which are arranged at intervals along the first direction X and both of which extend along the first direction X. The first type of control input signal line DI1 is directly connected to the first type of control input pin DI-J1 at one end thereof which is close to the first type of control output signal line DO1, and the first type of control output signal line DO1 is directly connected to the first type of control output pin DO-J1 at one end thereof which is close to the first type of control input signal line DI1.

[0122] As can be seen from FIG. 5, the first type of clock input signal line CI1 is located at the left of the first type of control input signal line DI1, and therefore the first type of clock input pin CI-J1 in the first type of driving chip 102a is arranged at the left of the first type of control input pin DI-J1 in the first type of driving chip 102a, which can facilitate the first type of clock input signal line CI1 and the first type of clock input pin CI-J1 to be closer to each other and the first type of control input signal line DI1 and the first type of control input pin DI-J1 to be closer to each other. In this way, the first type of clock input pin CI-J1 can be connected through a position which overlaps with the projection of the first type of clock input signal line CI1, and the first type of control input pin DI-J1 can be connected through a position which overlaps with the projection of the first type of control input signal line DI1.

[0123] Similarly, the first type of clock output signal line CO1 is located at the left of the first type of control output signal line DO1, and therefore the first type of clock output pin CO-J1 in the first type of driving chip 102a is arranged at the left of the first type of control output pin DO-J1 in the first type of driving chip 102a, which can facilitate the first type of clock output signal line CO1 and the first type of clock output pin CO-J1 to be closer to each other and the first type of control output signal line DO1 and the first type of control output pin DO-J1 to be closer to each other. In this way, the first type of clock output pin CO-J1 can be connected through a position which overlaps with the projection of the first type of clock output signal line CO1, and the first type of control output pin DO-J1 can be connected through a position which overlaps with the projection of the first type of control output signal line DO1.

[0124] As can be further seen with reference to Fig. 9, the first first-type ground signal line GND1-1 comprises a first-type ground main portion GND-Z1 and a first-type second ground connecting portion GND-L1-2 extending in the first direction X. The first-type second ground connecting portion GND-L1-2 is directly connected to the first-type ground main portion GND-Z1 at both ends thereof in the first direction X. The first-type ground main portion GND-Z1 and the first-type second ground connecting portion GND-L1-2 form a first closed region Q1, and the distance between the first-type second ground connecting portion GND-L1-2 and the first-type clock signal lines (CI1 and CO1) in the second direction Y is greater than the distance between the first-type ground main portion GND-Z1 and the first-type clock signal lines (CI1 and CO1) in the second direction Y.

[0125] The orthogonal projection of the first first-type ground pin GND-J1-1 on the substrate 1011 and the orthogonal projection of the second first-type ground pin GND-J1-2 on the substrate 1011 both overlap the orthogonal projection of the first-type second ground connecting portion GND-L1-2 on the substrate 1011. The first first-type ground pin GND-J1-1 and the second first-type ground pin GND-J1-2 are both directly connected to the first-type second ground connecting portion GND-L1-2. Alternatively, the first first-type ground pin GND-J1-1 and the second first-type ground pin GND-J1-2 can be directly connected through the position where the orthogonal projection of the first-type second ground connecting portion GND-L1-2 overlaps.

[0126] In the embodiments of the present application, the orthogonal projection of the last light emitting unit 103 of the two first sub light emitting regions F1 and the corresponding two first-type light emitting control pins S1 on the substrate 1011 are located within the first closed region Q1. In this way, the distance between the last light emitting unit 103 of the first sub light emitting region F1 and the corresponding first-type light emitting control pin S1 can be made relatively short, thereby facilitating the connection of the last light emitting unit 103 of each of the two first sub light emitting regions F1 to the corresponding one first-type light emitting control pin S1 through the second connecting signal line L2.

[0127] Optionally, referring to FIGS. 6 and 9, the orthographic projection of the last light emitting cell 103 of the first first sub light emitting area F11 and the last light emitting cell 103 of the second first sub light emitting area F12 on the substrate 1011 are both located within the first closed area Q1. The orthographic projection of the first first type light emitting control pin S1-1 corresponding to the first first sub light emitting area F11 and the second first type light emitting control pin S1-2 corresponding to the second first sub light emitting area F12 on the substrate 1011 are located within the first closed area Q1. Thus, the second light emitting electrode of the last light emitting cell 103 of the first first sub light emitting area F11 is connected to the first first type light emitting control pin S1-1 through a corresponding second connection signal line L2, and the second light emitting electrode of the last light emitting cell 103 of the second first sub light emitting area F12 is connected to the second first type light emitting control pin S1-2 through a corresponding second connection signal line L2.

[0128] Referring to FIG. 9, the first first type ground signal line GND1-1 further includes a first type third ground connection portion GND-L1-3 extending along the first direction X. One end of the first type third ground connection portion GND-L1-3 is connected to the first type ground main portion GND-Z1, and the other end has a spacing from the first type ground main portion GND-Z1.

[0129] The orthographic projection of the first type third ground connection portion GND-L1-3 on the substrate 1011 and the orthographic projection of the first type chip control pin VDD-J1 on the substrate 1011 do not overlap. The orthographic projection of the first type third ground connection portion GND-L1-3 on the substrate 1011 and the orthographic projection of the third first type ground pin GND-J1-3 on the substrate 1011 overlap. The other end of the first type third ground connection portion GND-L1-3 is directly connected to the third first type ground pin GND-J1-3. Optionally, the other end of the first type third ground connection portion GND-L1-3 is connected through a position overlapping the projection of the third first type ground pin GND-J1-3.

[0130] Referring to FIG. 9, the first type second ground connection portion GND-L1-2 and the first type ground main portion GND-Z1 constitute a first containing area W1 near one side of the first type clock signal line (CI1 and CO1). The orthographic projection of the last light emitting cell 103 of each of two first sub light emitting areas F1 (such as the third first sub light emitting area F13 and the fourth first sub light emitting area F14) of the plurality of first sub light emitting areas F1 on the substrate 1011 is located between the orthographic projection of the first type chip driving signal line VDD1 on the substrate 1011 and the orthographic projection of the second first type ground signal line GND1-2 on the substrate 1011.

[0131] The normal projection of the second connection signal line L2 corresponding to one of the first sub-light emitting areas F1 on the substrate substrate 1011 crosses the normal projection of the first type chip driving signal line VDD1, the first type control signal line (DI1 and DO1), the first type clock signal line (CI1 and CO1), and the first type third ground connection part GND-L1-3 on the substrate substrate 1011. For example, one end of the second connection signal line L2 corresponding to the third first sub-light emitting area F13 is connected with the second light emitting electrode of the last light emitting unit 103 in the third first sub-light emitting area F13, and the other end crosses the first type chip driving signal line VDD1, the first type control signal line (DI1 and DO1), the first type clock signal line (CI1 and CO1), and the first type third ground connection part GND-L1-3 and is connected with the third first light emitting control pin S1-3.

[0132] The normal projection of the second connection signal line L2 corresponding to one of the first sub-light emitting areas F1 on the substrate substrate 1011 crosses the normal projection of the first type chip driving signal line VDD1, the first type control signal line (DI1 and DO1), and the first type clock signal line (CI1 and CO1) on the substrate substrate 1011. For example, one end of the second connection signal line L2 corresponding to the fourth first sub-light emitting area F14 is connected with the second light emitting electrode of the last light emitting unit 103 in the fourth first sub-light emitting area F14, and the other end crosses the first type chip driving signal line VDD1, the first type control signal line (DI1 and DO1), and the first type clock signal line (CI1 and CO1) and is connected with the fourth first light emitting control pin S1-4.

[0133] In the embodiment of the present application, referring to FIG. 6, the first type clock signal line (CI1 and CO1) and the first type control signal line (DI1 and DO1) are arranged between the first type chip driving signal line VDD1 and the first type chip driving pin VDD-J1 in the first type driving chip 102a, so as to avoid affecting the first type clock signal line (CI1 and CO1) and the first type control signal line (DI1 and DO1) when the first type chip driving signal line VDD1 is connected with the first type chip driving pin VDD-J1. The connection can be realized by layer exchange. That is, the second conductive layer 1014 further includes a fourth connection signal line L4. One end of the fourth connection signal line L4 is connected with the first type chip driving signal line VDD1 through a via in the first insulating layer 1013, and the other end of the fourth connection signal line L4 is connected with the first type chip control pin VDD-J1. The normal projection of the fourth connection signal line L4 on the substrate substrate 1011 crosses the normal projection of the first type clock signal line (CI1 and CO1) and the first type control signal line (DI1 and DO1) on the substrate substrate 1011.

[0134] In the embodiment of the present application, as can be seen from FIG. 6, in the case where the first type of driving chip 102a is arranged transversely, the second conductive layer 1014 only needs to be provided with a first connection signal line L1 connecting the light emitting unit 103 and the light emitting driving signal line VLED, a second connection signal line L2 connecting the light emitting unit 103 and the light emitting control pin (such as the first type of light emitting control pin S1 in FIG. 6), a third connection signal line L3 for connecting a plurality of light emitting units 103 in series, and a fourth connection signal line L4 for connecting the chip driving signal line VDD and the chip control pin VDD-J. The second conductive layer 1014 needs to be provided with fewer connection signal lines, so that the layer change connection of the signal lines can be reduced, and the reliability and dependability of the lamp panel 100 can be improved.

[0135] Optionally, since the distance between the driving pin J in the first type of driving chip 102a and the first conductive layer 1012 in the driving substrate 101 is relatively far, and the distance between the driving pin J and the second conductive layer 1014 in the driving substrate 101 is relatively close, the thickness of the driving pin J which is overlapped with the first conductive layer 1012 needs to be set relatively thick, and the thickness of the driving pin J which is overlapped with the second conductive layer 1014 needs to be set relatively thin.

[0136] For example, in the first column of light emitting areas 100a1, the first and second first type of ground pins GND-J1-1 and GND-J1-2 which are connected with the first type of second ground connection part GND-L1-2 of the first conductive layer 1012, the third first type of ground pin GND-J1-3 which is connected with the first type of third ground connection part GND-L1-3 of the first conductive layer 1012, the first type of clock input pin CI-J1 which is connected with the first type of clock input signal line CI1 of the first conductive layer 1012, the first type of clock output pin CO-J1 which is connected with the first type of clock output signal line CO1 of the first conductive layer 1012, the first type of control input pin DI-J1 which is connected with the first type of control input signal line DI1 of the first conductive layer 1012, and the first type of control output pin DO-J1 which is connected with the first type of control output signal line DO1 of the first conductive layer 1012, are set to have a relatively thick thickness. The four first type of light emitting control pins S1 which are connected with the four second connection signal lines L2 of the second conductive layer 1014, and the first type of chip control pin VDD-J1 which is connected with the first type of chip driving signal line VDD1 of the second conductive layer 1014, are set to have a relatively thin thickness.

[0137] Of course, in order to make the thickness of each driving pin J of the first type of driving chip 102a the same, a plurality of overlapping blocks can be arranged on the second conductive layer 1014, which can be arranged between the signal lines in the first conductive layer 1012 and the corresponding driving pins J that need to be overlapped. The embodiments of the present application do not make specific limitations on this.

[0138] In the embodiments of the present application, referring to FIG. 10, the light-emitting area 100a further includes a second column of light-emitting areas 100a2 extending along the first direction X. The second column of light-emitting areas 100a2 and the first column of light-emitting areas 100a1 are arranged adjacent to each other along the second direction Y. The second column of light-emitting areas 100a2 includes a plurality of second control light-emitting areas 100a21 arranged along the second direction Y. Referring to FIG. 10, each second control light-emitting area 100a21 includes a plurality of second sub light-emitting areas F2. The lamp panel includes a plurality of light-emitting units 103 located in the plurality of second sub light-emitting areas F2. The second conductive layer 1014 includes a plurality of first connection signal lines L1 corresponding to the plurality of second sub light-emitting areas F2 and a plurality of second connection signal lines L2 corresponding to the plurality of second sub light-emitting areas F2.

[0139] For example, for each second control light-emitting area 100a21, the number of second sub light-emitting areas F2 included in the second control light-emitting area 100a21 can be equal to the number of first connection signal lines L1 included in the second conductive layer 1014 and located in the second control light-emitting area 100a21, and can be equal to the number of second connection signal lines L2 included in the second conductive layer 1014 and located in the first control light-emitting area 100a11.

[0140] Optionally, the plurality of light-emitting units 103 of each second sub light-emitting area F2 are connected in series with each other, and a first light-emitting unit 103 in the plurality of light-emitting units 103 connected in series with each other is connected to the light-emitting driving signal line VLED through the corresponding first connection signal line L1. That is, in the second sub light-emitting area F2, the first light-emitting unit 103 in the plurality of light-emitting units 103 connected in series with each other can directly receive the light-emitting driving signal provided by the light-emitting driving signal line VLED through the first connection signal line L1.

[0141] The plurality of driving chips 102 included in the lamp panel 100 further include a plurality of second type of driving chips 102b arranged along the first direction X. The plurality of second type of driving chips 102b are arranged corresponding to the plurality of second control light-emitting areas 100a21, and each second type of driving chip 102b is configured to control the light-emitting units 103 of the second sub light-emitting areas F2 in the corresponding second control light-emitting area 100a21. Each second type of driving chip 102b includes a plurality of second type of light-emitting control pins S2 corresponding to the plurality of second sub light-emitting areas F2, and each second type of light-emitting control pin S2 is connected to a last light-emitting unit 103 in the plurality of light-emitting units 103 connected in series with each other of the corresponding second sub light-emitting area F2 through the corresponding second connection signal line L2.

[0142] In the second column of light emitting areas 100a2, the second conductive layer 1014 further includes a plurality of third connection signal line groups L3z corresponding to the plurality of second sub light emitting areas F2. Each third connection signal line group L3z is used to connect a plurality of light emitting units 103 in the corresponding second sub light emitting area F2, so as to realize the mutual series connection of the plurality of light emitting units 103 in each second sub light emitting area F2.

[0143] In the embodiments of the present application, the difference between the second column of light emitting areas 100a2 and the first column of light emitting areas 100a1 is that the arrangement order of the plurality of types of signal lines in the second column of light emitting areas 100a2 and the plurality of types of signal lines in the first column of light emitting areas 100a1 in the second direction Y is opposite. The arrangement order in the second direction Y can refer to the arrangement order in the positive direction of the second direction Y.

[0144] For example, in the first column of light emitting areas 100a1, the signal lines arranged in the positive direction of the second direction Y are in turn the light emitting drive signal line VLED, the ground signal line GND, the clock signal lines (CI and CO), the control signal lines (DI and DO), the chip drive signal line VDD, the ground signal line GND and the light emitting drive signal line VLED. In the second column of light emitting areas 100a2, the signal lines arranged in the positive direction of the second direction Y are in turn the light emitting drive signal line, the ground signal line GND, the chip drive signal line VDD, the control signal lines (DI and DO), the clock signal lines (CI and CO), the ground signal line GND and the light emitting drive signal line.

[0145] As can be seen with reference to FIG. 10, in the second column of light emitting areas 100a2, the second conductive layer 1014 includes a first second-type light emitting drive signal line VLED2-1, a first second-type ground signal line GND2-1, a second-type chip drive signal line VDD2, second-type control signal lines (DI2 and DO2), second-type clock signal lines (CI2 and CO2), a second second-type ground signal line GND2-2 and a second second-type light emitting drive signal line VLED2-2 arranged in the second direction Y in turn. In this case, the second first-type ground signal line GND1-2 and the first second-type ground signal line GND2-1 are both located between the first first-type ground signal line GND1-1 and the second second-type ground signal line GND2-2.

[0146] Referring to FIG. 11, the first conductive layer 1012 further includes a third type of ground signal line GND3. The third type of ground signal line GND3 extends along the second direction Y and is located at one end of the first first type of ground signal line GND1-1 and the second second type of ground signal line GND2-2 close to the peripheral area 100b. The third type of ground signal line GND3 is directly connected to the first first type of ground signal line GND1-1 and the second second type of ground signal line GND2-2. That is, all the ground signal lines GND in the first column of light emitting areas 100a1 and the second column of light emitting areas 100a2 are directly connected together through the transverse third type of ground signal line GND3, realizing the connection of the ground signal lines of different columns of light emitting areas, so as to ensure that the ground signals of different ground signal lines are the same.

[0147] In the embodiment of the present application, referring to FIG. 12, the third type of ground signal line GND3 and the second first type of ground signal line GND1-2, the second first type of light emitting driving signal line VLED1-2, the first second type of light emitting driving signal line VLED2-1 and the first second type of ground signal line GND2-1 have a spacing in the first direction X. The spacing can be located at the edge of the light emitting area 100a close to the peripheral area 100b.

[0148] The first type of clock signal line (CI1 and CO1) includes the first type of clock output signal line CO1 and the second type of clock signal line (CI2 and CO2) includes the second type of clock input signal line CI2, which are connected as an integrated clock signal line C-T. That is, the clock signal line (CI and CO) located at the first column of light emitting areas 100a1 and the clock signal line (CI and CO) located at the second column of light emitting areas 100a2 are arranged in series.

[0149] The first type of control signal line (DI1 and DO1) includes the first type of control output signal line DO1 and the second type of control signal line (DI2 and DO2) includes the second type of control input signal line DI2, which are connected as an integrated control signal line D-T. That is, the control signal line (DI and DO) located at the first column of light emitting areas 100a1 and the clock signal line (CI and CO) located at the second column of light emitting areas 100a2 are arranged in series.

[0150] Referring to FIG. 12, the integrated clock signal line C-T and the integrated control signal line D-T are located in the first conductive layer 1012, and at least part of the integrated clock signal line C-T and at least part of the integrated control signal line D-T can be located in the interval to avoid mutual influence with other signal lines. The at least part of the integrated clock signal line C-T located in the interval can refer to a part of the integrated clock signal line C-T extending along the second direction Y, and the at least part of the integrated control signal line D-T located in the interval can refer to a part of the integrated control signal line D-T extending along the second direction Y. As can be seen from FIG. 12, the part of the integrated control signal line D-T located in the interval is farther away from the third type of ground signal line GND3 than the part of the integrated clock signal line C-T located in the interval.

[0151] In the embodiment of the present application, the series connection of the clock signal lines (CI and CO) in the first column of light emitting areas 100a1 and the second column of light emitting areas 100a2 is realized by the integrated clock signal line C-T in the first conductive layer 1012, and the series connection of the control signal lines (DI and DO) in the first column of light emitting areas 100a1 and the second column of light emitting areas 100a2 is realized by the integrated control signal line D-T in the first conductive layer 1012. In this way, when the clock connection signal line or the control connection signal line is provided in the second conductive layer 1014, the clock connection signal line or the control connection signal line can be prevented from being corroded and short-circuited due to the poor moisture resistance of the second insulating layer 1015, thereby ensuring the reliability and reliability of the lamp panel 100.

[0152] Referring to FIG. 11, the second conductive layer 1014 further includes a first type of fourth ground connection GND-L1-4 and a second type of fourth ground connection GND-L2-4. The orthogonal projection of the first type of fourth ground connection GND-L1-4 on the substrate substrate 1011 crosses the orthogonal projection of the integrated control signal line D-T and the integrated clock signal line C-T on the substrate substrate 1011. One end of the first type of fourth ground connection GND-L1-4 is connected to the second first type of ground signal line GND1-2 through a via in the first insulating layer 1013, and the other end is connected to the third type of ground signal line GND3 through a via in the first insulating layer 1013.

[0153] The orthogonal projection of the second type of fourth ground connection GND-L2-4 on the substrate substrate 1011 crosses the orthogonal projection of the integrated control signal line D-T and the integrated clock signal line C-T on the substrate substrate 1011, one end of the first type of fourth ground connection GND-L1-4 is connected to the first second type of ground signal line GND2-1 through a via in the first insulating layer 1013, and the other end is connected to the third type of ground signal line GND3 through a via in the first insulating layer 1013.

[0154] Optionally, referring to FIG. 11 and FIG. 12, the first first-type ground signal line GND1-1 and the third-type ground signal line GND3 are directly connected on the first conductive layer 1012. The second second-type ground signal line GND2-2 and the third-type ground signal line GND3 are directly connected on the first conductive layer 1012. In order to connect the clock signal lines (CI and CO) and the control signal lines (DI and DO) in series, it is necessary to set a spacing in the first direction X between the third-type ground signal line GND3 and the second first-type ground signal line GND1-2 and the first second-type ground signal line GND2-1. Therefore, the second first-type ground signal line GND1-2 and the third-type ground signal line GND3 are connected through the first fourth-type ground connection part GND-L1-4 of the second conductive layer 1014. The first second-type ground signal line GND2-1 and the third-type ground signal line GND3 are connected through the second fourth-type ground connection part GND-L2-4 of the second conductive layer 1014.

[0155] As can be further seen from FIG. 11, the first light emitting unit 103 of at least one second sub light emitting area F2 of the plurality of second sub light emitting areas F2 is connected to the first second-type light emitting driving signal line VLED2-1. The first light emitting unit 103 of at least one second sub light emitting area F2 of the plurality of second sub light emitting areas F2 is connected to the second second-type light emitting driving signal line VLED2-2. In this way, for the first light emitting unit 103 in each second sub light emitting area F2, one light emitting driving signal line that is closer to the second sub light emitting area F2 can be selected for connection, so as to avoid layer switching connection as much as possible and improve the reliability and dependability of the lamp panel 100.

[0156] As can be further seen from FIG. 10 and FIG. 11, the second second-type ground signal line GND2-2 is directly connected to the second-type ground pin GND-J2 of the second-type driving chip 102b. The first second-type ground signal line GND2-1 is not directly connected to the ground pin GND-J of the second-type driving chip 102b. Therefore, the second conductive layer 1014 further comprises a second-type first ground connection part GND-L2-1. The orthographic projection of the second-type first ground connection part GND-L2-1 on the substrate 1011 covers the orthographic projection of the second-type clock signal line (CI2 and CO2), the second-type control signal line (DI2 and DO2), and the second-type chip driving signal line VDD2 on the substrate 1011. One end of the second-type first ground connection part GND-L2-1 is connected to the first second-type ground signal line GND2-1 through a via in the first insulating layer 1013, and the other end is connected to the second second-type ground signal line GND2-2 through a via in the first insulating layer 1013.

[0157] The first second-type ground signal line GND2-1 and the second second-type ground signal line GND2-2 can be connected through the first second-type ground connection GND-L2-1. Since there are many signal lines around the driving chip 102, the first second-type ground connection GND-L2-1 can be designed to have a large distance from the projection of the driving chip 102 on the substrate 1011, so that the signal lines around the driving chip 102 can not be switched to another layer, and different types of signal lines can not be short-circuited due to corrosion of the signal lines.

[0158] FIG. 13 is a schematic diagram of the arrangement of the driving pins of a second-type driving chip according to an embodiment of the present application. Referring to FIG. 13, the second-type driving chip 102b includes 12 driving pins when each second control light-emitting area 100a21 includes four second sub-light-emitting areas F2. The 12 driving pins are arranged in two rows in the first direction X and six columns in the second direction Y.

[0159] The four second sub-light-emitting areas F2 are arranged in two rows in the first direction X and two columns in the second direction Y. In subsequent embodiments, the first second sub-light-emitting area F2 in the first row and the first column of the four second sub-light-emitting areas F2 is referred to as the first second sub-light-emitting area F21, the second second sub-light-emitting area F2 in the second row and the first column of the four second sub-light-emitting areas F2 is referred to as the second second sub-light-emitting area F22, the third second sub-light-emitting area F2 in the first row and the second column of the four second sub-light-emitting areas F2 is referred to as the third second sub-light-emitting area F23, and the fourth second sub-light-emitting area F2 in the second row and the second column of the four second sub-light-emitting areas F2 is referred to as the fourth second sub-light-emitting area F24. The order of the rows is from top to bottom in the drawing, and the order of the columns is from left to right in the drawing.

[0160] The first row of the 12 driving pins in the second-type driving chip 102b includes the second-type control output pin DO-J2, the second-type clock output pin CO-J2, the second-type chip control pin VDD-J2, the first second-type light-emitting control pin S2-1, the first second-type ground pin GND-J2-1, and the third second-type light-emitting control pin S2-3.

[0161] The second row of the 12 driving pins in the second-type driving chip 102b includes the second-type control input pin DI-J2, the second-type clock input pin CI-J2, the third second-type ground pin GND-J2-3, the second second-type light-emitting control pin S2-2, the second second-type ground pin GND-J2-2, and the fourth second-type light-emitting control pin S2-4.

[0162] The first second-type light-emitting control pin S2-1 corresponds to the first second sub-light-emitting area F21, and the third second-type light-emitting control pin S2-3 corresponds to the third second sub-light-emitting area F23. The second second-type light-emitting control pin S2-2 corresponds to the second second sub-light-emitting area F22, and the fourth second-type light-emitting control pin S2-4 corresponds to the fourth second sub-light-emitting area F24.

[0163] As shown in FIG. 13, the second-type control output pin DO-J2 and the second-type control input pin DI-J2 are arranged along the first direction X. The second-type clock output pin CO-J2 and the second-type clock input pin CI-J2 are arranged along the first direction X. The second-type chip control pin VDD-J2 and the third second-type ground pin GND-J2-3 are arranged along the first direction X. The first second-type light-emitting control pin S2-1 and the second second-type light-emitting control pin S2-2 are arranged along the first direction X, the first second-type ground pin GND-J2-1 and the second second-type ground pin GND-J2-2 are arranged along the first direction X, and the third second-type light-emitting control pin S2-3 and the fourth second-type light-emitting control pin S2-4 are arranged along the first direction X.

[0164] As shown in FIG. 10, FIG. 11 and FIG. 13, the first second-type light-emitting control pin S2-1 is the light-emitting control pin closest to the first second sub-light-emitting area F21, and thus the second light-emitting electrode of the last light-emitting unit 103 of the first second sub-light-emitting area F21 can be connected to the first second-type light-emitting control pin S2-1. The second second-type light-emitting control pin S2-2 is the light-emitting control pin closest to the second second sub-light-emitting area F22, and thus the second light-emitting electrode of the last light-emitting unit 103 of the second second sub-light-emitting area F22 can be connected to the second second-type light-emitting control pin S2-2. The third second-type light-emitting control pin S2-3 is the light-emitting control pin closest to the third second sub-light-emitting area F23, and thus the second light-emitting electrode of the last light-emitting unit 103 of the third second sub-light-emitting area F23 can be connected to the third second-type light-emitting control pin S2-3. The fourth second-type light-emitting control pin S2-4 is the light-emitting control pin closest to the fourth second sub-light-emitting area F24, and thus the second light-emitting electrode of the last light-emitting unit 103 of the fourth second sub-light-emitting area F24 can be connected to the fourth second-type light-emitting control pin S2-4.

[0165] In the embodiment of the present application, referring to FIG. 12 and FIG. 14, the second type of clock signal lines (CI2 and CO2) include the second type of clock input signal line CI2 and the second type of clock output signal line CO2 which are arranged along the first direction X and both extend along the first direction X. The second type of clock input signal line CI2 is directly connected to the second type of clock input pin CI-J2 at the end close to the second type of clock output signal line CO2. The second type of clock output signal line CO2 is directly connected to the second type of clock output pin CO-J2 at the end close to the second type of clock input signal line CI2.

[0166] Referring to FIG. 12 and FIG. 14, the second type of control signal lines (DI2 and DO2) include the second type of control input signal line DI2 and the second type of control output signal line DO2 which are arranged along the first direction X and both extend along the first direction X. The second type of control input signal line DI2 is directly connected to the first type of control input pin DI-J1 at the end close to the second type of control output signal line DO2, and the second type of control output signal line DO2 is directly connected to the second type of control output pin DO-J2 at the end close to the second type of control input signal line DI2.

[0167] As can be seen from FIG. 12 and FIG. 14, the second type of clock input signal line CI2 is located at the right side of the second type of control input signal line DI2, so that in the second type of driving chip 102b, the second type of clock input pin CI-J2 can be arranged at the right side of the second type of control input pin DI-J2, which can facilitate the second type of clock input signal line CI2 to be closer to the second type of clock input pin CI-J2 and the second type of control input signal line DI2 to be closer to the second type of control input pin DI-J2. Thus, the second type of clock input pin CI-J2 can be connected through the position overlapped with the projection of the second type of clock input signal line CI2, and the second type of control input pin DI-J2 can be connected through the position overlapped with the projection of the second type of control input signal line DI2.

[0168] Similarly, the second type of clock output signal line CO2 is located at the right side of the second type of control output signal line DO2, so that in the second type of driving chip 102b, the second type of clock output pin CO-J2 can be arranged at the right side of the second type of control output pin DO-J2, which can facilitate the second type of clock output signal line CO2 to be closer to the second type of clock output pin CO-J2 and the second type of control output signal line DO2 to be closer to the second type of control output pin DO-J2. Thus, the second type of clock output pin CO-J2 can be connected through the position overlapped with the projection of the second type of clock output signal line CO2, and the second type of control output pin DO-J2 can be connected through the position overlapped with the projection of the second type of control output signal line DO2.

[0169] As can be further seen with reference to FIG. 12 and FIG. 14, the second second-type ground signal line GND2-2 includes a second-type ground body portion GND-Z2 and a second-type second ground connecting portion GND-L2-2 extending in the first direction X. The second-type second ground connecting portion GND-L2-2 is connected to the second-type ground body portion GND-Z2 at both ends thereof in the first direction X. The second-type ground body portion GND-Z2 and the second-type second ground connecting portion GND-L2-2 form a second enclosed area Q2, and the distance between the second-type second ground connecting portion GND-L2-2 and the second-type clock signal lines (CI2 and CO2) in the second direction Y is greater than the distance between the second-type ground body portion GND-Z2 and the second-type clock signal lines (CI2 and CO2) in the second direction Y.

[0170] The first second-type ground pin GND-J2-1 and the second second-type ground pin GND-J2-2 are both directly connected to the second-type second ground connecting portion GND-L2-2. Optionally, the first second-type ground pin GND-J2-1 and the second second-type ground pin GND-J2-2 can be directly connected through the position where the projections of the second-type second ground connecting portion GND-L2-2 overlap.

[0171] In the embodiments of the present application, the last light emitting unit 103 of the two second sub light emitting areas F2 in the plurality of second sub light emitting areas F2 and the corresponding two second-type light emitting control pins S2 have their projections on the substrate 1011 within the second enclosed area Q2. In this way, the last light emitting unit 103 of the second sub light emitting area F2 and the corresponding second-type light emitting control pin S2 can be made closer, and thus the last light emitting unit 103 of each of the two second sub light emitting areas F2 can be connected to the corresponding second-type light emitting control pin S2 through the second connecting signal line L2.

[0172] Optionally, referring to FIG. 10, the orthographic projection of the last light emitting cell 103 of the third second sub light emitting area F23 of the plurality of second sub light emitting areas F2 and the last light emitting cell 103 of the fourth second sub light emitting area F24 on the substrate 1011 are both located within the second closed area Q2. The orthographic projection of the third second type light emitting control pin S2-3 corresponding to the third second sub light emitting area F23 and the fourth second type light emitting control pin S2-4 corresponding to the fourth second sub light emitting area F24 on the substrate 1011 are located within the second closed area Q2. Thus, the second light emitting electrode of the last light emitting cell 103 of the third second sub light emitting area F23 is connected through a corresponding second connection signal line L2 and the third second type light emitting control pin S2-3, and the second light emitting electrode of the last light emitting cell 103 of the fourth second sub light emitting area F24 is connected through a corresponding second connection signal line L2 and the fourth second type light emitting control pin S2-4.

[0173] Referring to FIGS. 12 and 14, the second second type ground signal line GND2-2 further includes a second type third ground connection portion GND-L2-3 extending along the first direction X. One end of the second type third ground connection portion GND-L2-3 is connected to the second type ground main portion GND-Z2, and the other end has a spacing from the second type ground main portion GND-Z2.

[0174] The orthographic projection of the second type third ground connection portion GND-L2-3 on the substrate 1011 and the orthographic projection of the second type chip control pin VDD-J2 on the substrate 1011 do not overlap. The orthographic projection of the second type third ground connection portion GND-L2-3 on the substrate 1011 and the orthographic projection of the third second type ground pin GND-J2-3 on the substrate 1011 overlap. The other end of the second type third ground connection portion GND-L2-3 is directly connected to the third second type ground pin GND-J2-3. Optionally, the other end of the second type third ground connection portion GND-L2-3 is connected through a position overlapping the projection of the third second type ground pin GND-J2-3.

[0175] Referring to FIGS. 12 and 14, the second type second ground connection portion GND-L2-2 and the second type ground main portion GND-Z2 form a second containing area W2 near one side of the second type clock signal line (CI2 and CO2). The orthographic projection of the last light emitting cell 103 of two second sub light emitting areas F2 (such as the first second sub light emitting area F21 and the second second sub light emitting area F22) of the plurality of second sub light emitting areas F2 on the substrate 1011 is located between the orthographic projection of the first second type ground signal line GND2-1 on the substrate 1011 and the orthographic projection of the second type chip driving signal line VDD2 on the substrate 1011.

[0176] The normal projection of the second connection signal line L2 corresponding to one of the plurality of second sub-light emitting areas F2 on the substrate 1011 crosses the normal projections of the second chip driving signal line VDD2, the second control signal line (DI2 and DO2), and the second clock signal line (CI2 and CO2) on the substrate 1011. For example, in FIG. 11, one end of the second connection signal line L2 corresponding to the first second sub-light emitting area F21 is connected to the second light emitting electrode of the last light emitting unit 103 in the first second sub-light emitting area F21, and the other end is connected to the first second light emitting control pin S2-1 after crossing the second chip driving signal line VDD2, the second control signal line (DI2 and DO2), and the second clock signal line (CI2 and CO2).

[0177] The normal projection of the second connection signal line L2 corresponding to one of the plurality of second sub-light emitting areas F2 on the substrate 1011 crosses the normal projections of the second chip driving signal line VDD2, the second control signal line (DI2 and DO2), the second clock signal line (CI2 and CO2), and the second third ground connection part GND-L2-3 on the substrate 1011. For example, in FIG. 11, one end of the second connection signal line L2 corresponding to the second second sub-light emitting area F22 is connected to the second light emitting electrode of the last light emitting unit 103 in the second second sub-light emitting area F22, and the other end is connected to the second second light emitting control pin S2-2 after crossing the second chip driving signal line VDD2, the second control signal line (DI2 and DO2), the second clock signal line (CI2 and CO2), and the second third ground connection part GND-L2-3.

[0178] In the embodiments of the present application, in combination with FIGS. 10 to 14, for the fourth first sub-light emitting area F14 of the last first control light emitting area 100a11 along the first direction X, the first chip driving signal line VDD1 can be cut off to the side of the second connection signal line L2 away from the peripheral area 100b when the first chip driving signal line VDD1 extends along the first direction X. Thus, the normal projection of the second connection signal line L2 corresponding to the fourth first sub-light emitting area F14 of the last first control light emitting area 100a11 along the first direction X on the substrate 1011 is connected to the fourth first light emitting control pin S1-4 after crossing the first control signal line (DI2 and DO2) and the first clock signal line (CI2 and CO2).

[0179] Referring to FIGS. 10-14, for the second second sub-emitting region F12 of the last second control emitting region 100a21 along the first direction X, the second type chip driving signal line VDD2 can be cut off to the side of the second connection signal line L2 away from the peripheral region 100b when the second type chip driving signal line VDD2 extends along the first direction X. Thus, the second connection signal line L2 corresponding to the second second sub-emitting region F22 of the last second control emitting region 100a21 along the first direction X is connected to the second second type light emitting control pin S2-2 after crossing the second type control signal line (DI2 and DO2), the second type clock signal line (CI2 and CO2), and the second type third ground connection GND-L2-3 on the substrate.

[0180] In the embodiments of the present application, referring to FIG. 10, the second type clock signal line (CI2 and CO2) and the second type control signal line (DI2 and DO2) are provided between the second type chip driving signal line VDD2 and the second type chip driving pin VDD-J2 of the second type driving chip 102b, and thus in order to avoid affecting the second type clock signal line (CI2 and CO2) and the second type control signal line (DI2 and DO2) when the second type chip driving signal line VDD2 is connected to the second type chip driving pin VDD-J2, the connection can be achieved by layer switching. That is, in the second column of emitting regions 100a2, the second conductive layer 1014 further includes a fourth connection signal line L4. One end of the fourth connection signal line L4 is connected to the second type chip driving signal line VDD2 through a via in the first insulating layer 1013, and the other end of the fourth connection signal line L4 is connected to the second type chip control pin VDD-J2. The orthogonal projection of the fourth connection signal line L4 on the substrate 1011 crosses the orthogonal projection of the second type clock signal line (CI2 and CO2) and the second type control signal line (DI2 and DO2) on the substrate 1011.

[0181] In the embodiments of the present application, as can be seen from FIGS. 10 and 11, in the case where the second type driving chip 102b is arranged horizontally, the second conductive layer 1014 only needs to provide the first connection signal line L1 for connecting the light emitting unit 103 and the light emitting driving signal line VLED, the second connection signal line L2 for connecting the light emitting unit 103 and the light emitting control pin S, the third connection signal line L3 for connecting the plurality of light emitting units 103 in series, and the fourth connection signal line L4 for connecting the chip driving signal line VDD and the chip control pin VDD-J. The second conductive layer 1014 needs to provide fewer connection signal lines, and thus the layer switching connection of the signal lines can be reduced, improving the reliability and reliability of the lamp panel.

[0182] Optionally, since the distance between the driving pins J in the second type of driving chip 102b and the first conductive layer 1012 in the driving substrate 101 is relatively far, and the distance between the driving pins J and the second conductive layer 1014 in the driving substrate 101 is relatively close, the thickness of the driving pins J that are overlapped with the first conductive layer 1012 is set to be relatively thick, and the thickness of the driving pins J that are overlapped with the second conductive layer 1014 is set to be relatively thin.

[0183] For example, the thickness of the first second type of ground pin GND-J2-1 and the second second type of ground pin GND-J2-2 that are connected with the second type of second ground connection part GND-L2-2 of the first conductive layer 1012, the third second type of ground pin GND-J2-3 that is connected with the second type of third ground connection part GND-L2-3 of the first conductive layer 1012, the second type of clock input pin CI-J2 that is connected with the second type of clock input signal line CI2 of the first conductive layer 1012, the second type of clock output pin CO-J2 that is connected with the second type of clock output signal line CO2 of the first conductive layer 1012, the second type of control input pin DI-J2 that is connected with the second type of control input signal line DI2 of the first conductive layer 1012, and the second type of control output pin DO-J2 that is connected with the second type of control output signal line DO2 of the first conductive layer 1012 are set to be relatively thick. The thickness of the four second type of light emitting control pins S2 that are connected with the four second connection signal lines L2 of the second conductive layer 1014, and the second type of chip control pin VDD-J2 that is connected with the second type of chip driving signal line VDD2 of the second conductive layer 1014 are set to be relatively thin.

[0184] Of course, in order to make the thickness of each driving pin J of the second type of driving chip 102b the same, a plurality of overlapping blocks can be arranged on the second conductive layer 1014, and the overlapping blocks can be arranged between the signal lines of the first conductive layer 1012 and the corresponding driving pins J. The embodiments of the present application do not make specific limitations on this.

[0185] In the embodiments of the present application, referring to FIG. 5, the light emitting area 100a includes a plurality of first column light emitting areas 100a1 and a plurality of second column light emitting areas 100a2, and the plurality of first column light emitting areas 100a1 and the plurality of second column light emitting areas 100a2 are staggered in the second direction Y. In this way, the clock signal lines (CI and CO) in the first column light emitting areas 100a1 and the clock signal lines (CI and CO) in the second column light emitting areas 100a2 can be connected in series, and the control signal lines (DI and DO) in the first column light emitting areas 100a1 and the control signal lines (DI and DO) in the second column light emitting areas 100a2 can be connected in series.

[0186] Optionally, in each two adjacent columns of the light emitting regions, the clock signal lines (CI and CO) in the first column of light emitting regions 100a1 and the clock signal lines (CI and CO) in the second column of light emitting regions 100a2 are connected in series. In each two adjacent columns of the light emitting regions, the control signal lines (DI and DO) in the first column of light emitting regions 100a1 and the control signal lines (DI and DO) in the second column of light emitting regions 100a2 are connected in series.

[0187] Alternatively, in each four adjacent columns of the light emitting regions 100a, the clock signal lines (CI and CO) in the first first column of light emitting regions 100a1, the first second column of light emitting regions 100a2, the second first column of light emitting regions 100a1 and the second second column of light emitting regions 100a2 are connected in series in turn, and the control signal lines (DI and DO) in the first first column of light emitting regions 100a1, the first second column of light emitting regions 100a2, the second first column of light emitting regions 100a1 and the second second column of light emitting regions 100a2 are connected in series in turn.

[0188] In the case that the clock signal lines (CI and CO) and the control signal lines (DI and DO) in the four columns of light emitting regions are connected in series in turn, the series connection between the first first column of light emitting regions 100a1 and the first second column of light emitting regions 100a2, and the series connection between the second first column of light emitting regions 100a1 and the second second column of light emitting regions 100a2 can refer to the series connection in FIG. 11. Moreover, the positions of the series connection between the first first column of light emitting regions 100a1 and the first second column of light emitting regions 100a2, and the positions of the series connection between the second first column of light emitting regions 100a1 and the second second column of light emitting regions 100a2 are located on the same side (for example, the lower side) of the display region close to the peripheral region 100b.

[0189] The positions of the series connection between the first second column of light emitting regions 100a2 and the second first column of light emitting regions 100a1 (for example, the upper side), and the positions of the series connection between the first first column of light emitting regions 100a1 and the first second column of light emitting regions 100a2 (for example, the lower side) are located on opposite sides of the light emitting region 100a close to the peripheral region 100b. Moreover, the clock signal lines (CI and CO) and the control signal lines (DI and DO) in the series connection between the first second column of light emitting regions 100a2 and the second first column of light emitting regions 100a1 are also located in the first conductive layer 1012.

[0190] In the embodiments of the present application, as shown in FIG. 15, the driving substrate 101 can further include a third insulating layer 1016 between the first conductive layer 1012 and the substrate substrate 1011. The third insulating layer 1016 can be a buffer layer (buffer) to facilitate the subsequent film formation of the conductive layer.

[0191] Optionally, the first conductive layer 1012 includes a first conductive sub-layer 10121 and a second conductive sub-layer 10122. The material of the first conductive sub-layer 10121 can be molybdenum-niobium alloy (MoNb), and the material of the second conductive sub-layer 10122 can be copper (Cu). The second conductive layer 1014 includes a third conductive sub-layer 10141 and a fourth conductive sub-layer 10142. The material of the third conductive sub-layer 10141 can be MoNb, and the material of the fourth conductive sub-layer 10142 can be Cu. That is, at the via position of the first insulating layer 1013, the third conductive sub-layer 10141 of the second conductive layer 1014 and the second conductive sub-layer 10122 are directly in contact and electrically connected.

[0192] Optionally, the first insulating layer 1013 can include a first sub-insulating layer 10131, a second sub-insulating layer 10132, a third sub-insulating layer 10133 and a fourth sub-insulating layer 10134 stacked in sequence in a direction away from the substrate base plate 1011. The material of the first sub-insulating layer 10131 and the fourth sub-insulating layer 10134 can be inorganic material, such as silicon nitride or silicon oxide. The first sub-insulating layer 10131 and the fourth sub-insulating layer 10134 can be passivation layer (PVX). The material of the second sub-insulating layer 10132 and the third sub-insulating layer 10133 can be organic material, such as optical (OC) glue.

[0193] Since the inorganic material has better water and oxygen isolation ability than the organic material, by making the first insulating layer 1013 include the first sub-insulating layer 10131 and the fourth sub-insulating layer 10134 of inorganic material, the possibility of corrosion of the first conductive layer 1012 and the second conductive layer 1014 can be reduced. In order to ensure the signal transmission performance of the driving substrate 101, the thickness of the first insulating layer 1013 needs to be greater than the thickness of the first conductive layer 1012, so by arranging the second sub-insulating layer 10132 and the third sub-insulating layer 10133 of organic material between the first sub-insulating layer 10131 and the fourth sub-insulating layer 10134 to increase the total thickness of the first insulating layer 1013. Optionally, the thickness of the second sub-insulating layer 10132 can reach 4.5 μm (microns), and the thickness of the third sub-insulating layer 10133 can reach 3 μm.

[0194] And referring to FIG. 15, the fourth insulating layer 10134 can wrap the inner wall of the via hole of the first insulating layer 10131, the second insulating layer 10132 and the third insulating layer 10133, so that the inner wall of the via hole of the second insulating layer 10132 and the third insulating layer 10133 of the organic material can avoid direct contact with the second conductive layer 1014, avoid more water and oxygen in the second insulating layer 10132 and the third insulating layer 10133 from invading into the second conductive layer 1014, and ensure the yield of the lamp panel 100.

[0195] Referring to FIG. 15, the second insulating layer 1015 can include a fifth insulating layer 10151 and a sixth insulating layer 10152 stacked in sequence in a direction away from the substrate 1011. The material of the fifth insulating layer 10151 is inorganic material, such as silicon nitride or silicon oxide, and the fifth insulating layer 10151 can be a passivation layer. The material of the sixth insulating layer 10152 is organic material, such as OC glue.

[0196] In the embodiment of the present application, the thickness of the fifth insulating layer 10151 can range from 2400A (angstrom) to 4000A, and the thickness of the sixth insulating layer 10152 can range from 3μm (micron) to 4μm.

[0197] Since the driving chip 102 is laterally arranged, the layer change connection of the signal line can be reduced. In this case, since the second conductive layer 1014 is provided with fewer connection signal lines, even if the thickness of the second insulating layer 1015 is set to be thinner, the different connection signal lines can be prevented from being short-circuited due to corrosion, and the performance of the lamp panel can be ensured, and the reliability and reliability of the lamp panel can be improved. And the thickness of the second insulating layer 1015 is set to be thinner, which can reduce the use cost of the material, and is helpful to improve the margin of the product process.

[0198] And although the depth of the via hole in the first insulating layer 1013 can cause photoresist or material dry etching residue, since the signal line needs to be connected in layers, the number of via holes in the first insulating layer 1013 can be less, thereby reducing the possibility of photoresist or material dry etching residue, reducing the impact of equipment and process fluctuations on the yield of the lamp panel, and improving the reliability and reliability of the lamp panel.

[0199] In the embodiment of the present application, referring to FIGS. 10 and 11, one end of the first type first ground connection GND-L1-1 can be connected through 9 via holes in the first insulating layer 1013 and the first first type ground signal line GND1-1, and the other end can be connected through 9 via holes in the first insulating layer 1013 and the second first type ground signal line GND1-2.

[0200] Each first connection signal line L1 is connected through 4 vias in the first insulating layer 1013 and the light-emitting driving signal line VLED.

[0201] One end of the first fourth ground connection GND-L1-4 is connected through 4 vias in the first insulating layer 1013 and the second first ground signal line GND1-2, and the other end is connected through 4 vias in the first insulating layer 1013 and the third ground signal line GND3. One end of the second fourth ground connection GND-L2-4 is connected through 4 vias in the first insulating layer 1013 and the first second ground signal line GND2-1, and the other end is connected through 4 vias in the first insulating layer 1013 and the third ground signal line GND3.

[0202] Of course, the number of vias at each position in the first insulating layer 1013 can also be other numbers, which are not limited in the embodiments of the present application.

[0203] In the embodiments of the present application, the light-emitting driving signal line VLED is connected with the light-emitting unit 103, for providing a light-emitting driving signal for the light-emitting unit 103. The light-emitting driving signal line VLED can also be referred to as a light-emitting power signal line. The chip driving signal line VDD is connected with the driving chip 102, for providing a chip driving signal for the driving chip 102. The chip driving signal line VDD can also be referred to as a chip power signal line.

[0204] In the case where the first type of driving chip 102a includes three ground pins, the first first ground pin GND-J1-1 and the second first ground pin GND-J1-2 are both for controlling the second light-emitting electrode of the light-emitting unit 103. The third first ground pin GND-J1-3 is for controlling the first type of driving chip 102a.

[0205] In the case where the second type of driving chip 102b includes three ground pins, the first second ground pin GND-J2-1 and the second second ground pin GND-J2-2 are both for controlling the second light-emitting electrode of the light-emitting unit 103. The third second ground pin GND-J2-3 is for controlling the second type of driving chip 102b.

[0206] Optionally, the lamp panel 100 can further include a driving circuit located in the peripheral region, the driving circuit being configured to provide driving signals for a plurality of types of signal lines included in the driving substrate. For example, the driving circuit can provide a light-emitting driving signal for a light-emitting driving signal line, a ground signal for a ground signal line, a clock signal for a clock signal line, a control signal for a control signal line, and a chip driving signal for a chip driving signal line. Correspondingly, the light-emitting driving signal obtained by the light-emitting driving signal line from the driving circuit can be provided to the light-emitting unit. The ground signal obtained by the ground signal line from the driving circuit, the clock signal obtained by the clock signal line from the driving circuit, the control signal obtained by the control signal line from the driving circuit, and the chip driving signal obtained by the chip driving signal line from the driving circuit can all be provided to the driving chip.

[0207] In summary, the embodiment of the present application provides a lamp panel including a driving substrate, a driving chip, and a light-emitting unit. The arrangement direction of the plurality of driving pins of the driving chip is consistent with the arrangement direction of the plurality of types of signal lines included in the driving substrate, so that the distance between the signal lines in the driving substrate and the driving pins in the driving chip that need to be connected is designed to be close. In the case where the plurality of types of signal lines included in the driving substrate are all arranged in the first conductive layer, only a small number of connection signal lines need to be arranged in the second conductive layer. In this way, the number of signal lines included in the driving substrate that need to be switched between the first conductive layer and the second conductive layer to achieve connection can be reduced, and the reliability and dependability of the lamp panel can be improved.

[0208] FIG. 16 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 16, the display device can include a power supply assembly 200 and a lamp panel 100 provided by the above-described embodiment. The power supply assembly 200 and the lamp panel 100 are connected, and configured to supply power to the lamp panel 100.

[0209] Optionally, the display device can be a liquid crystal panel, an electronic paper, an organic light-emitting diode (OLED) panel, an active-matrix organic light-emitting diode (AMOLED) panel, a passive-matrix organic light-emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0210] Since the display device can have substantially the same technical effects as the lamp panel described in the foregoing embodiments, for the purpose of brevity, the technical effects of the display device are not repeated here.

[0211] The terms used in the description of the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the common meanings of the technical terms or scientific terms to those skilled in the art.

[0212] The terms used in the description of the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the common meanings of the technical terms or scientific terms to those skilled in the art. The terms "first", "second", "third", and the like used in the patent application specification and claims of the present application do not represent any order, number, or importance, but are only used to distinguish different components. Similarly, "one" or "a" and the like do not represent a quantity limitation, but represent the existence of at least one. The terms "include" or "contain" and the like mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0213] The above is only an optional embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A light panel, characterized in that, The lamp panel has a light emitting area and a peripheral area surrounding the light emitting area; the lamp panel comprises: a driving substrate comprising a substrate, a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer stacked on one side of the substrate; the first conductive layer comprises a plurality of types of signal lines insulated from each other, the plurality of types of signal lines extend in a first direction, and different types of signal lines are arranged at intervals in a second direction, the second direction intersects the first direction; the plurality of types of signal lines comprises light emitting driving signal lines; a driving chip connected through a via in the second insulating layer and a conductive layer in the driving substrate, the driving chip comprises a plurality of driving pins arranged in the first direction and in the second direction, the number of driving pins arranged in the second direction is greater than the number of driving pins arranged in the first direction; the plurality of driving pins comprises light emitting control pins; and a light emitting unit in the light emitting area, the second conductive layer comprises first connection signal lines and second connection signal lines, the first connection signal lines are used to connect the light emitting unit and the light emitting driving signal lines, and the second connection signal lines are used to connect the light emitting unit and the light emitting control pins.

2. The lamp panel of claim 1, wherein, The plurality of types of signal lines further comprises: ground signal lines, clock signal lines, control signal lines and chip driving signal lines; the clock signal lines comprise clock input signal lines and clock output signal lines, and the control signal lines comprise control input signal lines and control output signal lines; The plurality of driving pins further comprises ground pins, clock input pins, clock output pins, control input pins, control output pins and chip control pins; The ground pins are connected with the ground signal lines, the clock input pins are connected with the clock input signal lines, the clock output pins are connected with the clock output signal lines, the control input pins are connected with the control input signal lines, the control output pins are connected with the control output signal lines, and the chip control pins are connected with the chip driving signal lines.

3. The lamp panel of claim 1, wherein, The light emitting area comprises a first column of light emitting areas extending in the first direction; the first column of light emitting areas comprises a plurality of first control light emitting areas arranged in the first direction, each first control light emitting area comprises a plurality of first sub-light emitting areas, the lamp panel comprises a plurality of light emitting units in the plurality of first sub-light emitting areas, the second conductive layer comprises a plurality of first connection signal lines corresponding to the plurality of first sub-light emitting areas and a plurality of second connection signal lines corresponding to the plurality of first sub-light emitting areas; the plurality of light emitting units in each first sub-light emitting area are connected in series with each other, and a first light emitting unit in the plurality of light emitting units connected in series is connected with the light emitting driving signal lines through the corresponding first connection signal line. The lamp panel comprises a plurality of driving chips, the plurality of driving chips comprise a plurality of first type driving chips arranged along the first direction, the plurality of first type driving chips and the plurality of first control light-emitting areas are correspondingly arranged, each of the first type driving chips comprises a plurality of first type light-emitting control pins corresponding to the plurality of first sub light-emitting areas, and each of the first type light-emitting control pins is connected with a last light-emitting unit of a plurality of light-emitting units in the corresponding first sub light-emitting area through a corresponding second connection signal line. The second conductive layer further comprises a plurality of first type third connection signal line groups corresponding to the plurality of first sub light-emitting areas, and each of the first type third connection signal line groups is used for connecting the plurality of light-emitting units in the corresponding first sub light-emitting area.

4. The lamp panel of claim 3, wherein, In the first column of light-emitting areas, the first conductive layer comprises a first first type light-emitting driving signal line arranged along the second direction, a first first type ground signal line, a first type clock signal line, a first type control signal line, a first type chip driving signal line, a second first type ground signal line and a second first type light-emitting driving signal line. A first light-emitting unit of at least one first sub light-emitting area in the plurality of first sub light-emitting areas is connected with the first first type light-emitting driving signal line, and a first light-emitting unit of at least one first sub light-emitting area in the plurality of first sub light-emitting areas is connected with the second first type light-emitting driving signal line. The first type ground signal line is connected with a first type ground pin of the first type driving chip, the second conductive layer further comprises a first type first ground connection part, a normal projection of the first type first ground connection part on the substrate substrate crosses the first type clock signal line, the first type control signal line and the first type chip driving signal line on the substrate substrate, one end of the first type first ground connection part is connected with the first first type ground signal line through a via in the first insulating layer, and the other end is connected with the second first type ground signal line through a via in the first insulating layer.

5. The lamp panel of claim 4, wherein, Each of the first control light-emitting areas comprises at least four first sub light-emitting areas, and the first type driving chip comprises 12 driving pins arranged in two rows in the first direction. The first row of driving pins in the 12 driving pins of the first type driving chip are respectively a first first type light-emitting control pin, a second first type ground pin, a third first type light-emitting control pin, a third first type ground pin, a first type clock input pin and a first type control input pin. The second row of driving pins in the 12 driving pins of the first type driving chip are respectively a second first type light-emitting control pin, a first first type ground pin, a fourth first type light-emitting control pin, a first type chip control pin, a first type clock output pin and a first type control output pin. The first first-type light-emitting control pin corresponds to the first first-type sub-light-emitting area, the third first-type light-emitting control pin corresponds to the third first-type sub-light-emitting area, the second first-type light-emitting control pin corresponds to the second first-type sub-light-emitting area, and the fourth first-type light-emitting control pin corresponds to the fourth first-type sub-light-emitting area.

6. The lamp panel of claim 5, wherein, The first-type clock signal lines include first-type clock input signal lines and first-type clock output signal lines, which are arranged at intervals along the first direction and extend along the first direction, and one end of the first-type clock input signal line close to the first-type clock output signal line is directly connected to the first-type clock input pin, and one end of the first-type clock output signal line close to the first-type clock input signal line is directly connected to the first-type clock output pin. The first-type control signal lines include first-type control input signal lines and first-type control output signal lines, which are arranged at intervals along the first direction and extend along the first direction, and one end of the first-type control input signal line close to the first-type control output signal line is directly connected to the first-type control input pin, and one end of the first-type control output signal line close to the first-type control input signal line is directly connected to the first-type control output pin.

7. The lamp panel of claim 5, wherein, The first first-type ground signal line includes a first-type ground main part and a first-type second ground connecting part extending along the first direction, the first-type second ground connecting part is connected to the first-type ground main part at both ends in the first direction, the first-type ground main part and the first-type second ground connecting part form a first closed area, and the distance between the first-type second ground connecting part and the first-type clock signal line in the second direction is greater than the distance between the first-type ground main part and the first-type clock signal line in the second direction.

8. The lamp panel of claim 7, wherein, The orthographic projection of the first first-type ground pin on the substrate and the orthographic projection of the second first-type ground pin on the substrate both overlap with the orthographic projection of the first-type second ground connecting part on the substrate. The first first-type ground pin and the second first-type ground pin are both directly connected to the first-type second ground connecting part.

9. The lamp panel of claim 7, wherein, The last light-emitting unit of each of two first-type sub-light-emitting areas in the plurality of first-type sub-light-emitting areas and the orthographic projection of the corresponding two first-type light-emitting control pins on the substrate are located in the first closed area. The last light-emitting unit of each of two first-type sub-light-emitting areas in the plurality of first-type sub-light-emitting areas is connected to the corresponding first-type light-emitting control pin through the corresponding second connecting signal line.

10. The lamp panel of claim 7, wherein, The first first-type ground signal line further includes a first-type third ground connecting part extending along the first direction, one end of the first-type third ground connecting part is connected to the first-type ground main part. The first type of third ground connection part is not overlapped with the first type of chip control pin in the substrate substrate, and the first type of third ground connection part is overlapped with the third first type of ground pin in the substrate substrate, and the other end of the first type of third ground connection part is directly connected with the third first type of ground pin.

11. The lamp panel of claim 10, wherein, The first type of second ground connection part is close to the side of the first type of clock signal line and the first type of ground body part to form a first containing area; The last light emitting unit of each first sub-light emitting area in two first sub-light emitting areas in the plurality of first sub-light emitting areas is overlapped with the first type of chip driving signal line and the second type of first ground signal line in the substrate substrate; The second connection signal line corresponding to one first sub-light emitting area in the plurality of first sub-light emitting areas is overlapped with the first type of chip driving signal line, the first type of control signal line, the first type of clock signal line and the first type of third ground connection part in the substrate substrate; The second connection signal line corresponding to one first sub-light emitting area in the plurality of first sub-light emitting areas is overlapped with the first type of chip driving signal line, the first type of control signal line and the first type of clock signal line in the substrate substrate.

12. The lamp panel of claim 7, wherein, The second conductive layer further comprises a first type of fourth connection signal line; One end of the first type of fourth connection signal line is connected with the first type of chip driving signal line through the via in the first insulating layer, and the other end of the first type of fourth connection signal line is connected with the first type of chip control pin; wherein the first type of fourth connection signal line is overlapped with the first type of clock signal line and the first type of control signal line in the substrate substrate.

13. The lamp panel of any of claims 3 to 12, wherein, The light emitting area further comprises a second column of light emitting areas extending along the first direction, and the second column of light emitting areas and the first column of light emitting areas are arranged adjacent along the second direction; the second column of light emitting areas comprises a plurality of second control light emitting areas arranged along the second direction, each second control light emitting area comprises a plurality of second sub-light emitting areas, the lamp panel comprises a plurality of light emitting units in the plurality of second sub-light emitting areas, and the second conductive layer comprises a plurality of first connection signal lines corresponding to the plurality of second sub-light emitting areas and a plurality of second connection signal lines corresponding to the plurality of second sub-light emitting areas; a plurality of light emitting units of each second sub-light emitting area are connected in series with each other, and a first light emitting unit in the plurality of light emitting units connected in series is connected with the light emitting driving signal line through the corresponding first connection signal line. The plurality of driving chips further include a plurality of second type driving chips arranged along the first direction, the plurality of second type driving chips and the plurality of second control light emitting areas are correspondingly arranged, each of the second type driving chips includes a plurality of second type light emitting control pins corresponding to the plurality of second sub light emitting areas, each of the second type light emitting control pins is connected with a last light emitting unit of a plurality of light emitting units connected in series in the corresponding second sub light emitting group through the corresponding second connection signal line; The second conductive layer further includes a plurality of second type third connection signal line groups corresponding to the plurality of second sub light emitting areas, each of the second type third connection signal line groups is used for connecting the plurality of light emitting units in the corresponding second sub light emitting area; and the arrangement sequence of the plurality of types of signal lines in the second column sub light emitting area and the plurality of types of signal lines in the first column sub light emitting area in the second direction is opposite.

14. The lamp panel of claim 13, wherein, In the second column light emitting area, the first conductive layer includes a first second type light emitting driving signal line, a first second type ground signal line, a second type chip driving signal line, a second type control signal line, a second type clock signal line, a second second type ground signal line and a second second type light emitting driving signal line arranged in sequence along the second direction; the second first type ground signal line and the first second type ground signal line are located between the first first type ground signal line and the second second type ground signal line. The first conductive layer further includes a third type ground signal line extending along the second direction and located at one end of the first first type ground signal line and the second second type ground signal line close to the peripheral area, and the third type ground signal line is directly connected with the first first type ground signal line and the second second type ground signal line.

15. The lamp panel of claim 13, wherein, The third type ground signal line, the second second type ground signal line, the second first type light emitting driving signal line, the first second type light emitting driving signal line and the first second type ground signal line have a spacing in the first direction. The first type clock signal line includes a first type clock output signal line and the second type clock signal line includes a second type clock input signal line, which are connected as an integrated clock signal line, at least part of the integrated clock signal line is located in the spacing. The first type control signal line includes a first type control output signal line and the second type control signal line includes a second type control input signal line, which are connected as an integrated control signal line, at least part of the integrated control signal line is located in the spacing. The part of the integrated control signal line located in the spacing is farther away from the third type ground signal line than the part of the integrated clock signal line located in the spacing. The second conductive layer further includes a first type fourth ground connection part and a second type fourth ground connection part.

16. The lamp panel of claim 15, wherein, ​ The first fourth ground connection part in the substrate substrate has a projection that crosses the integral control signal line and the integral clock signal line in the substrate substrate, one end of the first fourth ground connection part is connected with the second first ground signal line, and the other end is connected with the third ground signal line. The second fourth ground connection part in the substrate substrate has a projection that crosses the integral control signal line and the integral clock signal line in the substrate substrate, one end of the first fourth ground connection part is connected with the first second ground signal line, and the other end is connected with the third ground signal line.

17. The lamp panel of claim 15, wherein, The first light emitting unit of at least one second sub-light emitting area in the plurality of second sub-light emitting areas is connected with the first second light emitting driving signal line, and the first light emitting unit of at least one second sub-light emitting area in the plurality of second sub-light emitting areas is connected with the second second light emitting driving signal line. The second second ground signal line is directly connected with the second ground pin of the second driving chip, the second conductive layer further comprises a second first ground connection part, the projection of the second first ground connection part in the substrate substrate crosses the projection of the second clock signal line, the second control signal line, and the second chip driving signal line in the substrate substrate, one end of the second first ground connection part is connected with the first second ground signal line through a via in the first insulating layer, and the other end is connected with the second second ground signal line through a via in the first insulating layer.

18. The lamp panel of claim 17, wherein, Each of the second control light emitting areas comprises at least four second sub-light emitting areas; and the second driving chip comprises 12 driving pins, and the 12 driving pins are arranged in two rows in the first direction. The first row of driving pins in the 12 driving pins of the second driving chip are respectively a second control output pin, a second clock output pin, a second chip control pin, a first second light emitting control pin, a first second ground pin, and a third second light emitting control pin. The second row of driving pins in the 12 driving pins of the second driving chip are respectively a second control input pin, a second clock input pin, a third second ground pin, a second second light emitting control pin, a second second ground pin, and a fourth second light emitting control pin. The first second light emitting control pin corresponds to the first second sub-light emitting area, the third second light emitting control pin corresponds to the third second sub-light emitting area, the second second light emitting control pin corresponds to the second second sub-light emitting area, and the fourth second light emitting control pin corresponds to the fourth second sub-light emitting area.

19. The lamp panel of claim 18, wherein, The second type of clock signal lines include second type of clock input signal lines and second type of clock output signal lines arranged along the first direction at intervals and extending along the first direction, one end of the second type of clock input signal line close to the second type of clock output signal line is directly connected with the second type of clock input pin, and one end of the second type of clock output signal line close to the second type of clock input signal line is directly connected with the second type of clock output pin; The second type of control signal lines include second type of control input signal lines and second type of control output signal lines arranged along the first direction at intervals and extending along the first direction, one end of the second type of control input signal line close to the second type of control output signal line is directly connected with the second type of control input pin, and one end of the second type of control output signal line close to the second type of control input signal line is directly connected with the second type of control output pin.

20. The lamp panel of claim 13, wherein, The light emitting area includes a plurality of the first column light emitting areas and a plurality of the second column light emitting areas, and the plurality of the first column light emitting areas and the plurality of the second column light emitting areas are staggered arranged along the second direction.

21. A display device, characterized by The display device includes a power supply assembly and the light plate according to any one of claims 1 to 20. The power supply assembly is connected with the light plate, and the power supply assembly is configured to supply power to the light plate.

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