Processor, instruction processing method, and electronic device comprising processor

Abstract

Provided in the embodiments of the present disclosure are a processor, an instruction processing method, and an electronic device comprising the processor. The processor comprises a plurality of processor cores and an accelerator module, each of the plurality of processor cores being configured to execute first-type instructions; the accelerator module comprises at least one accelerator engine that is configured to execute second-type instructions different from the first-type instructions; the accelerator module is coupled to the plurality of processor cores and shared by the plurality of processor cores; each of the plurality of processor cores dispatches, from an instruction stream processed thereby, an object instruction belonging to the second-type instructions to the accelerator module for execution, and receives from the accelerator module an execution result message for the object instruction.

Description

Processor, instruction processing method, and electronic device including processor

[0001] This application claims priority to Chinese Patent Application No. 202411261193.6, filed on September 9, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a processor, an instruction processing method, and an electronic device including the processor. BACKGROUND

[0003] The accelerator unit (or simply "accelerator") of a central processing unit (CPU) generally refers to a technology that can improve the computing power of the CPU in a specific application field, for example, a technology that improves the processing speed and efficiency of the CPU in a specific application field. The accelerator unit integrated in the CPU is generally divided into two types: CPU core internal accelerator and CPU core external accelerator according to the connection relationship with the CPU core.

[0004] However, the CPU accelerator may have problems of low utilization of the accelerator unit or large load offloading overhead. SUMMARY

[0005] According to at least one embodiment of the present disclosure, a processor is provided, comprising: a plurality of processor cores, wherein each of the plurality of processor cores is configured to execute a first type of instruction; an accelerator module, wherein the accelerator module comprises at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction; wherein the accelerator module is coupled to and shared by the plurality of processor cores, and the plurality of processor cores respectively dispatch object instructions belonging to the second type of instruction in the instruction stream processed by themselves to the accelerator module for execution and receive execution result messages of the object instructions from the accelerator module.

[0006] For example, a processor according to an embodiment of the present disclosure, wherein: the accelerator module is dynamically coupled to the plurality of processor cores, and receives the same or different object instructions belonging to the second type of instruction from the plurality of processor cores.

[0007] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores is further configured to: identify whether a current instruction in the instruction stream is the first type of instruction or the second type of instruction, in response to the current instruction being the first type of instruction, issue the current instruction to a pipeline of itself, and in response to the current instruction being the second type of instruction, issue the current instruction to the accelerator module as the object instruction.

[0008] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores is further configured to: cause the object instruction to enter a dispatch queue to wait for dispatch, allocate an entry for the object instruction in a reorder buffer (ROB), and in response to the object instruction becoming an oldest instruction in the ROB, issue the object instruction to the accelerator module.

[0009] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores is further configured to: cause the object instruction to enter a dispatch queue to wait for dispatch, wait for a reorder buffer (ROB) to empty, and in response to the ROB emptying, issue the instruction to the accelerator module.

[0010] For example, a processor according to an embodiment of the present disclosure, wherein: the accelerator module is further configured to return a processing result of the object instruction to the corresponding processor core, and the execution result message of the object instruction comprises the execution result of the object instruction; or the accelerator module is further configured to store the processing result of the object instruction into a memory coupled with the plurality of processor cores, and the execution result message of the object instruction comprises a storage address of the execution result of the object instruction in the memory.

[0011] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores comprises: an instruction fetch module configured to fetch instructions; a decode module configured to decode the fetched instructions into one or more micro-operations (MOPs); and an issue module configured to issue the one or more MOPs to a processor core pipeline or the accelerator module.

[0012] For example, a processor according to an embodiment of the present disclosure, wherein the one or more MOPs comprise: a read and fill MOP to read an instruction argument and fill an operand, and a load offload MOP to issue a workload to an accelerator engine performing the one or more MOPs.

[0013] For example, a processor according to embodiments of the present disclosure, wherein, in response to the accelerator engine being in a synchronous mode of operation with a corresponding processor core, the accelerator module is configured to return an execution status to the corresponding processor core in response to the object instruction completing execution in the accelerator module.

[0014] For example, a processor according to embodiments of the present disclosure, wherein the one or more MOPs further comprise a read response MOP to cause the at least one accelerator engine to return an execution status to a corresponding processor core.

[0015] For example, a processor according to embodiments of the present disclosure, wherein the accelerator module further comprises an arbiter coupled between the plurality of processor cores and the at least one accelerator engine and configured to arbitrate the object instructions received from the plurality of processor cores for assignment to a target accelerator engine of the at least one accelerator engine.

[0016] For example, a processor according to embodiments of the present disclosure, wherein the accelerator module further comprises a memory interface coupled with the at least one accelerator engine and comprising a Translation Lookaside Buffer (TLB), wherein the at least one accelerator engine shares the TLB.

[0017] For example, a processor according to embodiments of the present disclosure, wherein the TLB comprises one or more TLB entries, each of the one or more TLB entries comprising a processor core ID, the processor core ID identifying a processor core of the plurality of processor cores to which a current TLB entry belongs.

[0018] For example, a processor according to embodiments of the present disclosure, wherein each of the one or more TLB entries further comprises a process ID, the process ID identifying a process to which a current TLB entry belongs.

[0019] For example, a processor according to embodiments of the present disclosure, wherein each of the plurality of processor cores is further configured to send a TLB entry operation instruction to the accelerator module, the TLB entry operation instruction, when executed, causing the accelerator module to perform one or more of the following operations: invalidate all TLB entries, invalidate TLB entries having a particular process ID, invalidate TLB entries having a particular process ID and a particular Virtual Page Number (VPN), invalidate TLB entries having a particular processor core ID, invalidate TLB entries having a particular processor core ID and a particular process ID, invalidate TLB entries having a particular processor core ID, a particular process ID, and a particular VPN.

[0020] For example, a processor according to an embodiment of the present disclosure, wherein the accelerator module further comprises a data cache, and wherein each of the plurality of processor cores is further configured to send a cache operation instruction to the accelerator module, the cache operation instruction when executed causing the accelerator module to perform one or more of the following: invalidate all cache lines in the data cache; invalidate one or more cache lines in the data cache; flush all cache lines in the data cache; and flush one or more cache lines in the data cache.

[0021] For example, a processor according to an embodiment of the present disclosure, wherein the at least one accelerator engine comprises a control register configured to store the TLB entry operation instruction and the cache operation instruction.

[0022] For example, a processor according to an embodiment of the present disclosure, wherein the accelerator module further comprises a page table walker (PTW) independent of the plurality of processor cores, wherein the accelerator module is further configured to, in response to a miss occurring at the TLB by the at least one accelerator engine, complete a page table access using the independent PTW.

[0023] For example, a processor according to an embodiment of the present disclosure, wherein the accelerator module further comprises a PTW router connected to a PTW in at least a portion of the plurality of processor cores, the object instruction further comprising a processor core ID, wherein the accelerator module is further configured to, in response to a miss occurring at the TLB by the at least one accelerator engine, access the PTW in a corresponding processor core based on the processor core ID using the PTW router to complete a page table access.

[0024] For example, a processor according to an embodiment of the present disclosure, wherein each of the at least one accelerator engine comprises: a fetch front-end module configured to decode the object instruction received from the arbiter; one or more back-end execution modules configured to execute the object instruction decoded by the fetch front-end module; a memory interface arbiter module arbitrating access memory requests of the one or more back-end execution modules; a completion unit module configured to submit a processing result of the object instruction.

[0025] For example, a processor according to an embodiment of the present disclosure, wherein the fetch front-end module comprises a load offload buffer configured to store object instruction parameters and operands.

[0026] According to at least one embodiment of the present disclosure, an electronic device is provided, comprising the above processor.

[0027] According to at least one embodiment of the present disclosure, an instruction processing method is provided, comprising: receiving, by a plurality of processor cores, an instruction stream to be executed, wherein the instruction stream comprises a first type of instruction and a second type of instruction different from the first type of instruction; processing, by the plurality of processor cores, respectively, the first type of instruction in the corresponding instruction stream; dispatching, by the plurality of processor cores, respectively, an object instruction belonging to the second type of instruction in the instruction stream processed by itself to an accelerator module for execution, and receiving an execution result message of the object instruction from the accelerator module, wherein the accelerator module comprises at least one accelerator engine configured to execute the second type of instruction, and the accelerator module is coupled to and shared by the plurality of processor cores. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above aspects and other aspects, features and advantages of certain embodiments of the present disclosure will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which:

[0029] FIG. 1A is a schematic diagram of a processor according to at least one embodiment of the present disclosure; FIG. 1B is a schematic diagram of an example of a processor core according to at least one embodiment of the present disclosure;

[0030] FIG. 2 is a schematic diagram of a processor according to at least one embodiment of the present disclosure;

[0031] FIG. 3 is a schematic diagram of data interaction between a processor core and an accelerator module according to at least one embodiment of the present disclosure;

[0032] FIG. 4 is a schematic diagram of a MOP according to at least one embodiment of the present disclosure;

[0033] FIG. 5 is a schematic diagram of access of an accelerator engine to a TLB and a PTW router according to at least one embodiment of the present disclosure;

[0034] FIG. 6 is a schematic diagram of operation of a processor core to a TLB and an optional data cache in an accelerator module according to at least one embodiment of the present disclosure;

[0035] FIG. 7 is a schematic diagram of a structure of an accelerator module according to at least one embodiment of the present disclosure;

[0036] FIG. 8 is an instruction processing method according to at least one embodiment of the present disclosure; and

[0037] FIG. 9 is an electronic device comprising a processor according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Before undertaking a detailed description of the principles of the disclosure in the present disclosure, it can be advantageous to set forth definitions of certain words and phrases used throughout this disclosure. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and / or. The phrase "associated with," as well as derivatives thereof, means any of the following: includes, includes in, interconnected with, contains, contains in, connected with or to, coupled with or to, communicates with, cooperates with, interleave, is proximate to, is bound to or with, has, has a property of, has a relationship with, or the like. The term "controller" means any device, system or part thereof that controls at least one operation. Such a controller can be implemented in hardware or a combination of hardware and software and / or firmware. The functionality associated with any particular controller can be centralized or distributed, whether locally or remotely. The phrase "at least one of," when used with respect to a list of items, means that a different combination of one or more of the listed items can be used and only one item in the list can be necessary. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0039] Definitions for other certain words and phrases used throughout this disclosure are provided throughout this disclosure. Those of ordinary skill in the art will understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0040] The principles of the disclosure in the present disclosure are described below with reference to various embodiments of the disclosure in the drawings, which are merely illustrative and should not be construed as limiting the scope of the disclosure in any way. Those of ordinary skill in the art will understand that the principles of the disclosure can be implemented in any appropriately arranged system or device. In some cases, the actions described in the specification can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain implementations, multi-tasking and parallel processing can be advantageous.

[0041] The accelerator units integrated in the CPU are generally divided into two types, i.e., CPU core internal accelerator and CPU core external accelerator, according to the connection relationship with the CPU core. The design feature of the CPU core internal accelerator can be that the CPU core internal accelerator uses the same instruction set architecture (ISA) as the CPU, and the CPU determines whether to dispatch the instruction to the accelerator for execution or to use the ordinary CPU arithmetic and logic unit (ALU) for execution according to the instruction code. The design feature of the CPU core external accelerator can be that the CPU core external accelerator is connected with the CPU core through an IO bus (for example, peripheral component interconnect express (PCIE) and the like), and the CPU operates the accelerator to perform calculation by reading and writing the IO address of the accelerator.

[0042] Due to the close combination with the CPU pipeline, the CPU core internal accelerator is generally in a one-to-one relationship with the CPU core (i.e., one CPU core is matched with one accelerator). For a multi-core CPU chip, if there are multiple types of accelerators, it is generally required that each CPU core is integrated with multiple types of accelerators of the same combination. However, in practice, most of the CPU workloads can not require all the CPU cores to run the same type of acceleration calculation task, which causes the utilization efficiency of a large number of accelerators to be relatively low. In addition, if each core of the multi-core CPU is integrated with multiple types of accelerators of different combinations according to the use requirement (for example, the type of CPU workload), the problem of multi-core heterogeneity can be caused, which brings challenges to software development / deployment and migration, and leads to the increase of development / deployment and migration costs.

[0043] For the CPU core external accelerator, although such an accelerator based on the IO bus connection mode can realize function sharing through the driver mode, the IO bus connection mode can have the problem of large load offloading overhead. In particular, under some workloads with small granularity, the efficiency of the CPU core external accelerator can be significantly reduced.

[0044] Modern multi-core CPUs generally package several (e.g., 4 to 8, etc.) CPU cores along with their attached Level 1 data cache (L1D$), Level 2 cache (L2$), Level 3 cache (L3$), etc. into a module called Core-Cluster for implementation and performance considerations. Several CPU cores in a Core-Cluster can generally share the L2$ or L3$. Several identical Core-Clusters can be connected together by using an internal interconnect to collectively form the overall multi-core CPU system.

[0045] The present disclosure provides a processor, comprising: a plurality of processor cores, wherein each of the plurality of processor cores is configured to execute a first type of instruction; and an accelerator module comprising at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction, wherein the accelerator module is coupled to and shared by the plurality of processor cores, and wherein each of the plurality of processor cores dispatches object instructions belonging to the second type of instruction in an instruction stream processed by itself to the accelerator module for execution and receives execution result messages of the object instructions from the accelerator module.

[0046] The processor according to the present disclosure can solve or mitigate the problem that it is difficult to share accelerator engines of the same or different functions among cores in a Core-Cluster. For example, in many application scenarios, the accelerators (e.g., types and numbers of accelerator engines) used by CPU loads of different types of CPU cores are different. However, due to the static binding manner between CPU cores and accelerators, the same type of accelerator engine must be integrated in each CPU core, which causes the problem that the utilization rate of accelerator engines is low in most cases.

[0047] The processor according to the present disclosure can solve or mitigate the problem that it is difficult to share accelerator engines of the same or different functions among cores in a Core-Cluster. For example, in many application scenarios, the accelerators (e.g., types and numbers of accelerator engines) used by CPU loads of different types of CPU cores are different. However, due to the static binding manner between CPU cores and accelerators, the same type of accelerator engine must be integrated in each CPU core, which causes the problem that the utilization rate of accelerator engines is low in most cases.

[0048] FIG. 1A is a schematic diagram of a processor according to at least one embodiment of the present disclosure; and FIG. 1B is a schematic diagram of an example of a processor core according to at least one embodiment of the present disclosure.

[0049] As shown in FIG. 1A, the processor 100 can include a plurality of processor cores 111, 112, …, 11n and an accelerator module 120.

[0050] The plurality of processor cores 111-11n can be components of the processor 100 that execute instructions. Each of the plurality of processor cores 111-11n can independently execute program code while handling different tasks or threads. The plurality of processor cores 111-11n can improve the parallel processing capabilities of the processor, enabling the computer to perform multiple tasks or more complex calculations more quickly. Each of the plurality of processor cores 111-11n can execute first-type instructions, such as instructions executed by the processor core's own pipeline, including but not limited to arithmetic logic instructions (e.g., add, subtract, multiply, divide, AND, OR, NOT, XOR, etc.), data transfer instructions (e.g., load, store, input, output, etc.), control flow instructions (e.g., unconditional jump, subroutine call and return, etc.), string handling instructions (e.g., compare, move, search string, etc.), floating point operation instructions (e.g., arithmetic operations for floating point numbers such as add, subtract, multiply, divide, square root, etc.), privileged instructions (e.g., for operating system level tasks such as interrupt control, virtual memory management, etc.), and the like. The plurality of processor cores 111-11n can form a core cluster 110.

[0051] Figure IB illustrates a pipeline of an exemplary processor core, with the arrowed dashed lines indicating redirected instruction flow. As shown in Figure IB, a processor core (e.g., a CPU core) of a single-core processor or a multi-core processor improves instruction level parallelism through pipelining. Inside the processor core, there are multiple stages of pipelining, such as program counter (PC) fetch from various sources, followed by branch prediction, instruction fetch, decode, dispatch and rename, execute, retire / complete, etc. Wait queues are provided between stages as needed, which are typically first-in-first-out (FIFO) queues. For example, a branch prediction (BP) FIFO queue is provided after the branch prediction unit to store branch prediction results; an instruction cache (IC) FIFO is provided after the instruction fetch unit to cache fetched instructions; a decode (DE) FIFO is provided after the decode unit to cache decoded instructions; and a retire (RT) FIFO is provided after the dispatch and rename unit to cache instructions waiting for retirement after execution. The pipeline of the processor core also includes an instruction queue to cache instructions waiting for execution after dispatch and rename. To support high operating frequencies, each stage of pipelining can include multiple stages (clock cycles). Although each stage performs limited operations, this allows each clock cycle to be as short as possible, thereby improving the operating frequency of the CPU and the performance of the CPU core. Each stage can also improve the performance of the processor core by accommodating more instructions (i.e., superscalar technology).

[0052] The processor core translates each architectural instruction into one or more micro-ops (mops) within the micro-architecture, each of which performs limited operations, thereby allowing each stage to be very short to improve the operating frequency of the processor core. For example, a memory load instruction can be translated into an address generation micro-op and a memory read micro-op, with the second micro-op dependent on the result of the first micro-op, so that the first micro-op is executed before the second micro-op. The micro-ops include multiple micro-architecture dependent fields to pass relevant information between stages.

[0053] Speculative execution is another technique to improve processor performance. This technique executes instructions following a given instruction before the given instruction is completed. Branch prediction unit (branch predictor) in the front end of the processor core predicts the jump direction of branch instructions, pre-fetches and executes instructions in the predicted direction; another technique of speculative execution is to execute a memory read instruction before the addresses of all preceding memory write instructions are obtained. Speculative execution further improves instruction-level parallelism, thereby greatly improving the performance of the processor core. When a speculative execution error occurs, such as a branch prediction error or a write instruction before a memory read instruction overwrites the same address, all instructions in the pipeline after the error instruction need to be flushed, and then the program jumps to the error point for re-execution to ensure the correctness of program execution. To support speculative execution, the microarchitecture of the processor core also needs to support an architectural register recovery mechanism to ensure that the architectural register always has the correct value during speculative execution.

[0054] An operating system usually needs to support multiple processes running simultaneously while using the CPU. To simplify multi-process management and enhance security, an application uses a complete virtual address, such as a 32-bit addressing application that has a maximum of 232 = 4 GB of virtual address space available for use. When the program runs, these virtual addresses are mapped to multiple memory pages, each with its own physical storage address. When the application program accesses instructions and data, the virtual address of the instructions and data must be translated into a physical address, and the legality of the application program's access to the page must be detected, and then the corresponding data is obtained from the memory or cache and delivered to the CPU core. The process of translating virtual addresses into physical addresses is called address translation. The mapping of virtual addresses to physical addresses is stored in tables in memory, and accessing these tables in memory also requires hundreds of clocks. To reduce these memory accesses, the CPU core uses multiple levels of cache to store recently used mappings. These specific caches are called translation lookaside buffers or table lookaside buffers (TLB). When a TLB lookup is missing or a miss occurs, the CPU core needs to browse the page table page through the page table walker (PTW) to find the required page table entry (PTE) for address translation.

[0055] The pipeline of the processor core of embodiments of the present disclosure is not limited to the example shown in FIG. 1A, and part of the components can be omitted or other components can be added as needed. Embodiments of the present disclosure do not limit the architecture of the processor core (such as x86, ARM, MIPS, RISC-V, etc.) and the instruction set being executed.

[0056] The accelerator module 120 can be coupled with and shared by the plurality of processor cores 111-11n. The accelerator module 120 can improve the performance or energy efficiency of the processor cores 111-11n in performing certain computing tasks or in certain scenarios, thereby improving the performance of the overall processor 100. For example, in some scenarios, not all processes running on the processor cores in a core cluster need to access the accelerator engine. That is, only individual processes running on the processor cores in a core cluster can need to access the accelerator engine. In such a case, it can be wasteful if each processor core is statically bound to an accelerator hardware module.

[0057] The accelerator module 120 can include at least one accelerator engine 121. Although only one accelerator engine 121 is shown in FIG. 1A, example embodiments can include more accelerator engines. The at least one accelerator engine 121 can include multiple accelerator engines of the same or different types. The accelerator engines can include, but are not limited to, application-specific integrated circuits (ASICs), graphics processing units (GPUs), tensor processing units (TPUs), neural network processing units (NPUs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), etc. The at least one accelerator engine 121 can be configured to execute second-type instructions that are different from the first-type instructions. The second-type instructions are instructions that can be executed by the accelerator module, such as, but not limited to, encryption and decryption, hash computation, compression and decompression, etc.

[0058] The plurality of processor cores 111-11n can respectively dispatch object instructions 131 belonging to the second-type instructions in the instruction streams processed by the plurality of processor cores 111-11n to the accelerator module 120 for execution. For example, the plurality of processor cores 111-11n can respectively dispatch object instructions 131 belonging to the second-type instructions to at least one accelerator engine 121 in the accelerator 120 for execution. The plurality of processor cores 111-11n can receive execution result messages of the object instructions from the accelerator module 120. For example, the plurality of processor cores 111-11n can receive execution result messages of the object instructions from at least one accelerator engine 121 in the accelerator module 120.

[0059] The plurality of processor cores 111-11n can share at least one accelerator engine 121 that is functionally the same or different. The types and number of accelerator engines 121 can be configured according to the application field that the CPU is facing, and there is no direct binding relationship between the number of the plurality of processor cores 111-11n.

[0060] In one embodiment, during the operation of the CPU, the accelerator module 120 can be dynamically coupled to the plurality of processor cores 111-11n, receive the same or different object instructions belonging to the second type of instructions from one or more of the processor cores 111-11n, for example, the same or different object instructions can be received from the plurality of processor cores in the same operation cycle (clock cycle) or different operation cycles. For example, at least one accelerator engine 121 in the accelerator module 120 can be dynamically coupled to the plurality of processor cores 111-11n.

[0061] For example, in response to the load of the processor 100 being the first type of load, the at least one accelerator engine 121 can receive an object instruction from one of the plurality of processor cores 111-11n (for example, the processor core 111) and send an execution result message of the object instruction to the processor core. In response to the load of the processor 100 changing from the first type of load to the second type of load, the at least one accelerator engine 121 can change to receive an object instruction from another one of the plurality of processor cores 111-11n (for example, one of the processor cores 112-11n) and send an execution result message of the object instruction to the another processor core.

[0062] In this way, the accelerator engines 121 can be dynamically allocated and bound to the plurality of processor cores 111-11n, thereby improving the utilization of the accelerator engines in different application scenarios.

[0063] FIG. 2 is a schematic diagram of a processor according to at least one embodiment of the present disclosure.

[0064] As shown in FIG. 2, the processor 2000 can include a plurality of processor cores 2010, 2020, …, 20n0and an accelerator module 2300 and a third level cache L3$2200 shared by the processor cores 2010, 2020, …, 20n0.

[0065] The plurality of processor cores 2010, 2020, …, 20n0may constitute a core cluster. Each core cluster can have 4-8 processor cores, that is, the number of the plurality of processor cores 2010, 2020, …, 20n0may be 4-8, but embodiments of the present disclosure are not limited thereto, and each core cluster can include more or fewer processor cores.

[0066] Although n processor cores 2010, 2020, …, 20n0(n is a natural number greater than 1) are shown in FIG. 2, this is merely an example, and the connection topology of the processor cores and the accelerator module in the core cluster can be more flexible. For example, one accelerator module can be shared by every two processor cores. For another example, more or fewer processor cores can share one or more accelerator modules, etc.

[0067] Although FIG. 2 illustrates the structure of the plurality of processor cores 2010, 2020,..., 20n0 as being the same, one skilled in the art can understand that one or more of the plurality of processor cores 2010, 2020,..., 20n0 can have different structures.

[0068] Each processor core can identify whether a current instruction in a respective instruction stream that the processor core processes is a first type of instruction or a second type of instruction. For example, each processor core can identify whether a current instruction to process is a processor core instruction or an accelerator instruction. In response to identifying that the current instruction is a processor core instruction, each processor core can dispatch the current instruction to its own pipeline. In response to identifying that the current instruction is an accelerator instruction, each processor core can dispatch the current instruction to the accelerator module 2300 as an object instruction.

[0069] The plurality of processor cores 2010, 2020,..., 20n0 can include fetch modules 2011, 2021,..., 20n1, respectively. Each of the fetch modules 2011, 2021,..., 20n1 can be configured to fetch instructions. For example, each fetch module can find a location of an instruction for the processor 2000 to execute in a memory through an address bus and fetch the instruction from the memory. Each fetch module can transmit the fetched instruction to a respective decode module.

[0070] The plurality of processor cores 2010, 2020,..., 20n0 can include decode modules 2012, 2022,..., 20n2, respectively. Each of the decode modules 2012, 2022,..., 20n2 can be configured to decode a fetched instruction into one or more MOPs. For example, each decode module can decode an instruction from a respective fetch module, identify a type of the instruction, and an operand required for the instruction.

[0071] The plurality of processor cores 2010, 2020,..., 20n0 can include dispatch modules 2013, 2023,..., 20n3, respectively. Each of the dispatch modules 2013, 2023,..., 20n3 can be configured to dispatch one or more MOPs to a processor core pipeline or an accelerator module, specific details of which are referred to below in relation to FIG. 4.

[0072] Each dispatch module can dispatch one or more MOPs to the accelerator module 2300 in accordance with the one or more MOPs from a respective decode module being MOPs for the accelerator module.

[0073] In one embodiment, each processor core can be configured to cause object instructions to be dispatched to the accelerator module 2300 to enter a dispatch queue (not shown in the figure) of the dispatch module to wait for dispatch. Each processor core can allocate an entry in a reorder buffer ROB for the object instructions. In response to the object instructions becoming the oldest instructions in the ROB, each processor core can dispatch the object instructions to the accelerator module 2300. The object instructions becoming the oldest instructions in the ROB means that the instructions before the object instructions have already executed and committed, so there will be no execution error for the object instructions due to instruction or data dependencies.

[0074] Alternatively or additionally, in another embodiment, each processor core can be configured to cause object instructions to enter a dispatch queue to wait for dispatch. Each processor core can wait for a reorder buffer ROB to empty. In response to the ROB emptying, each processor core can dispatch the instructions to the accelerator module 2300. The reorder buffer ROB emptying likewise means that the instructions before the object instructions have already executed and committed, so there will be no execution error for the object instructions due to instruction or data dependencies.

[0075] Each dispatch module can dispatch one or more MOPs to a respective issue module according to the one or more MOPs being MOPs for the processor core pipeline from the respective decode module.

[0076] The plurality of processor cores 2010, 2020,..., 20n0 can include issue modules 2014, 2024 (not shown in Figure 2),..., 20n4, respectively. Each of the issue modules 2014, 2024,..., 20n4 can fetch instructions from the dispatch queue of the processor core pipeline and distribute to subsequent modules for execution. For example, each issue module can fetch instructions from the dispatch queue of the processor core pipeline from the respective dispatch module and distribute to respective LSU modules and ALU modules.

[0077] The plurality of processor cores 2010, 2020,..., 20n0 can each include a load and store unit (LSU) module 2015, 2025 (not shown in FIG. 2),..., 20n5. Each of the LSU modules 2015, 2025,..., 20n5 can receive and execute instructions related to loads and stores. Instructions related to loads and stores allow the processor 2000 to access data stored in memory. In executing load and store operations, each LSU module can generate a virtual address. The virtual address can be translated to a physical address through an address translation process (e.g., through a respective TLB or PTW) to read or write data from physical memory. Each LSU module can load data from memory into a register of the processor 2000, or store data from a register of the processor 2000 back to memory. Each LSU module can send its execution results to a respective completion module.

[0078] The plurality of processor cores 2010, 2020,..., 20n0 can each include a separate level 1 data cache (e.g., L1D$ 2018, L1D$ 2028 (not shown in FIG. 2),..., L1D$ 20n8) and a level 2 cache (e.g., L2$ 2029, L2$ 2029 (not shown in FIG. 2),..., L2$ 20n9). The plurality of processor cores 2010, 2020,..., 20n0 can share a level 3 cache (L3$) 2200 via a memory coherence bus 2100. Each level 1 data cache can include a translation lookaside buffer (TLB) (e.g., TLB 20181, TLB 20281,..., TLB 20n81) and a page table walker (PTW) (e.g., PTW 20182, PTW 20282,..., PTW 20n82).

[0079] Each TLB can be used to store a copy of the page table entries that are currently most likely to be accessed by the respective processor core, which include mapping information of virtual addresses to physical addresses. When the respective processor core needs to access a certain virtual address, the processor core can first check whether the mapping information of the address already exists in the TLB. If it exists (i.e., a hit), the processor core can directly use the physical address in the TLB to access the memory, thereby avoiding accessing the page table in the memory directly, reducing the number of memory accesses, and improving the speed of address translation.

[0080] When there is no mapping information of a certain virtual address in the TLB (i.e., a TLB miss), the processor core can access the page table in the memory through the corresponding PTW to obtain the physical address corresponding to the virtual address. The PTW can find the matching virtual address by traversing the page table, and return the found physical address to the corresponding processor core. The PTW can also find the corresponding item from the page table and backfill to the TLB.

[0081] The plurality of processor cores 2010, 2020, …, 20n0 can respectively include arithmetic and logic unit (ALU) modules 2016, 2026 (not shown in FIG. 2), …, 20n6. Each of the LSU modules 2016, 2026, …, 20n6 can perform basic arithmetic and logic operations, etc. according to instructions received from the corresponding issue module. Each ALU module can send its execution result to the corresponding completion module.

[0082] The plurality of processor cores 2010, 2020, …, 20n0 can respectively include completion modules 2017, 2027 (not shown in FIG. 2), …, 20n7. Each of the completion modules 2017, 2027, …, 20n7 can mark the corresponding instruction as completed in the reorder buffer (ROB). Each completion module can also write the execution result of the corresponding instruction to the ROB for submission.

[0083] The processor 2000 can include an accelerator module 2300. The plurality of processor cores 2010, 2020, …, 20n0 can share an instruction set architecture (ISA) front end with the accelerator module 2300, e.g., including instruction fetching, decoding, and issuing. The accelerator module 2300 can include an arbiter 2310. The arbiter 2310 can be coupled between the plurality of processor cores and the accelerator engines. Since the accelerator module 2300 is shared by the plurality of processor cores, the arbiter 2310 of the accelerator module 2300 can arbitrate object instructions received from the plurality of processor cores to assign to a target accelerator engine in the accelerator engines, thereby improving the allocation and utilization efficiency of computing resources in the accelerator module. After an object instruction is assigned to a target accelerator engine by the arbiter 2310, the object instruction can start execution in the target accelerator engine. If an object instruction is not successfully arbitrated, the corresponding processor core can wait until the object instruction can be assigned to a suitable accelerator engine by the arbiter 2310.

[0084] The accelerator module 2300 can include a plurality of accelerator engines 2321, 2322,..., 232m, where m is a natural number greater than 0. The number and type of accelerator engines included in the accelerator module 2300 can be flexibly configured according to the usage requirement of the processor. The description of the accelerator engines can refer to the description of FIG. 1A, which is not repeated here.

[0085] The accelerator module 2300 can include a memory interface 2350 independent of the plurality of processor cores to access the memory. The accelerator module 2300 can complete the address translation from a virtual address to a physical address independently of the plurality of processor cores. The memory interface 2350 can be coupled with the accelerator engines 2321, 2322,..., 232m and include a TLB 2351. The TLB 2351 can be shared by the accelerator engines 2321, 2322,..., 232m.

[0086] When a corresponding accelerator engine needs to access a certain virtual address, the accelerator engine can first check whether there is mapping information of the address in the TLB. If there is (i.e., hit), the accelerator engine can directly use the physical address in the TLB to access the memory. The specific details of the page table entry in the TLB 2351 can refer to the description of FIG. 5 below.

[0087] The accelerator module 2300 can include a PTW router 2340. When a TLB miss occurs, the page table access can be completed using the PTW in the processor core to which the accelerator engine is bound. In this case, a separate PTW can not be configured in the accelerator module 2300. For example, the corresponding accelerator engine can access the page table in the memory through the PTW router 2340 to obtain the physical address corresponding to the virtual address. When the processor core dispatches instructions to the accelerator module, the process ID of the current process and the processor core ID of the current processor core in the core cluster can be carried in the dispatched instructions. The corresponding accelerator engine can use the PTW router 2340 when a TLB miss occurs and find the PTW in the corresponding processor core according to the processor core ID, so as to obtain the required page table entry.

[0088] The memory interface 2350 can include an optional PTW 2352. The accelerator module 2300 can use the PTW 2352 to independently complete the access of the page table without accessing the PTW in the processor core. For example, in the case that the accelerator module 2300 includes an independent PTW 2352, when a TLB miss occurs, the accelerator engine can access the page table in the memory through the PTW 2352 to obtain the physical address corresponding to the virtual address. By independently configuring the PTW 2352 for the accelerator module 2300, the wires required for the PTW router 2340 to access the processor core can be omitted. Thus, the volume of the processor 2000 can be reduced.

[0089] In at least one embodiment, the accelerator module 2300 can include an optional data cache 2360. For example, in the case that the accelerator module 2300 needs to improve the memory access performance, the optional data cache 2360 can be configured. In the case that an independent data cache 2360 is not needed, the accelerator module 2300 can directly interface to the third level cache L3$ shared by the plurality of cores in the core cluster through the memory interface 2350.

[0090] The accelerator module 2300 can include a completion module 2330. The completion module 2330 can mark the corresponding instruction as completed in the reorder buffer ROB. The completion module 2330 can also send the execution result of the corresponding instruction to the corresponding completion module in the completion module 2017, 2027, …, 20n7. The details of the data interaction between the accelerator module 2300 and the processor core can refer to the description of FIG. 3 below.

[0091] FIG. 3 is a schematic diagram of the data interaction between a processor core and an accelerator module according to at least one embodiment of the present disclosure.

[0092] FIG. 4 is a schematic diagram of a MOP according to at least one embodiment of the present disclosure.

[0093] As shown in FIG. 3, the processor core 3100 can interact with the accelerator module 3200. The accelerator module 3200 can include an arbiter 3210 and accelerator engines 3221, 3222, …, 322m. The specific description of the processor core, the accelerator module, the arbiter, and the accelerator engine can refer to the description in FIG. 1A and FIG. 2, which will not be repeated here.

[0094] The processor core 3100 can send handshake and status signals to the accelerator module 3200 and can receive handshake and status signals from the accelerator module 3200. The handshake and status signals can include valid, ready, busy, etc. The handshake and status signals can coordinate and synchronize operations between the processor core 3100 and the accelerator module 3200 to ensure correctness and safety of data transfer, to improve reliability and correctness of data transfer.

[0095] The processor core 3100 can send a load offload instruction to the accelerator module 3200. The load offload instruction can include an instruction code and operands required for execution of the instruction. The processor core 3100 can receive a load offload response from the accelerator module 3200. The load offload response can include an instruction execution status and optionally an instruction execution result. For example, the accelerator module 3200 can return a processing result of an object instruction to a corresponding processor core, and the execution result message of the object instruction can include the execution result of the object instruction. For another example, the accelerator module 3200 can also store the processing result of the object instruction into a memory coupled with the plurality of processor cores, and the execution result message of the object instruction can include a storage address of the execution result of the object instruction in the memory. The instruction execution status can indicate whether the execution of the object instruction is successful or whether there is an exception to be processed.

[0096] From the perspective of ISA, all instructions sent by the processor core 3100 to the accelerator module 3200 can be split into one or more MOPs in the decoding stage. One or more MOPs are described with reference to FIG. 4.

[0097] The object instruction in FIG. 4 requires 4 instruction parameters, e.g., param1, param2, param3, param4. The processor core can use 4 general purpose registers (GRP) including register R1, R2, R3, and R4 to buffer the 4 instruction parameters param1-param4, respectively. The instructions “mov R1, param1”, “mov R2, param2”, “mov R3, param3”, and “mov R4, param4” can be the first type of instructions dispatched to the processor core pipeline to cause the processor core to buffer the 4 instruction parameters param1-param4 to the 4 general purpose registers R1-R4.

[0098] An object instruction "acc_offload R1" dispatched to the accelerator module can be used to invoke the acceleration function of the accelerator module. The object instruction "acc_offload R1" can be divided into four MOPs including MOP1, MOP2, MOP3 and optional MOP4. MOP1 and MOP2 can be read and fill MOPs. The read and fill MOPs can be used to read the object instruction parameters and fill the operands. For example, the read and fill MOPs can move the 4 instruction parameters in GPRs to the load offload buffer of the accelerator module. MOP3 can be a load offload MOP. The load offload MOP can issue a workload to the accelerator engine executing one or more MOPs to start the accelerator engine. The optional MOP4 can be a read response MOP. The read response MOP makes the corresponding accelerator engine return the instruction execution status to the processor core. After the instruction execution is completed, the result obtained by the accelerator can be written into the general register R1 for subsequent use, but the present disclosure is not limited thereto, and the result can also be written into other general registers.

[0099] Returning to FIG. 3, in one embodiment, in the case where the processor core 3100 and the corresponding accelerator engine in the accelerator module 3200 are in the synchronous operation mode, the processor core 3100 can not send a read response MOP to the accelerator module 3200. The accelerator engine can return the execution status to the corresponding processor core 3100 in response to the end of the execution of the object instruction in the accelerator module.

[0100] In another embodiment, in the case where the processor core 3100 and the corresponding accelerator engine in the accelerator module 3200 are in the asynchronous operation mode, the processor core 3100 can send a read response MOP to the accelerator module 3200. The read response MOP can synchronize the processor core 3100 with the corresponding accelerator engine and process the exception status returned by the corresponding accelerator engine. For example, if the execution of the object instruction in the accelerator module 3200 occurs an exception, the accelerator module 3200 can save the exception status internally. The exception status can be reported back to the processor core 3100 when the read response MOP is executed. In response to receiving the exception status sent by the accelerator module 3200, the processor core 3100 can jump into the exception handling program. When the exception handling is completed, the entire accelerator instruction (including all split MOPs) can be re-executed. When the read response MOP is re-executed, the instruction execution result can be correctly executed and committed.

[0101] FIG. 5 is a schematic diagram of the access mode of the accelerator engine to the TLB and the PTW router according to at least one embodiment of the present disclosure.

[0102] To improve the utilization efficiency of TLBs in the accelerator module, a centralized TLB 520 is employed in the entire accelerator module. That is, all TLB entries in the TLB 520 can be dynamically shared and allocated among the plurality of accelerator engines 511-51m. Each TLB entry can include:

[0103] Each TLB entry in the TLB 520 can include a processor core ID, a process ID, and a virtual page number (VPN). The processor core ID can identify the processor core to which the current TLB entry belongs among the plurality of processor cores. The process ID can identify the process to which the current TLB entry belongs. In one embodiment, the process ID can be an address space identifier (ASID) in the TLB entry to identify which virtual address space the TLB entry belongs to. The VPN can refer to a virtual address page table index number in the TLB entry of the processor.

[0104] When a processor core dispatches an instruction to an accelerator engine 511-51m in the accelerator module, the process ID of the current process and the processor core ID of the current processor core in the core cluster can be carried in the dispatched instruction. When a corresponding accelerator engine needs to access a certain virtual address, the accelerator engine can first check whether there is mapping information of the address in the TLB entries in the TLB 520 according to the process ID and the processor core ID, etc. If there is (i.e., a hit), the accelerator engine can directly use the physical address in the TLB 520 to access the memory.

[0105] The corresponding accelerator engine can use the PTW router 530 and find the PTW in the corresponding processor core (e.g., the PTW of the processor cores 541-processor cores 54n) according to the processor core ID when a TLB miss occurs, so as to obtain the required page table entry.

[0106] There is no fixed correspondence between the accelerator engines 511-51m in the accelerator module and the processor cores 541-processor cores 54n in the core cluster. The accelerator module can include m accelerator engines 511-51m. Since these accelerator engines are independent of each other and have concurrent memory access requirements, the TLB 520 also needs to provide m read-write ports accordingly. Since each of the m accelerator engines 511-51m can receive object instructions from each of the n processor cores 541-processor cores 54n, the PTW router 530 is needed to find the PTW connection path of the corresponding processor core when a TLB miss occurs.

[0107] FIG. 6 is a schematic diagram of the operation of TLBs in an accelerator module and optional data cache by processor cores, according to at least one embodiment of the present disclosure. Details regarding processor cores 611-61n, at least one accelerator engine 620, memory interface 630, TLBs 631, PTW 632, optional data cache 640, and L3$ can refer to the specific descriptions in FIG. 2, which are not repeated here.

[0108] In the case where the accelerator module and the processor cores are in a synchronous execution relationship, the control of TLBs 631 and optional data cache 640 in the accelerator module needs to be synchronized with the corresponding processor cores. TLBs 631 and optional data cache 640 in the accelerator module need to be managed and controlled by the corresponding processor cores.

[0109] Each of the plurality of processor cores 611-61n can send a TLB entry operation instruction to the accelerator module. The TLB entry operation instruction, when executed, can cause the accelerator module to perform one or more of the following operations: invalidate all TLB entries, invalidate TLB entries with a particular process ID, invalidate TLB entries with a particular process ID and a particular VPN, invalidate TLB entries with a particular processor core ID, invalidate TLB entries with a particular processor core ID and a particular process ID, and invalidate TLB entries with a particular processor core ID, a particular process ID, and a particular VPN.

[0110] In the case where the accelerator module includes optional data cache 640, each of the plurality of processor cores 611-61n can also send a cache operation instruction to the accelerator module. The cache operation instruction, when executed, can cause the accelerator module to perform one or more of the following operations: invalidate all cache lines in the data cache; invalidate one or more cache lines in the data cache; flush all cache lines in the data cache; and flush one or more cache lines in the data cache.

[0111] FIG. 7 is a structural schematic diagram of an accelerator module, according to at least one embodiment of the present disclosure. Components in accelerator module 7000 in FIG. 7 that are the same as in FIG. 2 are not described again.

[0112] Accelerator module 7000 in FIG. 7 can also include accelerator engines 7200, 7300, but the present disclosure is not limited thereto, and accelerator module 7000 can include more accelerator engines. The structures of the accelerator engines can be similar. For example, accelerator engine 7200 can include control registers 7210, fetch front end 7220, back-end execution modules 7230, 7240, completion module 7250, memory interface arbiter 7260.

[0113] The control register 7210 can store the TLB entry operation instructions and the cache operation instructions described with reference to FIG. 6. For example, the memory core can configure the behavior of the accelerator engine 7200, 7300, etc. by reading and writing the control register 7210. These parameters are issued to the accelerator engine using MOP1 and MOP2 split by the “acc_offload R1” instruction described with reference to FIG. 4.

[0114] The fetch front-end module 7220 can decode the object instructions received from the arbiter 7100 and dispatch to one or more back-end execution modules for execution. In the accelerator engine, since there can be concurrent memory access demands from multiple back-end execution modules, the accelerator module 7000 includes a memory interface arbiter 7260 to arbitrate the memory access requests from the multiple back-end execution modules. As shown in FIG. 3, the object instructions can have variable-length instruction parameters, and the object instructions can be split into multiple MOPs by the decoding module of the processor core. Such design enables an object instruction to have the capability to describe multiple parallel operations. For example, an object instruction can describe two parallel matrix multiply-accumulate operations, which are split into two MOPs to enable parallel execution in the decoding stage.

[0115] The fetch front-end module 7220 can include a load offload buffer 7221. The load offload buffer 7221 can store the object instruction parameters and operands.

[0116] The one or more back-end execution modules 7230, 7240 can execute the object instructions decoded by the fetch front-end module 7220. Although two back-end execution modules 7230, 7240 are shown in FIG. 7, the accelerator engine 7200 can include more back-end execution modules. The back-end execution module 7230 can include a control unit 7231, a load unit 7232, an execution unit 7233, a store unit 7234, and a scratchpad 7235.

[0117] The control unit 7231 can perform the control flow of instructions and data. The load unit 7232 can read data from memory or other storage devices and prepare the data for use by other functional units (e.g., the execution unit 7233). The execution unit 7233 can perform various arithmetic and logical operations. The store unit 7234 can write the data processed by the execution unit 7233 back to memory or other storage devices. The scratchpad 7235 can be a cache area on the processor for storing temporary data.

[0118] FIG. 8 is a method of instruction processing according to at least one embodiment of the present disclosure. The method includes steps S802, S804, S806.

[0119] At step S802, a plurality of processor cores can receive an instruction stream to be executed, wherein the instruction stream comprises instructions of a first type and instructions of a second type different from the first type.

[0120] At step S804, the plurality of processor cores can process the instructions of the first type in the respective instruction streams.

[0121] At step S806, the plurality of processor cores can respectively dispatch an object instruction belonging to the second type of instructions in the instruction stream processed by the processor core to an accelerator module for execution, and receive an execution result message of the object instruction from the accelerator module, wherein the accelerator module comprises at least one accelerator engine configured to execute the second type of instructions, and the accelerator module is coupled to and shared by the plurality of processor cores.

[0122] The instruction processing method according to at least one embodiment of the present disclosure can further comprise dynamically coupling the accelerator module to the plurality of processor cores, and receiving the same or different object instructions belonging to the second type of instructions from the plurality of processor cores.

[0123] The instruction processing method according to at least one embodiment of the present disclosure can further comprise identifying, by each of the plurality of processor cores, whether a current instruction in the instruction stream is of the first type or of the second type. In response to the current instruction being of the first type, dispatching the current instruction to a pipeline of the processor core itself. In response to the current instruction being of the second type, dispatching the current instruction to the accelerator module as an object instruction by the processor core.

[0124] The instruction processing method according to at least one embodiment of the present disclosure can further comprise entering, by each of the plurality of processor cores, the object instruction into a dispatch queue to wait for dispatch, and allocating an entry in a ROB for the object instruction. In response to the object instruction becoming the oldest instruction in the ROB, dispatching the object instruction to the accelerator module by the processor core.

[0125] The instruction processing method according to at least one embodiment of the present disclosure can further comprise entering, by each of the plurality of processor cores, the object instruction into a dispatch queue to wait for dispatch, and waiting for the ROB to be empty. In response to the ROB being empty, dispatching the instruction to the accelerator module by the processor core.

[0126] The instruction processing method according to at least one embodiment of the present disclosure can further comprise returning, by the accelerator module, a processing result of the object instruction to the corresponding processor core, and the execution result message of the object instruction comprises the processing result of the object instruction. Alternatively or additionally, the processing result of the object instruction can be stored, by the accelerator module, into a memory coupled to the plurality of processor cores, and the execution result message of the object instruction comprises a storage address of the processing result of the object instruction in the memory.

[0127] The instruction processing method according to at least one embodiment of the present disclosure can further include obtaining, by an instruction fetch module of each of the plurality of processor cores, instructions; decoding, by a decode module of the processor core, the obtained instructions into one or more micro-operations (MOPs); and issuing, by an issue module of the processor core, the one or more MOPs to a processor core pipeline or an accelerator module.

[0128] The instruction processing method according to at least one embodiment of the present disclosure can further include reading, by the accelerator module and using a read and fill MOP of the one or more MOPs, instruction parameters and filling operands, offloading, by the accelerator module and using a load offload MOP of the one or more MOPs, a workload to an accelerator engine executing the one or more MOPs.

[0129] The instruction processing method according to at least one embodiment of the present disclosure can further include, in response to the accelerator engine being in a synchronous mode of operation with the corresponding processor core, returning, by the accelerator module, an execution status to the corresponding processor core in response to the object instruction completing execution in the accelerator module.

[0130] The instruction processing method according to at least one embodiment of the present disclosure can further include, by the accelerator module, using a read response MOP of the one or more MOPs to cause the at least one accelerator engine to return the execution status to the corresponding processor core.

[0131] The instruction processing method according to at least one embodiment of the present disclosure can further include arbitrating, by an arbiter of the accelerator module coupled between the plurality of processor cores and the at least one accelerator engine, object instructions received from the plurality of processor cores for assignment to a target accelerator engine of the at least one accelerator engine.

[0132] The instruction processing method according to at least one embodiment of the present disclosure can further include causing the at least one accelerator engine to share a TLB included in a memory interface of the accelerator module.

[0133] The instruction processing method according to at least one embodiment of the present disclosure can further include sending, by each of the plurality of processor cores, a TLB entry operation instruction to the accelerator module, causing the accelerator module to execute the TLB entry operation instruction to perform one or more of the following: invalidate all TLB entries, invalidate TLB entries having a particular process ID, invalidate TLB entries having a particular process ID and a particular virtual page number (VPN), invalidate TLB entries having a particular processor core ID, invalidate TLB entries having a particular processor core ID and a particular process ID, invalidate TLB entries having a particular processor core ID, a particular process ID, and a particular VPN.

[0134] The instruction processing method according to at least one embodiment of the present disclosure can further include sending, by each of the plurality of processor cores, the cache operation instruction to the accelerator module, and executing, by the accelerator module, the cache operation instruction to perform one or more of the following: invalidating all cache lines in the data cache; invalidating one or more cache lines in the data cache; flushing all cache lines in the data cache; and flushing one or more cache lines in the data cache.

[0135] The instruction processing method according to at least one embodiment of the present disclosure can further include storing, by a control register of the at least one accelerator engine, the TLB entry operation instruction and the cache operation instruction.

[0136] The instruction processing method according to at least one embodiment of the present disclosure can further include, in response to a miss occurring for the TLB by the at least one accelerator engine, completing, by the accelerator module, the page table walk using a separate PTW included in the accelerator module.

[0137] The instruction processing method according to at least one embodiment of the present disclosure can further include, in response to a miss occurring for the TLB by the at least one accelerator engine, routing, by the accelerator module, the page table walk using a PTW router included in the accelerator module to access a PTW in a corresponding processor core based on a processor core ID included in the object instruction.

[0138] The instruction processing method according to at least one embodiment of the present disclosure can further include decoding, by a fetch front-end module included in each of the at least one accelerator engine, the object instruction received from the arbiter; executing, by one or more back-end execution modules included in the accelerator engine, the object instruction decoded by the fetch front-end module; arbitrating, by a memory interface arbiter module included in the accelerator engine, access memory requests of the one or more back-end execution modules; and committing, by a completion unit module included in the accelerator engine, a processing result of the object instruction.

[0139] The instruction processing method according to at least one embodiment of the present disclosure can further include storing, by a load offload buffer included in the fetch front-end module, an object instruction parameter and an operand.

[0140] FIG. 9 is an electronic device including a processor according to at least one embodiment of the present disclosure.

[0141] As shown in FIG. 9, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 includes one or more computer program modules 921. The one or more computer program modules 921 are stored in the memory 920 and can be configured to be read and executed by the processor 910.

[0142] The memory 920 and the processor 910 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown). For example, the bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0143] The processor 910 can include the processor described above with reference to FIGS. 1A-7. For example, the electronic device can include a central processing unit (CPU), a digital signal processor (DSP), a graphic processing unit (GPU), or other forms of processing units having data processing and / or program executing capabilities, such as a field-programmable gate array (FPGA), etc. The processor 910 can be a general purpose processor or a special purpose processor, and can control other components in the electronic device 900 to perform desired functions.

[0144] For example, the memory 920 can include any combination of one or more computer program products, which can include various forms of computer-readable storage media, for example, volatile memory and / or non-volatile memory. For example, the volatile memory can include random access memory (RAM), cache, etc. The non-volatile memory can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 921 can be stored in the computer-readable storage media, and the processor 910 can execute the one or more computer program modules 921 to implement various functions of the electronic device 900. Various application programs and various data used by the application programs and various data generated by the application programs, etc. can also be stored in the computer-readable storage media.

[0145] For example, the electronic device 900 can further include an input device such as a camera, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device including, for example, a liquid crystal display, a speaker, a vibrator, etc.; a storage device including, for example, a magnetic tape, a hard disk (HDD or SDD), etc.; and a communication device such as a LAN card, a modem, etc. The communication device can allow the electronic device 900 to perform wireless or wired communication with other devices to exchange data, perform communication processing via a network such as the Internet. A driver is connected to the I / O interface as needed. A removable storage medium such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the driver as needed, so that a computer program read out from the same is installed in the storage device as needed.

[0146] For example, the electronic device 900 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, such as a USB interface, a lighting interface, and the like. The communication device can communicate with networks and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any of a plurality of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0147] The electronic device 900 may, for example, be a system on chip (SOC) or a device including the SOC, such as a mobile phone, a tablet computer, a notebook computer, an e-book, a game console, a television, a digital photo frame, a navigator, a household appliance, a communication base station, an industrial controller, a server, or any device, and can be any combination of data processing apparatus and hardware, and embodiments of the present disclosure are not limited thereto. The specific functions and technical effects of the electronic device 900 can be referred to the description of the processor and additional aspects thereof according to at least one embodiment of the present disclosure above, and will not be described here again.

[0148] The processor according to the present disclosure can not implement an accelerator module for a specific accelerator function. The accelerator module is characterized by having independent memory access capability, and can automatically load data, process data, and write back data. Workloads that meet these characteristics can be accelerated by implementing a corresponding accelerator engine to accelerate the computational load of the processor core. The processor according to the present disclosure can improve the configuration flexibility of the accelerator engine within the processor core cluster and between the processor cores, while improving the efficiency of the use of the processor accelerator engine.

[0149] The text and drawings in the present disclosure are provided only as examples to help understand the present disclosure. They should not be interpreted as limiting the scope of the present disclosure in any way. Although certain embodiments and examples have been provided, it will be clear to those skilled in the art based on the disclosure herein that changes can be made to the embodiments and examples shown without departing from the scope of the present disclosure.

[0150] While the present disclosure has been described with an example embodiment, various changes and modifications can be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0151] No aspect of the disclosure described should be deemed critical, essential, or required, except for the claims. The scope of the disclosure should therefore be determined with reference to the appended claims, along with their full scope of equivalents.

Claims

1. A processor comprising: a plurality of processor cores, wherein each of the plurality of processor cores is configured to execute a first class of instructions; an accelerator module, wherein the accelerator module comprises at least one accelerator engine configured to execute a second class of instructions different from the first class of instructions; wherein the accelerator module is coupled to and shared by the plurality of processor cores, and each of the plurality of processor cores dispatches an object instruction belonging to the second class of instructions in an instruction stream processed by itself to the accelerator module for execution and receives an execution result message of the object instruction from the accelerator module.

2. The processor of claim 1, wherein: the accelerator module is dynamically coupled to the plurality of processor cores to receive the same or different object instructions belonging to the second class of instructions from the plurality of processor cores.

3. The processor of claim 1 or 2, wherein, each of the plurality of processor cores is further configured to: identify whether a current instruction in the instruction stream is the first class of instructions or the second class of instructions, in response to the current instruction being the first class of instructions, dispatch the current instruction to a pipeline of itself, and in response to the current instruction being the second class of instructions, dispatch the current instruction to the accelerator module as the object instruction.

4. The processor of claim 1 or 2, wherein, each of the plurality of processor cores is further configured to: enter the object instruction into a dispatch queue to wait for dispatch, allocate an entry in a reorder buffer for the object instruction, and in response to the object instruction becoming an oldest instruction in the reorder buffer, dispatch the object instruction to the accelerator module.

5. The processor of claim 1 or 2, wherein, each of the plurality of processor cores is further configured to: enter the object instruction into a dispatch queue to wait for dispatch, wait for a reorder buffer to empty, and in response to the reorder buffer emptying, dispatch the object instruction to the accelerator module.

6. The processor of any one of claims 1-5, wherein: the accelerator module is further configured to return a processing result of the object instruction to a corresponding processor core, and the execution result message of the object instruction comprises the processing result of the object instruction; or the accelerator module is further configured to store a processing result of the object instruction into a memory coupled to the plurality of processor cores, and the execution result message of the object instruction comprises a storage address of the processing result of the object instruction in the memory.

7. The processor of any one of claims 1-6, wherein, each of the plurality of processor cores comprises: an instruction fetch module configured to fetch instructions; a decode module configured to decode fetched instructions into one or more micro-operations; and a dispatch module configured to dispatch the one or more micro-operations to a processor core pipeline or the accelerator module.

8. The processor of claim 7, wherein, the one or more micro-operations comprise: a read and fill micro-operation to read an instruction parameter and fill an operand, a load offload micro-operation to issue a workload to an accelerator engine executing the one or more micro-operations.

9. The processor of any one of claims 1-8, wherein, In response to the accelerator engine being in a synchronized mode of operation with a corresponding processor core, the accelerator module is configured to return an execution status to the corresponding processor core in response to the object instruction completing execution in the accelerator module.

10. The processor of claim 8, wherein, The one or more micro-ops further include: a read response micro-op to cause the at least one accelerator engine to return an execution status to a corresponding processor core.

11. The processor of any one of claims 1-10, wherein, The accelerator module further includes: an arbiter coupled between the plurality of processor cores and the at least one accelerator engine and configured to arbitrate the object instructions received from the plurality of processor cores for assignment to a target accelerator engine of the at least one accelerator engine.

12. The processor of any one of claims 1-11, wherein, The accelerator module further includes: a memory interface coupled with the at least one accelerator engine and including a translation lookaside buffer, wherein the at least one accelerator engine shares the translation lookaside buffer.

13. The processor of claim 12, wherein, The translation lookaside buffer includes one or more translation lookaside buffer entries, Each of the one or more translation lookaside buffer entries includes a processor core identity to identify a processor core to which a current translation lookaside buffer entry belongs among the plurality of processor cores.

14. The processor of claim 13, wherein, Each of the one or more translation lookaside buffer entries further includes: a process identity to identify a process to which a current translation lookaside buffer entry belongs.

15. The processor of claim 14, wherein, Each of the plurality of processor cores is further configured to send a translation lookaside buffer entry operation instruction to the accelerator module that, when executed, causes the accelerator module to perform one or more of: invalidate all translation lookaside buffer entries; invalidate translation lookaside buffer entries having a particular process identity; invalidate translation lookaside buffer entries having a particular process identity and a particular virtual page number; invalidate translation lookaside buffer entries having a particular processor core identity; invalidate translation lookaside buffer entries having a particular processor core identity and a particular process identity; and invalidate translation lookaside buffer entries having a particular processor core identity, a particular process identity, and a particular virtual page number.

16. The processor of claim 15, wherein, The accelerator module further includes a data cache, and wherein each of the plurality of processor cores is further configured to send a cache operation instruction to the accelerator module that, when executed, causes the accelerator module to perform one or more of: invalidate all cache lines in the data cache; invalidate one or more cache lines in the data cache; flush all cache lines in the data cache; and flush one or more cache lines in the data cache.

17. The processor of claim 16, wherein, The at least one accelerator engine includes a control register, The control register is configured to store the translation lookaside buffer entry operation instructions and the cache operation instructions.

18. The processor of any one of claims 1-17, wherein, The accelerator module further includes a page table walker independent of the plurality of processor cores, The page table walker is configured to perform one or more of: walk a page table to determine a virtual to physical address translation for a memory access request; walk a page table to determine a virtual to physical address translation for a memory access request in response to a cache miss; and walk a page table to determine a virtual to physical address translation for a memory access request in response to a cache miss and a translation lookaside buffer miss. The accelerator module is further configured to, in response to the at least one accelerator engine missing the translation lookaside buffer, perform a page table walk using the independent page table walker.

19. The processor of any one of claims 1-17, wherein, The accelerator module further comprises a page table walker router connected to at least a portion of the plurality of processor cores, and the object instruction further comprises a processor core identity, The accelerator module is further configured to, in response to the at least one accelerator engine missing the translation lookaside buffer, access a page table walker in a corresponding processor core based on the processor core identity using the page table walker router to perform a page table walk.

20. The processor of claim 11, wherein, Each of the at least one accelerator engine comprises: a fetch front-end module configured to decode the object instruction received from the arbiter; one or more back-end execution modules configured to execute the object instruction decoded by the fetch front-end module; a memory interface arbiter module to arbitrate access memory requests of the one or more back-end execution modules; a completion unit module configured to submit a processing result of the object instruction.

21. The processor of claim 20, wherein, The fetch front-end module comprises a load offload buffer configured to store object instruction parameters and operands.

22. An electronic device comprising the processor of any one of claims 1-21.

23. A method of processing instructions, comprising: receiving, by a plurality of processor cores, a stream of instructions to be executed, wherein the stream of instructions comprises a first type of instruction and a second type of instruction different from the first type of instruction; processing, by the plurality of processor cores, respectively, the first type of instruction in a corresponding stream of instructions; and dispatching, by the plurality of processor cores, respectively, an object instruction belonging to the second type of instruction in a stream of instructions processed by itself to an accelerator module for execution and receiving, from the accelerator module, an execution result message of the object instruction, wherein the accelerator module comprises at least one accelerator engine configured to execute the second type of instruction, and the accelerator module is coupled to and shared by the plurality of processor cores.

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