Chip, server board, server cabinet, display system, and display method

Abstract

The present application relates to the technical field of computers and provides a chip, a server board, a server cabinet, a display system, and a display method. The chip comprises a plurality of graphics processing modules, a display interface, and a switching module. The display interface and the plurality of graphics processing modules are all connected to the switching module. Each graphics processing modules outputs, to the switching module, system screen data of a host to which the graphics processing module is connected. The switching module selects, from the plurality of graphics processing modules, a graphics processing module corresponding to a target host, and enables a transmission path between the graphics processing module corresponding to the target host and the display interface, so as to output system screen data of the graphics processing module corresponding to the target host to the display interface. The display interface outputs the system screen data received from the switching module, so as to display a system screen of the target host. A single chip is used to switch the display of different system screens without requiring an external KVM switch, and the switching logic can be implemented within the chip, thereby reducing costs and saving resources.

Description

Chip, server single board, server cabinet, display system and display method

[0001] The present application claims priority to the Chinese patent application No. 202411237015.X, filed on September 4, 2024, and entitled "Chip, server single board, server cabinet, display system and display method", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computers, and in particular to a chip, a server single board, a server cabinet, a display system and a display method. BACKGROUND

[0003] The board management controller (BMC) chip is a chip deployed in a computing device. The BMC chip can manage a master chip in the computing device as a management chip, or the BMC chip itself can also control as a master chip in the computing device.

[0004] In the related art, the BMC chip includes a graphics processing module and a display interface. The graphics processing module is connected to an operating system, and the display interface is connected to a display device. The operating system provides system picture data to the graphics processing module. The graphics processing module transmits the system picture data to the display interface, which is output to the display device. The display device presents a system picture of the operating system based on the system picture data.

[0005] However, in the above method, if it is desired to switch to display two different system pictures on the same display device, two BMC chips need to be deployed. A keyboard video and mouse (KVM) switch is deployed between the display interfaces of the two BMC chips and the display device. The KVM switch is used to control the display device to display the system picture data output by the display interface of which BMC chip. However, this method has a high cost. SUMMARY

[0006] The present application provides a chip, a server single board, a server cabinet, a display system and a display method. Different system pictures can be switched and displayed by one chip, which can reduce costs and save resources. The technical solution is as follows:

[0007] In a first aspect, the present application provides a chip, wherein the chip includes a plurality of graphics processing modules, a display interface and a switching module. The plurality of graphics processing modules are connected to the display interface. The display interface and the plurality of graphics processing modules are connected to the switching module.

[0008] The plurality of graphic processing modules are connected with a plurality of hosts respectively, and are configured to output system picture data of the host connected with each of the graphic processing modules to the switching module;

[0009] The switching module is configured to select a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and to turn on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed.

[0010] The display interface is configured to output the system picture data received from the switching module.

[0011] In the above chip, the plurality of graphic processing modules in the chip share one display interface, and the switching module can switch the system picture data output by which graphic processing module to provide to the display interface, and then the display interface outputs the system picture data to display the corresponding system picture. Therefore, only one chip is used to switch and display different system pictures, and there is no need to externally connect a KVM switch, and the switching logic can be completed in the chip, thereby reducing the cost and saving resources. Moreover, there is no need to deploy one display interface for each graphic processing module, thereby saving the number of display interfaces, reducing the cost of the chip, and saving the chip space.

[0012] Optionally, the switching module comprises a first multiplexer group and a control unit, and the plurality of graphic processing modules, the control unit and the display interface are connected with the first multiplexer group.

[0013] The control unit is configured to control the first multiplexer group to output the system picture data from the graphic processing module indicated by the control unit to the display interface in response to the switching instruction.

[0014] The first multiplexer group can select one path from a plurality of input paths as an output path, and the control unit can control the first multiplexer group to output which path of the system picture data, thereby dynamically switching which graphic processing module outputs the system picture data to the first multiplexer group, and facilitating to improve the flexibility and switching speed of switching and displaying pictures.

[0015] Optionally, the first multiplexer group comprises a first multiplexer and a second multiplexer, the plurality of graphic processing modules and the control unit are connected with the first multiplexer, and the first multiplexer, the control unit and the display interface are connected with the second multiplexer.

[0016] The control unit is configured to instruct the first multiplexer to output system picture data received from the target host corresponding graphic processing module in response to the switching instruction.

[0017] The control unit is further configured to instruct the second multiplexer to output preset system picture data if the phase-locked loop is not configured, and to output system picture data received from the first multiplexer if the phase-locked loop is configured, the phase-locked loop being configured to provide clock signals to the plurality of graphic processing modules.

[0018] The first multiplexer is configured to output the system picture data indicated by the control unit from the received system picture data to the second multiplexer.

[0019] The second multiplexer is configured to output the system picture data indicated by the control unit from the received system picture data to the display interface.

[0020] The control unit can control the first multiplexer to output system picture data of which graphic processing module, and the control unit can control the second multiplexer to output preset system picture data or system picture data of which graphic processing module. During the display switching process, the preset system picture data is outputted by the control unit to the second multiplexer to display the preset system picture, so as to avoid the problem of display mura caused by the confusion of system picture data during the switching process.

[0021] Optionally, the plurality of graphic processing modules are further configured to output a vertical synchronization signal to the control unit after outputting a frame of system picture data.

[0022] The control unit is configured to instruct the second multiplexer to output system picture data received from the first multiplexer if the phase-locked loop is configured and the vertical synchronization signal of the target host corresponding graphic processing module is received.

[0023] The vertical synchronization signal means that the graphic processing module has outputted a frame of complete system picture data, and will output the next frame of system picture data. When the vertical synchronization signal is detected, the control unit controls the second multiplexer to output the system picture data provided by the graphic processing module, so as to avoid the second multiplexer outputting residual frame of system picture data, thereby ensuring that the system picture displayed after switching is a frame of complete system picture, and improving the switching display effect.

[0024] Optionally, the chip further comprises a phase-locked loop, the plurality of graphic processing modules are connected with the phase-locked loop, and the phase-locked loop is connected with the switching module.

[0025] The plurality of graphic processing modules are configured to output system picture data to the switching module based on the received clock signal, and are further configured to output configuration information provided by the host connected thereto to the switching module.

[0026] The switching module is further configured to turn on a transmission path between the graphic processing module corresponding to the target host and the phase-locked loop, so as to output the configuration information of the graphic processing module corresponding to the target host to the phase-locked loop.

[0027] The phase-locked loop is configured to be configured by the configuration information received from the switching module, and is configured to output a clock signal to the plurality of graphic processing modules.

[0028] The plurality of graphic processing modules in the chip share one phase-locked loop, and the switching module can switch the configuration information output by which graphic processing module to provide to the display interface, so that the phase-locked loop outputs the clock signal required by the graphic processing module, and then the graphic processing module outputs accurate system picture data to display accurate system picture. Therefore, the display picture needs to be switched to the system picture corresponding to which graphic processing module, and the phase-locked loop is configured based on the configuration information provided by which graphic processing module, thereby realizing the multiplexing of the phase-locked loop, without the need to deploy a phase-locked loop for each graphic processing module, thereby saving the number of phase-locked loops, saving not only resource costs but also chip space.

[0029] Optionally, the switching module comprises a second multiplexer group and a control unit, and the plurality of graphic processing modules, the control unit and the phase-locked loop are connected with the second multiplexer group.

[0030] The control unit is configured to instruct the second multiplexer group to output the configuration information received from the graphic processing module corresponding to the target host.

[0031] The second multiplexer group is configured to output the configuration information from the graphic processing module instructed by the control unit to the phase-locked loop.

[0032] The second multiplexer group can select one path from multiple input paths as output, and the control unit can control the second multiplexer group to output which path of configuration information, thereby dynamically switching the configuration information of which graphic processing module output by the first multiplexer group, which is conducive to improving the flexibility and switching speed of switching the configuration information of the phase-locked loop.

[0033] Optionally, the second multiplexer group comprises a third multiplexer and a fourth multiplexer, the plurality of graphic processing modules and the control unit are connected with the third multiplexer, and the third multiplexer, the control unit and the phase-locked loop are connected with the fourth multiplexer.

[0034] The control unit is configured to cache configuration information of the graphics processing module corresponding to the host, and output the cached configuration information to the fourth multiplexer;

[0035] The control unit is further configured to instruct the third multiplexer to output the configuration information received from the graphics processing module corresponding to the target host;

[0036] The control unit is further configured to instruct the fourth multiplexer to output the configuration information received from the control unit if the phase-locked loop is not configured, and instruct the fourth multiplexer to output the configuration information received from the third multiplexer if the phase-locked loop is configured;

[0037] The third multiplexer is configured to output the configuration information indicated by the control unit from the received configuration information to the fourth multiplexer;

[0038] The fourth multiplexer is configured to output the configuration information indicated by the control unit from the received configuration information to the phase-locked loop.

[0039] The configuration information of the graphics processing module may change during the configuration process of the phase-locked loop. If the configuration information of the graphics processing module is directly output to the phase-locked loop, the configuration process of the phase-locked loop will be incorrect if the configuration information of the graphics processing module changes during the configuration process. Therefore, the control unit caches the configuration information of the graphics processing module first, controls the phase-locked loop to be configured based on the cached configuration information, that is, the configuration right of the phase-locked loop is given to the control unit, and controls the phase-locked loop to be configured based on the configuration information of the graphics processing module after the configuration is completed, that is, the configuration right of the phase-locked loop is returned to the host. In this way, the configuration information provided to the phase-locked loop during the configuration process is a set of accurate and unaltered information, which can improve the orderliness and accuracy of reconfiguring the phase-locked loop and is beneficial to reducing the error rate of the configuration process.

[0040] Optionally, the control unit is configured to output each item in the cached configuration information to the fourth multiplexer.

[0041] The configuration information includes a plurality of configuration items, and the configuration process of the phase-locked loop is performed step by step. The control unit outputs the plurality of configuration items to the phase-locked loop one by one, and at least one configuration item can be output to the phase-locked loop each time.

[0042] Optionally, the switching module further includes a plurality of configuration units, each of the graphics processing modules is connected with a corresponding configuration unit, and the control unit and the third multiplexer are connected with each of the configuration units.

[0043] The plurality of graphic processing modules are configured to output configuration information before switching and configuration information after switching to the respective connected configuration units.

[0044] The control unit is configured to instruct each configuration unit to output configuration information after switching if the phase-locked loop configuration is successful.

[0045] The control unit is further configured to instruct each configuration unit to output configuration information before switching if the phase-locked loop configuration fails.

[0046] The plurality of configuration units are configured to output the configuration information indicated by the control unit from the received configuration information to the third multiplexer.

[0047] After the phase-locked loop configuration is completed, the configuration information cached by the control unit is used by the configured phase-locked loop. If the configuration information provided by the graphic processing module changes during the configuration process, the configuration information obtained by the phase-locked loop will be inconsistent with the currently used configuration information when the configuration right of the phase-locked loop is returned to the host, which will further cause an error. Therefore, in the present scheme, if the phase-locked loop configuration is successful, it indicates that the configuration information of the graphic processing module has not changed, and therefore the configuration information after switching is provided to the phase-locked loop. If the phase-locked loop configuration fails, it indicates that the configuration information provided by the graphic processing module has changed, and therefore the configuration information before switching is provided to the phase-locked loop. In this way, the configuration information provided to the phase-locked loop before and after the handover of the configuration right is consistent, thereby completing the seamless handover of the configuration right.

[0048] Optionally, the configuration unit comprises a first register and a fifth multiplexer, the graphic processing module, the third multiplexer, the control unit and the first register are connected with the fifth multiplexer, and the graphic processing module and the control unit are connected with the first register.

[0049] The graphic processing module is configured to output configuration information before switching to the first register and output configuration information after switching to the fifth multiplexer.

[0050] The first register is configured to store the received configuration information from the graphic processing module and output the stored configuration information to the fifth multiplexer.

[0051] The fifth multiplexer is configured to output the configuration information indicated by the control unit from the received configuration information to the third multiplexer.

[0052] The configuration unit is composed of the first register corresponding to each graphic processing module and the fifth multiplexer, and the first register stores the configuration information of the graphic processing module before switching, so as to realize backup of the configuration information before switching. The control unit controls the fifth multiplexer to output the configuration information before switching or the configuration information after switching, which is beneficial to improve the flexibility and switching speed of the output configuration information.

[0053] Optionally, the graphic processing module comprises a second register, and the switching module further comprises a third register, and the second register stores the configuration information of the graphic processing module.

[0054] The control unit is configured to store the configuration information in the second register into the third register.

[0055] The third register is configured to output the stored configuration information to the fourth multiplexer.

[0056] The graphic processing module and the switching module have respective registers, the switching module stores the configuration information in the second register of the graphic processing module into the third register of the switching module, so as to realize caching of the configuration information of the graphic processing module. On the one hand, the configuration information of the graphic processing module is backed up to prevent errors caused by changes in the configuration information during switching. On the other hand, the reading speed of the configuration information can be improved.

[0057] Optionally, the switching module is configured to detect the state of the phase-locked loop, and if the phase-locked loop is in a non-configuration state, the transmission path between the graphic processing module corresponding to the target host and the phase-locked loop is turned on to output the configuration information of the graphic processing module corresponding to the target host to the phase-locked loop.

[0058] The phase-locked loop is reconfigured when the phase-locked loop is in a non-configuration state, so as to prevent the original configuration progress of the phase-locked loop from being disturbed when the phase-locked loop is reconfigured in a configuration state, which is beneficial to reduce the error rate of the entire process.

[0059] Optionally, the switching module is configured to control the phase-locked loop to output a reference clock signal to the plurality of graphic processing modules if the phase-locked loop is not configured.

[0060] The switching module is configured to control the phase-locked loop to output a clock signal generated after configuration to the plurality of graphic processing modules if the phase-locked loop is configured.

[0061] The phase-locked loop is reconfigured at the beginning of the switching, and the phase-locked loop cannot output a stable clock signal during the configuration process. Therefore, a reference clock signal is provided to the graphic processing module to ensure the normal operation of the internal processing logic of the graphic processing module. After the configuration is completed, the phase-locked loop can output a stable clock signal. Therefore, a stable clock signal is provided to the graphic processing module, so that the graphic processing module generates accurate system picture data based on the accurate clock signal, thereby ensuring the realizability and orderliness of the entire display switching process.

[0062] Optionally, the switching module comprises a logic circuit and a plurality of registers connected in sequence.

[0063] The logic circuit is configured to assign a first register to trigger a first control signal, and in response to the first control signal, assign a next register connected to the first register to trigger a next control signal. The control signal is used to turn on the transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output the system picture data of the graphic processing module corresponding to the target host to the display interface.

[0064] In the display switching process, the logic circuit triggers the control signal by assigning the register. The logic circuit automatically assigns the next register to trigger the next control signal according to the control signal. In this way, the logic circuit triggers a plurality of control signals in sequence, thereby controlling the output of the system picture data of the target host to the display interface, and realizing the display switching based on hardware. Since the speed of assigning the register by hardware is very fast, the overall speed of display switching is improved.

[0065] Optionally, the switching module comprises a controller and a plurality of registers.

[0066] The controller is configured to run a switching program, and read and write the plurality of registers in sequence through the switching program to trigger a plurality of control signals. The control signal is used to turn on the transmission path between the graphic processing module corresponding to the target host and the display interface, and output the system picture data of the graphic processing module corresponding to the target host to the display interface.

[0067] In the display switching process, the register is read and written in sequence according to the preset instruction in the switching program to trigger the control signal, thereby controlling the output of the system picture data of the target host to the display interface, and realizing the display switching based on software. Since the software has configurability, the control logic can be adjusted by changing the code or configuration, thereby providing higher flexibility for the control process of display switching, so that the control process of display switching can adapt to different scenes and requirements, and is more easily realized in a customized control mode.

[0068] Optionally, the chip comprises a processor, and each of the plurality of graphic processing modules is connected to a host on the processor.

[0069] The plurality of graphic processing modules in the chip are connected to the processor inside the chip, and process the system picture data of the processor inside the chip, so that the processor inside the chip can provide a plurality of different system picture data to the graphic processing modules, thereby realizing switching display of a plurality of different system pictures of the same system, and making the chip applicable to a multi-screen switching application scenario of the same system.

[0070] Optionally, the chip is connected to a plurality of master chips, and each of the plurality of graphic processing modules is connected to a host on a master chip.

[0071] The plurality of graphic processing modules in the chip can be connected to processors in other different master chips respectively, one chip can provide services for a plurality of different master chips, switching display of system pictures of a plurality of different master chips is realized, chips do not need to be deployed respectively for each master chip, the number of chips is saved, resource cost is saved, and deployment space is saved.

[0072] In a second aspect, the present application provides a server single board, comprising a circuit board, and a management chip and a master chip mounted on the circuit board, the management chip comprising a plurality of graphic processing modules, a display interface and a switching module, the management chip further comprising an interface corresponding to each of the graphic processing modules, the interface corresponding to the graphic processing module being used to connect the graphic processing module to a host on any master chip; the plurality of graphic processing modules are connected to the display interface, and the display interface and the plurality of graphic processing modules are connected to the switching module.

[0073] The plurality of graphic processing modules are connected to a plurality of hosts respectively, and are used to output system picture data of the connected host to the switching module;

[0074] The switching module is used to select a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and to turn on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed.

[0075] The display interface is used to output system picture data received from the switching module.

[0076] In a third aspect, the present application provides a server cabinet, comprising a cabinet body, the cabinet body comprising a backboard, the server cabinet further comprising a plurality of server single boards mounted on the backboard, the server single boards being mounted with master control chips, the plurality of server single boards being mounted with a same management chip, the management chip comprising a plurality of graphic processing modules, a display interface and a switching module, each of the graphic processing modules being connected with a host on a master control chip; the plurality of graphic processing modules being connected with the display interface, and the display interface and the plurality of graphic processing modules being connected with the switching module;

[0077] The plurality of graphic processing modules are respectively connected with a plurality of hosts, and are configured to output system picture data of the host connected with each of the graphic processing modules to the switching module;

[0078] The switching module is configured to select a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and to turn on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed;

[0079] The display interface is configured to output the system picture data received from the switching module.

[0080] In a fourth aspect, the present application provides a display system, comprising a server cabinet and a display device, the server cabinet comprising a plurality of server single boards, the server single boards being mounted with master control chips, the plurality of server single boards being mounted with a same management chip, the management chip comprising a plurality of graphic processing modules, a display interface and a switching module, each of the graphic processing modules being connected with a host on a master control chip, the display interface being connected with the display device; the plurality of graphic processing modules being connected with the display interface, and the display interface and the plurality of graphic processing modules being connected with the switching module;

[0081] The plurality of graphic processing modules are respectively connected with a plurality of hosts, and are configured to output system picture data of the host connected with each of the graphic processing modules to the switching module;

[0082] The switching module is configured to select a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and to turn on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed;

[0083] The display interface is configured to output system picture data received from the switching module.

[0084] In a fifth aspect, the present application provides a display method applied to a chip, the method comprising:

[0085] receiving system picture data of a first host and system picture data of a second host;

[0086] in response to a display instruction of a display device, controlling the chip to output the system picture data of the first host to the display device;

[0087] receiving a switching instruction of the display device, the switching instruction being used to switch a display picture of the display device from the system picture of the first host to the system picture of the second host;

[0088] in response to the switching instruction, controlling the chip to output the system picture data of the second host to the display device.

[0089] Optionally, the step of controlling the chip to output the system picture data of the second host to the display device in response to the switching instruction comprises:

[0090] in response to the switching instruction, starting reconfiguration of a phase-locked loop so as to make the phase-locked loop provide a clock signal of the system picture data of the second host;

[0091] in a configuration process, controlling the chip to output data of a preset system picture to the display device;

[0092] if the phase-locked loop is configured, controlling the chip to output the system picture data of the second host to the display device.

[0093] Optionally, the step of controlling the chip to output the system picture data of the second host to the display device if the phase-locked loop is configured comprises:

[0094] if the phase-locked loop is configured and a vertical synchronization signal is detected, controlling the chip to output the system picture data of the second host to the display device;

[0095] The vertical synchronization signal indicates that a complete frame of the system picture data of the second host has been acquired.

[0096] Optionally, the method further comprises:

[0097] receiving configuration information of the first host and configuration information of the second host;

[0098] in response to the switching instruction, configuring the phase-locked loop based on the configuration information of the second host.

[0099] Optionally, the configuring the phase-locked loop based on the configuration information of the second host in response to the switching instruction comprises:

[0100] In response to the switching instruction, caching the configuration information of the second host, and configuring the phase-locked loop based on the cached configuration information.

[0101] If the phase-locked loop is configured, configuring the phase-locked loop based on the configuration information of the second host.

[0102] Optionally, the configuring the phase-locked loop based on the configuration information of the second host comprises:

[0103] If the phase-locked loop is configured successfully, configuring the phase-locked loop based on the configuration information of the second host after the switching is started, and if the phase-locked loop is configured unsuccessfully, configuring the phase-locked loop based on the configuration information of the second host before the switching is started.

[0104] Optionally, the configuring the phase-locked loop based on the configuration information of the second host in response to the switching instruction comprises:

[0105] In response to the switching instruction, detecting the state of the phase-locked loop, and if the phase-locked loop is in a non-configuration state, configuring the phase-locked loop based on the configuration information of the second host.

[0106] Optionally, the method further comprises:

[0107] If the phase-locked loop is not configured, controlling the phase-locked loop to output a reference clock signal to a graphic processing module.

[0108] If the phase-locked loop is configured, controlling the phase-locked loop to output a clock signal obtained after the configuration is completed to the graphic processing module. BRIEF DESCRIPTION OF DRAWINGS

[0109] Fig. 1 is a structural schematic diagram of a chip according to an embodiment of the present application;

[0110] Fig. 2 is a structural schematic diagram of another chip according to an embodiment of the present application;

[0111] Fig. 3 is a structural schematic diagram of another chip according to an embodiment of the present application;

[0112] Fig. 4 is a state transition schematic diagram of a hardware state machine according to an embodiment of the present application;

[0113] Fig. 5 is a system architecture diagram of a display scenario according to an embodiment of the present application;

[0114] FIG. 6 is a system architecture diagram of another display scenario provided by an embodiment of the present application;

[0115] FIG. 7 is a flowchart of a display method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0116] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be described in further detail below with reference to the drawings. It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the chips, configuration information, system screen data, etc. involved in the present application are obtained under full authorization.

[0117] In order to switch the display screen on the same display device, the present application relates to a chip for switching which system screen data of which graphics processing module is output to the display interface through a switching module for display.

[0118] The structure of the chip of the present application will be introduced below.

[0119] FIG. 1 is a structural schematic diagram of a chip provided by an embodiment of the present application, referring to FIG. 1, the chip 10 includes a plurality of graphics processing modules 11, a display interface 12 and a switching module 13, the plurality of graphics processing modules 11 are all connected with the display interface 12, and the display interface 12 and the plurality of graphics processing modules 11 are both connected with the switching module 13. The plurality of graphics processing modules 11 are respectively connected with a plurality of hosts, for outputting system screen data of the host connected respectively to the switching module 13; the switching module 13 is used for selecting a graphics processing module 11 corresponding to a target host from the plurality of graphics processing modules 11 in response to a switching instruction, and conducting a transmission path between the graphics processing module 11 corresponding to the target host and the display interface 12, so as to output the system screen data of the graphics processing module 11 corresponding to the target host to the display interface 12, the target host being a host corresponding to a system screen to be displayed; the display interface 12 is used for outputting the system screen data received from the switching module 13.

[0120] It should be noted that, in order to facilitate display, FIG. 1 only shows two graphics processing modules 11 in the chip 10, and in fact the chip 10 can also include more graphics processing modules 11, which are not limited by FIG. 1. The graphics processing module 11, the switching module 13 and the display interface 12 will be introduced respectively as follows.

[0121] (1) Graphics processing module 11

[0122] The graphics processing module 11 is a module with graphics processing capability in the chip 10, and the plurality of graphics processing modules 11 in the chip 10 are independent modules, and the system picture data output by each graphics processing module 11 is different. Each graphics processing module 11 is connected with a host, and the graphics processing module 11 is used to provide image data processing function for the connected host, that is, the host provides system operation data to the graphics processing module 11, and the graphics processing module 11 generates system picture data based on the system operation data provided by the host, and the system picture data indicates a system picture that can reflect the system running of the host, or a system picture generated based on the operation of the system of the host.

[0123] Optionally, the hosts connected to each graphics processing module 11 can be the same or different. Optionally, the structures of each graphics processing module 11 are the same. Optionally, the graphics processing module 11 can be a graphics processing unit (GPU) or a neural processing unit (NPU) or any computing module with graphics processing capability.

[0124] (2) Switching module 13

[0125] The switching module 13 is a module with display switching capability in the chip 10. Although the chip 10 includes a plurality of graphics processing modules 11, and each graphics processing module 11 is connected with the display interface 12 through the switching module 13, in the running process, except that the transmission path between one graphics processing module 11 and the display interface 12 is turned on, the transmission paths between other graphics processing modules 11 and the display interface 12 are not turned on. The above transmission path turned on means that the system picture data output by the graphics processing module 11 can be transmitted to the display interface 12, and the transmission path not turned on means that the system picture data output by the graphics processing module 11 cannot be transmitted to the display interface 12. The switching module 13 turns on the transmission path between one graphics processing module 11 and the display interface 12 among the plurality of graphics processing modules 11 through switching, so as to output the system picture data of the graphics processing module 11 to the display interface 12. The switching module 13 can control which graphics processing module 11 outputs the system picture data to the display interface 12 inside the chip 10. That is, the plurality of graphics processing modules 11 share one display interface 12, and at the same time, the display interface 12 can only receive the system picture data output by one graphics processing module 11, and the switching module 13 can provide the system picture data of the graphics processing module 11 corresponding to the display request of the display device to the display interface 12.

[0126] In the embodiment of the present application, when the display device requests to switch the currently displayed system picture to the system picture of the target host, the switching module 13 turns on the transmission path between the target host corresponding graphic processing module 11 and the display interface 12, so as to output the system picture data of the target host corresponding graphic processing module 11 to the display interface 12.

[0127] (3) Display interface 12

[0128] The display interface 12 is connected with the display device outside the chip 10 in a wired or wireless manner, and is used to transmit the received system picture data to the display device, so that the display device displays the system picture based on the system picture data.

[0129] Optionally, the display interface 12 is composed of at least one type of interface. For example, the display interface 12 can be composed of at least one type of interface such as a video graphics array (VGA) interface, a low-voltage differential serial signaling (LVDS) interface, a display port (DP), and a network port, etc. The VGA interface is a video transmission standard used to transmit picture data to the display device. The LVDS interface is a data transmission and interface technology, which has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation, etc. The DP is a protocol used for digital video and audio transmission. The network port is a bridge between the chip 10 and the external network, which is used to send data in the chip 10 to the network.

[0130] The display interface 12 in the chip 10 can include one or more of the above-mentioned VGA interface, LVDS interface, DP or network port. The system picture can be displayed locally through the VGA interface, LVDS interface or DP. After the system picture data is processed through at least one of the VGA interface, LVDS interface or DP, it is sent to the display device in a wired manner, and the display device displays the system picture based on the system picture data, thereby realizing local display of the system picture. In addition, the system picture can be displayed remotely through the network port. A video compression engine (VCE) can also be deployed in the chip 10. The VCE is used to compress the system picture data, and the compressed system picture data is sent to the network through the network port. The system picture data is sent to the display device in a wireless manner through the network, and the display device displays the system picture based on the system picture data, thereby realizing remote display of the system picture.

[0131] In the chip 10, a plurality of graphic processing modules 11 are arranged, the plurality of graphic processing modules 11 share one display interface 12, and a switching module 13 is added in the chip 10, through the switching module 13, the transmission path between any host corresponding graphic processing module 11 and the display interface 12 can be turned on, so that the system picture data received by the display interface 12 from which host is flexibly controlled. Therefore, the present application can realize display switching different system pictures by using only one chip 10, and does not need to externally connect a KVM switch, and the switching logic can be completed in the chip 10, so that the display cost is reduced, and resources are saved. Moreover, the plurality of graphic processing modules 11 in the chip 10 can share one display interface 12, and one display interface 12 does not need to be arranged for each graphic processing module 11, not only the number of display interfaces 12 is saved, and the cost of the chip 10 is reduced, but also the space of the chip 10 is saved. Moreover, since the chip 10 provides the display switching capability, the chip 10 only needs to externally connect one display device, and different system pictures are switched on one display device, and a plurality of display devices do not need to be externally connected, so that the number of display devices is saved, and the display cost is further reduced.

[0132] On the basis of FIG. 1, the present application embodiment provides the structural schematic diagram shown in FIG. 2, and the internal structure and working principle of the switching module 13 for switching system picture data are introduced as follows in combination with FIG. 2.

[0133] Referring to FIG. 2, the switching module 13 includes a first multiplexer group 131 and a control unit 132, the plurality of graphic processing modules 11, the control unit 132 and the display interface 12 are connected with the first multiplexer group 131. The control unit 132 is used for responding to a switching instruction, and controlling the first multiplexer group 131 to output the system picture data from the graphic processing module 11 indicated by the control unit 132 in the received system picture data to the display interface 12.

[0134] The first multiplexer group 131 is a kind of combination logic circuit, and the first multiplexer group 131 has the function of selecting one way from multiple inputs as output. In the present application embodiment, the input of the first multiplexer group 131 includes the system picture data output by the plurality of graphic processing modules 11, and the output of the first multiplexer group 131 is one of the received multiple system picture data. The first multiplexer group 131 can respond to the control signal input into the first multiplexer group 131 to determine which way of system picture data is output.

[0135] The control unit 132 is configured to control which path of the system picture data is output by the first multiplexer group 131. The control unit 132 controls the first multiplexer group 131 to switch among the multiple paths of the system picture data by outputting different control signals to the first multiplexer group 131, so as to dynamically switch the output of the first multiplexer group 131. In the case where the display device requests to switch the currently displayed system picture to the system picture of the target host, the control unit 132 triggers the control signal of the first multiplexer group 131 in response to the switching instruction, and the control signal instructs the first multiplexer group 131 to output the system picture data received from the graphic processing module 11 corresponding to the target host. Therefore, after the control unit 132 outputs the control signal to the first multiplexer group 131, the first multiplexer group 131 outputs the system picture data instructed by the control signal to the display interface 12 in response to the control signal, that is, outputs the system picture data received from the graphic processing module 11 corresponding to the target host to the display interface 12, so as to turn on the transmission path between the graphic processing module 11 corresponding to the target host and the display interface 12.

[0136] In the chip 10 shown in FIG. 2, the first multiplexer group 131 is arranged between the graphic processing module 11 and the display interface 12, and the control unit 132 dynamically switches which system picture data of the graphic processing module 11 is output to the display interface 12 by outputting different control signals to the first multiplexer group 131, so as to dynamically switch which transmission path between the graphic processing module 11 and the display interface 12 is turned on, which is beneficial to improve the flexibility and switching speed of the switching process.

[0137] Optionally, the first multiplexer group 131 includes at least one multiplexer. In a possible implementation, referring to FIG. 2, the first multiplexer group 131 includes a first multiplexer and a second multiplexer. Correspondingly, the multiple graphic processing modules 11 and the control unit 132 are connected with the first multiplexer, and the first multiplexer, the control unit 132 and the display interface 12 are connected with the second multiplexer.

[0138] In this structure, the control unit 132 is configured to instruct the first multiplexer to output the system picture data received from the target host corresponding graphics processing module 11 in response to a switching instruction, and the control unit 132 is further configured to instruct the second multiplexer to output preset system picture data if the phase-locked loop 14 is not configured, and to output the system picture data received from the first multiplexer if the phase-locked loop 14 is configured, the phase-locked loop 14 being configured to provide clock signals to the plurality of graphics processing modules 11, the first multiplexer being configured to output the system picture data instructed by the control unit 132 from the received system picture data to the second multiplexer, and the second multiplexer being configured to output the system picture data instructed by the control unit 132 from the received system picture data to the display interface 12.

[0139] The first multiplexer is configured to select which system picture data of which graphics processing module 11 to output. The input of the first multiplexer includes multiple paths, each path inputting the system picture data outputted by one of the graphics processing modules 11, and the output of the first multiplexer is one of the received multiple paths of system picture data. The first multiplexer can determine which path of system picture data to output in response to a control signal inputted into the first multiplexer. The first multiplexer is controlled by the control unit 132, and the control unit 132 instructs the first multiplexer to output which path of system picture data by outputting different control signals to the first multiplexer. In the case that the display device requests to switch the currently displayed system picture to the system picture of the target host, the control unit 132 triggers the control signal of the first multiplexer in response to a switching instruction, and the control signal instructs the first multiplexer to output the system picture data received from the target host corresponding graphics processing module 11. Therefore, after the control unit 132 outputs the control signal to the first multiplexer, the first multiplexer outputs the system picture data instructed by the control signal to the second multiplexer in response to the control signal, i.e. outputs the system picture data received from the target host corresponding graphics processing module 11 to the second multiplexer.

[0140] The second multiplexer is used to output the system picture data of the graphic processing module 11 or the preset system picture data in different cases. The input of the second multiplexer includes two paths, one of which is the preset system picture data, and the other is the system picture data output by the first multiplexer. The output of the second multiplexer is one of the preset system picture data and the system picture data output by the first multiplexer. The second multiplexer can determine which path of the system picture data to output in response to the control signal input into the second multiplexer. The second multiplexer is also controlled by the control unit 132, which indicates the second multiplexer to output which path of the system picture data by outputting different control signals to the second multiplexer. In the case where the display device requests to switch the currently displayed system picture to the system picture of the target host, the control unit 132 needs to configure the phase-locked loop 14 according to the configuration information provided by the target host, so that the phase-locked loop 14 provides the clock signal required to obtain the system picture data of the target host for the graphic processing module 11 corresponding to the target host. If the clock signal output to the graphic processing module 11 is incorrect, it will cause the system picture data output by the graphic processing module 11 to be incorrect. When the phase-locked loop 14 is not configured, the phase-locked loop 14 cannot provide accurate clock signals for the graphic processing module 11, and after the phase-locked loop 14 is configured, the phase-locked loop 14 can provide accurate clock signals for the graphic processing module 11. Based on this, the control process of the control unit 132 to the second multiplexer is divided into a phase-locked loop 14 not configured stage and a phase-locked loop 14 configured stage. In the phase-locked loop 14 not configured stage, the phase-locked loop 14 cannot provide accurate clock signals for the graphic processing module 11, so the system picture data output by the graphic processing module 11 is incorrect, and the control unit 132 indicates the second multiplexer to output the preset system picture data to the display interface 12 by outputting a control signal to the second multiplexer. In the phase-locked loop 14 configured stage, the phase-locked loop 14 can provide accurate clock signals for the graphic processing module 11, so the system picture data output by the graphic processing module 11 is correct, and the control unit 132 indicates the second multiplexer to output the system picture data received from the first multiplexer to the display interface 12 by outputting a control signal to the second multiplexer, that is, the system picture data of the graphic processing module 11 corresponding to the target host is output to the display interface 12.

[0141] Optionally, the preset system picture data is any preset system picture data, for example, the preset system picture data can be black screen picture data. Since the phase-locked loop 14 cannot provide an accurate clock signal for the graphics processing module 11 when the phase-locked loop 14 is not configured, which further causes the system picture data output by the graphics processing module 11 to be inaccurate, in this case, the control unit 132 controls the second multiplexer to output the black screen picture data to the display interface 12, so as to perform black screen display.

[0142] In some embodiments, when the graphics processing module 11 outputs system picture data, a complete frame of system picture data is not output at one time, but is output in batches, for example, the graphics processing module 11 outputs only one quarter of a frame of system picture data each time, and the output operation is performed four times in sequence to complete the output of a complete frame of system picture data. Therefore, the graphics processing module 11 outputs a vertical synchronization signal to the control unit 132 each time a complete frame of system picture data is output, to inform the control unit 132 that a complete frame of system picture data has been output, and the next frame of system picture data is about to be output. That is, the graphics processing module 11 outputs the vertical synchronization signal to the control unit 132 at a time point after a complete frame of system picture data is output and before the next frame of system picture data is started to be output. Then, in the above phase-locked loop 14 configuration completion phase, if the control unit 132 detects that the phase-locked loop 14 is configured as soon as possible, the output of the second multiplexer is switched from the preset system picture data to the system picture data of the graphics processing module 11 corresponding to the target host, which may cause the system picture data currently output by the second multiplexer to be residual frame data, resulting in that the display device cannot display a complete frame of system picture. In order to avoid the above problem, when the phase-locked loop 14 is configured and the vertical synchronization signal output by the graphics processing module 11 corresponding to the target host is received, the control unit 132 instructs the second multiplexer to output the system picture data received from the first multiplexer. That is, the timing of switching the output of the second multiplexer from the preset system picture data to the system picture data of the graphics processing module 11 corresponding to the target host is when the phase-locked loop 14 is configured and the vertical synchronization signal output by the graphics processing module 11 corresponding to the target host is received, so as to avoid that the second multiplexer outputs residual frame system picture data.

[0143] The vertical synchronization signal is a vsync signal. The vsync signal is a synchronization pulse signal output by the graphics processing module 11 when a complete frame of system picture data is output. Optionally, the graphics processing module 11 includes a digital visual interface (DVI) interface, and the graphics processing module 11 outputs the vsync signal to the control unit 132 through the DVI interface.

[0144] The completion of the configuration of the phase-locked loop 14 means that the system picture data currently received by the second multiplexer is accurate, and the reception of the vertical synchronization signal means that the graphics processing module 11 has output a frame of system picture data, i.e., is about to output the next frame of system picture data. Therefore, when the above two conditions are met, the control unit 132 performs the switching of the output of the second multiplexer, so that the display of the system picture can be avoided, and the displayed system picture is a complete frame of system picture, thereby improving the display switching effect.

[0145] Next, the phase-locked loop 14 in the chip 10 and the working principle of the internal structure related to the phase-locked loop 14 will be described below in combination with FIG. 1.

[0146] Referring to FIG. 1, the chip 10 further includes the phase-locked loop 14, and the plurality of graphics processing modules 11 are connected with the phase-locked loop 14, and the phase-locked loop 14 is connected with the switching module 13. The plurality of graphics processing modules 11 are configured to output system picture data to the switching module 13 based on the received clock signal, and are further configured to output configuration information provided by the host connected therewith to the switching module 13; the switching module 13 is further configured to turn on the transmission path between the graphics processing module 11 corresponding to the target host and the phase-locked loop 14, so as to output the configuration information of the graphics processing module 11 corresponding to the target host to the phase-locked loop 14; and the phase-locked loop 14 is configured to be configured by the configuration information received from the switching module 13, and output a clock signal to the plurality of graphics processing modules 11. The phase-locked loop 14 will be described below.

[0147] (4) Phase-locked loop 14

[0148] The phase-locked loop 14 is a component in the chip 10 for providing a clock signal to the graphics processing module 11. The clock signal is the basis for the graphics processing module 11 to implement timing logic, and the graphics processing module 11 generates system picture data of the host based on the clock signal. The resolution of the output system picture data is different due to the different clock signals used by the graphics processing module 11. What kind of clock signal the phase-locked loop 14 outputs depends on how the phase-locked loop 14 is configured. In the embodiment of the present application, the host can generate corresponding configuration information based on the resolution of the system picture required by the user, output the configuration information to the graphics processing module 11, and the graphics processing module 11 provides the configuration information to the phase-locked loop 14. Then the phase-locked loop 14 generates a clock signal after being configured by the configuration information, and provides the clock signal to the graphics processing module 11, and then the graphics processing module 11 generates system picture data meeting the resolution requirement based on the clock signal.

[0149] Although each of the graphic processing modules 11 in the chip 10 is connected with the phase-locked loop 14 through the switching module 13, during operation, the transmission path between one of the graphic processing modules 11 and the phase-locked loop 14 is on, and the transmission paths between the other graphic processing modules 11 and the phase-locked loop 14 are off. The on of the transmission path means that the configuration information output by the graphic processing module 11 can be transmitted to the phase-locked loop 14, and the off means that the configuration information output by the graphic processing module 11 cannot be transmitted to the phase-locked loop 14. The switching module 13 switches to make the transmission path between one of the graphic processing modules 11 and the phase-locked loop 14 on, so as to output the configuration information of the graphic processing module 11 to the phase-locked loop 14. The switching module 13 can control which graphic processing module 11 outputs the configuration information to the phase-locked loop 14 inside the chip 10. That is, the plurality of graphic processing modules 11 share one phase-locked loop 14, and at the same time, the phase-locked loop 14 can only receive the configuration information output by one of the graphic processing modules 11, and the switching module 13 can provide the configuration information of the graphic processing module 11 corresponding to the host requested to be displayed by the display device to the phase-locked loop 14.

[0150] In the embodiment of the present application, when the display device requests to switch the currently displayed system screen to the system screen of the target host, the switching module 13 makes the transmission path between the graphic processing module 11 corresponding to the target host and the phase-locked loop 14 on, so as to output the configuration information of the graphic processing module 11 corresponding to the target host to the phase-locked loop 14.

[0151] In the chip 10, one phase-locked loop 14 is arranged, the plurality of graphic processing modules 11 share one phase-locked loop 14, and the switching module 13 can make the transmission path between any graphic processing module 11 corresponding to the host and the phase-locked loop 14 on, so as to flexibly control which host the phase-locked loop 14 receives the configuration information of, and make the phase-locked loop 14 output the clock signal required by the graphic processing module 11 corresponding to the host. Therefore, the embodiment of the present application only arranges one phase-locked loop 14 in the chip 10, which can ensure that the graphic processing module 11 corresponding to the host of the system screen to be displayed works normally, and there is no need to arrange one phase-locked loop 14 for each graphic processing module 11, which not only saves the number of phase-locked loops 14 and reduces the cost of the chip 10, but also saves the space of the chip 10.

[0152] In a possible implementation, if the phase-locked loop 14 is in the configuring state, it indicates that a host is currently configuring the phase-locked loop 14, and if the switching module 13 outputs the configuration information of the target host corresponding to the graphic processing module 11 to the phase-locked loop 14 at this time, the original configuration progress of the phase-locked loop 14 will be broken, and the phase-locked loop 14 will be configured incorrectly. In order to avoid the above problem, the switching module 13 responds to the switching instruction, and first detects the state of the phase-locked loop 14. If the phase-locked loop 14 is in the non-configuring state, the transmission path between the graphic processing module 11 corresponding to the target host and the phase-locked loop 14 is turned on, so as to output the configuration information of the graphic processing module 11 corresponding to the target host to the phase-locked loop 14. If the phase-locked loop 14 is in the configuring state, the switching module 13 enters the waiting state until it is detected that the phase-locked loop 14 is in the non-configuring state, and the switching module 13 performs the logic of switching the configuration information output to the phase-locked loop 14.

[0153] In the embodiment of the application, the condition for the switching unit to reconfigure the phase-locked loop 14 includes that the phase-locked loop 14 is in the non-configuring state, so that the problem that the control unit 132 starts to reconfigure the phase-locked loop 14 when the host is in the configuring state and breaks the original configuration progress of the phase-locked loop 14 can be prevented, and the orderly progress of the configuration process of the phase-locked loop 14 can be ensured, which is beneficial to reduce the error rate in the display switching process.

[0154] In another possible implementation, the clock signal output by the phase-locked loop 14 is obtained by frequency conversion on the reference clock signal according to the configuration information. When the phase-locked loop 14 is not configured completely, the phase-locked loop 14 cannot generate the clock signal, and after the phase-locked loop 14 is configured completely, the phase-locked loop 14 can generate the accurate clock signal based on the configuration information. Based on this, the control unit 132 controls which clock signal the phase-locked loop 14 outputs to the graphic processing module 11 according to the state of the phase-locked loop 14. If the phase-locked loop 14 is not configured completely, it indicates that the phase-locked loop 14 cannot currently generate the accurate clock signal, and therefore the switching module 13 controls the phase-locked loop 14 to output the reference clock signal to the plurality of graphic processing modules 11. If the phase-locked loop 14 is configured completely, it indicates that the phase-locked loop 14 can currently generate the accurate clock signal, and therefore the switching module 13 controls the phase-locked loop 14 to output the clock signal generated after the configuration to the plurality of graphic processing modules 11.

[0155] In the embodiment of the present application, the reconfiguration of the phase-locked loop 14 is started at the beginning of the switching, and the phase-locked loop 14 cannot output a stable clock signal during the reconfiguration. Therefore, the reference clock signal is provided to the graphics processing module 11 to ensure the normal operation of the internal processing logic of the graphics processing module 11. After the reconfiguration is completed, the phase-locked loop 14 can output a stable clock signal. Therefore, the stable clock signal is provided to the graphics processing module 11 to enable the graphics processing module 11 to generate accurate system picture data based on the accurate clock signal, thereby ensuring the realizability and orderliness of the entire display switching process.

[0156] In the above method, different clock signals are provided to the graphics processing module 11 in different cases. When the phase-locked loop 14 currently cannot generate an accurate clock signal, the reference clock signal is provided to the graphics processing module 11 to ensure the normal operation of the internal processing logic of the graphics processing module 11. When the phase-locked loop 14 currently can generate an accurate clock signal, the accurate clock signal is provided to the graphics processing module 11 to enable the graphics processing module 11 to generate accurate system picture data based on the accurate clock signal, thereby displaying accurate system pictures and ensuring the orderliness of the entire display switching process.

[0157] In another possible implementation, the switching module 13 is configured to output each item in the configuration information of the graphics processing module 11 corresponding to the target host to the phase-locked loop 14 one by one. That is, the configuration information includes a plurality of configuration items, and the configuration process of the phase-locked loop 14 is performed step by step. The switching module 13 outputs the plurality of configuration items to the phase-locked loop 14 one by one, and outputs at least one configuration item to the phase-locked loop 14 each time.

[0158] Optionally, the graphics processing module 11 includes a second register, and the configuration information is stored in the second register. Different configuration items are stored in different bits of the second register. The correspondence between the configuration items and the number of bits of the second register is as follows.

[0159] assign ppll2_bypass=pll_cntl_out

[0029] ;ppll2_bypass represents the bypass signal of the reference clock inside the phase-locked loop 14. The low level indicates that the locked clock signal is output, and the high level indicates that the reference clock signal is output.

[0160] assign ppl12_fout2xpd=pll_cntl_out

[0028] ;assign ppl12_fout2xpd represents the powerdown signal of the oscillator output clock inside the phase-locked loop 14. The low level indicates normal operation, and the high level indicates power down.

[0161] assign ppll2_foutpostdivpd = pll_cntl_out[2]; ppll2_foutpostdivpd indicates the powerdown signal for the main output clock inside the phase locked loop 14. Low indicates normal operation, high indicates power down.

[0162] assign ppll2_fout4phasepd = pll_cntl_out[2]; ppll2_fout4phasepd indicates the powerdown signal for the divide-by-two four-phase clock inside the phase locked loop 14. Low indicates normal operation, high indicates power down.

[0163] assign ppll2_mode = pll_cntl_out[2]; ppll2_mode indicates the mode selection for the phase locked loop 14. Low indicates fractional mode, high indicates integer mode.

[0164] assign ppll2_pd = pll_cntl_out[2]; ppll2_pd indicates the powerdown signal for the global clock inside the phase locked loop 14. Low indicates normal operation, high indicates power down.

[0165] assign ppll2_postdiv2 = pll_cntl_out[23:21]; ppll2_postdiv2 is used to configure the divide ratio for the second stage divider inside the phase locked loop 14.

[0166] assign ppll2_postdivl = pll_cntl_out[20:18]; ppll2_postdivl is used to configure the divide ratio for the first stage divider inside the phase locked loop 14.

[0167] assign ppll2_fbdiv = pll_cntl_out[17:6]; ppll2_fbdiv is used to configure the feedback divide ratio configuration for the phase locked loop 14.

[0168] assign ppll2_refdiv = pll_cntl_out[5:0]; ppll2_refdiv is used to configure the reference clock division for the phase locked loop 14.

[0169] assign ppll2_frac = pll_cntl_out[63:32]; ppll2_frac is used to configure the output clock frequency for the phase locked loop 14.

[0170] assign gpu_bypass = pll_cntl out

[0030] ;gpu_bypass is used to configure the switching reference clock signal. Low level indicates outputting the reference clock signal, and high level indicates outputting the main clock signal of the phase-locked loop 14.

[0171] Optionally, the switching module 13 outputs each configuration item in the configuration information to the phase-locked loop 14 one by one based on the flow in Table 1 below, so as to configure the phase-locked loop 14.

[0172] Table 1

[0173] On the basis of FIG. 1, the embodiment of the present application provides the structural schematic diagram shown in FIG. 3. The internal structure and working principle of the switching module 13 for switching the configuration information are introduced as follows in combination with FIG. 3.

[0174] Referring to FIG. 3, the switching module 13 comprises a second multiplexer group 133 and a control unit 132. Correspondingly, the plurality of graphic processing modules 11, the control unit 132 and the phase-locked loop 14 are connected with the second multiplexer group 133. Under this structure, the control unit 132 is used to instruct the second multiplexer group 133 to output the configuration information received from the graphic processing module 11 corresponding to the target host; and the second multiplexer group 133 is used to output the configuration information from the graphic processing module 11 instructed by the control unit 132 in the received configuration information to the phase-locked loop 14.

[0175] The second multiplexer group 133 is a kind of combination logic circuit, and the second multiplexer group 133 has the function of selecting one way from multiple inputs as the output. In the embodiment of the present application, the input of the second multiplexer group 133 comprises the configuration information output by the plurality of graphic processing modules 11, and the output of the second multiplexer group 133 is one of the received multiple configuration information. The second multiplexer group 133 can determine which way of configuration information to output in response to the control signal input into the second multiplexer group 133.

[0176] The control unit 132 is configured to control the second multiplexer group 133 to output which configuration information. The control unit 132 controls the second multiplexer group 133 to switch among different configuration information by outputting different control signals to the second multiplexer group 133, so as to realize dynamic switching of the output of the second multiplexer group 133. In the case that the display device requests to switch the currently displayed system screen to the system screen of the target host, the control unit 132 triggers the control signal of the second multiplexer group 133 in response to the switching instruction, and the control signal instructs the second multiplexer group 133 to output the configuration information received from the graphic processing module 11 corresponding to the target host. Therefore, after the control unit 132 outputs the control signal to the second multiplexer group 133, the second multiplexer group 133 outputs the configuration information instructed by the control signal to the phase-locked loop 14 in response to the control signal, that is, outputs the configuration information received from the graphic processing module 11 corresponding to the target host to the phase-locked loop 14, so as to turn on the transmission path between the graphic processing module 11 corresponding to the target host and the phase-locked loop 14.

[0177] In the chip 10 shown in FIG. 3, the second multiplexer group 133 is arranged between the graphic processing module 11 and the phase-locked loop 14, and the control unit 132 dynamically switches which configuration information of the graphic processing module 11 is output to the phase-locked loop 14 by outputting different control signals to the second multiplexer group 133, so as to dynamically switch which transmission path between the graphic processing module 11 and the phase-locked loop 14 is turned on, which is beneficial to improve the flexibility and switching speed of the switching process.

[0178] Optionally, the second multiplexer group 133 includes at least one multiplexer. In a possible implementation, referring to FIG. 3, the second multiplexer group 133 includes a third multiplexer and a fourth multiplexer. Correspondingly, the plurality of graphic processing modules 11 and the control unit 132 are connected with the third multiplexer, and the third multiplexer, the control unit 132 and the phase-locked loop 14 are connected with the fourth multiplexer.

[0179] In this structure, the control unit 132 is configured to cache the configuration information of the target host corresponding graphics processing module 11, and output the cached configuration information to the fourth multiplexer; the control unit 132 is further configured to instruct the third multiplexer to output the configuration information received from the target host corresponding graphics processing module 11; the control unit 132 is further configured to instruct the fourth multiplexer to output the configuration information received from the control unit 132 if the phase-locked loop 14 is not configured, and to output the configuration information received from the third multiplexer if the phase-locked loop 14 is configured; the third multiplexer is configured to output the configuration information instructed by the control unit 132 from the received configuration information to the fourth multiplexer; and the fourth multiplexer is configured to output the configuration information instructed by the control unit 132 from the received configuration information to the phase-locked loop 14.

[0180] For ease of illustration, the configuration information cached by the control unit 132 is referred to as configuration information a, and the configuration information of the target host corresponding graphics processing module 11 is referred to as configuration information b. Although the configuration information a and the configuration information b are both obtained from the target host corresponding graphics processing module 11, the configuration information a and the configuration information b are not the configuration information at the same time. The difference between the configuration information a and the configuration information b is described in detail as follows: (1) the configuration information a is the configuration information before the start of switching, which means before the control unit 132 starts to execute the display switching process in response to the switching instruction, and before the phase-locked loop 14 starts to reconfigure the phase-locked loop 14. The configuration information a is cached in the control unit 132, and the configuration information a cached in the control unit 132 will not change during the configuration process of the phase-locked loop 14, so the configuration information a received by the fourth multiplexer is stable and unchanging. (2) The configuration information b is the configuration information after the start of switching, which means after the control unit 132 starts to execute the display switching process in response to the switching instruction, and after the phase-locked loop 14 starts to reconfigure the phase-locked loop 14. The configuration information b is stored in the target host corresponding graphics processing module 11, and the target host can change the configuration information stored in the graphics processing module 11 at any time, so the configuration information b can change dynamically, and the configuration information b stored in the graphics processing module 11 can change during the configuration process of the phase-locked loop 14, so the configuration information b received by the fourth multiplexer can change. If the target host changes the configuration information stored in the graphics processing module 11 during the configuration process of the phase-locked loop 14, the configuration information a input to the fourth multiplexer is different from the configuration information b. If the target host does not change the configuration information stored in the graphics processing module 11 during the configuration process of the phase-locked loop 14, the configuration information a input to the fourth multiplexer is the same as the configuration information b.

[0181] After the difference between the configuration information a and the configuration information b is understood, the working principle of the third multiplexer and the fourth multiplexer is introduced as follows.

[0182] The third multiplexer is used to select which configuration information of the graphic processing module 11 is output. The input of the third multiplexer includes multiple paths, each path input is the configuration information output by one of the graphic processing modules 11, and the output of the third multiplexer is one of the received multiple configuration information. The third multiplexer can determine which path configuration information is output in response to the control signal input into the third multiplexer. The third multiplexer is controlled by the control unit 132, and the control unit 132 indicates which path configuration information is output by the third multiplexer by outputting different control signals to the third multiplexer. In the case that the display device requests to switch the currently displayed system screen to the system screen of the target host, the control unit 132 triggers the control signal of the third multiplexer in response to the switching instruction, and the control signal indicates that the third multiplexer outputs the configuration information b received from the graphic processing module 11 corresponding to the target host. Therefore, after the control unit 132 outputs the control signal to the third multiplexer, the third multiplexer outputs the configuration information indicated by the control signal to the fourth multiplexer in response to the control signal, that is, outputs the configuration information b received from the graphic processing module 11 corresponding to the target host to the fourth multiplexer.

[0183] The fourth multiplexer is used to output the configuration information b received from the third multiplexer or the configuration information a received from the control unit 132 in different cases. The input of the fourth multiplexer includes two paths, one of which is the configuration information b output by the third multiplexer, and the other of which is the configuration information a output by the control unit 132, and the output of the fourth multiplexer is one of the two paths. The fourth multiplexer can determine which path of configuration information to output in response to a control signal input into the fourth multiplexer. The fourth multiplexer is also controlled by the control unit 132, which indicates which path of configuration information the fourth multiplexer outputs by outputting different control signals to the fourth multiplexer. In the case where the display device requests to switch the currently displayed system screen to the system screen of the target host, the control unit 132 needs to configure the phase-locked loop 14 according to the configuration information provided by the target host, so that the phase-locked loop 14 provides the clock signal required to obtain the system screen data of the target host for the target host corresponding graphics processing module 11. However, during the configuration process of the phase-locked loop 14, there is a possibility that the configuration information b output by the third multiplexer will change. If the configuration information b changes during the configuration process of the phase-locked loop 14, it will cause the configuration information received by the phase-locked loop 14 to be inaccurate, and thus cause the configuration process to fail. Based on this, the control process of the fourth multiplexer by the control unit 132 is divided into a phase-locked loop 14 not configured completion stage and a phase-locked loop 14 configuration completion stage. In the phase-locked loop 14 not configured completion stage, the configuration information b provided by the target host corresponding graphics processing module 11 in real time can change, and the configuration information a output by the control unit 132 will not change, so the control unit 132 outputs a control signal to the fourth multiplexer to indicate the fourth multiplexer to output the configuration information a received from the control unit 132 to the phase-locked loop 14, thereby avoiding configuration based on chaotic configuration information. In the phase-locked loop 14 configuration completion stage, the control unit 132 outputs a control signal to the fourth multiplexer to indicate the fourth multiplexer to output the configuration information b received from the third multiplexer to the phase-locked loop 14, that is, to output the configuration information of the target host corresponding graphics processing module 11, thereby returning the configuration right of the phase-locked loop 14 from the control unit 132 to the host.

[0184] The present scheme transfers the configuration right of the phase-locked loop 14 from the host to the control unit 132 when starting to switch the configuration information of the phase-locked loop 14, and returns the configuration right of the phase-locked loop 14 from the control unit 132 to the host after completing the switching of the configuration information of the phase-locked loop 14. In this way, it can be ensured that the configuration information provided to the phase-locked loop 14 during the configuration process of the phase-locked loop 14 is an accurate and unaltered set of information, which can improve the orderliness and accuracy of reconfiguring the phase-locked loop 14 and is beneficial to reduce the error rate of the configuration process.

[0185] In a possible implementation, the control unit 132 is configured to output each item in the cached configuration information to the fourth multiplexer one by one. That is, the configuration information includes a plurality of configuration items, and the control unit 132 configures the phase-locked loop 14 step by step, and the switching module 13 outputs the plurality of configuration items to the phase-locked loop 14 one by one, and at least one configuration item is output to the phase-locked loop 14 each time. The process in which the control unit 132 configures the phase-locked loop 14 step by step can refer to Table 1, and will not be described here again.

[0186] In another possible implementation, referring to FIG. 3, the switching module 13 further includes a plurality of configuration units 134, each of the plurality of graphic processing modules 11 is connected with a corresponding configuration unit 134, and the control unit 132 and the third multiplexer are connected with each configuration unit 134. In this structure, the plurality of graphic processing modules 11 are configured to output the configuration information before switching starts and the configuration information after switching starts to the corresponding configuration unit 134; the control unit 132 is configured to instruct each configuration unit 134 to output the configuration information after switching starts if the phase-locked loop 14 is configured successfully; the control unit 132 is further configured to instruct each configuration unit 134 to output the configuration information before switching starts if the phase-locked loop 14 is configured unsuccessfully; and the plurality of configuration units 134 are configured to output the configuration information indicated by the control unit 132 in the received configuration information to the third multiplexer.

[0187] The configuration information before switching starts refers to the configuration information before the control unit 132 starts to execute the display switching process in response to the switching instruction, and also refers to the configuration information before the phase-locked loop 14 starts to reconfigure the phase-locked loop 14. The configuration information after switching starts refers to the configuration information after the control unit 132 starts to execute the display switching process in response to the switching instruction, and also refers to the configuration information after the phase-locked loop 14 starts to reconfigure the phase-locked loop 14. Actually, the configuration information before switching starts is the same as the configuration information a, and the configuration information after switching starts is the same as the configuration information b.

[0188] The configuration unit 134 is configured to output the pre-switching configuration information or the post-switching configuration information received from the graphics processing module 11 in different situations. The fourth multiplexer has two inputs, one of which is the pre-switching configuration information output by the graphics processing module 11, and the other of which is the post-switching configuration information output by the graphics processing module 11. The output of the fourth multiplexer is one of the two inputs. The configuration unit 134 can determine which configuration information to output in response to a control signal input to the configuration unit 134. The configuration unit 134 is also controlled by the control unit 132, which instructs the configuration unit 134 to output which configuration information by outputting different control signals to the configuration unit 134. In the present embodiment, during the configuration of the phase-locked loop 14, the control unit 132 has the configuration right of the phase-locked loop 14, and the control unit 132 provides the cached configuration information to the phase-locked loop 14 for configuration. The configuration information cached by the control unit 132 is the pre-switching configuration information, so the configuration process of the phase-locked loop 14 uses the pre-switching configuration information. After the configuration is completed, the control unit 132 returns the configuration right of the phase-locked loop 14 to the target host, and the graphics processing module 11 corresponding to the target host provides the configuration information to the phase-locked loop 14 for configuration. However, during the configuration of the phase-locked loop 14, the target host can change the configuration information stored in the graphics processing module 11 at any time. If the configuration information of the graphics processing module 11 changes during the configuration, the post-switching configuration information is different from the configuration information currently used by the phase-locked loop 14, resulting in a change in the configuration information obtained by the phase-locked loop 14 when the configuration right of the phase-locked loop 14 is returned to the target host, and further resulting in an error. Based on this, the control unit 132 controls the configuration unit 134 to output the pre-switching configuration information or the post-switching configuration information to the third multiplexer according to the configuration state of the phase-locked loop 14, which is specifically divided into the following two situations.

[0189] The first situation is that if the configuration of the phase-locked loop 14 is successful, it indicates that the target host has not changed the configuration information of the graphics processing module 11, so the post-switching configuration information is consistent with the configuration information currently used by the phase-locked loop 14. Then the control unit 132 controls the configuration unit 134 to output the post-switching configuration information to the third multiplexer. In this case, when the configuration is completed, the configuration information output by the third multiplexer to the fourth multiplexer is the post-switching configuration information.

[0190] In the second case, if the configuration of the phase-locked loop 14 fails, it indicates that the target host has changed the configuration information of the graphics processing module 11, and thus the configuration information after the switch is inconsistent with the configuration information currently adopted by the phase-locked loop 14, and the configuration information before the switch is consistent with the configuration information currently adopted by the phase-locked loop 14. Then the control unit 132 controls the configuration unit 134 to output the configuration information before the switch to the third multiplexer. In this case, when the configuration is completed, the configuration information output by the third multiplexer to the fourth multiplexer is the configuration information before the switch.

[0191] By arranging the configuration unit 134 between the graphics processing module 11 and the third multiplexer, the configuration information before the switch or the configuration information after the switch can be output to the third multiplexer according to the configuration of the phase-locked loop 14, so as to ensure that the configuration information provided to the phase-locked loop 14 before and after the configuration right is returned to the host is consistent, thereby completing the seamless switch of the configuration right.

[0192] In another possible implementation, referring to FIG. 3, the configuration unit 134 includes a first register and a fifth multiplexer. Correspondingly, the graphics processing module 11, the third multiplexer, the control unit 132, and the first register are connected with the fifth multiplexer, and the graphics processing module 11 and the control unit 132 are connected with the first register. In this structure, the graphics processing module 11 is configured to output the configuration information before the switch to the first register and output the configuration information after the switch to the fifth multiplexer; the first register is configured to store the configuration information received from the graphics processing module 11 and output the stored configuration information to the fifth multiplexer; and the fifth multiplexer is configured to output the configuration information indicated by the control unit 132 from the received configuration information to the third multiplexer.

[0193] The first register is used to store the configuration information before the switch starts, and outputs the stored configuration information to the fifth multiplexer. Alternatively, the graphic processing module 11 outputs the configuration information to the first register periodically, and the first register stores the received configuration information in response to a control signal input to the first register. The first register can be controlled by the control unit 132, which indicates when the first register stores the received configuration information by outputting different control signals to the first register. In the embodiment of the present application, the control unit 132 triggers the control signal of the first register in response to the switch instruction, which indicates the first register to store the received configuration information. Therefore, after the control unit 132 outputs the control signal to the first register, the first register stores the currently received configuration information in response to the control signal, thereby storing the configuration information before the switch starts before the display switch process is performed, and then outputting the configuration information before the switch starts to the fifth multiplexer.

[0194] The fifth multiplexer is used to select the configuration information before the switch starts or the configuration information after the switch starts. The input of the fifth multiplexer includes two paths, one of which is the configuration information before the switch starts output by the first register, and the other of which is the configuration information after the switch starts output by the graphic processing module 11, and the output of the fifth multiplexer is one of the two inputs. The fifth multiplexer can determine which configuration information to output in response to a control signal input to the fifth multiplexer. The fifth multiplexer is also controlled by the control unit 132, which indicates which configuration information to output by outputting different control signals to the fifth multiplexer. If the phase-locked loop 14 is successfully configured, the configuration information after the switch starts is consistent with the configuration information currently used by the phase-locked loop 14, so the control unit 132 triggers the control signal indicating the output of the configuration information after the switch starts, and outputs the control signal to the fifth multiplexer. The fifth multiplexer outputs the configuration information after the switch starts to the third multiplexer in response to the control signal. If the phase-locked loop 14 fails to configure, the configuration information before the switch starts is consistent with the configuration information currently used by the phase-locked loop 14, so the control unit 132 triggers the control signal indicating the output of the configuration information before the switch starts, and outputs the control signal to the fifth multiplexer. The fifth multiplexer outputs the configuration information before the switch starts to the third multiplexer in response to the control signal.

[0195] The configuration unit 134 is designed to be composed of registers corresponding to the graphic processing modules 11 and multiplexers. The registers store the configuration information of the graphic processing modules 11 before switching, so as to realize backup of the configuration information before switching. The multiplexers control output of the configuration information before switching or the configuration information after switching, which is beneficial to improve flexibility and switching speed of the output configuration information.

[0196] In another possible implementation, referring to FIG. 3, the graphic processing modules 11 include second registers, and the switching module 13 further includes third registers. The second registers store the configuration information of the graphic processing modules 11. In this structure, the control unit 132 is configured to store the configuration information in the second registers into the third registers, and the third registers are configured to output the stored configuration information to the fourth multiplexers.

[0197] In the embodiment, each of the graphic processing modules 11 and the switching module 13 has a register. The switching module 13 stores the configuration information in the register of the graphic processing module 11 into its own register, so as to realize caching of the configuration information of the graphic processing module 11. On one hand, the configuration information of the graphic processing module 11 is backed up, so as to prevent errors caused by changes of the configuration information during switching. On the other hand, the reading speed of the configuration information is improved.

[0198] Based on the above-mentioned FIG. 3, the logic of performing display switching in the chip 10 is mainly that the control unit 132 controls the control signals of the multiplexers. In this case, the switching module 13 further includes a control register connected to each of the multiplexers and a control register connected to the first register. The control register connected to each of the multiplexers is configured to store a value of a control signal of the multiplexer, and the control register connected to the first register is configured to store a value of a control signal of the first register. The control unit 132 changes the values of the control registers, so as to output different control signals, and then controls the multiplexers to output data of which path and controls the first register to store the configuration information at which time.

[0199] As described above, the switching module 13 includes a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, and a first register. In the following, the control register connected to the first multiplexer is referred to as control register 1, the control register connected to the second multiplexer is referred to as control register 2, the control register connected to the third multiplexer is referred to as control register 3, the control register connected to the fourth multiplexer is referred to as control register 4, the control register connected to the fifth multiplexer is referred to as control register 5, and the control register connected to the first register is referred to as control register 6. Alternatively, the control registers 1-6 described above can be different registers or can be the same register, for example, the values of the control signals of the different multiplexers can be stored in different bits of the same register.

[0200] For the convenience of understanding, the processing logic when the display switching is not performed is described first below, taking the chip 10 including the first graphic processing module 11 and the second graphic processing module 11 as an example, and taking the display screen as the system screen corresponding to the first graphic processing module 11 as an example. When the display screen is the system screen corresponding to the first graphic processing module 11, the processing logic of the chip 10 is as follows:

[0201] 1. The first graphic processing module 11 stores the configuration information of the first graphic processing module 11 in the second register thereof, and the first graphic processing module 11 outputs the configuration information in the second register to the fifth multiplexer and the first register respectively.

[0202] 2. The control register 1 stores the value 0, triggers the control signal gpu_sel[0]_0, the control register 2 stores the value 1, triggers the control signal gpu_sel[1]_1, the control register 3 stores the value 0, triggers the control signal pll_sel_0, the control register 4 stores the value 0, triggers the control signal switch_sel_0, the control register 5 stores the value 0, stores the control signal switch_fail_0, and the control register 6 stores the value 0, triggers the control signal switch_begin_0. The configuration information currently stored in the third register is output to the fourth multiplexer. The configuration information stored in the third register is obtained by the control unit 132 in the second register corresponding to the first graphic processing module 11.

[0203] The control signal gpu_sel[0]_0 is the control signal of the first multiplexer, and the control signal gpu_sel[0]_0 is triggered when the configuration of the phase-locked loop 14 is completed. The control signal gpu_sel[0]_0 indicates that the first multiplexer outputs the system screen data received from the first graphic processing module 11.

[0204] The control signal gpu_sel[1]_1 is a control signal of the second multiplexer, and is triggered when the configuration of the phase-locked loop 14 is completed and the vertical synchronization signal generated by the first graphics processing module 11 is detected. The control signal gpu_sel[1]_1 instructs the second multiplexer to output the system screen data received from the first multiplexer.

[0205] The control signal pll_sel_0 is a control signal of the third multiplexer, and is triggered when the received switching instruction indicates that the system screen corresponding to the first graphics processing module 11 is to be displayed. The control signal pll_sel_0 instructs the third multiplexer to output the configuration information received from the fifth multiplexer corresponding to the first graphics processing module 11.

[0206] The control signal switch_sel_0 is a control signal of the fourth multiplexer, and is triggered when the configuration of the phase-locked loop 14 is completed. The control signal switch_sel_0 instructs the fourth multiplexer to output the configuration information received from the third multiplexer.

[0207] The control signal switch_fail_0 is a control signal of the fifth multiplexer, and is triggered when the configuration of the phase-locked loop 14 is successful. The control signal instructs the fifth multiplexer to output the configuration information received from the second register.

[0208] The control signal switch_begin_0 is a control signal of the first register, and is triggered when the configuration of the phase-locked loop 14 is completed. The control signal switch_begin_0 instructs the first register not to store the currently received configuration information.

[0209] 3、The first register, upon receiving the control signal switch_begin_0, does not store the configuration information received from the second register, but outputs the configuration information already stored in the first register to the fifth multiplexer. The fifth multiplexer receives the configuration information from the second register and the configuration information from the first register, and the fifth multiplexer outputs the configuration information received from the second register to the third multiplexer in response to the control signal switch_fail_0. The third multiplexer receives the configuration information from each fifth multiplexer, and the third multiplexer outputs the configuration information received from the fifth multiplexer corresponding to the first graphics processing module 11 to the fourth multiplexer in response to the control signal pll_sel_0. The fourth multiplexer receives the configuration information from the third multiplexer and the configuration information from the third register, and the fourth multiplexer outputs the configuration information received from the third multiplexer to the phase-locked loop 14 in response to the control signal switch_sel_0.

[0210] 4、The phase-locked loop 14 is configured based on the received configuration information to generate a clock signal, and the clock signal is input to the first graphics processing module 11 and the second graphics processing module 11. In this case, based on the above steps 1-3, the configuration information received by the phase-locked loop 14 is actually the configuration information in the second register of the first graphics processing module 11, i.e., the configuration information of the first graphics processing module 11. Then, the phase-locked loop 14 can generate the clock signal required by the first graphics processing module 11 based on the configuration information of the first graphics processing module 11.

[0211] 5、The first graphics processing module 11 obtains the system screen data of the host connected to the first graphics processing module 11 based on the clock signal received from the phase-locked loop 14, and outputs the system screen data to the first multiplexer. The first multiplexer receives the system screen data of the first graphics processing module 11 and the system screen data of the second graphics processing module 11, and the first multiplexer outputs the system screen data received from the first graphics processing module 11 to the second multiplexer in response to the control signal gpu_sel[0]_0. The second multiplexer receives the preset system screen data and the system screen data from the first multiplexer, and the second multiplexer outputs the system screen data received from the first multiplexer to the display interface 12 in response to the control signal gpu_sel[1]_1.

[0212] 6、The display interface 12 outputs the received system screen data, and in this case, the system screen data received by the display interface 12 is the system screen data of the first graphics processing module 11, so that the system screen data of the first graphics processing module 11 is finally output, thereby realizing the display of the system screen of the host connected to the first graphics processing module 11.

[0213] Further, the process of changing the value of the control register can be implemented based on the control unit 132, which can be a logic circuit or a controller running a switching program. That is, the process of switching the display picture can be implemented based on a logic circuit or a switching program. Switching the display picture based on a logic circuit is equivalent to implementing the switching process by hardware, and switching the display picture based on a switching program is equivalent to implementing the switching process by software. Accordingly, the process of switching the display picture includes the following two modes.

[0214] The first mode: the switching module 13 includes a logic circuit and a plurality of registers connected in sequence. Among them, the logic circuit is the control unit 132 described above. Under this structure, the logic circuit responds to the switching instruction to assign the first register to trigger the first control signal, and in response to the first control signal, the next register connected to the first register is assigned to trigger the next control signal. Wherein, the control signal is used to turn on the transmission path between the target host corresponding graphics processing module 11 and the display interface 12, so as to output the system picture data of the target host corresponding graphics processing module 11 to the display interface 12. In this way, the value of the register can be changed through the logic circuit, thereby realizing the hardware switching process.

[0215] Among them, the plurality of registers are the control registers 1-6 described above.

[0216] Taking the chip 10 including the first graphics processing module 11 and the second graphics processing module 11 as an example, and taking the display picture as the system picture corresponding to the first graphics processing module 11 as an example, when switching the display picture from the system picture corresponding to the first graphics processing module 11 to the system picture corresponding to the second graphics processing module 11 based on the logic circuit, the processing logic is as follows.

[0217] 1. The logic circuit receives the switching instruction, which indicates that the display picture is switched from the system picture corresponding to the first graphics processing module 11 to the system picture corresponding to the second graphics processing module 11. The logic circuit responds to the switching instruction and assigns the switch_direction register to 1. Wherein, the value of the switch_direction register is 0, indicating that the system picture corresponding to the first graphics processing module 11 is displayed, and the value of the switch_direction register is 1, indicating that the system picture corresponding to the second graphics processing module 11 is displayed.

[0218] 2. The logic circuit changes the value of the control register 1 to trigger the control signal gpu_sel[0]_0, and changes the value of the control register 2 to trigger the control signal gpu_sel[1]_0. The control signal gpu_sel[0]_0 is the control signal of the first multiplexer, and the control signal gpu_sel[0]_0 indicates the first multiplexer to output the system picture data received from the first graphic processing module 11. The control signal gpu_sel[1]_0 is the control signal of the second multiplexer, and the control signal gpu_sel[1]_0 indicates the second multiplexer to output the preset system picture data. By performing the step, the display picture of the display device is switched to the preset system picture indicated by the preset system picture data.

[0219] The logic circuit changes the value of the control register 4 to trigger the control signal switch_sel_1, and changes the value of the control register 3 to trigger the control signal pll_sel_1. The control signal pll_sel_1 is the control signal of the third multiplexer, and the control signal pll_sel_1 indicates the third multiplexer to output the configuration information received from the fifth multiplexer corresponding to the second graphic processing module 11. The control signal switch_sel_1 is the control signal of the fourth multiplexer, and the control signal switch_sel_1 indicates the fourth multiplexer to output the configuration information received from the third register corresponding to the control unit 132. By performing the step, the configuration right of the phase-locked loop 14 is given to the control unit 132.

[0220] 3. The logic circuit and the control registers 1-6 constitute a hardware state machine, as shown in FIG. 4. The hardware state machine completes the configuration switching of the phase-locked loop 14 by sequentially jumping to the following states.

[0221] (1) Idle state: the control signal switch_begin is 0, and the control signal pll2_cfg_fms_en is 0. The control signal switch_begin is 0 indicates that the configuration information of the phase-locked loop 14 is not started to be switched, and the control signal switch_begin is 1 indicates that the configuration information of the phase-locked loop 14 is started to be switched. The control signal pll2_cfg_fms_en is 0 indicates that the state machine is not working, and the control signal pll2_cfg_fms_en is 1 indicates that the state machine is working normally.

[0222] (2) First preparation state (prepare state): when the control signal swith_begin is switched to 1 and the control signal pll2_cfg_fms_en is switched to 1, the hardware state machine is switched from the idle state to the first preparation state. In the first preparation state, the hardware state machine judges whether the control signal gpu0_pd and the control signal gpu1_pd are 0 and the control signal gpu_bypass is 1. If yes, the next state is entered, and if not, it continues to wait until the control signal gpu0_pd and the control signal gpu1_pd are 0 and the control signal gpu_bypass is 1 are detected.

[0223] The control signal gpu0_pd is the power-down signal of the first graphics processing module 11, and the control signal gpu1_pd is the power-down signal of the second graphics processing module 11. The control signal gpu_bypass is 0, indicating that the current phase-locked loop 14 is in a configuration state, and the reference clock signal is output to the graphics processing module 11. The control signal gpu_bypass is 1, indicating that the current phase-locked loop 14 is in a non-configuration state, and the clock signal based on the configuration information is output to the graphics processing module 11. Therefore, detecting that the control signal gpu0_pd and the control signal gpu1_pd are 0 and the control signal gpu_bypass is 1 is equivalent to detecting that the phase-locked loop 14 is in a non-configuration state.

[0224] (3) Second preparation state (pre_step2 state): the hardware state machine assigns the control signal gpu_bypass to 0, so that the reference clock signal is output to the first graphics processing module 11 and the second graphics processing module 11.

[0225] (4) First configuration state (step2 state): the hardware state machine performs the register assignment process of step 2 in Table 1, so that the phase-locked loop 14 is powered down, and after completion, the next state is entered.

[0226] (5) Second configuration state (step3 state): the hardware state machine performs the register assignment process of step 3 in Table 2, so that each item in the configuration information is output to the phase-locked loop 14. Wherein, the control signal switch_direction is 1, then the hardware state machine stores the configuration information in the second register corresponding to the first graphics processing module 11 into the third register, and then performs 5us timing, and after the timing is completed, the next state is entered. It can be considered that after the timing is completed, the configuration information in the third register has been transferred to the phase-locked loop 14.

[0227] (6) Third configuration state (step 4 state): the hardware state machine performs the register assignment process of step 4 in Table 2, thereby powering on the phase-locked loop 14. In entering the third configuration state, the 5us timer in the second configuration state is cleared, and the control signal cnt_step3_5us_done is configured as 0. In the third configuration state, the hardware state machine assigns the control signal pll2_pd as 0, thereby powering on the phase-locked loop 14, and then enters the next state.

[0228] (7) Fourth configuration state (step 5 state): the hardware state machine performs the register assignment process of step 5 in Table 2, thereby determining whether the phase-locked loop 14 locks the clock signal. In the fourth configuration state, the state is waited for 20us, and the control signal lock is queried in a loop. If the control signal lock is 1 for three consecutive times, the next state is entered. If the query time exceeds 500us, a timeout is reported, and the idle state is returned.

[0229] (8) Fifth configuration state (step 6 state): the hardware state machine performs the register assignment process of step 6 in Table 2, and assigns the control signal gpu_bypass as 1 at the same time, and then enters the next state after completion.

[0230] (9) Judge state (judge state): the state is divided into the following two cases.

[0231] The first case, if the pll2_fms_judge_enable register is 1, the following logic is executed. The value of the control signal host_intervene is judged. If the control signal host_intervene is 1, it indicates that the configuration information of the graphics processing module 11 is changed by other hosts during the configuration process of the phase-locked loop 14, and the hardware state machine returns to the first preparation state, waits for the host to complete the configuration, and then starts the configuration process again. If the control signal host_intervene is 0, it indicates that the configuration information of the graphics processing module 11 is not changed by other hosts during the configuration process of the phase-locked loop 14, and the hardware state machine returns to the idle state, and assigns the control signal pll2_switch_status as 1, indicating that the configuration of the phase-locked loop 14 is completed.

[0232] In the second case, if the pll2_fms_judge_enable register is 0, the above-mentioned logic does not need to be executed, and the control signal pll2_switch_status is directly assigned a value of 1, indicating that the configuration of the phase-locked loop 14 is complete. After the configuration process is complete, if the control signal switch_fail is 1, it indicates that the configuration fails, i.e., the configuration information of the graphics processing module 11 is changed by another host during the configuration process of the phase-locked loop 14. If the control signal switch_fail is 0, it indicates that the configuration is successful, i.e., the configuration information of the graphics processing module 11 is not changed by another host during the configuration process of the phase-locked loop 14, and the process of switching the display can be restarted by re-triggering the switching instruction.

[0233] The value of the control signal switch_fail is also the value of the control register 5. When the control signal switch_fail is 0, it is recorded as a control signal switch_fail_0, which indicates that the fifth multiplexer outputs the configuration information received from the second register. When the control signal switch_fail is 1, it is recorded as a control signal switch_fail_1, which indicates that the fifth multiplexer outputs the configuration information received from the first register.

[0234] The value of the control signal swith_begin is also the value of the control register 6. When the control signal switch_begin is 0, it is recorded as a control signal switch_begin_0, which indicates that the first register does not need to store the currently received configuration information. When the control signal swith_begin is 0, it is recorded as a control signal switch_begin_1, which indicates that the first register stores the currently received configuration information.

[0235] It should be noted that the assignment process of each register described above is achieved through a logic circuit. When the value of a register in a state changes, the value of the register in the next state is automatically triggered to change based on the logic circuit, thereby achieving the switching process based on hardware.

[0236] 4、After the configuration switching of the phase-locked loop 14 is completed, the logic circuit changes the value of the control register 4 to trigger the control signal switch_sel_0, which indicates that the fourth multiplexer outputs the configuration information received from the third multiplexer. By performing this step, the configuration right of the phase-locked loop 14 is returned to the host computer. The logic circuit changes the value of the control register 1 to trigger the control signal gpu_sel[0]_1 and changes the value of the control register 2 to trigger the control signal gpu_sel[1]_0. The control signal gpu_sel[0]_1 is the control signal of the first multiplexer, which indicates that the first multiplexer outputs the system picture data received from the second graphics processing module 11. The control signal gpu_sel[1]_0 is the control signal of the second multiplexer, which indicates that the second multiplexer outputs the system picture data received from the first multiplexer. By performing this step, the display picture of the display device is switched to the system picture corresponding to the second graphics processing module 11.

[0237] 5、After the above process is completed, the current display is the system picture corresponding to the second graphics processing module 11, and the host computer corresponding to the second graphics processing module 11 can change the configuration information of the second graphics processing module 11 to adjust the resolution of the system picture corresponding to the second graphics processing module 11.

[0238] In the above scheme, during the display switching process, the logic circuit triggers the control signals by assigning values to the registers. The logic circuit automatically assigns values to the next register to trigger the next control signal according to the control signal, and so on. The logic circuit triggers multiple control signals in sequence, thereby controlling the output of the system picture data of the target host computer corresponding graphics processing module 11 to the display interface 12, and realizing display switching based on hardware. Since the speed of assigning values to the registers by hardware is very fast, the overall speed of display switching is improved.

[0239] The second mode: the switching module 13 includes a controller and multiple registers. In this structure, the controller runs a switching program, which reads and writes the multiple registers in sequence to trigger multiple control signals. The control signals are used to turn on the transmission path between the target host computer corresponding graphics processing module 11 and the display interface 12, and output the system picture data of the target host computer corresponding graphics processing module 11 to the display interface 12. In this way, the value of the register can be changed by the switching program in the controller, thereby realizing the software switching process.

[0240] Among them, the multiple registers are the control register 1 to the control register 6.

[0241] Taking the chip 10 including the first graphics processing module 11 and the second graphics processing module 11 as an example, taking the display screen as the system screen corresponding to the first graphics processing module 11 as an example, when the display screen is switched from the system screen corresponding to the first graphics processing module 11 to the system screen corresponding to the second graphics processing module 11 based on the controller, the processing logic is as follows. Wherein, when the control signal pll2_cfg_fms_en is 0, the switching process is realized by the controller.

[0242] 1. The controller receives a switching instruction indicating that the display screen is switched from the system screen corresponding to the first graphics processing module 11 to the system screen corresponding to the second graphics processing module 11. The controller reads the pll2_switch_allow register in response to the switching instruction. If the pll2_switch_allow register is 1, it indicates that the graphics processing module 11 is working normally at this time, and the phase-locked loop 14 is currently in a non-configuration state, and the switching process can be started. Then go to the next step; if the pll2_switch_allow register is 0, it indicates that the phase-locked loop 14 is currently in a configuration state, and needs to wait for the end of the phase-locked loop 14 configuration before starting the switching process.

[0243] 2. The controller reads the control register 6 through the switching program, writes the control register 6 as 1 to trigger the control signal switch_begin_1, and starts the configuration switching process of the phase-locked loop 14.

[0244] 3. The controller reads the control register 1 and the control register 2 through the switching program, the value of the control register 1 remains unchanged, and the control register 2 is written as 0 to trigger the control signal gpu_sel[1]_0. The control signal gpu_sel[1]_0 indicates that the second multiplexer outputs the preset system screen data.

[0245] 4. The controller reads the switch_direction register through the switching program and writes the switch_direction register as 1. Wherein, switch_direction is 1, indicating that the second graphics processing module 11 corresponding system screen is displayed.

[0246] 5、The controller reads bit

[0030] of the BMC_PLL_CFG_0 register through the switching program, writes 0 to bit

[0030] of the BMC_PLL_CFG_0 register, and bit

[0030] of the BMC_PLL_CFG_0 register is used to store the value of the control signal gpu_bypass. Writing 0 to bit

[0030] of the BMC_PLL_CFG_0 register, that is, assigning 0 to the control signal gpu_bypass, so as to output the reference clock signal to the first graphics processing module 11 and the second graphics processing module 11.

[0247] 6、The controller reads bit[29:26] and bit

[0024] of the BMC_PLL_CFG_0 register through the switching program, which is equivalent to executing step 2 in the above table 1.

[0248] 7、The controller reads bit

[0025] and bit[23:0] of the GPU1_PLL_INFO_0 register and bit[31:0] of the GPU1_PLL_INFO_1 register through the switching program, and writes them into the corresponding bits of the BMC_PLL_CFG_0 register and the BMC_PLL_CFG_1 register, which is equivalent to executing step 3 in the above table 1. After executing this step, wait for 5us, and then execute the next step.

[0249] Among them, the GPU1_PLL_INFO_0 register is the second register corresponding to the second graphics processing module 11, and the BMC_PLL_CFG_0 register is the third register, so as to realize storing the configuration information of the second graphics processing module 11 into the third register of the switching module 13.

[0250] 8、The controller reads bit

[0024] of the BMC_PLL_CFG_0 register through the switching program, writes 0 to bit

[0024] of the BMC_PLL_CFG_0 register, which is equivalent to executing step 4 in the above table 1.

[0251] 9、Wait for 100us, and then execute the next step. Among them, after waiting for 100us, it is defaulted that the phase-locked loop 14 has locked the clock signal, and this step is equivalent to step 5 in the above table 1.

[0252] 10、The controller reads bit[29:26] and bit

[0030] of the BMC_PLL_CFG_0 register through the switching program, writes 0 to bit[29:26] of the BMC_PLL_CFG_0 register, and writes 1 to bit

[0030] of the BMC_PLL_CFG_0 register, which is equivalent to executing step 6 in the above table 1.

[0253] 11. The controller reads the switch_end register through the switching program, and writes the switch_end register as 1, indicating that the configuration of the phase-locked loop 14 is completed.

[0254] 12. The controller reads the pll2_switch_status register through the switching program, and when the pll2_switch_status register is 1, it indicates that the switching is successful, and then the next step is entered; when the pll2_switch_status register is 0, it indicates that the switching fails, and then the configuration switching process of the phase-locked loop 14 is re-executed.

[0255] 13. The controller reads the control register 1 and the control register 2 through the switching program, writes the value of the control register 1 as 1 to trigger the control signal gpu_sel[0]_1, and writes the control register 2 as 1 to trigger the control signal gpu_sel[1]_1. The control signal gpu_sel[0]_1 indicates that the first multiplexer outputs the system picture data received from the second graphics processing module 11. The control signal gpu_sel[1]_1 indicates that the second multiplexer outputs the system picture data received from the first multiplexer.

[0256] 14. After the above process is completed, the current display is the system picture corresponding to the second graphics processing module 11, and the host corresponding to the second graphics processing module 11 can change the configuration information of the second graphics processing module 11 to adjust the resolution of the system picture corresponding to the second graphics processing module 11.

[0257] It should be noted that the reading and writing processes of each of the above registers are realized by the switching program running on the controller, and the values of each register are read and written in sequence according to the switching program, so as to realize the switching process based on software.

[0258] In the above scheme, during the display switching process, the registers are read and written in sequence according to the instructions preset in the switching program to trigger the control signals, so as to control the output of the system picture data of the graphics processing module 11 corresponding to the target host to the display interface 12, thereby realizing the display switching based on software. Since the software has configurability, the control logic can be adjusted by changing the code or configuration, thereby providing higher flexibility for the control process of display switching, so that the control process of display switching can adapt to different scenes and requirements, and is more easily realized in a customized control mode.

[0259] The above chip can be applied in various scenes, and the graphics processing module 11 in the chip 10 can be connected to hosts in different scenes. Two scenes are introduced below.

[0260] The first scenario is shown in FIG. 5. The chip 10 further includes a processor 15. Each of the plurality of graphic processing modules 11 is connected to a host on the processor 15.

[0261] The chip 10 can be applied to an industrial control scenario. In the industrial control scenario, the chip 10 can be used as a master chip in a computing device for control. For example, the chip 10 can be installed in a robot and used as a master chip of the robot for control.

[0262] In this scenario, the hosts connected by the plurality of graphic processing modules 11 in the chip 10 are located on the chip 10. That is, each of the plurality of graphic processing modules 11 in the chip 10 is connected to the same host inside the chip 10. The host can provide different system picture data for each graphic processing module 11, so as to realize switching display of different system pictures on the same host, and make the chip 10 applicable to the use requirement of dual-screen switching or more screen switching of the same host.

[0263] The second scenario is shown in FIG. 6. The chip 10 is connected to a plurality of master chips 20. Each of the plurality of graphic processing modules 11 is connected to a host on a master chip 20. For ease of display, two master chips 20 are connected in FIG. 6.

[0264] The chip 10 can be applied to a server scenario. In the server scenario, the chip 10 and other master chips 20 are installed on a server. The chip 10 can be used as a management chip for management of the master chips 20 on the server.

[0265] In this scenario, the hosts connected by the plurality of graphic processing modules 11 in the chip 10 are located on other master chips 20 outside the chip 10. Each of the graphic processing modules 11 is connected to a host on a different master chip 20. The hosts connected by different graphic processing modules 11 are different. Therefore, one chip 10 can provide services for a plurality of different master chips 20, realize switching display of system pictures of the hosts of the plurality of different master chips 20, and does not need to deploy a chip for each master chip 20, thereby saving the number of chips, saving resource cost, and saving deployment space.

[0266] The embodiment of the present application provides a server single board. The server single board includes a circuit board and a management chip and a master chip installed on the circuit board. The management chip includes a plurality of graphic processing modules, a display interface and a switching module. The management chip further includes an interface corresponding to each graphic processing module. The interface corresponding to the graphic processing module is used to connect the graphic processing module to a host on any master chip. Each of the plurality of graphic processing modules is connected to the display interface. The display interface and the plurality of graphic processing modules are connected to the switching module.

[0267] a plurality of graphic processing modules, respectively connected with the plurality of hosts, for outputting system picture data of the host connected with each of the graphic processing modules to the switching module;

[0268] a switching module, for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and conducting a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output the system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed;

[0269] a display interface, for outputting the system picture data received from the switching module.

[0270] The internal structure and processing logic of the management chip are the same as those of the chips shown in FIGS. 1-3, and will not be described in detail here.

[0271] The embodiments of the present application also provide a server cabinet, which comprises a cabinet body, the cabinet body comprises a back plate, the server cabinet further comprises a plurality of server single boards installed on the back plate, the server single boards are installed with master control chips, the plurality of server single boards are installed with one management chip, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, each of the graphic processing modules is connected with a host on one master control chip; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module.

[0272] a plurality of graphic processing modules, respectively connected with the plurality of hosts, for outputting system picture data of the host connected with each of the graphic processing modules to the switching module;

[0273] a switching module, for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and conducting a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output the system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed;

[0274] a display interface, for outputting the system picture data received from the switching module.

[0275] The internal structure and processing logic of the management chip are the same as those of the chips shown in FIGS. 1-3, and will not be described in detail here.

[0276] The embodiment of the present application provides a display system, the display system comprises a server cabinet and a display device, the server cabinet comprises a plurality of server single boards, the server single boards are installed with master control chips, the plurality of server single boards are installed with a same management chip, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, each graphic processing module is connected with a host on the master control chip, and the display interface is connected with the display device; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module;

[0277] The plurality of graphic processing modules are connected with the plurality of hosts respectively, and are used for outputting system picture data of the host connected to the switching module;

[0278] The switching module is used for selecting the graphic processing module corresponding to the target host from the plurality of graphic processing modules in response to a switching instruction, and conducting a transmission path between the graphic processing module corresponding to the target host and the display interface, so that the system picture data of the graphic processing module corresponding to the target host is output to the display interface, and the target host is a host corresponding to a system picture to be displayed;

[0279] The display interface is used for outputting the system picture data received from the switching module.

[0280] The internal structure and processing logic of the management chip are the same as those of the chip shown in FIGS. 1-3, and will not be described in detail here.

[0281] FIG. 7 is a flowchart of a display method provided by the embodiment of the present application, the display method is applied to a chip, and the chip can be the chip shown in FIGS. 1-3. As shown in FIG. 7, the method comprises the following steps.

[0282] 701, receiving system picture data of a first host and system picture data of a second host, and receiving configuration information of the first host and configuration information of the second host.

[0283] The system picture data of the first host is used for presenting a system picture of the first host, and the system picture data of the second host is used for presenting a system picture of the second host. The system picture data of the first host and the system picture data of the second host are different, and the chip has the capability of receiving different system picture data. In the embodiment of the present application, the chip can output one of the two routes of system picture data, one of which is the system picture data of the first host, and the other of which is the system picture data of the second host, to display the system picture of one of the hosts.

[0284] The configuration information of the host is used to configure a phase-locked loop, and the phase-locked loop is used to generate a clock signal required by a graphic processing module based on the configuration information, and the graphic processing module acquires system picture data based on the clock signal. Wherein, the phase-locked loop can generate different clock signals based on different configuration information, and the graphic processing module can acquire system picture data with different resolutions based on different clock signals. Therefore, by changing the configuration information provided for the phase-locked loop, the resolution of the acquired system picture data can be changed. In the embodiment of the application, the first host can configure the resolution of the system picture data of the first host by providing configuration information, and the second host can configure the resolution of the system picture data of the second host by providing configuration information.

[0285] Optionally, the graphic processing module used to acquire the system picture data of the first host and the graphic processing module used to acquire the system picture data of the second host share one phase-locked loop, and then the chip can provide the configuration information of the host corresponding to the current system picture to be displayed to the phase-locked loop after receiving the configuration information of the two hosts.

[0286] Optionally, the first host and the second host can be hosts inside the chip, in which case, the first host and the second host can be the same host, and the chip acquires two different system picture data provided by the same host.

[0287] Optionally, the first host and the second host can also be hosts of other master control chips outside the chip, in which case, the first host and the second host are hosts of different master control chips.

[0288] 702、in response to a display instruction of the display device, the chip outputs the system picture data of the first host to the display device.

[0289] Wherein, the display instruction indicates to display the system picture of the first host, and then the chip provides the system picture data of the first host to the display device, and the display device displays the system picture of the first host based on the system picture data of the first host.

[0290] 703、receiving a switching instruction of the display device, the switching instruction is used to switch the display picture of the display device from the system picture of the first host to the system picture of the second host.

[0291] Wherein, the switching instruction of the display device is triggered based on user operation.

[0292] For example, a picture switching option is displayed on the display device, and in response to the triggering operation of the picture switching option, the display device generates the switching instruction and sends the switching instruction to the chip.

[0293] 704、in response to the switching instruction, the phase-locked loop is configured based on the configuration information of the second host.

[0294] Since the display needs to switch the display screen to the system screen of the second host, the configuration information of the phase-locked loop needs to be updated, and the configuration information used by the phase-locked loop is switched from the configuration information of the first host to the configuration information of the second host. The process of switching the configuration information used by the phase-locked loop from the configuration information of the first host to the configuration information of the second host is realized by the control unit, the configuration unit, the third multiplexer and the fourth multiplexer in the above embodiment. The control unit, the configuration unit, the third multiplexer and the fourth multiplexer can turn on the transmission path for transmitting the configuration information of the first host to the phase-locked loop.

[0295] In a possible implementation, in response to the switching instruction, the configuration information of the second host is cached, and the phase-locked loop is configured based on the cached configuration information; and if the configuration of the phase-locked loop is completed, the phase-locked loop is configured based on the configuration information of the second host.

[0296] In the switching process, the configuration information of the second host may change, which may cause a configuration error. To avoid this problem, the configuration information of the second host is cached before the phase-locked loop is configured. Since the cached configuration information does not change, the phase-locked loop is configured based on the cached configuration information, which can ensure the smooth progress of the configuration process of the phase-locked loop. After the configuration is completed, the phase-locked loop is configured based on the configuration information of the second host.

[0297] In this scheme, the configuration information of the second host is cached in advance. By providing the cached configuration information to the phase-locked loop, it can be ensured that the configuration information provided to the phase-locked loop in the configuration process of the phase-locked loop is a set of accurate and unaltered information, which can improve the orderliness and accuracy of reconfiguring the phase-locked loop and is beneficial to reducing the error rate of the configuration process.

[0298] Optionally, if the configuration of the phase-locked loop is successful, the phase-locked loop is configured based on the configuration information of the second host after the switching starts; and if the configuration of the phase-locked loop fails, the phase-locked loop is configured based on the configuration information of the second host before the switching starts.

[0299] If the configuration of the phase-locked loop is successful, it indicates that the configuration information of the second host does not change in the switching process, and the configuration information of the second host after the switching starts is the same as the cached configuration information, that is, the configuration information of the second host after the switching starts is the same as the current configuration information used by the phase-locked loop. Therefore, the phase-locked loop is configured based on the configuration information of the second host after the switching starts.

[0300] If the configuration of the phase-locked loop fails, it indicates that the configuration information of the second host changes during the switching process, the configuration information of the second host before the start of the switching is the same as the buffered configuration information, that is, the configuration information of the second host before the start of the switching is the same as the configuration information currently used by the phase-locked loop, and therefore the phase-locked loop is configured based on the configuration information of the second host before the start of the switching.

[0301] In the scheme, after the configuration of the phase-locked loop is completed, the configuration information before the start of the switching or the configuration information after the start of the switching is provided to the phase-locked loop according to the configuration of the phase-locked loop, so as to ensure that the configuration information provided to the phase-locked loop before and after the configuration right is returned to the host is consistent, thereby completing the seamless switching of the configuration right.

[0302] In a possible implementation, in response to the switching instruction, the state of the phase-locked loop is detected, if the phase-locked loop is in the non-configuration state, the phase-locked loop is configured based on the configuration information of the second host. If the phase-locked loop is in the configuration state, the state of the phase-locked loop is continuously detected until the phase-locked loop is in the non-configuration state, and then the step of configuring the phase-locked loop based on the configuration information of the second host is performed.

[0303] In the scheme, the condition for reconfiguring the phase-locked loop includes that the phase-locked loop is in the non-configuration state, so as to prevent the reconfiguration of the phase-locked loop from being started when the host is in the configuration state, thereby preventing the original configuration progress of the phase-locked loop from being disturbed, and ensuring the orderly progress of the configuration process of the phase-locked loop, which is beneficial to reduce the error rate in the display switching process.

[0304] In a possible implementation, if the configuration of the phase-locked loop is not completed, the phase-locked loop is controlled to output a reference clock signal to the graphics processing module; if the configuration of the phase-locked loop is completed, the phase-locked loop is controlled to output a clock signal obtained after the completion of the configuration to the graphics processing module.

[0305] In the scheme, the reconfiguration of the phase-locked loop is started when the switching is started, and the phase-locked loop cannot output a stable clock signal during the configuration process, and therefore a reference clock signal is provided to the graphics processing module to ensure the normal progress of the internal processing logic of the graphics processing module. After the configuration is completed, the phase-locked loop can output a stable clock signal, and therefore a stable clock signal is provided to the graphics processing module, so that the graphics processing module generates accurate system picture data based on the accurate clock signal, thereby ensuring the realizability and orderliness of the entire display switching process.

[0306] It should be noted that the embodiments of the present application only take the configuration information of the first host and the configuration information of the second host as examples to illustrate the process of switching the configuration information of the phase-locked loop from the configuration information of the first host to the configuration information of the second host. In another embodiment, the configuration information of the first host and the configuration information of the second host can be the same, and then the above step 704 need not be performed.

[0307] 705、in response to the switching instruction, the control chip outputs the system picture data of the second host to the display device.

[0308] The process of switching the system picture data output by the display device from the system picture data of the first host to the system picture data of the second host is realized by the control unit, the first multiplexer and the second multiplexer in the above embodiments. The transmission path for transmitting the system picture data of the second host to the display device can be turned on by the control unit, the first multiplexer and the second multiplexer.

[0309] In a possible implementation, in response to the switching instruction, the phase-locked loop is started to be reconfigured to make the phase-locked loop provide the clock signal of the system picture data of the second host; during the configuration process, the control chip outputs the data of a preset system picture to the display device; and if the configuration of the phase-locked loop is completed, the control chip outputs the system picture data of the second host to the display device.

[0310] Optionally, if the configuration of the phase-locked loop is completed and the vertical synchronization signal is detected, the control chip outputs the system picture data of the second host to the display device; wherein the vertical synchronization signal indicates that a complete frame of the system picture data of the second host has been acquired.

[0311] In the present solution, the completion of the configuration of the phase-locked loop means that the system picture data currently received by the second multiplexer is accurate, and the detection of the vertical synchronization signal means that the graphic processing module has output a frame of system picture data, i.e. is about to output the next frame of system picture data. Therefore, when the above two conditions are met, the logic of outputting the system picture data of the second host is executed, so that the system picture with errors can be avoided, and the system picture displayed is a complete frame of system picture, thereby improving the switching effect of display.

[0312] In the embodiments of the present application, the chip receives the system picture data of the two hosts, and when the switching instruction is received, the system picture data of the first host is switched to the system picture data of the second host by the processing logic in the chip, so that the display device is switched from displaying the system picture of the first host to displaying the system picture of the second host. Therefore, the present application can switch the display of different system pictures on the display device by using only one chip, and does not need to externally connect a KVM switch. The switching logic can be completed in the chip, thereby reducing the cost and saving resources.

[0313] The terms "first", "second", and the like in the present application are used to distinguish between similar or identical items or elements having substantially the same function and should be understood as not having a logical or chronological dependency between "first", "second", "n-th", and the like. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described examples, a first operator can be called a second operator, and similarly, a second operator can be called a first operator. The first operator and the second operator can both be operators, and in some cases, can be separate and distinct operators.

[0314] The term "at least one" in the present application means one or more, and the term "a plurality" in the present application means two or more, for example, a plurality of operators means two or more operators.

[0315] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0316] In the above-described embodiments, all or part can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part can be implemented in the form of program structure information. The program structure information includes one or more program instructions. When the program instructions are loaded and executed on a computing device, all or part of the processes or functions in the embodiments of the present application are produced.

[0317] A person of ordinary skill in the art can understand that all or part of the steps of the above-described embodiments can be completed by hardware, or by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0318] The above-described embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized by The chip comprises a plurality of graphic processing modules, a display interface and a switching module, the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are connected with a plurality of hosts respectively, and are used for outputting system picture data of the host connected respectively to the switching module; The switching module is used for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and conducting a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, wherein the target host is a host corresponding to a system picture to be displayed; The display interface is used for outputting the system picture data received from the switching module.

2. The chip according to claim 1, characterized in that, The switching module comprises a first multiplexer group and a control unit, the plurality of graphic processing modules, the control unit and the display interface are connected with the first multiplexer group; The control unit is used for controlling the first multiplexer group to output system picture data from the graphic processing module indicated by the control unit in the received system picture data to the display interface in response to the switching instruction.

3. The chip of claim 2, wherein, The first multiplexer group comprises a first multiplexer and a second multiplexer, the plurality of graphic processing modules and the control unit are connected with the first multiplexer, and the first multiplexer, the control unit and the display interface are connected with the second multiplexer; The control unit is used for instructing the first multiplexer to output system picture data received from the graphic processing module corresponding to the target host in response to the switching instruction; The control unit is also used for instructing the second multiplexer to output preset system picture data if a phase-locked loop is not configured, and instructing the second multiplexer to output system picture data received from the first multiplexer if the phase-locked loop is configured, wherein the phase-locked loop is used for providing a clock signal to the plurality of graphic processing modules; The first multiplexer is used for outputting the system picture data indicated by the control unit in the received system picture data to the second multiplexer; The second multiplexer is used for outputting the system picture data indicated by the control unit in the received system picture data to the display interface.

4. The chip of claim 3, wherein The plurality of graphic processing modules are also used for outputting a vertical synchronization signal to the control unit after outputting a frame of system picture data; The control unit is used for instructing the second multiplexer to output system picture data received from the first multiplexer if the phase-locked loop is configured and the vertical synchronization signal of the graphic processing module corresponding to the target host is received.

5. The chip of claim 1, wherein The chip further comprises a phase-locked loop, and the plurality of graphic processing modules are connected with the phase-locked loop, and the phase-locked loop is connected with the switching module; The plurality of graphic processing modules are configured to output system picture data to the switching module based on the received clock signal, and output configuration information provided by the host connected thereto to the switching module. The switching module is further configured to turn on a transmission path between the graphic processing module corresponding to the target host and the phase-locked loop, so as to output the configuration information of the graphic processing module corresponding to the target host to the phase-locked loop. The phase-locked loop is configured to be configured by the configuration information received from the switching module, and output a clock signal to the plurality of graphic processing modules.

6. The chip of claim 5, wherein, The switching module comprises a second multiplexer group and a control unit, and the plurality of graphic processing modules, the control unit and the phase-locked loop are connected to the second multiplexer group. The control unit is configured to instruct the second multiplexer group to output the configuration information received from the graphic processing module corresponding to the target host. The second multiplexer group is configured to output the configuration information from the graphic processing module instructed by the control unit in the received configuration information to the phase-locked loop.

7. The chip of claim 6, wherein The second multiplexer group comprises a third multiplexer and a fourth multiplexer, the plurality of graphic processing modules and the control unit are connected to the third multiplexer, and the third multiplexer, the control unit and the phase-locked loop are connected to the fourth multiplexer. The control unit is configured to cache the configuration information of the graphic processing module corresponding to the target host, and output the cached configuration information to the fourth multiplexer. The control unit is further configured to instruct the third multiplexer to output the configuration information received from the graphic processing module corresponding to the target host. The control unit is further configured to instruct the fourth multiplexer to output the configuration information received from the control unit if the phase-locked loop is not configured, and instruct the fourth multiplexer to output the configuration information received from the third multiplexer if the phase-locked loop is configured. The third multiplexer is configured to output the configuration information instructed by the control unit in the received configuration information to the fourth multiplexer. The fourth multiplexer is configured to output the configuration information instructed by the control unit in the received configuration information to the phase-locked loop.

8. The chip of claim 7, wherein, The control unit is configured to output each item of the cached configuration information to the fourth multiplexer one by one.

9. The chip of claim 7, wherein, The switching module further comprises a plurality of configuration units, each of the graphic processing modules is connected to a corresponding configuration unit, and the control unit and the third multiplexer are connected to each of the configuration units. The plurality of graphic processing modules are configured to output configuration information before switching and configuration information after switching to the configuration unit connected thereto. The control unit is configured to instruct each of the configuration units to output the configuration information after switching if the phase-locked loop is configured successfully. The control unit is further configured to instruct each of the configuration units to output the configuration information before switching if the phase-locked loop is configured unsuccessfully. The plurality of configuration units are configured to output the configuration information indicated by the control unit in the received configuration information to the third multiplexer.

10. The chip of claim 9, wherein, The configuration unit comprises a first register and a fifth multiplexer, the graphic processing module, the third multiplexer, the control unit and the first register are connected with the fifth multiplexer, and the graphic processing module and the control unit are connected with the first register. The graphic processing module is configured to output configuration information before switching to the first register and output configuration information after switching to the fifth multiplexer. The first register is configured to store the configuration information received from the graphic processing module and output the stored configuration information to the fifth multiplexer. The fifth multiplexer is configured to output the configuration information indicated by the control unit in the received configuration information to the third multiplexer.

11. The chip of claim 7, wherein, The graphic processing module comprises a second register, and the switching module further comprises a third register, and the second register stores configuration information of the graphic processing module. The control unit is configured to store the configuration information in the second register to the third register. The third register is configured to output the stored configuration information to the fourth multiplexer.

12. The chip of claim 5, wherein, The switching module is configured to detect the state of the phase-locked loop, and if the phase-locked loop is in a non-configuration state, turn on the transmission path between the graphic processing module corresponding to the target host and the phase-locked loop to output the configuration information of the graphic processing module corresponding to the target host to the phase-locked loop.

13. The chip of claim 5, wherein, The switching module is configured to control the phase-locked loop to output a reference clock signal to the plurality of graphic processing modules if the phase-locked loop is not configured. The switching module is configured to control the phase-locked loop to output a clock signal generated after configuration to the plurality of graphic processing modules if the phase-locked loop is configured.

14. The chip of claim 1, wherein, The switching module comprises a logic circuit and a plurality of registers connected in sequence. The logic circuit is configured to assign a first register to trigger a first control signal, and in response to the first control signal, assign a next register connected to the first register to trigger a next control signal; wherein the control signal is used to turn on the transmission path between the graphic processing module corresponding to the target host and the display interface to output system picture data of the graphic processing module corresponding to the target host to the display interface.

15. The chip of claim 1, wherein, The switching module comprises a controller and a plurality of registers. The controller is configured to run a switching program, and read and write the plurality of registers in sequence through the switching program to trigger a plurality of control signals; wherein the control signal is used to turn on the transmission path between the graphic processing module corresponding to the target host and the display interface to output system picture data of the graphic processing module corresponding to the target host to the display interface.

16. The chip of claim 1, wherein, The chip comprises a processor, and the plurality of graphic processing modules are connected with the host on the processor.

17. The chip of claim 1, wherein, The chip is connected with a plurality of master control chips, and the plurality of graphic processing modules are respectively connected with the host on one master control chip.

18. A server single board, characterized by The server single board comprises a circuit board and a management chip and a master control chip mounted on the circuit board, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, the management chip further comprises an interface corresponding to each graphic processing module, and the interface corresponding to the graphic processing module is used for connecting the graphic processing module with a host on any master control chip; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are respectively connected with a plurality of hosts, and are used for outputting system picture data of the host connected with each graphic processing module to the switching module; The switching module is used for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and turning on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, wherein the target host is a host corresponding to a system picture to be displayed; The display interface is used for outputting the system picture data received from the switching module.

19. A server cabinet characterized by The server cabinet comprises a cabinet body, the cabinet body comprises a back plate, and the server cabinet further comprises a plurality of server single boards mounted on the back plate, the server single boards are mounted with master control chips, the plurality of server single boards are mounted with the same management chip, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, each graphic processing module is connected with a host on a master control chip; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are respectively connected with a plurality of hosts, and are used for outputting system picture data of the host connected with each graphic processing module to the switching module; The switching module is used for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and turning on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, wherein the target host is a host corresponding to a system picture to be displayed; The display interface is used for outputting the system picture data received from the switching module.

20. A display system, comprising: The display system comprises a server cabinet and a display device, the server cabinet comprises a plurality of server single boards, the server single boards are mounted with master control chips, the plurality of server single boards are mounted with the same management chip, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, each graphic processing module is connected with a host on a master control chip, and the display interface is connected with the display device; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are connected with a plurality of hosts respectively, and are configured to output system picture data of the host connected therewith to the switching module; The switching module is configured to select a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and to turn on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed; The display interface is configured to output the system picture data received from the switching module.

21. A display method characterized by comprising: The method is applied to a chip, and the method comprises: receiving system picture data of a first host and system picture data of a second host; in response to a display instruction of a display device, controlling the chip to output the system picture data of the first host to the display device; receiving a switching instruction of the display device, the switching instruction being used to switch a display picture of the display device from the system picture of the first host to the system picture of the second host; in response to the switching instruction, controlling the chip to output the system picture data of the second host to the display device.

22. The method of claim 21, wherein, The response to the switching instruction and the control of the chip to output the system picture data of the second host to the display device comprise: in response to the switching instruction, starting reconfiguration of a phase-locked loop, so that the phase-locked loop provides a clock signal of the system picture data of the second host; in a configuration process, controlling the chip to output data of a preset system picture to the display device; if the phase-locked loop is configured, controlling the chip to output the system picture data of the second host to the display device.

23. The method of claim 22, wherein, The control of the chip to output the system picture data of the second host to the display device if the phase-locked loop is configured comprises: if the phase-locked loop is configured and a vertical synchronization signal is detected, controlling the chip to output the system picture data of the second host to the display device; wherein the vertical synchronization signal indicates that a complete frame of system picture data of the second host has been acquired.

24. The method of claim 21, wherein, The method further comprises: receiving configuration information of the first host and configuration information of the second host; in response to the switching instruction, configuring the phase-locked loop based on the configuration information of the second host.

25. The method of claim 24, wherein, The response to the switching instruction and the configuration of the phase-locked loop based on the configuration information of the second host comprise: in response to the switching instruction, buffering the configuration information of the second host, and configuring the phase-locked loop based on the buffered configuration information; if the phase-locked loop is configured, configuring the phase-locked loop based on the configuration information of the second host.

26. The method of claim 25, wherein, The configuration of the phase-locked loop based on the configuration information of the second host comprises: if the phase-locked loop is configured successfully, configuring the phase-locked loop based on configuration information of the second host after the switching starts, and if the phase-locked loop is configured unsuccessfully, configuring the phase-locked loop based on configuration information of the second host before the switching starts.

27. The method of claim 24, wherein, The response to the switching instruction, based on the configuration information of the second host, configuring a phase-locked loop, comprising: In response to the switching instruction, detecting the state of the phase-locked loop, if the phase-locked loop is in a non-configuration state, configuring the phase-locked loop based on the configuration information of the second host.

28. The method of claim 24, wherein, The method further comprises: If the phase-locked loop is not configured, the phase-locked loop is controlled to output a reference clock signal to the graphics processing module; If the phase-locked loop is configured, the phase-locked loop is controlled to output a clock signal obtained after configuration to the graphics processing module.

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