Accelerator card, server system, data processing method and related device

Abstract

The present application provides an accelerator card, a server system, a data processing method, and a related device. The accelerator card comprises: a plurality of partitions (101), each partition (101) comprising an operator unit (201) for data acceleration, and at least two partitions (101) having different acceleration functions; an interface unit (102), the interface unit (102) being used for connecting to an external processing device, and receiving an acceleration task input by the external processing device; and an input processing unit (103), the input processing unit (103) being connected to the interface unit (102) and the partitions (101), and being used for determining a target partition on the basis of the acceleration task, and sending task data of the acceleration task to the target partition.

Description

Accelerator card, server system, data processing method and related device

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 2024112265774, filed on September 3, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of information technology, and in particular to an accelerator card, a server system, a data processing method and related device. BACKGROUND

[0004] An accelerator card is a hardware component specially designed to improve the performance of a computer system, mainly used to accelerate data processing tasks. The accelerator card in the related art is usually designed to process a corresponding acceleration function for a certain specific acceleration application, and cannot meet the needs of other acceleration functions, making the accelerator card less versatile. SUMMARY

[0005] Embodiments of the present application provide an accelerator card, a server system, a data processing method and related device.

[0006] In a first aspect, an embodiment of the present application provides an accelerator card, comprising: a plurality of partitions, each of the partitions comprising an operator unit for data acceleration, and the acceleration functions of at least two of the partitions being different; an interface unit, the interface unit being configured to connect to an external processing device and receive an acceleration task input by the external processing device; an input processing unit, the input processing unit being connected to the interface unit and the partitions, and configured to determine a target partition according to the acceleration task, and send task data of the acceleration task to the target partition, so as to obtain an acceleration result by performing data acceleration on the task data by the operator unit of the target partition; and the interface unit is further configured to output the acceleration result to the processing device.

[0007] In a second aspect, an embodiment of the present application provides a server system, comprising: a processing device, the processing device being configured to obtain an acceleration task; and at least one accelerator card as described in the first aspect.

[0008] In a third aspect, an embodiment of the present application provides a data processing method of an acceleration card. The acceleration card comprises a plurality of partitions, each of the partitions comprising an operator unit for data acceleration, and the acceleration functions of at least two of the partitions are different. The method comprises: obtaining task data of an acceleration task; selecting a target partition from the plurality of partitions according to the acceleration task; and sending the task data to the target partition for data acceleration to obtain an acceleration result.

[0009] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: at least one processor; at least one memory configured to store at least one program; and at least one processor configured to implement the data processing method of the acceleration card according to the third aspect when executing the at least one program.

[0010] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program. The program is executed by a processor to implement the data processing method of the acceleration card according to the first aspect.

[0011] In a sixth aspect, an embodiment of the present application provides a computer program product, which comprises a computer program. The computer program is executed by a processor to implement the data processing method of the acceleration card according to the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a structural schematic diagram of an acceleration card according to an embodiment of the present application;

[0013] FIG. 2 is a structural schematic diagram of a partition according to an embodiment of the present application;

[0014] FIG. 3 is a structural schematic diagram of a server system according to an embodiment of the present application;

[0015] FIG. 4 is a flow schematic diagram of a data processing method of an acceleration card according to an embodiment of the present application;

[0016] FIG. 5 is a schematic diagram of a plurality of sub-acceleration tasks according to an embodiment of the present application;

[0017] FIG. 6 is a schematic diagram of an operator information table according to an embodiment of the present application;

[0018] FIG. 7 is a flow schematic diagram of parallel execution of a plurality of sub-acceleration tasks according to an embodiment of the present application;

[0019] FIG. 8 is a flow schematic diagram of cascade execution of a plurality of sub-acceleration tasks according to an embodiment of the present application;

[0020] FIG. 9 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purposes, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0022] An accelerator card is a hardware component specifically designed to enhance the performance of a computer system. It integrates high-performance processors or application-specific integrated circuits to accelerate specific types of data processing tasks, such as graphics rendering, machine learning, scientific computing, etc.

[0023] An acceleration task refers to a computing task that can significantly improve processing speed and efficiency through an accelerator card, such as large-scale parallel computing, deep learning training, image processing, and video encoding, etc. By using an accelerator card, the time required to complete these tasks can be significantly reduced, thereby improving the performance and efficiency of the entire system.

[0024] Currently, the accelerator card in the related art is usually designed to correspond to a specific acceleration application processing corresponding acceleration function, and cannot meet the needs of other acceleration functions. For example, an accelerator card designed for sorting acceleration function cannot support other acceleration functions except sorting acceleration, thereby making the universality of the accelerator card lower.

[0025] Therefore, the embodiments of the present application provide an accelerator card, a server system, a data processing method and related equipment, aiming to solve the technical problem of the universality of the accelerator card. First, an accelerator card provided by the present application will be described. In the present embodiment, the accelerator card can be a graphics processing unit (GPU) accelerator card, a field-programmable gate array (FPGA) accelerator card, an application-specific integrated circuit (ASIC) accelerator card, and a digital signal processor (DSP) accelerator card, etc. The specific type of accelerator card does not affect the implementation of the present application.

[0026] Figure 1 is a structural schematic diagram of an accelerator card provided by the embodiments of the present application. As shown in Figure 1, the accelerator card 100 includes a plurality of partitions 101 (such as partition 1, partition 2, partition 3, etc. shown in Figure 1), an interface unit 102, an input processing unit 103, an interconnection bus unit 104, an output processing unit 105, a reconfiguration function unit 106, a control unit 107, a cross-card transceiver unit 108, a logical dynamic unit 109, a memory access management unit 110, and a storage unit 111.

[0027] Each partition 101 includes a plurality of operator units 201 for implementing data acceleration of a certain specific acceleration function, and the operator units 201 in at least two different partitions 101 implement different acceleration functions, for example, the operator units 201 in the first partition 101 can be used to implement numerical simulation acceleration, such as processing simulation of molecular dynamics, fluid dynamics, etc.; the operator units 201 in the second partition 101 can be used to implement matrix operation acceleration, such as matrix multiplication, Fourier transform, etc.

[0028] In some examples, the acceleration functions that the acceleration card 100 can implement also include machine learning acceleration, such as computation of convolutional neural networks, recurrent neural networks; digital signal processing acceleration, such as audio and video encoding / decoding, filtering; cryptography operation acceleration, such as execution of Advanced Encryption Standard (AES) encryption algorithm, Rivest-Shamir-Adleman (RSA) asymmetric encryption algorithm; data compression and decompression; image processing, such as edge detection, feature extraction, etc.

[0029] In addition, all partitions 101 in the acceleration card 100 are connected through the interconnection bus unit 104, so as to realize data flow between different partitions 101 in the acceleration card.

[0030] In some examples, the interconnection bus unit 104 can be a High-Speed Serial Bus, Crossbar Switches, Custom Interconnect Networks, etc.

[0031] The interface unit 102 realizes Peripheral Component Interconnect Express (PCIe) or Compute Express Link (CXL) through Direct Memory Access (DMA) technology, so as to connect the acceleration card with other devices and interact with the connected devices, including receiving task data corresponding to the acceleration task input by the external processing device.

[0032] In some examples, Direct Memory Access is a technology that allows external devices (such as hard disks, network interface cards, sound cards, etc.) to directly exchange data with the system memory without the intervention of the processing device in the system in the data transmission process. This allows the processing device in the system to focus on other tasks, thereby improving the overall performance and efficiency of the system.

[0033] In some examples, the interface unit 102 can be a PCIe interface unit, a CXL interface unit, a serial interface unit, a storage interface unit, and the like.

[0034] The input processing unit 103 is used to connect the interface unit 102 and the interconnection bus unit 104, and connect each partition 101 through the interconnection bus unit 104.

[0035] In some examples, when the interface unit 102 receives an acceleration task input by an external device, and transmits task data corresponding to the acceleration task to the input processing unit 103, the input processing unit 103 is used to find a partition 101 corresponding to an acceleration function as a target partition from the plurality of partitions 101 according to the required implementation of the acceleration function corresponding to the acceleration task, and transmit acceleration data corresponding to the acceleration task to the target partition through the interconnection bus unit 104 for data acceleration.

[0036] It can be understood that, by arranging the interconnection bus unit 104 in the acceleration card 100, the data intercommunication between the partitions 101 can be realized without arranging a corresponding management module in the acceleration card 100, thereby reducing the setting cost of the acceleration card.

[0037] FIG. 2 is a structural schematic diagram of a partition according to an embodiment of the present application. As shown in FIG. 2, each partition 101 includes a plurality of operator units 201, a partition network unit 202, and a common function unit 203. The partition network unit 202 is used to connect the interconnection bus unit 104 and each operator unit 201. The common function unit 203 provides functions commonly used by each partition, such as a partition register, a register access interface, and the like.

[0038] The output processing unit 105 is used to connect the interface unit 102 and the interconnection bus unit 104, and each partition 101 is connected to the output processing unit 105 through the interconnection bus unit 104.

[0039] In some examples, when the partition network unit 202 receives task data of an input acceleration task, the partition network unit 202 transmits the task data to an operator unit 201 capable of data acceleration for data acceleration, and obtains an acceleration result corresponding to the acceleration task after the data acceleration is completed, and sequentially outputs the acceleration result to an external processing device through the interconnection bus unit 104, the output processing unit 105, and the interface unit 102 to complete the execution process of the acceleration task.

[0040] It can be understood that the embodiment of the application can realize different acceleration functions by setting multiple partitions 101 on a single acceleration card 100. When an acceleration task is input into the acceleration card 100, the input processing unit 103 determines the partition 101 corresponding to the acceleration function required to implement the acceleration task to perform data acceleration, so as to realize the acceleration task with different acceleration function requirements, execute the corresponding acceleration function, and thus effectively improve the universality of the acceleration card.

[0041] When the interface unit 102 receives an acceleration task with multiple sub-acceleration tasks and different acceleration functions required by different sub-acceleration tasks, the input processing unit 103 is used to find, for each sub-acceleration task, a partition 101 corresponding to the acceleration function required by each sub-acceleration task and having an operator unit 201 for data acceleration as a sub-target partition corresponding to the sub-acceleration task, and send the task data corresponding to each sub-acceleration task to the corresponding sub-target partition for data acceleration, and obtain the sub-acceleration result of the sub-acceleration task after acceleration; then, the sub-target partition transmits the sub-acceleration result to the output processing unit 105 through the interconnection bus unit 104; next, the output processing unit 105 integrates all received sub-acceleration results to obtain the acceleration result corresponding to the acceleration task, and transmits the acceleration result to the external processing device through the interface unit 102.

[0042] It can be understood that the embodiment sets the input processing unit 103 and the output processing unit 105 and the interconnection bus unit 104 in the acceleration card 100. When an acceleration task with multiple acceleration function requirements is input, the multiple partitions 101 in the acceleration card 100 that can implement different acceleration functions are used to execute multiple sub-acceleration tasks of the acceleration task, and the output processing unit 105 integrates multiple sub-acceleration results after acceleration of the multiple partitions 101 to obtain the acceleration result corresponding to the complex acceleration task, so as to effectively improve the reliability of executing the complex acceleration task when the complex acceleration task is required, and further improve the universality of the acceleration card 100.

[0043] In some examples, all partitions 101 in the acceleration card 100 belong to the logical dynamic unit 109. The configuration parameters of each granularity can be dynamically adjusted by the reconfiguration function unit 106.

[0044] The reconfiguration function unit 106 is connected with each partition 101, and when a certain partition 101 needs to be reconfigured to change the acceleration function that can be implemented by the operator unit 201 in the partition 101, the reconfiguration function unit 106 is configured to receive the loading data transmitted by the drive module of the external device through the interface unit 102, and then reconfigure the configuration data of the partition 101 based on the loading data, so as to change the acceleration function that can be implemented by the operator unit 201 in the partition 101, without affecting the normal use of other partitions, thereby further improving the flexibility and universality of the acceleration card and the data processing method.

[0045] Taking the FPGA chip as an example, the resource area of the FPGA chip is pre-divided according to the resource condition of the FPGA chip and the resource consumption condition of the operator unit 201, and a plurality of partitions 101 are demarcated. After the partitions 101 are divided, the design and implementation of the acceleration function of the operator unit 201 are performed on the partitions. After the acceleration function of the operator unit 201 is implemented, a loading data file of each operator unit 201 can be obtained in the FPGA chip. All the loading data files of the operator units 201 are stored on the server system in the outside world. The drive program of the server system is responsible for managing these loading data files. When needed, the drive program updates the loading data file of the specified partition to the corresponding partition of the FPGA, and reconfigures the function implementation thereof.

[0046] In some examples, the control unit 107 is connected with the input processing unit 103, and when the input processing unit 103 receives an acceleration task, the control unit 107 is configured to assist in analyzing the acceleration function required by the acceleration task, and assist the input processing unit 103 in determining the target partition corresponding to the acceleration task.

[0047] In some examples, the cross-card transceiver unit 108 is connected with the interface unit 102 and the interconnection bus unit 104, and when data transmission between a plurality of acceleration cards 100 needs to be performed, for example, a single acceleration task needs to be processed by a plurality of acceleration cards 100 in cooperation, and during the cooperative processing, a certain acceleration processing result needs to be transmitted from a certain partition 101 of a previous acceleration card 100 to another partition 101 of a next acceleration card 100, the cross-card transceiver unit 108 between different acceleration cards 100 and the interface unit 102 can be used to implement the data interaction process.

[0048] In some examples, the memory access management units 110 are connected with the interface units 102, the interconnection bus units 104, and the plurality of memory units 111, and the memory access management units 110 are configured to implement access management and access interfaces of the memory units 111 by other units inside the acceleration card 100. The memory units 111 can be double data rate synchronous dynamic random access memory (DDR) memory sticks or DDR particles.

[0049] The embodiments of the present application also provide a server system, and FIG. 3 is a structural schematic diagram of a server system provided by the embodiments of the present application.

[0050] As shown in FIG. 3, the server system 300 includes at least one processing device 301 and at least one acceleration card 100 as shown in FIG. 1.

[0051] In some examples, the processing device 301 is provided with an application software module, a software interface and a driver layer, a task scheduling software module, and a device interface unit. The software interface and the driver layer are connected with the application software module, the task scheduling software module, and the device processing interface, and the processing device 301 is connected with the interface unit 102 of the acceleration card 100 through the device interface unit.

[0052] In some examples, the server system 300 is provided with 8 acceleration cards 100, each of which is provided with 16 partitions 101, and each of the partitions 101 is provided with 8 operator units 201, so that there are 8*16*8=1024 operator units 201 in the server system 300, thereby expanding the execution capability of the server system 300.

[0053] In some examples, application software modules refer to program components that directly face users, which usually implement specific business logic or functions. They are usually located at the higher layer of the software stack and use services and functions provided by other lower layers. Application software modules can be a standalone application or a component in a larger software system. Software interface and driver layer refers to software components that directly interact with hardware, usually including: software interface provides an abstract interface for upper layer applications to access hardware resources, so that applications do not have to care about the specific implementation details of the underlying hardware; driver program, a software component that directly communicates with hardware, responsible for controlling the operation of hardware devices, such as reading and writing data, starting and stopping, etc. Task orchestration software module refers to a software component responsible for managing and coordinating the execution order and dependency relationship between different tasks. This type of software module is usually used in complex systems, such as big data processing, workflow automation, etc. Device interface unit refers to a software or hardware component used to connect and control specific hardware devices. It can be a part of software or an interface board or module on hardware.

[0054] In some examples, application software modules are used to run some application software, such as Structured Query Language (SQL), Spark, etc. Then some acceleration function requirement data will be generated during the running of the application software, and then the acceleration function requirement data is transmitted to the task orchestration software module through the software interface and driver layer to generate an acceleration task; next, the task data of the acceleration task is transmitted to the acceleration card 100 through the software interface and driver layer and the device interface unit for data acceleration.

[0055] For example, the application software modules in the server system 300 are running software application processes A, B, and C at the same time. Process A needs to perform a data compression task, so it issues a compression acceleration task and occupies operator unit 1 for processing; process B needs to perform a data encryption task, so it issues an encryption acceleration task and occupies operator 4 for processing; process C needs to perform a database query, which first filters data, then connects, and finally aggregates, so it issues a data stream processing task and occupies operator unit 2 for filtering function, operator unit 1 for connection function, and operator unit 3 for aggregation function, and performs data processing in series.

[0056] In addition, in the server system 300, through the interface unit 102 between the acceleration cards 100, the data intercommunication between the acceleration cards 100 can be directly implemented without setting an additional switching chip in the acceleration card 100, thereby reducing the setting cost of the server system 300. For example, in the server system 300, each acceleration card 100 can allocate a unique address space in the uniform memory space. Based on the input / output stack (I / O stack) support of the processing device 301, the direct point-to-point transmission between the acceleration cards 100 is implemented through direct address access.

[0057] The embodiment of the present application further provides a data processing method of the acceleration card 100. FIG. 4 is a flowchart of a data processing method of an acceleration card provided by the embodiment of the present application. The method can be applied to the acceleration card 100 and is executed by the common entity in the acceleration card 100. As shown in FIG. 4, the method comprises the following steps S100 to S300.

[0058] In step S100, task data of an acceleration task is acquired.

[0059] The step S100 is described in detail as follows.

[0060] In some examples, when the processing device 301 in the server system 300 as shown in FIG. 3 generates an acceleration task and transmits the acceleration task to a certain acceleration card 100 through the interface unit 102 of the acceleration card 100, the acceleration card 100 first acquires the task data of the acceleration task after responding to the data acceleration of the acceleration task, so as to subsequently execute the data acceleration based on the task data.

[0061] In step S200, a target partition 101 is selected from the plurality of partitions 101 according to the acceleration task.

[0062] The step S200 is described in detail as follows.

[0063] In some examples, when the acceleration card 100 receives the acceleration task through the interface unit 102 and transmits the acceleration task to the input processing unit 103, the input processing unit 103 and the control unit 107 of the acceleration card 100 together select a partition 101 corresponding to an operator unit 201 that can implement the acceleration function required by the acceleration task and currently exists and can be used for data acceleration as the target partition 101 for executing the acceleration task according to the corresponding acceleration function required by the acceleration task, so as to subsequently transmit the task data of the acceleration task to the target partition 101 for data acceleration.

[0064] In some examples, the task data of each acceleration task includes a target function identifier for identifying the acceleration function required to be performed by the acceleration task, and the target function identifier can be used to further confirm the acceleration function required to be performed by the acceleration task.

[0065] FIG. 5 is a schematic diagram of multiple sub-acceleration tasks according to an embodiment of the present application. As shown in FIG. 5, the acceleration task transmitted to the acceleration card 100 for data acceleration includes multiple sub-acceleration tasks, and different sub-acceleration tasks can require different acceleration functions to be performed. For example, as shown in FIG. 5, the sub-acceleration task 1 requires acceleration function 1 to be performed, and the sub-acceleration task 3 requires acceleration function 2 to be performed. Therefore, for such a complex acceleration task, the input processing unit 103 and the control unit 107 of the acceleration card 100 need to select multiple partitions 101 to cooperatively perform data acceleration of the acceleration task, which will be described in detail as follows.

[0066] In some examples, when the acceleration card 100 performs selection of the target partition 101 from the multiple partitions according to the acceleration task, the execution step includes the following steps S210 to S220.

[0067] Step S210, for each sub-acceleration task, selecting a target operator unit 201 from the multiple operator units 201 according to the acceleration function required by the sub-acceleration task.

[0068] Step S220, taking the partition 101 corresponding to the target operator unit 201 as the target partition 101 corresponding to the sub-acceleration task.

[0069] Step S210 will be described in detail as follows.

[0070] In some examples, for the complex acceleration task shown in FIG. 5, the input processing unit 103 and the control unit 107 of the acceleration card 100 select, for each sub-acceleration task, an operator unit 201 that can be used to implement the acceleration function required by the sub-acceleration task from the multiple operator units 201 as the target operator unit 201 according to the acceleration function required by the sub-acceleration task, and take the partition 101 where the target operator unit 201 is located as the target partition 101 for performing the sub-acceleration task, so as to subsequently transmit the task data corresponding to each sub-acceleration task to the corresponding target partition 101 for data acceleration. How to select the target operator unit 201 corresponding to each sub-acceleration task will be described in further detail as follows.

[0071] In some examples, when the acceleration card 100 performs selection of the target operator unit 201 from the multiple operator units 201 according to the acceleration function required by the sub-acceleration task, the execution step includes the following steps S211 to S213.

[0072] Step S211, obtaining a preset operator information table.

[0073] In step S212, the target function identifier corresponding to the acceleration function of the sub-acceleration task is obtained, and based on the operator information table, the operator unit 201 whose function identifier matches the target function identifier is selected as the candidate operator.

[0074] In step S213, the candidate operator in the idle state is selected as the target operator unit 201.

[0075] The steps S211 to S213 are described in detail below.

[0076] In some examples, after receiving the acceleration task, the acceleration card 100 will first obtain the preset operator information table. It can be understood that the operator information table stores the function identifiers corresponding to the acceleration functions that can be implemented by the different partitions 101 in the plurality of acceleration cards 100 in the server system 300. The operator information table can be stored in the storage area of the processing device 301 in the server system 300, or can be stored in the storage unit 111 of each acceleration card 100.

[0077] FIG. 6 is a schematic diagram of an operator information table according to an embodiment of the present application. As shown in FIG. 6, the operator information table includes the acceleration card number of each acceleration card 100 in the server system 300, the partition number of each partition 101 in each acceleration card 100, the function identifier corresponding to the acceleration function that can be implemented by each partition 101, the operator unit number of each operator unit 201 in each partition 101, and the operator state corresponding to the operator unit 201. The operator state includes the idle state, the allocated state, and the working state, etc. It can be understood that the related numbers and identifiers shown in FIG. 6 are only examples, and the information can be added or modified according to actual use requirements; in addition, the storage content and storage method of the operator information table shown in FIG. 6 are only examples, and the information can be added or modified according to actual use requirements.

[0078] In some examples, after receiving the acceleration task, the acceleration card 100 obtains the target function identifier corresponding to the acceleration function required by each sub-acceleration task of the acceleration task from the sub-task data corresponding to each sub-acceleration task. Next, based on the obtained operator information table, the operator unit 201 in the partition 101 whose function identifier matches the target function identifier is selected from the operator information table as the candidate operator, so as to determine that the data acceleration of the sub-acceleration task can be implemented.

[0079] After determining the alternative operator, it is further necessary to determine whether there is an operator unit 201 in the alternative operator at the current time which can be used for data acceleration, i.e., in an idle state, according to the operator state of the alternative operator in the operator information table; if it is determined that there is an idle operator unit 201 in the alternative operator at the current time, the operator unit 201 is taken as the target operator unit 201 for executing the data acceleration of the sub-acceleration task, so as to effectively ensure the reliability of the execution data acceleration process of the acceleration task.

[0080] It can be understood that when there are multiple idle operator units 201 in the alternative operator at the current time, the partition number of the partition 101 in which the operator unit 201 is located is further determined according to the operator unit number of the operator unit 201, and the partition 101 in which the maximum number of idle operator units 201 in the alternative operator is located is taken as the target partition 101 for executing the data acceleration of the sub-acceleration task, and the idle operator units 201 in the partition 101 are taken as the target operator units 201 for executing the data acceleration of the sub-acceleration task, so as to effectively improve the execution efficiency of the acceleration task.

[0081] On the other hand, after the target operator unit 201 is selected, the operator state corresponding to the target operator unit 201 in the operator information table will be immediately updated from the idle state to the allocated state, and when the target operator unit 201 starts to execute the data acceleration of the sub-acceleration task, the operator state corresponding to the target operator unit 201 in the operator information table will be further updated from the allocated state to the working state, and after the data acceleration of the sub-acceleration task is executed, it will be restored to the idle state.

[0082] In some examples, when the operator information table indicates that there is no operator unit 201 with a function identifier matching the target function identifier in the server system 300, and there is a partition 101 in an idle state, the acceleration card 100 executes the step of selecting the target operator unit 201 from the plurality of operator units 201 according to the acceleration function required by the sub-acceleration task, and the execution step further includes the following steps S214 to S217.

[0083] Step S214, taking the partition 101 in the idle state as the idle partition 101.

[0084] Step S215, receiving the loading data from the driver module.

[0085] Step S216, performing acceleration function reconfiguration on the operator units 201 in the idle partition 101 based on the loading data and the reconfiguration function unit.

[0086] Step S217, taking the operator units 201 in the reconfigured idle partition 101 as the target operator units 201.

[0087] The steps S214 to S217 are described in detail as follows.

[0088] In some examples, after the acceleration card 100 receives the acceleration task, and determines that none of the function identifiers of all operator units 201 in all acceleration cards 100 in the server system 300 matches the target function identifier, i.e., there is no acceleration function in the server system 300 at the current time that can implement a certain sub-acceleration task (or acceleration task), in order to further improve the reliability of the data processing method provided in the present application, it is first determined whether there is a partition 101 in which all operator units 201 are in an idle state, i.e., whether there is a partition 101 in an idle state, if there is a partition 101 in an idle state at the current time, the data of the partition 101 will be further reconfigured so that the partition 101 can implement the acceleration function corresponding to the target function identifier.

[0089] In some examples, reconfiguring the partition 101 specifically includes first taking the partition 101 in an idle state as an idle partition 101; then receiving loading data of a configuration data file corresponding to the target function identifier from a driver module in the server system 300; next, based on the loading data and the reconfiguration function unit 106 in the acceleration card 100, reconfiguring the configuration data of the idle partition 101 to implement acceleration function reconfiguration of the operator units 201 in the idle partition 101, so that the reconfigured operator units 201 can implement the acceleration function corresponding to the target function identifier, and the operator units 201 in the reconfigured idle partition 101 are taken as the processing function corresponding to the target function identifier for executing the sub-acceleration task (or acceleration task), and since the data of each partition 101 in the acceleration card 100 as shown in FIG. 1 can be dynamically updated and does not affect the data processing process of other partitions 101 in the updating process, the flexibility, universality and reliability of data processing are effectively improved.

[0090] Step S300, sending task data to the target partition for data acceleration to obtain an acceleration result.

[0091] The step S300 is described in detail as follows.

[0092] In some examples, after determining the target partition 101 corresponding to the acceleration task, the task data corresponding to the acceleration task is further sent to the corresponding target partition 101, and the target operator unit 201 corresponding to the task data for executing the acceleration task in the target partition 101 is used to perform data acceleration on the task data, and the acceleration result of the acceleration task is obtained after acceleration.

[0093] In some examples, when the acceleration task has multiple sub-acceleration tasks, the acceleration card 100 performs the step of sending the task data to the target partition 101 for data acceleration to obtain the acceleration result, which includes the following steps S310-S320.

[0094] Step S310, send each sub-task data to the target partition 101 corresponding to the sub-acceleration task for data acceleration to obtain the sub-acceleration result.

[0095] Step S320, integrate all sub-acceleration results to obtain the acceleration result.

[0096] The steps S310-S320 are described in detail below.

[0097] In some examples, when the target partition 101 corresponding to the multiple sub-acceleration tasks in the acceleration task is determined, and it is determined that these sub-acceleration tasks are executed in parallel, the task data corresponding to each sub-acceleration task is sent to the corresponding target partition 101, and the target operator unit 201 corresponding to the task data used to execute the sub-acceleration task in the target partition 101 is used to perform data acceleration on the task data, and the sub-acceleration result of the sub-acceleration task is obtained after acceleration. Then, based on the output processing unit 105 in the acceleration card 100, all sub-acceleration results are integrated to obtain the acceleration result of the acceleration task, thereby effectively improving the reliability of executing the parallel execution of the complex acceleration task with complex requirements, and further improving the universality of the data processing method of the acceleration card 100.

[0098] Figure 7 is a flowchart of a parallel execution of multiple sub-acceleration tasks according to an embodiment of the present application. As shown in Figure 7, the acceleration task has sub-acceleration task 1, sub-acceleration task 2 and sub-acceleration task 3 executed in parallel, and the target partitions 101 corresponding to the sub-acceleration task 1, sub-acceleration task 2 and sub-acceleration task 3 are partition 1, partition 4 and partition 2 respectively. After the partition 1, partition 4 and partition 2 receive the task data corresponding to the sub-acceleration task and perform data acceleration, the corresponding sub-acceleration result 1, sub-acceleration result 2 and sub-acceleration result 3 are obtained. Next, all sub-acceleration results are integrated by the output processing unit 105 in the acceleration card 100 to obtain the acceleration result of the acceleration task.

[0099] In some examples, when the acceleration card 100 performs the step of sending the task data to the target partition 101 for data acceleration to obtain the acceleration result, the execution step further includes the following steps S330-S340.

[0100] Step S330, obtain the cascade execution order of the multiple sub-acceleration tasks.

[0101] Step S340, based on the cascade execution sequence, the task data is transmitted to the first target partition 101 for data acceleration, and the intermediate acceleration data is obtained, and the intermediate acceleration data is transmitted to the next target partition 101 through the interconnection bus unit 104 for data acceleration, until the task data passes through all the target partitions 101, and the acceleration result is obtained.

[0102] The steps S330 to S340 will be described in detail below.

[0103] In some examples, when the target partitions 101 corresponding to the plurality of sub-acceleration tasks in the acceleration task are determined, and it is determined that these sub-acceleration tasks are cascade execution (i.e. serial), the cascade execution sequence of the plurality of sub-acceleration tasks is obtained, and then based on the cascade execution sequence, the task data of the acceleration task is transmitted to the first target partition 101 for data acceleration, and the intermediate acceleration data is obtained after the target operator unit 201 in the first target partition 101 performs data acceleration on the task data. Next, according to the cascade execution sequence, the intermediate acceleration data is transmitted to the second target partition 101 for data acceleration, until the task data passes through all the target partitions 101 to complete the execution step of the acceleration task, and finally the output processing unit 105 of the acceleration card 100 is arranged to obtain the acceleration result of the acceleration task, so as to effectively improve the reliability of executing the complex acceleration task of cascade execution for complex requirements, and further improve the universality of the data processing method of the acceleration card 100.

[0104] In some examples, when the intermediate acceleration data flows through the plurality of partitions 101 in the acceleration card 100, the data flow between different partitions 101 is realized through the interconnection bus unit 104 inside the acceleration card 100, so that a corresponding management module does not need to be set in the acceleration card 100, and the data flow between the partitions 101 during the execution of the acceleration task can also be realized, thereby reducing the setting cost of the acceleration card 100.

[0105] In some examples, when the server system 300 sets multiple acceleration cards 100, the target partitions 101 selected for the acceleration task may be in different two acceleration cards 100, and in this case, during the execution of the cascade calculation task by the acceleration card 100, the step of transmitting the intermediate acceleration data to the next target partition 101 through the interconnection bus unit 104 for data acceleration further includes the following steps S341 to S343.

[0106] S341, obtaining the current partition number of the current target partition 101, and obtaining the subsequent partition number of the next target partition 101.

[0107] S342, when the current partition number and the subsequent partition number represent that the current target partition 101 and the next target partition 101 are not in the same acceleration card 100, determining the current acceleration card 100 where the current target partition 101 is located based on the current partition number, and determining the subsequent acceleration card 100 where the next target partition 101 is located based on the subsequent partition number.

[0108] S343, transmitting the intermediate acceleration data to the subsequent acceleration card 100 through the interface unit 102 of the current acceleration card 100 and the interface unit 102 of the subsequent acceleration card 100, so that the subsequent acceleration card 100 transmits the intermediate acceleration data to the next target partition 101 through the interconnection bus unit 104 for data acceleration.

[0109] The steps S341 to S343 will be described in detail below.

[0110] In some examples, during the execution of the cascaded computing task by the acceleration card 100, after the current target partition 101 completes data acceleration and obtains intermediate acceleration data, the current partition number of the current target partition 101 and the subsequent partition number of the next target partition 101 are obtained, and it is determined whether the current target partition 101 and the next target partition 101 are in the same acceleration card 100 according to the current partition number and the subsequent partition number. In some examples, taking the operator information table shown in FIG. 6 as an example, the partition number of each partition 101 is prefixed with the acceleration card number of the acceleration card 100 where the partition 101 is located, and the operator unit number of each operator unit 201 is prefixed with the partition number where the operator unit 201 is located. Therefore, after the partition number of the target partition 101 is determined, the acceleration card 100 where the target partition 101 is located can be further determined. Taking the current partition number 01-01 and the subsequent partition number 02-02 as an example, the acceleration card number of the current acceleration card 100 where the current target partition 101 is located can be determined as 01 through the prefix 01 of the current partition number, and the acceleration card number of the subsequent acceleration card 100 where the next target partition 101 is located can be determined as 02 through the prefix 02 of the subsequent partition number, so that it is determined that the current target partition 101 and the next target partition 101 are not in the same acceleration card 100.

[0111] Based on this, when the current partition number and the subsequent partition number are not in the same accelerator card 100, the intermediate acceleration data will be transmitted from the current accelerator card 100 to the subsequent accelerator card 100 through the interface unit 102, the cross-card transceiver unit 108 of the current accelerator card 100, and the interface unit 102, the cross-card transceiver unit 108 of the subsequent accelerator card 100, and then transmitted to the next target partition 101 for data acceleration through the interconnection bus unit 104 in the subsequent accelerator card 100. When a complex acceleration task that needs to be cooperatively accelerated between accelerator cards 100 is executed, the data intercommunication between the accelerator cards 100 can be directly realized without setting an additional switching chip in each accelerator card 100, thereby reducing the setting cost of the server system 300.

[0112] FIG. 8 is a flowchart of a multi-sub-acceleration task cascade execution provided by an embodiment of the present application. As shown in FIG. 8, the acceleration task has cascade execution sub-acceleration task 1, sub-acceleration task 2, and sub-acceleration task 3, and the target partitions 101 corresponding to the sub-acceleration task 1, the sub-acceleration task 2, and the sub-acceleration task 3 are partition 1, partition 4, and partition 2, respectively. Next, according to the cascade execution order, the task data is sequentially subjected to data acceleration through the partition 1, the partition 4, and the partition 2, and the acceleration result of the acceleration task is obtained after the arrangement.

[0113] In some examples, when the target partitions 101 corresponding to the multiple sub-acceleration tasks in the acceleration task are determined, and it is determined that the sub-acceleration tasks are combined with cascade execution and parallel execution, the input processing unit 103 and the control unit 107 in the accelerator card 100 will construct the transmission execution order of the data of the multiple sub-acceleration tasks between the partitions 101 according to the cascade execution order and the parallel relationship therein, thereby effectively accelerating the data of the acceleration task combined with cascade execution and parallel execution.

[0114] In some examples, the present application also provides a data processing method of a server system 300, which is specifically described as follows.

[0115] In the server system 300, multiple accelerator cards 100 are configured, and each accelerator card 100 is loaded with partitions 101 and operator units 201 for implementing multiple types of acceleration functions by default. After the server system 300 is powered on, the installed accelerator cards 100 in the server system 300 are initially scanned and identified by a driver, and the number of accelerator cards in the system, the number of partitions in each accelerator card 100, the implemented acceleration functions and the number of operator units 201 in each partition 101 are obtained by scanning the partition information register of each accelerator card 100, and an operator information table is generated. Then the driver establishes and maintains the operator information table to record the related information of the accelerator card 100, the partition 101, and the operator unit 201. The driver stores and manages the loading data files of various functions of each partition 101 on the server.

[0116] The driver performs initialization configuration of each accelerator card 100. Each card is numbered and written into the accelerator card number register, and each operator unit 201 in the system is uniquely numbered by the accelerator card number plus the operator unit number. The accelerator card numbers of all accelerator cards 100 in the system and the unique address space information allocated to each accelerator card 100 are written into each accelerator card 100.

[0117] An application software generates a specific computing task during operation. This computing task is usually a specified computing process on a large amount of data (kilobyte (kB) to terabyte (TB) scale). The application software prepares data, describes the data processing steps (each step corresponds to an operator unit 201) one by one according to the data processing process, and forms data processing path information. Then the application software calls the driver application programming interface (API), and sends the computing task, the accompanying data, and the processing path information to the driver.

[0118] After receiving the computing task, the driver analyzes the data processing path information and performs task scheduling. The task scheduling module queries the operator information table according to the specified operator type requirement of each step, and if there is a free operator unit 201 with the corresponding function, the operator unit 201 is allocated and the operator unit number is updated in the processing path information. If the operator units 201 on one accelerator card 100 cannot meet the acceleration function requirement of the acceleration task, the remaining required operator resources can be allocated on other accelerator cards 100, and the operator unit number is updated in the processing path information.

[0119] If there is no idle unit operator of the acceleration function on all the acceleration cards 100 in the server system 300, the driver finds an idle partition 101 in which all the operators are idle. The driver reconfigures the found idle partition 101, loads the data file corresponding to the required acceleration function through the PCIe interface, and reconfigures the partition 101. After the configuration is completed, the acceleration function implemented by the operator unit 201 of the partition 101 can be replaced with the required acceleration function. If the driver cannot find an idle partition 101 on all the acceleration cards 100, it means that the operators are busy, and no operator resource can be allocated. The driver can return a failure.

[0120] The driver splits the updated data processing path information according to the acceleration card number, forms a subtask data processing path for each acceleration card 100, and sends the subtask data processing path to the corresponding acceleration card 100. After receiving the new task, the control module of the acceleration card 100 acquires and parses the subtask data processing path, configures each computing unit according to the steps described in the subtask data processing path. After the configuration of the acceleration card 100 is completed, the input parsing module starts to acquire the task data of the acceleration task to be processed through the interface unit 102, parses the input task data, and sends the data to the target partition 101 through the interconnection bus unit 104 for data acceleration.

[0121] After receiving the task data, the operator unit 201 of the target partition 101 performs data calculation and processing according to the configured processing mode, and outputs the acceleration result data after the calculation. If there are other operator units 201 of the same acceleration card 100 to be processed, the output data is sent to the next step of the operator unit 201 through the interconnection bus unit 104. If there are other operator units 201 of other acceleration cards 100 to be processed, the output data is sent to the cross-card transceiver unit 108. The cross-card transceiver unit 108 queries the destination acceleration card number and address space mapping information, and then sends the output data to the destination acceleration card 100 according to the destination acceleration card address. After the output data is received by the cross-card transceiver unit 108 of the destination acceleration card 100, it is sent to the operator unit 201 of the destination acceleration card 100 through the interconnection bus unit 104 according to the operator unit number of the destination operator unit 201. Then the similar calculation and sending process is repeated. If there is no other computing unit to be processed, the output data is sent to the output processing module through the interconnection bus unit 104. The output assembly module assembles the calculated data according to the specified format requirement, and then returns to the memory of the server system 300 and notifies the application software that the calculation task is completed. After receiving the notification, the application software acquires the result data from the server memory and performs subsequent processing.

[0122] The embodiment of the present application sets multiple partitions 101 on the single acceleration card 100, and sets one or more operator units 201 in each partition 101, which can implement the same acceleration function, and designs operator units 201 in different partitions 101 to implement different acceleration functions, so as to implement different acceleration demand applications, implement corresponding acceleration functions, and effectively improve the universality of the acceleration card 100.

[0123] In addition, on the basis of multiple dynamic partitions 101, function reconstruction is implemented with the partition 101 as the minimum granularity, instead of function reconstruction of the entire acceleration card 100. On the one hand, the reconstruction can conveniently implement on-demand adjustment of the acceleration function of the partition 101; on the other hand, for the partition 101 that does not need to be reconstructed, the acceleration function of the operator unit 201 is not affected and can continue to run; and does not depend on an additional switching chip, can conveniently implement interconnection of multiple acceleration cards 100 in the server system 300, and does not need an additional management chip for link management.

[0124] In addition, by setting the input analysis unit and the output assembly unit and the interconnection network in the acceleration card 100, when multiple cascaded or parallel acceleration tasks are required for multiple acceleration functions, the multiple acceleration function demand sub-tasks in the acceleration task are analyzed and confirmed to correspond to the partition 101, and the task data is sent to multiple partitions 101 for parallel data acceleration or cascaded data acceleration, and after acceleration, multiple data acceleration results are assembled by the output assembly unit to obtain the acceleration result data corresponding to the acceleration task, so as to effectively improve the reliability of executing the complex acceleration task when the complex demand acceleration task is required, and further improve the universality of the acceleration card 100.

[0125] The embodiment of the present application also provides an electronic device, as shown in FIG. 9, the electronic device 900 comprises:

[0126] one or more processors 910;

[0127] a memory 920, on which one or more programs are stored, when the one or more programs are executed by the one or more processors 910, the one or more processors 910 implement the data processing method provided by any one of the embodiments of the present application.

[0128] The memory 920, as a non-transitory network system, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 920 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory 920 can optionally include a memory 920 that is remotely arranged relative to the processor 910, and the remote memory 920 can be connected to the processor 910 through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0129] The memory 920 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 920 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the related program codes are stored in the memory 920 and are called and executed by the processor 910 to implement the data processing method of the embodiments of the present application.

[0130] The processor 910 can be implemented in the form of a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0131] In some embodiments, the electronic device further includes:

[0132] An input / output interface for realizing information input and output;

[0133] A communication interface for realizing communication interaction between the device and other devices, which can realize communication through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0134] A bus for transmitting information between various components (such as the processor 910, the memory 920, the input / output interface, and the communication interface) of the device;

[0135] The processor 910, the memory 920, the input / output interface, and the communication interface can realize communication connection between each other inside the device through the bus.

[0136] An embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions for executing the data processing method provided by any one of the embodiments of the present application.

[0137] An embodiment of the present application further provides a computer program product, which comprises a computer program or computer instructions stored in a computer readable storage medium, and a processor of a computer device reads the computer program or computer instructions from the computer readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes the data processing method provided by any one of the embodiments of the present application.

[0138] According to the scheme implemented by the present application, by setting multiple partitions on a single acceleration card, and setting one or more acceleration units implementing the same acceleration function in each partition, and setting acceleration units implementing different acceleration functions in different partitions, when executing an acceleration task, the data processing of the acceleration task is directly executed by using the partition corresponding to the acceleration function that can be used to implement the acceleration task on the acceleration card, thereby effectively improving the universality of the acceleration card.

[0139] The system architecture and application scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the evolution of system architecture and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0140] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in this application is intended to include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0141] Those skilled in the art can understand that all or some steps of the above-mentioned methods and systems can be implemented as software, firmware, hardware and appropriate combinations thereof. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, those skilled in the art know that communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0142] It should be understood that, in the description of the embodiments of the present application, if there is description to "first", "second" and the like, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of the indicated technical features. "At least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. Wherein A, B can be singular or plural. The character " / " generally represents that the associated objects before and after it are in an "or" relationship. "At least one of the following" and the like means any group of these items, including any group of single items or multiple items. For example, at least one of a, b and c can mean: a, b, c, a and b, a and c, b and c, or a and b and c, wherein a, b, c can be single or multiple.

[0143] In addition, the technical features involved in each embodiment described in the present application can be combined with each other as long as there is no conflict.

[0144] The above describes some embodiments of the present application with reference to the drawings, but does not limit the scope of the present application. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and essence of the present application shall be within the scope of the present application.

Claims

1. An acceleration card, comprising: a plurality of partitions, each of the partitions comprising operator units for data acceleration, at least two of the partitions having different acceleration functions; an interface unit for connecting to an external processing device and receiving an acceleration task input by the external processing device; an input processing unit connected to the interface unit and the partitions, for determining a target partition according to the acceleration task and sending task data of the acceleration task to the target partition for data acceleration by the operator units of the target partition to obtain an acceleration result; the interface unit is further configured to output the acceleration result to the processing device.

2. The accelerator card of claim 1, wherein, The acceleration card further comprises an interconnection bus unit connected to each of the partitions and the input processing unit.

3. The accelerator card of claim 2, wherein, The acceleration card further comprises an output processing unit connected to the interconnection bus unit and the interface unit; The input processing unit is further configured to, in the case that the acceleration task comprises a plurality of sub-acceleration tasks, determine a sub-target partition corresponding to each of the sub-acceleration tasks and send sub-task data of each of the sub-acceleration tasks to the corresponding sub-target partition for data acceleration to obtain a sub-acceleration result; The output processing unit is configured to integrate all the sub-acceleration results to obtain the acceleration result.

4. The accelerator card of claim 1, wherein, The acceleration card further comprises a reconfiguration function unit connected to each of the partitions, the reconfiguration function unit being configured to reconfigure the acceleration functions implemented by the operator units in the partitions.

5. A server system, comprising: a processing device configured to obtain an acceleration task; at least one acceleration card according to any one of claims 1-4.

6. A data processing method of an acceleration card, wherein, The acceleration card comprises a plurality of partitions, each of the partitions comprising operator units for data acceleration, at least two of the partitions having different acceleration functions, and the method comprises: obtaining task data of an acceleration task; selecting a target partition from the plurality of partitions according to the acceleration task; sending the task data to the target partition for data acceleration to obtain an acceleration result.

7. The data processing method of an accelerator card according to claim 6, wherein, The acceleration task comprises a plurality of sub-acceleration tasks, and the selecting a target partition from the plurality of partitions according to the acceleration task comprises: for each of the sub-acceleration tasks, selecting a target operator unit from the plurality of operator units according to the acceleration function required by the sub-acceleration task; taking the partition corresponding to the target operator unit as the target partition corresponding to the sub-acceleration task.

8. The data processing method of an acceleration card according to claim 7, wherein, The task data comprises sub-task data corresponding to each of the sub-acceleration tasks, and the sending the task data to the target partition for data acceleration to obtain an acceleration result comprises: sending each of the sub-task data to the target partition corresponding to the sub-acceleration task for data acceleration to obtain a sub-acceleration result; integrating all the sub-acceleration results to obtain the acceleration result.

9. The data processing method of an accelerator card according to claim 7, wherein, The accelerator card is provided with an interconnection bus unit, and the sending of the task data to the target partition for data acceleration to obtain an acceleration result comprises: obtaining a cascade execution sequence of the plurality of sub-acceleration tasks; based on the cascade execution sequence, transmitting the task data to a first target partition for data acceleration to obtain intermediate acceleration data, and transmitting the intermediate acceleration data to a next target partition for data acceleration through the interconnection bus unit until the task data passes through all the target partitions to obtain the acceleration result.

10. The data processing method of an accelerator card according to claim 9, wherein, The number of the accelerator cards is multiple, and the target partition comprises a partition number, and the transmitting of the intermediate acceleration data to the next target partition for data acceleration through the interconnection bus unit comprises: obtaining a current partition number of the current target partition and a subsequent partition number of the next target partition; when the current partition number and the subsequent partition number represent that the current target partition and the next target partition are not on the same accelerator card, determining a current accelerator card where the current target partition is based on the current partition number, and determining a subsequent accelerator card where the next target partition is based on the subsequent partition number; transmitting the intermediate acceleration data to the subsequent accelerator card through an interface unit of the current accelerator card and an interface unit of the subsequent accelerator card, so that the subsequent accelerator card transmits the intermediate acceleration data to the next target partition for data acceleration through the interconnection bus unit.

11. The data processing method of an accelerator card according to claim 7, wherein, The selecting of the target operator unit from the plurality of operator units according to the acceleration function required by the sub-acceleration task comprises: obtaining a preset operator information table, and the operator information table has a function identifier of the operator unit; obtaining a target function identifier corresponding to the acceleration function of the sub-acceleration task, selecting the operator unit having a function identifier matched with the target function identifier as a candidate operator based on the operator information table; and selecting the candidate operator in an idle state as the target operator unit.

12. The data processing method of an accelerator card according to claim 11, wherein, When the operator information table represents that there is no operator unit having a function identifier matched with the target function identifier in the server system and there is a partition in an idle state, the selecting of the target operator unit from the plurality of operator units according to the acceleration function required by the sub-acceleration task further comprises: taking the partition in the idle state as an idle partition; receiving loading data from a driver module, the loading data being a configuration data file corresponding to the target function identifier; based on the loading data and a reconfiguration function unit, reconfiguring the acceleration function of the operator unit of the idle partition; and taking the reconfigured operator unit in the idle partition as the target operator unit.

13. An electronic device comprising a memory and a processor, the memory storing a computer program, wherein, The processor executes the computer program to implement the data processing method of the accelerator card according to any one of claims 6 to 12.

14. A computer readable storage medium having stored thereon a computer program, wherein, The computer program is executed by the processor to implement the data processing method of the accelerator card according to any one of claims 6 to 12.

15. A computer program product comprising a computer program, wherein, The computer program, which is executed by a processor, implements the data processing method of the accelerator card as claimed in any one of claims 6 to 12.

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