Semiconductor device

Abstract

The present application relates to a semiconductor device, comprising: a source region (134); a drain region (132), wherein the drain region (132) is of the same conductivity type as the source region (134); a field oxide layer (150), which is located between the source region (134) and the drain region (132); a gate (138), which is located between the source region (134) and the drain region (132) and extends from an edge of the source region (134) onto the field oxide layer (150); and a resistive field plate (140), which is located on the field oxide layer (150), wherein a plurality of series-connected diodes obtained by means of N-type doping and / or P-type doping are formed on the resistive field plate (140), the conduction directions of some of the series-connected diodes are opposite to those of the others, and the resistive field plate (140) is electrically connected to both the drain region (132) and the gate (138).

Description

Semiconductor device

[0001] Related applications

[0002] This application claims priority to the Chinese patent application with the application number 2024112273107 and the title "Semiconductor device" filed on September 3, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device. BACKGROUND

[0004] The statements herein are provided only to enhance understanding of the present application and are not necessarily intended to constitute the prior art.

[0005] The field plate structure is the mainstream technology for preventing high-voltage cross-line and terminal charge concentration. In an ideal state, the floating field plate has better coupling effect. However, the floating field plate actually manufactured in the Fab (semiconductor wafer factory) cannot achieve perfect ideal coupling, and the actual test results of the product are quite different from the simulation results.

[0006] The theoretical and actual measurement results of the resistive field plate such as a resistive field plate are closer, but the resistive field plate has a leakage problem. SUMMARY

[0007] According to various embodiments of the present application, a semiconductor device is provided.

[0008] A semiconductor device includes: a source region; a drain region, the drain region having the same conductivity type as the source region; a field oxide layer between the source region and the drain region; a gate between the source region and the drain region and extending from the edge of the source region to the field oxide layer; a resistive field plate on the field oxide layer, the resistive field plate being formed with a plurality of series diodes obtained by N-type doping and / or P-type doping, and a part of the series diodes having a conduction direction opposite to another part; and the resistive field plate being electrically connected to the drain region and the gate, respectively.

[0009] In one embodiment, the semiconductor device further includes: a drift region at least partially between the source region and the drain region; a diode region including an N-type doped region and a P-type doped region, the N-type doped region and the P-type doped region forming a target diode; an isolation structure between the drift region and the diode region for electrically isolating the drift region from the diode region; a metal layer above the N-type doped region and above the gate, the N-type doped region and the gate being electrically connected through the metal layer; a gate lead electrically connected to the P-type doped region; and the gate lead being connected to the gate through the target diode.

[0010] In one embodiment, the semiconductor device further comprises: an interlayer dielectric layer covering the source region, the drain region, the diode region, the isolation structure, the field oxide layer, the gate and the resistive field plate; the metal layer is on the interlayer dielectric layer, the metal layer comprises a first metal line, the first metal line is electrically connected to the N-type doped region through the conductive material in the contact hole above the N-type doped region, and is electrically connected to the gate through the conductive material in the contact hole above the gate; the gate lead is electrically connected to the P-type doped region through the conductive material in the contact hole above the P-type doped region.

[0011] In one embodiment, the metal layer comprises a second metal line, the second metal line is electrically connected to the resistive field plate through the conductive material in the contact hole above the resistive field plate, and is electrically connected to the drain region through the conductive material in the contact hole above the drain region.

[0012] In one embodiment, the diode region further comprises: an N-type region, the N-type doped region is in the N-type region, and the doping concentration of the N-type doped region is greater than the doping concentration of the N-type region; a P-well, the P-type doped region is in the P-well, and the doping concentration of the P-type doped region is greater than the doping concentration of the P-well.

[0013] In one embodiment, the material of the resistive field plate is high-resistance polysilicon or semi-insulating polysilicon.

[0014] In one embodiment, the resistive field plate comprises an outer ring and a spiral part inside the outer ring, the spiral part is connected to the outer ring, and the ring width of the outer ring is greater than the strip width of the spiral part.

[0015] In one embodiment, the doping of the resistive field plate and the doping of the source region and the drain region use the same photomask.

[0016] In one embodiment, the semiconductor device further comprises: a second-conductivity-type buried region in the drift region between the source region and the drain region; the source region, the drain region and the drift region have a first conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types; a top doping in the drift region above the second-conductivity-type buried region and below the field oxide layer, comprising at least one first-conductivity-type doped layer, and the doping concentration of the first-conductivity-type doped layer is greater than the doping concentration of the drift region.

[0017] In one embodiment, the top doping comprises at least two first-conductivity-type doped layers with different junction depths, and the doping concentration of the first-conductivity-type doped layer of the top layer in the top doping is greater than the doping concentration of the remaining first-conductivity-type doped layers, and adjacent first-conductivity-type doped layers are separated by a part of the drift region.

[0018] In one embodiment, a top surface of the first conductivity type doped layer of the top layer directly contacts a bottom surface of the field oxide layer.

[0019] In one embodiment, the semiconductor device is a lateral device.

[0020] In one embodiment, the lateral device is a silicon-on-insulator lateral device, including a substrate and an insulating buried layer on the substrate.

[0021] In one embodiment, the substrate is a silicon substrate, and the material of the insulating buried layer is an oxide of silicon.

[0022] In one embodiment, the lateral device is a lateral diffusion metal oxide semiconductor field effect transistor, the lateral device further includes a first conductivity type well region and a second conductivity type well region, the drain region is located in the first conductivity type well region, and the source region is located in the second conductivity type well region; the first conductivity type and the second conductivity type are opposite conductivity types.

[0023] In one embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0024] In one embodiment, the material of the isolation structure is an oxide of silicon, and a bottom of the isolation structure extends to the insulating buried layer of the silicon-on-insulator lateral device.

[0025] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the application or in the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the application, and other accompanying drawings can be obtained by those skilled in the art without any creative effort based on the disclosed accompanying drawings.

[0027] FIG. 1 is a structural schematic diagram of a semiconductor device in an embodiment of the application.

[0028] FIG. 2 is an equivalent circuit diagram of a resistive field plate 140 in an embodiment of the application.

[0029] FIG. 3 is a layout of the resistive field plate 140 in an embodiment of the application.

[0030] FIG. 4 is a layout of doping the resistive field plate to form a series diode in an embodiment of the application.

[0031] Figure 5 is a layout of doping a resistive field plate to form a series diode in another embodiment of the application.

[0032] Figure 6 is a structure diagram of a semiconductor device in another embodiment of the application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0036] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature is still oriented "above" the other element or feature or vice versa. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments of the present application and intermediate structures thereof. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, an implanted region formed by implantation can result in some implant in a region between the implanted region and a surface over which implantation occurs. Thus, the regions illustrated in the figures are schematic and are not intended to illustrate actual dimensions but are intended to be exemplary of the regions used in the present application. The term "doped" refers to the presence of a dopant in a region, which can be a desired presence of a dopant in a region, an undesired presence of a dopant in a region, or a presence of a dopant in a region that is not desired but is unavoidable.

[0039] As used herein, semiconductor art terms are used by those skilled in the art, for example, P-type and N-type impurities are used to distinguish doping concentrations, simply P+ type represents heavily doped P-type, P-type represents medium doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N-type represents medium doped N-type, N- type represents lightly doped N-type.

[0040] The material of the resistive field plate is usually semi-insulating polysilicon or high-resistance polysilicon. The leakage problem of the resistive field plate using high-resistance polysilicon is more serious than that of the semi-insulating polysilicon.

[0041] The present application provides a semiconductor device capable of improving the leakage problem of the resistive field plate. Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application, which includes a source region 134, a drain region 132, a gate 138, a field oxide layer 150 and a resistive field plate 140. The conductive type of the drain region 132 is the same as that of the source region 134, which means that both are N-type or both are P-type. The field oxide layer 150 is located between the source region 134 and the drain region 132. The gate 138 is located above the region between the source region 134 and the drain region 132 and extends from the edge of the source region 134 to the field oxide layer 150. The resistive field plate 140 is located on the field oxide layer 150. The resistive field plate 140 is formed with a plurality of series-connected diodes, which are obtained by N-type doping, or by P-type doping, or by N-type doping + P-type doping. The conduction directions of some of the series-connected diodes are opposite to those of the others. Fig. 2 is an equivalent circuit diagram of the resistive field plate 140 according to an embodiment of the present application. The drain side of the resistive field plate 140 is electrically connected to the drain region 132, and the gate side of the resistive field plate 140 is electrically connected to the gate 138.

[0042] In the above semiconductor device, the resistive field plate 140 is formed with a plurality of series-connected diodes by N-type doping and / or P-type doping, and the conduction directions of some of the series-connected diodes are opposite to those of the others. Thus, when there is a potential difference between the gate and the drain of the device, some of the diodes will be reverse-biased, thereby preventing leakage.

[0043] Fig. 3 is a layout of the resistive field plate 140 according to an embodiment of the present application, which does not show the doping for forming the series-connected diodes. In the embodiment shown in Fig. 3, the resistive field plate 140 includes an outer ring 342 and a spiral portion 344 located inside the outer ring 342. The spiral portion 344 is connected to the outer ring 342, and the ring width of the outer ring 342 is greater than the strip width of the spiral portion 344. Fig. 4 is a layout of the resistive field plate according to an embodiment of the present application, which is doped to form the series-connected diodes. The layout of the resistive field plate in Fig. 4 is the same as that in Fig. 3. Fig. 5 is a layout of the resistive field plate according to another embodiment of the present application, which is doped to form the series-connected diodes. The layout of the resistive field plate in Fig. 5 is the same as that in Fig. 3. In the embodiment shown in Fig. 5, the doping of the resistive field plate and the doping of the drain region 132 and the source region 134 are performed by using the same photomask to perform the photolithography of the doping window, so as to save the photomask. Therefore, the innermost side of the spiral portion 344 (not shown in Fig. 5) and the outer side of the outer ring 342 (not shown in Fig. 5) are also provided with doping regions, which correspond to the doping of the drain region 132 and the doping of the source region 134, respectively, which is different from that in Fig. 4.

[0044] In one embodiment of the application, the semiconductor device further includes a drift region 110 located at least partially between the source region 134 and the drain region 132. The drift region 110 has the same conductivity type as the source region 134 and the drain region 132.

[0045] In one embodiment of the application, the semiconductor device further includes a second conductivity type buried region 112 and a top doping 120. The second conductivity type buried region 112 is located in the drift region 110 between the source region 134 and the drain region 132. The top doping 120 includes at least one first conductivity type doped layer. In the embodiment shown in FIG. 1, the first conductivity type is N-type and the second conductivity type is P-type, thus the second conductivity type buried region 112 is a P-bury in the N-type drift region 110 and the top doping 120 is Ntop. The top doping 120 includes two first conductivity type doped layers, i.e., N-type layer 122 and N-type layer 124. The first conductivity type doped layers have a higher doping concentration than the drift region 110. In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0046] In one embodiment of the application, the top doping 120 includes at least two first conductivity type doped layers with different junction depths, i.e., one first conductivity type doped layer is disposed above another first conductivity type doped layer, and these first conductivity type doped layers are arranged from top to bottom in the drift region 110 above the second conductivity type buried region 112. The top first conductivity type doped layer in the top doping 120 has a higher doping concentration than the rest of the first conductivity type doped layers, e.g., the N-type layer 122 has a higher doping concentration than the N-type layer 124 in FIG. 1, and the adjacent first conductivity type doped layers are separated by a portion of the drift region 110. In the embodiment shown in FIG. 1, the top surface of the top first conductivity type doped layer, i.e., the N-type layer 122, in the top doping 120 directly contacts the bottom surface of the field oxide layer 150.

[0047] In the embodiment shown in FIG. 1, the drain side of the resistive field plate 140 is electrically connected to the drain region 132 by a metal layer 160. Specifically, the semiconductor device further includes an interlayer dielectric (ILD) layer (not shown in FIG. 1) covering the source region 134, the drain region 132, the field oxide layer 140, the gate 138, and the resistive field plate 140. The metal layer 160 is located on the interlayer dielectric layer, the metal layer 160 is electrically connected to the resistive field plate 140 through a conductive material in a contact hole above the resistive field plate 140, and the metal layer 160 is electrically connected to the drain region 132 through a conductive material in a contact hole above the drain region 132, the contact holes penetrating through the interlayer dielectric layer.

[0048] In the embodiment shown in FIG. 1, the semiconductor device is a silicon-on-insulator (SOI) device. The device includes a substrate 10 and an insulating buried layer 20 on the substrate 10. A drift region 110 is located on the insulating buried layer 20. In the embodiment shown in FIG. 1, the substrate 10 is a P-type silicon substrate and the material of the insulating buried layer 20 is an oxide of silicon, such as silicon dioxide. Further, the semiconductor device shown in FIG. 1 is an LDMOSFET.

[0049] In one embodiment of the present application, the gate 138 is of polysilicon material, although in other embodiments, metals, metal nitrides, metal silicides, or the like can be used as the material of the gate 138.

[0050] In one embodiment of the present application, a gate dielectric layer (not shown in FIG. 1) is also provided under the gate 138. The gate dielectric layer can include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant as measured in a vacuum of from about 4 to about 20, or the gate dielectric layer can include a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanates (BSTs), and lead zirconium titanates (PZTs).

[0051] In the embodiment shown in FIG. 1, the semiconductor device also includes a first conductivity type well region 114 and a second conductivity type well region 116. A drain region 132 is located in the first conductivity type well region 114 and a source region 134 is located in the second conductivity type well region 116. The drift region 110 is located at least partially between the first conductivity type well region 114 and the second conductivity type well region 116. The second conductivity type buried region 112 is located between the first conductivity type well region 114 and the second conductivity type well region 116. The source region 134 and the drain region 132 have a greater doping concentration than the first conductivity type well region 114. In one embodiment of the present application, the first conductivity type well region 114 has a greater doping concentration than the drift region 110. In the embodiment shown in FIG. 1, the source region 134 and the drain region 132 are N+ regions.

[0052] In the embodiment shown in FIG. 1, the semiconductor device also includes a body tie region 136 located in the second conductivity type well region 116. The body tie region 136 has a greater doping concentration than the second conductivity type well region 116. In the embodiment shown in FIG. 1, the body tie region 136 is a P+ region.

[0053] In the embodiment shown in FIG. 1, the resistive field plate 140 is of high resistance polysilicon. In another embodiment, the resistive field plate 140 can also be of semi-insulating polysilicon.

[0054] The isolation effect of the resistive field plate 140 of the semiconductor device shown in Fig. 1 is better in the super-high voltage semiconductor device with a working voltage of 500 V or higher, and is also better in the semiconductor device with a longer drift region. For the semiconductor device with a working voltage of 300 V or lower, and the semiconductor device with a shorter drift region, the present application proposes a further improved semiconductor device structure, which connects a low-voltage diode between the gate and the drain to isolate the leakage current.

[0055] Fig. 6 is a schematic diagram of the structure of a semiconductor device according to another embodiment of the present application. In the embodiment shown in Fig. 6, the semiconductor device further includes an isolation structure 152, a diode region, and a metal layer 160. The diode region includes an N-type doped region 172 and a P-type doped region 174, which form a target diode. The isolation structure 152 is located between the drift region 110 and the diode region, and is used to electrically isolate the drift region 110 from the diode region. The metal layer 160 is located above the N-type doped region 172 and the gate 138, and the N-type doped region 172 and the gate 138 are electrically connected through the metal layer 160. The gate lead-out 166 above the P-type doped region 174 is electrically connected to the P-type doped region 174, so that the gate lead-out 166 and the gate 138 are connected through the target diode. When the working voltage is applied to the gate lead-out 166, the target diode is forward-biased. When a high voltage is applied to the drain, if the resistive field plate 140 cannot completely isolate the leakage current, the target diode can further isolate the leakage current.

[0056] In one embodiment of the present application, the isolation structure 152 is made of silicon oxide. The bottom of the isolation structure 152 extends to the buried insulating layer 20, and the top of the isolation structure 152 extends to the top of the top silicon on the buried insulating layer 20, thereby isolating the current between the drift region 110 and the diode region in the lateral direction.

[0057] In the embodiment shown in Fig. 6, the semiconductor device further includes an interlayer dielectric layer (not shown in Fig. 6) covering the source region 134, the drain region 132, the diode region, the isolation structure 152, the field oxide layer 150, the gate 138, and the resistive field plate 140. The metal layer 160 includes a first metal wire 162, which is electrically connected to the N-type doped region 172 through a conductive material in a contact hole above the N-type doped region 172, and is electrically connected to the gate 138 through a conductive material in a contact hole above the gate 138. The gate lead-out 166 is electrically connected to the P-type doped region 174 through a conductive material in a contact hole above the P-type doped region 174. Each contact hole penetrates the interlayer dielectric layer. In one embodiment of the present application, the gate lead-out 166 is also part of the metal layer 160.

[0058] In the embodiment shown in FIG. 6, the semiconductor device metal layer 160 further includes a second metal line 164. The second metal line 164 is electrically connected to the resistive field plate 140 through the conductive material in the contact hole above the resistive field plate 140, and is electrically connected to the drain region 132 through the conductive material in the contact hole above the drain region 132.

[0059] In the embodiment shown in FIG. 6, the diode region further includes an N-type region 171 and a P-well 173. An N-type doped region 172 is located in the N-type region 171, and the N-type doped region 172 has a doping concentration greater than that of the N-type region 171. A P-type doped region 174 is located in the P-well 173, and the P-type doped region 174 has a doping concentration greater than that of the P-well 173. In one embodiment of the present application, the P-well 173 is located in the N-type region 171.

[0060] In one embodiment of the present application, the drift region 110 and the N-type region 171 are part of an N-type epitaxial layer on the insulating buried layer 20.

[0061] In the description of the specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the description of the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0062] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present application.

[0063] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor device, comprising: a source region; a drain region, the drain region having the same conductivity type as the source region; a field oxide layer between the source region and the drain region; a gate between the source region and the drain region, the gate extending from an edge of the source region to the field oxide layer; and a resistive field plate on the field oxide layer, the resistive field plate having a plurality of series-connected diodes formed by N-type doping or P-type doping, and a portion of the series-connected diodes having a conduction direction opposite to another portion of the series-connected diodes, the resistive field plate electrically connected to the drain region and the gate, respectively. further comprising:

2. The semiconductor device according to claim 1, wherein a drift region at least partially between the source region and the drain region; a diode region including an N-type doped region and a P-type doped region, the N-type doped region and the P-type doped region forming a target diode; an isolation structure between the drift region and the diode region for electrically isolating the drift region from the diode region; a metal layer over the N-type doped region and over the gate, the N-type doped region and the gate electrically connected by the metal layer; and a gate lead electrically connected to the P-type doped region, the gate lead electrically connected to the gate by the target diode. further comprising: an interlayer dielectric layer covering the source region, the drain region, the diode region, the isolation structure, the field oxide layer, the gate, and the resistive field plate; 3. The semiconductor device of claim 2, wherein the metal layer on the interlayer dielectric layer, the metal layer including a first metal line electrically connected to the N-type doped region by a conductive material in a contact hole over the N-type doped region, and electrically connected to the gate by a conductive material in a contact hole over the gate, the gate lead electrically connected to the P-type doped region by a conductive material in a contact hole over the P-type doped region. the metal layer including a second metal line electrically connected to the resistive field plate by a conductive material in a contact hole over the resistive field plate, and electrically connected to the drain region by a conductive material in a contact hole over the drain region. the diode region further comprising:

4. The semiconductor device according to claim 3, wherein an N-type region, the N-type doped region located in the N-type region, the N-type doped region having a higher doping concentration than the N-type region; and 5. The semiconductor device of claim 2, wherein a P-well, the P-type doped region located in the P-well, the P-type doped region having a higher doping concentration than the P-well. the resistive field plate having a material of high-resistance polysilicon or semi-insulating polysilicon. the resistive field plate including an outer ring and a spiral portion inside the outer ring, the spiral portion connected to the outer ring, the outer ring having a ring width greater than a strip width of the spiral portion.

6. The semiconductor device of claim 1, wherein the resistive field plate doped using a same photomask as the source region and the drain region.

7. The semiconductor device of claim 1, wherein the semiconductor device further comprising:

8. The semiconductor device of claim 1, wherein, a second-conductivity-type buried region in the drift region between the source region and the drain region, the source region, the drain region, and the drift region having a first conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; and 9. The semiconductor device of claim 2, wherein, a second-conductivity-type buried region in the drift region between the source region and the drain region, the source region, the drain region, and the drift region having a first conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types. ​ A top doping in a drift region above the second conductivity type buried region and below the field oxide layer includes at least one first conductivity type doping layer, the first conductivity type doping layer having a doping concentration greater than a doping concentration of the drift region.

10. The semiconductor device of claim 9, wherein, The top doping includes at least two first conductivity type doping layers having different junction depths, and a top first conductivity type doping layer of the top doping has a doping concentration greater than a doping concentration of the remaining first conductivity type doping layers, the adjacent first conductivity type doping layers being separated by a portion of the drift region.

11. The semiconductor device of claim 10, wherein, A top surface of the top first conductivity type doping layer directly contacts a bottom surface of the field oxide layer.

12. The semiconductor device of claim 1, wherein The semiconductor device is a lateral device.

13. The semiconductor device of claim 2, wherein The semiconductor device is a silicon-on-insulator lateral device.

14. The semiconductor device of claim 12, wherein, The lateral device is a lateral diffused metal oxide semiconductor field effect transistor, the lateral device further including a first conductivity type well region and a second conductivity type well region, the drain region being in the first conductivity type well region and the source region being in the second conductivity type well region; the first conductivity type and the second conductivity type being opposite conductivity types.

15. The semiconductor device of claim 14, wherein, The first conductivity type is N-type and the second conductivity type is P-type.

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