Semiconductor device

Abstract

Provided is a semiconductor device that exhibits little variation in electrical characteristics between transistors. The semiconductor device includes a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, and a semiconductor layer. The first insulating layer is located on the first conductive layer and the second conductive layer is located on the first insulating layer. End parts of the first insulating layer and the second conductive layer coincide or substantially coincide in plan view, and the first insulating layer and the second conductive layer assume the shape of a concave polygon in a plan view. Two sides configuring an internal angle that exceeds 180 degrees in the concave polygon overlap the first conductive layer in plan view. The semiconductor layer is located on the first conductive layer and the second conductive layer so as to have a region overlapping the two sides in plan view, and the semiconductor layer is in contact with the upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, and the upper surface of the second conductive layer.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of the above, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] In order to achieve even higher resolution in display devices, further miniaturization of semiconductor devices included in the display devices is required. On the other hand, the more miniaturization of transistors included in semiconductor devices is pursued, the more difficult it becomes to ensure good electrical characteristics, maintain processing accuracy, and reduce variations in electrical characteristics between transistors.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a small size and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a short channel length and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high field-effect mobility and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with favorable electrical characteristics and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device with small variation in electrical characteristics between transistors and a manufacturing method thereof.

[0012] Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed and a manufacturing method thereof.Another object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area and a manufacturing method thereof.Another object of one embodiment of the present invention is to provide a semiconductor device or display device that consumes low power and a manufacturing method thereof.Another object of one embodiment of the present invention is to provide a high-resolution display device.Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device or display device with high productivity.Another object of one embodiment of the present invention is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, and a semiconductor layer. The first insulating layer is located over the first conductive layer, and the second conductive layer is located over the first insulating layer. Ends of the first insulating layer and the second conductive layer are aligned or substantially aligned in a plan view and have a concave polygonal shape in a plan view. Two sides of the concave polygon that form an interior angle exceeding 180 degrees overlap with the first conductive layer in a plan view. The semiconductor layer is located over the first conductive layer and the second conductive layer so as to have a region overlapping with the two sides in a plan view. The semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, and a top surface of the second conductive layer.

[0015] In the above, it is preferable that the semiconductor layer is an oxide semiconductor layer containing indium, the first insulating layer has a second insulating layer, a third insulating layer over the second insulating layer, and a fourth insulating layer over the third insulating layer, the second insulating layer and the fourth insulating layer each contain silicon and nitrogen, and the third insulating layer contains silicon and oxygen.

[0016] In the above, the interior angle is preferably 270 degrees.

[0017] In the above, the concave polygon preferably has a shape that combines straight lines and curves.

[0018] In the above, the interior angle is preferably greater than 180 degrees and less than 270 degrees.

[0019] In the above, the concave polygon preferably has a shape that combines straight lines and curves.

[0020] In the above, the interior angle is preferably greater than 270 degrees and less than 360 degrees.

[0021] In the above, the concave polygon preferably has a shape that combines straight lines and curves.

[0022] In the above, it is preferable that the transistor has a fifth insulating layer and a third conductive layer, the fifth insulating layer is located on the semiconductor layer, and the third conductive layer is located on the fifth insulating layer and has a region facing a side surface of the first insulating layer via the semiconductor layer and the fifth insulating layer.

[0023] In the above, it is preferable that an end of the third conductive layer coincides or substantially coincides with an end of the fifth insulating layer.

[0024] In the above, it is preferable that the edge of the semiconductor layer coincides or substantially coincides with the edge of the third conductive layer and the edge of the fifth insulating layer.

[0025] In the above, it is preferable that a sixth insulating layer is located under the transistor, the upper surface of the sixth insulating layer is in contact with the first conductive layer, and the sixth insulating layer contains silicon and hydrogen.

[0026] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a semiconductor device including a transistor with a short channel length and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a semiconductor device including a transistor with high field-effect mobility and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a semiconductor device with small variation in electrical characteristics between transistors and a manufacturing method thereof can be provided.

[0027] According to one embodiment of the present invention, a semiconductor device that operates at high speed and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device that occupies a small area and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device or display device that consumes low power and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a high-resolution display device can be provided. According to one embodiment of the present invention, a manufacturing method of a semiconductor device or display device with high productivity can be provided. According to one embodiment of the present invention, a novel transistor, a semiconductor device, a display device, or a manufacturing method thereof can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0029] FIG. 1A is a plan view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A and 2B are perspective views showing an example of a semiconductor device. FIG. 3A is a plan view showing an example of a semiconductor device. FIG. 3B is a cross-sectional view showing an example of a semiconductor device. FIGS. 4A and 4B are perspective views showing an example of a semiconductor device. FIG. 5A is a plan view showing an example of a semiconductor device. FIGS. 5B and 5C are cross-sectional views showing an example of a semiconductor device. FIGS. 6A and 6B are perspective views showing an example of a semiconductor device. FIGS. 7A and 7B are plan views showing an example of a semiconductor device. FIGS. 8A and 8B are plan views showing an example of a semiconductor device. FIG. 9A is a plan view showing an example of a semiconductor device. FIG. 9B is a cross-sectional view showing an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are plan views showing an example of a semiconductor device. FIGS. 13A and 13B are plan views showing an example of a semiconductor device. 14A and 14B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 14C is a cross-sectional view illustrating an indium oxide film. FIG. 15A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 15B and 15C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 16A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 16B and 16C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 17A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 17B and 17C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 18B and 18C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 19A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 19B and 19C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 20A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 20B and 20C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. 21A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 21B and 21C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.FIG. 22A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 22B and 22C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 23A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 23B and 23C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 24A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 24B and 24C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 25B and 25C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 26 is a perspective view illustrating an example of a display device. FIGS. 27A and 27B are cross-sectional views illustrating an example of a display device. FIG. 28 is a cross-sectional view illustrating an example of a display device. FIGS. 29A, 29B, and 29C are cross-sectional views illustrating an example of a display device. FIGS. 30A and 30B are cross-sectional views illustrating an example of a display device. FIG. 31 is a cross-sectional view illustrating an example of a display device. FIGS. 32A, 32B, and 32C are cross-sectional views illustrating an example of a display device. Fig. 33 is a cross-sectional view showing an example of a display device. Figs. 34A and 34B are cross-sectional views showing an example of a display device. Figs. 35A, 35B, 35C, and 35D are diagrams showing an example of an electronic device. Figs. 36A, 36B, 36C, 36D, 36E, and 36F are diagrams showing an example of an electronic device. Figs. 37A, 37B, 37C, 37D, 37E, 37F, and 37G are diagrams showing an example of an electronic device.

[0030] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0031] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0032] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0033] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number assigned to a component in one part of this specification may not match an ordinal number assigned to the same component in another part of this specification or in the claims.

[0034] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0035] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0036] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as a source terminal and a drain terminal, a source electrode and a drain electrode, or the like, depending on the situation.

[0037] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0038] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no exchange of an electric signal or an interaction of electric potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B.

[0039] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0040] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0041] In this specification, unless otherwise specified, on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and source (also referred to as Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0042] In this specification, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0043] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0044] In this specification, the top surface shape of a component refers to the contour shape of the component in a plan view (also referred to as a top view). The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0045] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0046] In this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface on which a substrate is to be formed. The angle formed between the inclined side surface and the substrate surface or the surface on which a substrate is to be formed is sometimes referred to as a taper angle.

[0047] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution resulting from the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0048] In this specification and the like, a structure in which light-emitting layers are separately formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0049] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer in a light-emitting element may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0050] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0051] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0052] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0053] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0054] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 13B. FIG.

[0055] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer.

[0056] A transistor of one embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, and a second insulating layer.

[0057] The first conductive layer functions as one of a source electrode and a drain electrode of the transistor. The second conductive layer functions as the other of the source electrode and the drain electrode of the transistor. The third conductive layer functions as a gate electrode of the transistor. The second insulating layer functions as a gate insulating layer of the transistor. A region of the oxide semiconductor layer in contact with the first conductive layer functions as one of a source region and a drain region of the transistor. A region of the oxide semiconductor layer in contact with the second conductive layer functions as the other of the source region and the drain region of the transistor. A channel formation region of the transistor is located between the source region and the drain region of the oxide semiconductor layer.

[0058] The first insulating layer is located on the first conductive layer. The first insulating layer is provided in an island shape and has a region in contact with the top surface and side surfaces of the first conductive layer. The second conductive layer is located on the first insulating layer. The top surface shapes of the first insulating layer and the second conductive layer are the same or approximately the same. That is, the ends of the first insulating layer and the second conductive layer are the same or approximately the same in plan view.

[0059] The first insulating layer and the second conductive layer have a concave polygonal shape (a polygon with at least one interior angle exceeding 180 degrees) in a plan view, and the first insulating layer and the second conductive layer are provided so that two sides of the concave polygon that form an interior angle exceeding 180 degrees have an area that overlaps with the first conductive layer in a plan view.

[0060] The oxide semiconductor layer is located on the first conductive layer, the first insulating layer, and the second conductive layer. The oxide semiconductor layer is provided to have regions that overlap with the two sides in a plan view. The oxide semiconductor layer has a region in contact with a top surface of the first conductive layer, a region in contact with a side surface of the first insulating layer, a region in contact with a side surface of the second conductive layer, and a region in contact with a top surface of the second conductive layer.

[0061] The second insulating layer is located on the oxide semiconductor layer. The second insulating layer has a region in contact with the top surface and side surface of the oxide semiconductor layer, a region in contact with the top surface and side surface of the first conductive layer, a region in contact with the side surface of the first insulating layer, and a region in contact with the top surface and side surface of the second conductive layer. The third conductive layer is located on the second insulating layer. The third conductive layer is provided to have a region overlapping with the oxide semiconductor layer. The third conductive layer has a region facing the side surface of the first insulating layer with the second insulating layer and the oxide semiconductor layer interposed therebetween.

[0062] The first insulating layer preferably contains oxygen. The oxygen contained in the first insulating layer is supplied to the oxide semiconductor layer through the side surface of the insulating layer. This reduces oxygen vacancies (V Ｏ : Oxygen Vacancy) is compensated for, and a transistor with good electrical characteristics can be realized.

[0063] Here, consider a case where the first insulating layer and the second conductive layer have, for example, a convex polygonal shape (a polygon in which all interior angles are 180 degrees or less) in a planar view. For example, if the oxide semiconductor layer is provided to have a region overlapping two sides that form one of the interior angles of the convex polygon in a planar view, there is a possibility that the amount of oxygen supplied to the oxide semiconductor layer will differ between the region of the first insulating layer corresponding to the two sides and the region of the first insulating layer corresponding to the connection portion (convex portion) of the two sides. Specifically, there is a possibility that the amount of oxygen supplied from the convex portion will be less than the amount of oxygen supplied from the region corresponding to the two sides.

[0064] In contrast, in a semiconductor device according to one embodiment of the present invention, as described above, the first insulating layer and the second conductive layer have a concave polygonal shape in a plan view. The oxide semiconductor layer is provided to have a region overlapping with two sides of the concave polygon that form interior angles exceeding 180 degrees in a plan view. This can prevent a difference in the amount of oxygen supplied to the oxide semiconductor layer (mainly the channel formation region) between the regions of the first insulating layer corresponding to the two sides and the regions of the first insulating layer corresponding to the connection portions (concave portions) of the two sides. This can stabilize the electrical characteristics of the transistor and prevent variations in the electrical characteristics among multiple transistors within the substrate plane.

[0065] Furthermore, the transistor of one embodiment of the present invention is a vertical transistor whose channel length can be controlled by the thickness of the first insulating layer sandwiched between the first conductive layer and the second conductive layer. That is, unlike a planar transistor, the channel length of the transistor is not affected by the exposure performance of an exposure apparatus used for manufacturing the transistor. Therefore, the channel length of the transistor can be made shorter than the minimum value of the dimension that the exposure apparatus can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, the transistor can have a large on-state current. Therefore, a semiconductor device that operates at high speed can be provided.

[0066] Furthermore, since a source electrode, an oxide semiconductor layer, and a drain electrode of a vertical transistor can be provided in a stacked manner, the area occupied by the transistor can be smaller than that of a planar transistor. Therefore, the area occupied by a semiconductor device including the vertical transistor can be reduced. For example, by applying the semiconductor device to a display device, the display device can have higher resolution.

[0067] <Configuration Example 1> A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a plan view (also referred to as a top view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 1A. Note that some of the components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some of the components may also be omitted in the plan views of the semiconductor device in the following drawings.

[0068] The semiconductor device 10 includes a transistor 100 and an insulating layer 110. The transistor 100 is provided over a substrate .

[0069] 1B and 1C show an example in which the insulating layer 110 has a laminated structure of an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. An insulating material that contains oxygen and can release oxygen is used for the insulating layer 110b. Furthermore, an insulating material that can suppress oxygen permeation (an insulating material that has barrier properties against oxygen) is used for each of the insulating layers 110a and 110c.

[0070] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0071] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode, and part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode. A region of the semiconductor layer 108 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region of the semiconductor layer 108 that is in contact with the drain electrode functions as a drain region.

[0072] 2A and 2B show perspective views of the semiconductor device 10. Fig. 2A is a perspective view of the semiconductor device 10 with the conductive layer 104 and the insulating layer 106 omitted. Note that the insulating layer 110 is shown as a single layer without distinguishing between the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c. Fig. 2B is a perspective view of the semiconductor layer 108 omitted from the perspective view of Fig. 2A.

[0073] A conductive layer 112a is provided over a substrate 102. An insulating layer 110 is provided over the conductive layer 112a and the substrate 102 so as to have a region overlapping with the conductive layer 112a. A conductive layer 112b is provided over the insulating layer 110. The conductive layer 112a has a region in contact with the substrate 102. The conductive layer 112a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. The insulating layer 110 is in contact with each of the conductive layer 112a and the conductive layer 112b and has a region sandwiched between them. The conductive layer 112a has a region overlapping with the conductive layer 112b with the insulating layer 110 interposed therebetween.

[0074] The insulating layer 110 is provided in an island shape and has a region in contact with the upper surface and side surfaces of the conductive layer 112a and the upper surface of the substrate 102. The conductive layer 112b has a region in contact with the upper surface of the insulating layer 110. The insulating layer 110 and the conductive layer 112b have the same or approximately the same top surface shape. That is, the insulating layer 110 and the conductive layer 112b have the same or approximately the same end portions in a plan view.

[0075] The insulating layer 110 and the conductive layer 112b, which are provided in an island shape, have a concave polygonal shape in plan view. The insulating layer 110 and the conductive layer 112b are provided so that two sides of the concave polygon that form an interior angle exceeding 180 degrees have an area that overlaps with the conductive layer 112a in plan view (see FIGS. 1A and 2B, etc.).

[0076] The semiconductor layer 108 is located over the conductive layer 112a, the insulating layer 110, and the conductive layer 112b. The semiconductor layer 108 is provided so as to have a region overlapping the two sides in a plan view. That is, the semiconductor layer 108 is provided across a region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are provided and a region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are not provided. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 112b, and a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface of the conductive layer 112a, the side surface of the insulating layer 110, and the top and side surfaces of the conductive layer 112b (see FIGS. 1A, 2A, etc.).

[0077] The semiconductor material used for the semiconductor layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities that serve as dopants.

[0078] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0079] The semiconductor layer 108 can be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. Furthermore, a transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0080] The semiconductor layer 108 preferably includes a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be referred to as an oxide semiconductor layer or a metal oxide layer.

[0081] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0082] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0083] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.

[0084] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ), and defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ H) can be reduced.

[0085] The insulating layer 106, which functions as a gate insulating layer of the transistor 100, is provided to cover the semiconductor layer 108. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, the top surface and side surfaces of the conductive layer 112a, and the top surface of the substrate 102.

[0086] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 also has a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the semiconductor layer 108 interposed therebetween. The conductive layer 104 is provided to cover at least a region where the semiconductor layer 108 is in contact with the side surface of the insulating layer 110. This allows the region to function as a channel formation region of the transistor 100.

[0087] 1A to 2B , in the transistor 100, the semiconductor layer 108 is provided in contact with two adjacent side surfaces of the insulating layer 110, which is provided in an island shape, so as to cover these surfaces. In FIG. 2B , hatched patterns are used to indicate regions of the side surfaces of the insulating layer 110 where the semiconductor layer 108 is in contact. Therefore, in the transistor 100, regions of the semiconductor layer 108 facing the two side surfaces can function as channel formation regions. In FIG. 2A , a region of the semiconductor layer 108 corresponding to the channel width of the transistor 100 is indicated by a two-dot chain line with a double-headed arrow.

[0088] The conductive layer 104 preferably covers the entire semiconductor layer 108. As shown in FIG. 1A , the conductive layer 104 preferably encompasses the semiconductor layer 108 in a plan view. Covering the semiconductor layer 108 with the conductive layer 104 can prevent the semiconductor layer 108 from being damaged when layers are formed on the transistor 100. This makes it possible to realize a highly reliable transistor 100 that exhibits favorable electrical characteristics. Note that the semiconductor layer 108 may have a region that is not covered with the conductive layer 104.

[0089] A step is formed between a region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are provided and a region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are not provided, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 can be provided along the step.

[0090] In the transistor 100, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, and a drain current flows perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows vertically or approximately vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can be called a vertical channel transistor, a vertical transistor, or a vertical field effect transistor (VFET).

[0091] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high accuracy. Furthermore, the variation in electrical characteristics among the plurality of transistors 100 can be reduced. Therefore, the operation of the semiconductor device 10 can be stabilized and the reliability can be improved. Furthermore, the reduced variation in the electrical characteristics of the transistors 100 increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device 10 can be reduced. Therefore, the power consumption of the semiconductor device 10 can be reduced.

[0092] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which the source electrode, the semiconductor layer, and the drain electrode are arranged on a plane.

[0093] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the area occupied by the transistor 100 and the wirings can be reduced. Therefore, a semiconductor device 10 with a small area can be realized.

[0094] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0095] In addition to the transistor 100, examples of a vertical transistor in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along a step between a region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are provided and a region where they are not provided, and the region of the semiconductor layer 108 along the side of the step functions as a channel formation region, include, for example, a transistor 100X included in the semiconductor device 10X shown in FIGS. 3A and 3B or a transistor 100Y included in the semiconductor device 10Y shown in FIGS. 5A to 5C.

[0096] Each of the transistors 100X and 100Y is a vertical transistor having a source electrode, a semiconductor layer, and a drain electrode that are stacked on top of each other, similar to the transistor 100. Therefore, the area occupied by the transistor within the substrate surface can be significantly reduced compared to a planar transistor.

[0097] Fig. 4A is a perspective view of the semiconductor device 10X from which the conductive layer 104 and the insulating layer 106 are omitted. Regarding the insulating layer 110, the insulating layers 110a, 110b, and 110c are shown as a single layer without distinguishing between them. Fig. 4B is a perspective view from which the semiconductor layer 108 is further omitted from the perspective view shown in Fig. 4A.

[0098] The semiconductor device 10X has a configuration in which the semiconductor layer 108 is in contact with only one of the side surfaces of the insulating layer 110, which is provided in an island shape. In FIG. 4B , the region of the side surface of the insulating layer 110 where the semiconductor layer 108 is in contact is indicated by a hatched pattern. Therefore, in the transistor 100X, the region of the semiconductor layer 108 facing the one side surface can function as a channel formation region. In FIG. 4A , the region of the semiconductor layer 108 corresponding to the channel width of the transistor 100X is indicated by a double-arrowed, two-dot chain line.

[0099] As described above, the transistor 100X has a structure in which a channel formation region is provided along only one of the side surfaces of the island-shaped insulating layer 110. In contrast, the transistor 100 can have a structure in which a channel formation region is provided along two adjacent side surfaces of the island-shaped insulating layer 110. Therefore, even when the transistors have the same channel width, the transistor 100 can occupy a smaller area within the substrate than the transistor 100X (see FIGS. 1A and 3A ).

[0100] On the other hand, in the transistor 100, the semiconductor layer 108 needs to be provided along two adjacent side surfaces of the insulating layer 110 (see FIG. 2B ), whereas in the transistor 100X, the semiconductor layer 108 needs to be provided along only one side surface of the insulating layer 110 (see FIG. 4B ). Therefore, the semiconductor layer 108 (the same applies to the insulating layer 106 and the conductive layer 104) can be formed with good coverage on the side surfaces of the insulating layer 110 more easily in the transistor 100X than in the transistor 100, which may increase the manufacturing yield of the transistor.

[0101] Fig. 6A is a perspective view of the semiconductor device 10Y from which the conductive layer 104 and the insulating layer 106 are omitted. Regarding the insulating layer 110, the insulating layers 110a, 110b, and 110c are shown as a single layer without being distinguished from one another. Fig. 6B is a perspective view from which the semiconductor layer 108 is further omitted from the perspective view of Fig. 6A.

[0102] In the semiconductor device 10Y, the insulating layer 110 and the conductive layer 112b, which are provided in an island shape, have a convex polygonal shape in a plan view. The insulating layer 110 and the conductive layer 112b are provided so that two sides constituting one of the interior angles of the convex polygon have an area overlapping with the conductive layer 112a in a plan view (see, for example, FIGS. 5A and 6B).

[0103] Although the island-shaped insulating layer 110 and conductive layer 112b of the semiconductor device 10Y are configured to have a convex polygonal shape in a plan view, the present invention is not limited to this and they may also have a concave polygonal shape, in which case two sides of the concave polygon that form an interior angle of less than 180 degrees have an area that overlaps with the conductive layer 112a in a plan view.

[0104] In the semiconductor device 10Y, the semiconductor layer 108 is configured to contact two adjacent side surfaces of the insulating layer 110 so as to have an area overlapping the two sides in a plan view. In Fig. 6B, the area of ​​the side surface of the insulating layer 110 where the semiconductor layer 108 contacts can be indicated by a hatched pattern. Therefore, in the transistor 100Y, the area of ​​the semiconductor layer 108 facing the two side surfaces can function as a channel formation region. In Fig. 6A, the area of ​​the semiconductor layer 108 corresponding to the channel width of the transistor 100Y is indicated by a double-arrowed, two-dot chain line.

[0105] As described above, the transistor 100Y has a structure in which the semiconductor layer 108 is provided in contact with two adjacent side surfaces of the island-shaped insulating layer 110, similar to the transistor 100. Therefore, the transistor 100Y can occupy a smaller area in the substrate plane than the transistor 100X (see FIGS. 3A and 5A). Furthermore, the area can be reduced to a similar extent as that of the transistor 100 (see FIGS. 1A and 5A).

[0106] The semiconductor device 10 and the semiconductor device 10Y differ in the shapes of the insulating layer 110 and the conductive layer 112b, which are provided in an island shape. Specifically, in the semiconductor device 10, the insulating layer 110 and the conductive layer 112b have a concave polygonal shape in plan view (see FIGS. 1A and 2B ), whereas in the semiconductor device 10Y, the insulating layer 110 and the conductive layer 112b have a convex polygonal shape in plan view (see FIGS. 5A and 6B ). The transistor 100 included in the semiconductor device 10 has a configuration in which the semiconductor layer 108 is provided in contact with side surfaces of the insulating layer 110 corresponding to two sides that form an interior angle exceeding 180 degrees of the concave polygon (see FIG. 2A ), whereas the transistor 100Y included in the semiconductor device 10Y has a configuration in which the semiconductor layer 108 is provided in contact with side surfaces of the insulating layer 110 that correspond to two sides that form one of the interior angles of the convex polygon (see FIG. 6A ). Therefore, there is a possibility that the semiconductor device 10 and the semiconductor device 10Y may differ in the way oxygen is supplied from the insulating layer 110 to the semiconductor layer 108.

[0107] FIG. 7A shows a plan view of only the insulating layer 110 of the semiconductor device 10Y, and FIG. 7B shows a plan view of only the insulating layer 110 of the semiconductor device 10. In FIGS. 7A and 7B, arrows indicate the direction in which oxygen is released from the side surface of each insulating layer 110. FIG. 8A shows a plan view in which a semiconductor layer 108 is added to the plan view shown in FIG. 7A, and FIG. 8B shows a plan view in which a semiconductor layer 108 is added to the plan view shown in FIG. 7B. FIGS. 7A and 8A are plan views corresponding to FIG. 5A, and FIGS. 7B and 8B are plan views corresponding to FIG. 1A.

[0108] In the case of semiconductor device 10Y, as shown in FIG. 7A , oxygen contained in insulating layer 110 can be released in a direction perpendicular or approximately perpendicular to each side of the convex polygon constituting insulating layer 110 in a planar view. In FIG. 7A , the region from which oxygen is released along each side of the convex polygon constituting insulating layer 110 is shown as region RH. Meanwhile, around the corner (corner CL) of the convex polygon, a region may be created in which oxygen is not easily supplied from either of the two sides (X direction and Y direction) sandwiching corner CL. Therefore, this region may be a region in which oxygen release from insulating layer 110 is extremely low compared to region RH. In FIG. 7A , this region is shown as region RL.

[0109] 8A, in the semiconductor device 10Y, the region of the semiconductor layer 108 that can function as a channel formation region (the region surrounded by the dashed line) overlaps with both the region RH and the region RL. That is, in the semiconductor device 10Y, the amount of oxygen supplied from the insulating layer 110 may differ depending on the portion of the semiconductor layer 108 (mainly the channel formation region).

[0110] On the other hand, in the case of the semiconductor device 10, as shown in FIG. 7B , the insulating layer 110 has a concave polygonal shape in a plan view. Therefore, oxygen contained in the insulating layer 110 can be released from three regions: each side of the concave polygon, a convex corner (corner CL), and a concave corner (corner CH). Of these, a region RL where little oxygen is released from the insulating layer 110 can be formed around the corner CL, as described above. However, the region around the corner CH is a region where oxygen can be supplied from both sides (the X direction and the Y direction) that sandwich the corner CH, and therefore cannot be a region where very little oxygen is released from the insulating layer 110, like the region RL.

[0111] 8B , in the semiconductor device 10, the region (encircled by the dashed line) that can function as a channel formation region of the semiconductor layer 108 overlaps only with the region RH. That is, in the semiconductor device 10, it is possible to prevent the amount of oxygen supplied from the insulating layer 110 from varying depending on the portion of the semiconductor layer 108 (mainly the channel formation region). Therefore, it is possible to stabilize the electrical characteristics of the transistor 100 included in the semiconductor device 10. Furthermore, it is possible to prevent variations in the electrical characteristics between multiple transistors within the substrate plane.

[0112] On the other hand, in the semiconductor device 10, it is necessary to form the semiconductor layer 108 so that it overlaps the corners CH of the insulating layer 110 but does not overlap the corners CL (see FIG. 8B ), whereas in the semiconductor device 10Y, the insulating layer 110 does not have corners CH, so it is sufficient to form the semiconductor layer 108 while paying attention only to overlapping the corners CL of the insulating layer 110 (see FIG. 8A ). Therefore, the semiconductor device 10Y does not require as high a processing precision for the semiconductor layer 108 as the semiconductor device 10.

[0113] Materials that can be used for each component of the semiconductor device 10 of one embodiment of the present invention will be described below.

[0114] The conductive layer 112a can be formed using, for example, a conductive metal oxide (also referred to as an oxide conductor). Examples of oxide conductors (OC) include indium oxide (also referred to as indium oxide), zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, oxide conductors containing indium have high conductivity and are therefore suitable for use in the conductive layer 112a.

[0115] The insulating layer 110 preferably has a stacked structure. In Fig. 1B and other figures, the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can each be made of the materials listed for the insulating layer 110.

[0116] In the transistor 100, a region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region. As described above, the insulating layer 110b preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. Typically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b.

[0117] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor having good electrical characteristics can be realized.

[0118] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere. Then, the film can be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 3.

[0119] The insulating layer 110b is preferably formed by a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, by using a sputtering method without using a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) in the film formation gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen can be prevented from being supplied to the channel formation region, and the electrical characteristics of the transistor 100 can be stabilized.

[0120] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a and the substrate 102. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layers 110a and 110c preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layers 110a and 110c preferably are impermeable to substances. The insulating layers 110a and 110c can also function as barrier films. Specifically, the insulating layers 110a and 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layers 110a and 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor exhibiting favorable electrical characteristics can be realized.

[0121] As described above, it is preferable to use a material that is less permeable to oxygen for each of the insulating layer 110a and the insulating layer 110c. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, reducing oxygen vacancies (V Ｏ ) and V ＯH can be reduced. This makes it possible to realize a transistor with good electrical characteristics and high reliability. Furthermore, it is possible to prevent the conductive layer 112a from being oxidized by oxygen contained in the insulating layer 110b and the electrical resistance of the conductive layer 112a from increasing. Similarly, it is possible to prevent the conductive layer 112b from being oxidized by oxygen contained in the insulating layer 110b and the electrical resistance of the conductive layer 112b from increasing. Therefore, it is possible to realize a transistor with a large on-state current.

[0122] The insulating layer 110a and the insulating layer 110c can each be made of the materials listed above for the barrier film. For example, the insulating layer 110a and the insulating layer 110c can each be made of one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. The insulating layer 110a and the insulating layer 110c can each be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can each be made of different materials.

[0123] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0124] One or more of the insulating layers 110a, 110b, and 110c can have a stacked structure. For example, the insulating layer 110c can have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0125] The thickness of the insulating layer 110c is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 200 nm. For example, as shown in Figure 9B, the thickness T110c of the insulating layer 110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

[0126] The thickness T110c is preferably a value that at least functions as a barrier film against oxygen. The thickness T110c can be thinner than the thickness of the insulating layer 110a. If the thickness T110c of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c increases, which may result in a larger amount of impurities diffusing into the channel formation region. On the other hand, if the thickness T110c is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b via the insulating layer 110c, which may result in a reduced amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ The thickness T110c is not limited to the above range.

[0127] The thickness of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 250 nm, even more preferably 150 nm to 250 nm. For example, as shown in Figure 9B, the thickness T110a of the insulating layer 110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a in a cross-sectional view.

[0128] If the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, which may reduce the amount of oxygen supplied to the channel formation region. On the other hand, if the thickness T110a is large, the amount of impurities released from the insulating layer 110a may increase, which may increase the amount of impurities diffusing into the channel formation region. By setting the thickness T110a within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ The thickness T110a is not limited to the above range.

[0129] The thickness T110a can be made thicker than the thickness T110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, the distance from the source region or the drain region to the gate electrode can be made more uniform by making the thickness T110a thicker. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform.

[0130] At least one of the region of the semiconductor layer 108 in contact with the insulating layer 110a and the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a region having lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be referred to as a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a contains impurities, and this region can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c contains impurities, and this region can be a low-resistance region. The semiconductor layer 108 may have a low-resistance region between a region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low-resistance region may function as a buffer region for reducing the drain electric field. Note that the low-resistance region may also function as a source region or a drain region.

[0131] Note that impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b or via one of the source region and the drain region of the semiconductor layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b or via the other of the source region and the drain region of the semiconductor layer 108. However, since oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses the shift of the threshold voltage, and a transistor can be realized that has both a small cutoff current (drain current when the gate voltage is 0 V) ​​and a large on-current. Therefore, a semiconductor device that has both low power consumption and high performance can be realized.

[0132] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, the impurities contained in the semiconductor layer 108 increase. As a result, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of released impurities is small.

[0133] The insulating layer 110a has a region in contact with the top surface of the substrate 102 and the top surface and side surfaces of the conductive layer 112a, which can suppress impurities contained in the substrate 102 and the conductive layer 112a from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layer 110b.

[0134] Note that although the insulating layer 110 has a three-layer stacked structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b. A structure without one or both of the insulating layer 110a and the insulating layer 110c is also possible. Alternatively, the insulating layer 110 may have a stacked structure of four or more layers.

[0135] [Semiconductor Layer 108] Metal oxides that can be used for the semiconductor layer 108 will be specifically described. Examples of metal oxides include indium oxide. Examples of metal oxides include gallium oxide and zinc oxide. The metal oxide preferably contains at least indium. The metal oxide preferably contains one or both of indium and zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0136] The semiconductor layer 108 can include, for example, indium oxide (In-O, also referred to as IO). The semiconductor layer 108 can also include, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide), etc. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide) can be used.

[0137] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0138] The metal oxide may contain one or more nonmetallic elements. The presence of a nonmetallic element in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0139] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0140] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0141] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0142] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, and the transistor can be a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0143] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0144] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In: Examples of the composition include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0145] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0146] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0147] By using a material with a high indium content for the semiconductor layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0148] Here, when a polycrystalline metal oxide is used for the semiconductor layer 108, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layer 108, the surface of the semiconductor layer 108 may become uneven. This increases the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layer 108 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0149] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure and is therefore suitable for use in the semiconductor layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. Specifically, metal oxides of In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be preferably used. When indium tin oxide containing silicon (ITSO) is used for the semiconductor layer 108, it is preferable that the ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0150] A metal oxide not containing element M can be used for the semiconductor layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0151] The composition of the semiconductor layer 108 can be analyzed by, for example, Energy Dispersive X-ray Spectrometry (EDX), X-ray Photoelectron Spectroscopy (XPS), or Electron Spectrometry for Chemical Analysis (ESCA), Inductively Coupled Plasma-Mass Spectrometry (ICP-MS), or Inductively Coupled Plasma-Atomic Emission Spectroscopy (ICP-AES). Spectrometry) can be used. Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or the content of element M may be below the lower detection limit.

[0152] The metal oxide film can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide film is formed by sputtering, the composition of the formed metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide film may decrease to about 50% of that of the sputtering target.

[0153] A crystalline metal oxide is preferably used for the semiconductor layer 108. Examples of the structure of a crystalline metal oxide include a C-Axis Aligned Crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0154] The semiconductor layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0155] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 is formed. The semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b and layered crystals parallel to or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the side surface of the insulating layer 110 where the semiconductor layer 108 is formed. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel to or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0156] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0157] The higher the substrate temperature during deposition of a metal oxide film, the higher the crystallinity of the metal oxide film that can be formed. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for deposition or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the metal oxide film that can be formed.

[0158] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0159] When a metal oxide is used for the semiconductor layer 108, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which defects such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0160] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0161] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0162] The semiconductor layer 108 may also include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be realized.

[0163] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0164] The semiconductor layer 108 can have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 can be the same or approximately the same. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in the semiconductor layer 108 are the same or approximately the same, the boundaries (interfaces) of these metal oxide layers may not be clearly identified.

[0165] The channel length and channel width of the transistor 100 will be described with reference to FIGS. 9A and 9B . FIG. 9A is a plan view of the semiconductor device 10. FIG. 9B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 9A . Note that, in the following description, a portion of the semiconductor layer 108 in contact with a side surface of the insulating layer 110b is referred to as a channel formation region.

[0166] In FIG. 9B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the contact between the semiconductor layer 108 and the side surface of the insulating layer 110b in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b in the region overlapping with the conductive layer 112a. Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools for mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0167] The channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L100 can be 100 nm or more and 1 μm or less.

[0168] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0169] The channel length L100 can be controlled by adjusting the thickness T110b of the insulating layer 110b.

[0170] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0171] 1B and the like show a configuration in which the shape of the side surface of the insulating layer 110 is straight in a cross-sectional view, but one embodiment of the present invention is not limited to this. The shape of the side surface of the insulating layer 110 can also be curved in a cross-sectional view. Alternatively, the shape of the side surface of the insulating layer 110 can include both a region in which the side surface is straight and a region in which the side surface is curved in a cross-sectional view.

[0172] The top surface shape of the conductive layer 112b preferably coincides with or substantially coincides with that of the insulating layer 110. FIG. 1A and other figures illustrate a configuration in which the top surface shape of the conductive layer 112b coincides with that of the insulating layer 110. The conductive layer 112b and the insulating layer 110 can be formed using the same mask layer. For example, an insulating film that will become the insulating layer 110 and a conductive film that will become the conductive layer 112b on the insulating film are formed, and a mask layer (e.g., a resist mask) is formed on the conductive film. Then, the conductive film and the insulating film are processed using the mask layer as a mask to form the conductive layer 112b and the insulating layer 110 whose top surface shapes coincide with or substantially coincide with each other. Processing the insulating film that will become the insulating layer 110 and the conductive film that will become the conductive layer 112b in the same process can reduce manufacturing costs. Note that, although FIG. 1A and other figures illustrate the top surface shapes of the conductive layer 112b and the insulating layer 110 as concave polygons with interior angles of 270 degrees, this is not limiting. Other examples of the top surface shapes of the conductive layer 112b and the insulating layer 110 that can be included in the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 12A to 13B.

[0173] 1B and 1C, it is preferable that there is no step between the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface of the insulating layer 110 facing the semiconductor layer 108, and that they are flat (i.e., the two surfaces are flush or approximately flush). This can improve the coverage of layers (e.g., the semiconductor layer 108) provided on the insulating layer 110 and the conductive layer 112b. Note that a structure in which the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface of the insulating layer 110 facing the semiconductor layer 108 are discontinuous may also be used. Furthermore, a structure in which the top surface shape of the conductive layer 112b does not match the top surface shape of the insulating layer 110 may also be used.

[0174] Here, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110. If the conductive layer 112b is in contact with the side surface of the insulating layer 110 as well, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top surface shape of the conductive layer 112b and the top surface shape of the insulating layer 110 match or approximately match. Alternatively, it is preferable that the insulating layer 110 encompasses the conductive layer 112b in a plan view.

[0175] The channel width of the transistor 100 is the length of a region where a channel formation region in the semiconductor layer 108 overlaps with the conductive layer 104 in a plan view. In Figure 9A, the channel width W100 of the transistor 100 is indicated by a double-arrowed, two-dot chain line.

[0176] When the semiconductor layer 108 and the conductive layer 104 are formed by lithography, the channel width W100 is equal to or greater than the resolution limit of an exposure apparatus. The channel width W100 can be, for example, 20 nm to less than 500 μm, 50 nm to 200 μm, 100 nm to 100 μm, 200 nm to 50 μm, 500 nm to 20 μm, 1 μm to 10 μm, or 1 μm to 5 μm.

[0177] Note that although the example in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region has been described here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region of the semiconductor layer 108 in contact with the insulating layer 110c may also function as a channel formation region.

[0178] [Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 104] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0179] An oxide conductor can be used for each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. For the oxide conductor, the above description can be referred to.

[0180] Oxygen deficiency (V) in metal oxides with semiconducting properties Ｏ When hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0181] The conductive layers 112a, 112b, and 104 can each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0182] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied to each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. By using a Cu-X alloy film, it is possible to process the film by wet etching, thereby reducing manufacturing costs.

[0183] Note that the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can be formed using the same material, or at least one of them can be formed using a different material.

[0184] The conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, for the conductive layer 112a and the conductive layer 112b, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor.

[0185] For the conductive layer 112a and the conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108.

[0186] The conductive layer 112a and the conductive layer 112b can each be formed using any of the above-described oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide to which gallium is added can be used. In particular, oxide conductors containing indium have high conductivity and can therefore be suitably used for the conductive layer 112a and the conductive layer 112b.

[0187] The conductive layers 112a and 112b may each be made of a nitride conductor, such as tantalum nitride or titanium nitride.

[0188] [Insulating Layer 106] The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0189] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the insulating layer 110, and the substrate 102. When a metal oxide is used for the semiconductor layer 108, any of the above-described oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be suitably used for the insulating layer 106.

[0190] Note that in a miniaturized transistor, a thinner gate insulating layer may result in a larger leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a lower voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0191] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

[0192] When the insulating layer 106 has a stacked-layer structure, an oxide or an oxynitride is preferably used for the insulating layer on the semiconductor layer 108 side. For example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide can be preferably used. Alternatively, a nitride or a nitride oxide can be used. For example, aluminum nitride can be preferably used.

[0193] At least one of the layers constituting the insulating layer 106 preferably functions as a barrier film. By providing the barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100 into the semiconductor layer 108 through the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the insulating layer 110b into the conductive layer 104 through the insulating layer 106. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, thereby reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be realized. Furthermore, the conductive layer 104 can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which would increase the electrical resistance of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be realized. The above-mentioned materials can be used for the barrier film. For example, one or more of silicon nitride, aluminum oxide, and aluminum nitride can be suitably used for one or more layers constituting the insulating layer 106.

[0194] [Substrate 102] The material of the substrate 102 is not particularly limited, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. A substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited, and can be, for example, circular or rectangular.

[0195] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0196] In this specification and the like, flexibility refers to the property of an object being soft and able to bend, i.e., the property of an object being able to deform in response to an external force applied to the object, regardless of whether the object has elasticity or the ability to return to its original shape before deformation.

[0197] For example, a flexible electronic device can deform in response to an external force. A flexible electronic device can be used in a fixed deformed state, or can be used after repeated deformation, or can be used in an undeformed state. A flexible display device (also referred to as a flexible display device, flexible display device, flexible display, etc.) can deform in response to an external force. A flexible display device can be used in a fixed deformed state, or can be used after repeated deformation, or can be used in an undeformed state. A flexible substrate (also referred to as a flexible substrate, flexible substrate, etc.) can deform in response to an external force. A flexible substrate can be used in a fixed deformed state, or can be used after repeated deformation, or can be used in an undeformed state. Note that the above phrase "deform in response to an external force" refers to deformation of an object without requiring excessive force by the hand of an average adult. Note that flexibility can be quantified as deformation of an object in response to an external force using a testing machine (such as a tensile testing machine or a compression testing machine) capable of measuring stress-strain.

[0198] Furthermore, in this specification, when an object is described as being flexible, it means that at least a part of the object is flexible. In other words, a flexible object may also have an inflexible part (also called a hard part).

[0199] In this specification, "high flexibility" means that when two objects are deformed by the same external force, the object that deforms more is said to be the object with high flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with high flexibility.

[0200] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same function as the configuration example described above may be indicated with the same hatching pattern and may not be assigned reference numerals.

[0201] 10A is a cross-sectional view of a semiconductor device 10A according to one embodiment of the present invention, taken along dashed line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0202] In the following, differences from the semiconductor device 10 shown in FIG. 1B etc. will be mainly described, and descriptions of overlapping parts may be omitted.

[0203] The semiconductor device 10A includes a transistor 100A and an insulating layer 110. The semiconductor device 10A differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the side surfaces of the insulating layer 110 and the conductive layer 112b are tapered relative to the top surface of the conductive layer 112a.

[0204] In the transistor 100A, the channel length is determined by the thickness of the insulating layer 110b in the region overlapping with the conductive layer 112a and the angle θ110 formed between the side surface of the insulating layer 110 and the surface on which the insulating layer 110 is formed (here, the top surface of the conductive layer 112a).

[0205] Therefore, in the transistor 100A, the channel length can be controlled by adjusting the thickness and angle θ110 of the insulating layer 110b.

[0206] The angle θ110 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 75 degrees or less, 50 degrees or more and 70 degrees or less, 55 degrees or more and 70 degrees or less, 60 degrees or more and 70 degrees or less, or 65 degrees or more and 70 degrees or less. By reducing the angle θ110, the coverage of a layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved compared to the transistor 100. Furthermore, the smaller the angle θ110, the longer the channel length can be.

[0207] On the other hand, as in the semiconductor device 10 shown in FIG. 1B, by making the angle between the insulating layer 110 and the conductive layer 112a perpendicular or approximately perpendicular, the channel length of the transistor can be shortened and the occupied area of ​​the semiconductor device can be reduced.

[0208] With respect to the semiconductor device 10A shown in FIG. 10A, the contents described for the semiconductor device 10 shown in FIG. 1B and the like can be referred to for other matters.

[0209] 10B is a cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention, taken along dashed line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0210] In the following, differences from the semiconductor device 10 shown in FIG. 1B etc. will be mainly described, and descriptions of overlapping parts may be omitted.

[0211] The semiconductor device 10B includes a transistor 100B, an insulating layer 110, and an insulating layer 109. The semiconductor device 10B differs from the semiconductor device 10 shown in FIG.

[0212] The insulating layer 109 is provided over the substrate 102. The conductive layer 112a is provided over the insulating layer 109, and the insulating layer 110 is provided over the conductive layer 112a and the insulating layer 109. The top surface of the substrate 102 is in contact with the insulating layer 109, and the top surface of the insulating layer 109 has a region in contact with each of the conductive layer 112a and the insulating layer 110. In the semiconductor device 10B, the transistor 100B is provided over the insulating layer 109.

[0213] The insulating layer 109 can be made of the same material as that used for the insulating layer 110 described above.

[0214] The insulating layer 109 preferably has a barrier property. The insulating layer 109 is preferably made of a material through which impurities (e.g., water and hydrogen) contained in the substrate 102 do not easily diffuse. This can prevent impurities from diffusing from the substrate 102 to the transistor 100B.

[0215] The insulating layer 109 functioning as a barrier film can be formed using, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 109 can be formed using, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0216] The insulating layer 109 preferably contains impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108 and is made of a material that releases the impurities. The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a that is in contact with the insulating layer 109. Furthermore, when the impurities diffused into the conductive layer 112a diffuse into a region of the semiconductor layer 108 that is in contact with the conductive layer 112a, the region contains the impurities and can reduce the electrical resistance of the region. That is, the electrical resistance of one of the source region and the drain region can be reduced. Therefore, the transistor 100B may have a larger on-state current than the transistor 100.

[0217] When a metal oxide is used for the semiconductor layer 108, the impurities released from the insulating layer 109 preferably contain hydrogen. When hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108 through the conductive layer 112a, a region of the semiconductor layer 108 in contact with the conductive layer 112a contains hydrogen, and the carrier concentration of the region increases. That is, the electrical resistance of one of the source region and the drain region can be reduced. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be used for the insulating layer 109.

[0218] It is more preferable to use a material that releases impurities that reduce the electrical resistance of the conductive layer 112a for the insulating layer 109. This can reduce the electrical resistance of the conductive layer 112a.

[0219] The thickness of the insulating layer 109 is preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, further preferably 20 nm to 100 nm, and further preferably 20 nm to 50 nm. By setting the thickness of the insulating layer 109 in the above range, oxygen vacancies (V Ｏ ) and V Ｏ An increase in H can be suppressed, and the electrical resistance of the conductive layer 112a and the electrical resistance of one of the source region and the drain region of the transistor 100B can be reduced.

[0220] When a metal oxide is used for the conductive layer 112a, the impurities released from the insulating layer 109 preferably contain hydrogen. The impurities released from the insulating layer 109 diffuse into the conductive layer 112a, causing the conductive layer 112a to contain the impurities. This increases the carrier concentration of the conductive layer 112a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a can function as a wiring, thereby achieving a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112a can be the same as the impurities that reduce the electrical resistance of the semiconductor layer 108. Alternatively, these impurities can be different from each other.

[0221] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The hydrogen content of the insulating layer 109 and the like can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0222] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region through the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V ＯH can be reduced. This suppresses the shift of the threshold voltage, and a transistor that achieves both a small cutoff current and a large on-state current can be realized. Therefore, a semiconductor device that achieves both low power consumption and high performance can be realized.

[0223] The amount of released hydrogen can be adjusted by varying the deposition conditions of the insulating layer 109 and the insulating layer 110a. Specifically, the insulating layer 109 and the insulating layer 110a can be made different from each other in one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density of the insulating layer 109 lower than the deposition power density of the insulating layer 110a, the hydrogen content in the insulating layer 109 can be made higher than the hydrogen content in the insulating layer 110a. This allows the amount of hydrogen released from the insulating layer 109 to be increased by heat applied to the insulating layer 109.

[0224] The deposition gas used to form the insulating layer 109 preferably contains more hydrogen than the deposition gas used to form the insulating layer 110a. Specifically, when a silicon nitride film or a silicon nitride oxide film is formed for each of the insulating layer 109 and the insulating layer 110a by a PECVD method, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a. By depositing the insulating layer 109 under the condition of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. Furthermore, the amount of hydrogen released from the insulating layer 109 due to heat applied to the insulating layer 109 can be increased.

[0225] The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. This can prevent hydrogen contained in the insulating layer 109 from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layers 110a and 110b. The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, whereas a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, the insulating layer 110a may appear darker (darker) in the TE image than the insulating layer 109. Even if the insulating layer 109 and the insulating layer 110a are made of the same material, the film densities are different, and therefore the boundary between them can sometimes be observed as a difference in contrast in a cross-sectional TEM image.

[0226] With respect to the semiconductor device 10B shown in FIG. 10B, the contents described for the semiconductor device 10 shown in FIG. 1B and the like can be referred to for other matters.

[0227] 11A is a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention, taken along dashed line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0228] In the following, differences from the semiconductor device 10 shown in FIG. 1B etc. will be mainly described, and descriptions of overlapping parts may be omitted.

[0229] The semiconductor device 10C includes a transistor 100C and an insulating layer 110. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that an end of the insulating layer 106 coincides or substantially coincides with an end of the conductive layer 104.

[0230] In the semiconductor device 10C, the top surfaces of the conductive layers 112a and 112b are exposed in regions that do not overlap with the insulating layer 106. Therefore, for example, when elements such as transistors and capacitors are stacked on the semiconductor device 10C, a conductive layer or the like that serves as a plug connecting to the conductive layer 112a or the conductive layer 112b can be directly formed on the exposed regions. Therefore, the number of steps involved in the entire manufacturing process can be reduced in some cases compared to when the semiconductor device 10 is used.

[0231] With respect to the semiconductor device 10C shown in FIG. 11A, the contents described for the semiconductor device 10 shown in FIG. 1B and the like can be referred to for other matters.

[0232] 11B is a cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention, taken along dashed line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0233] In the following, differences from the semiconductor device 10C shown in FIG. 11A will be mainly described, and descriptions of overlapping portions may be omitted.

[0234] The semiconductor device 10D includes a transistor 100D and an insulating layer 110. The semiconductor device 10D differs from the semiconductor device 10C shown in FIG. 11A mainly in that the ends of the insulating layer 106 and the conductive layer 104 are approximately aligned with the ends of the semiconductor layer 108.

[0235] In the semiconductor device 10C, the formation of the semiconductor layer 108 and the formation of the insulating layer 106 and the conductive layer 104 must be performed using separate masks, whereas in the semiconductor device 10D, the formation of the semiconductor layer 108, the formation of the insulating layer 106, and the formation of the conductive layer 104 can be performed simultaneously using the same mask. Therefore, the number of steps involved in the fabrication of the semiconductor device 10D can be reduced compared to the semiconductor device 10C.

[0236] With respect to the semiconductor device 10D shown in FIG. 11B, the contents described for the semiconductor device 10C shown in FIG. 11A can be referred to for other aspects.

[0237] 12A is a plan view of a semiconductor device 10E according to one embodiment of the present invention, which corresponds to the plan view of the semiconductor device 10 shown in FIG.

[0238] In the following, differences from the semiconductor device 10 shown in FIG. 1A etc. will be mainly described, and descriptions of overlapping parts may be omitted.

[0239] The semiconductor device 10E differs from the semiconductor device 10 shown in FIG. 1A etc. mainly in that the insulating layer 110 and conductive layer 112b, which are arranged in an island shape, have a concave polygonal shape with rounded corners CH in a planar view.

[0240] Because the semiconductor device 10E has the above-described configuration, the coverage of the semiconductor layer 108 (mainly the channel formation region) over the entire side surfaces of the insulating layer 110 and the conductive layer 112b, including the corners CH, can be improved compared to the semiconductor device 10.

[0241] With respect to the semiconductor device 10E shown in FIG. 12A, the contents described for the semiconductor device 10 shown in FIG. 1A and the like can be referred to for the rest of the description.

[0242] 12B is a plan view of a semiconductor device 10F according to one embodiment of the present invention, which corresponds to the plan view of the semiconductor device 10 shown in FIG.

[0243] In the following, differences from the semiconductor device 10 shown in FIG. 1A etc. will be mainly described, and descriptions of overlapping parts may be omitted.

[0244] 1A, etc. in that the insulating layer 110 and the conductive layer 112b, which are provided in an island shape, have a polygonal shape with a concave arc in a plan view. Specifically, the side surfaces of the insulating layer 110 and the conductive layer 112b in the region in contact with the semiconductor layer 108 each have a concave arc in a plan view.

[0245] The semiconductor device 10F having the above-described structure can improve coverage of the semiconductor layer 108 (mainly the channel formation region) on the side surfaces of the insulating layer 110 compared to the semiconductor device 10. Furthermore, by changing the length of the arc, the channel width of the transistor included in the semiconductor device 10F can be adjusted. As described above, in the semiconductor device of one embodiment of the present invention, the island-shaped insulating layer 110 and the conductive layer 112b can also have a polygonal shape formed by combining straight lines and curves in a plan view.

[0246] With respect to the semiconductor device 10F shown in FIG. 12B, the contents described for the semiconductor device 10 shown in FIG. 1A and the like can be referred to for the rest of the description.

[0247] 13A is a plan view of a semiconductor device 10G according to one embodiment of the present invention, which corresponds to the plan view of the semiconductor device 10 shown in FIG.

[0248] In the following, differences from the semiconductor device 10 shown in FIG. 1A etc. will be mainly described, and descriptions of overlapping parts may be omitted.

[0249] The semiconductor device 10G differs from the semiconductor device 10 shown in FIG. 1A, etc., mainly in that, in a plan view, the angle (angle θCH) formed by the two sides constituting the corner CH of the insulating layer 110 and the conductive layer 112b, which are arranged in an island shape, is an obtuse angle greater than 90 degrees and less than 180 degrees (i.e., the interior angle at the corner CH of the insulating layer 110 and the conductive layer 112b is greater than 180 degrees and less than 270 degrees).

[0250] The semiconductor device 10G having the above-described configuration can form a transistor having a channel width longer than that of the transistor 100 of the semiconductor device 10, thereby increasing the on-state current. Furthermore, the angle θ CH is not limited to 90 degrees (i.e., the interior angle at the corner CH between the insulating layer 110 and the conductive layer 112b is 270 degrees), which increases the degree of freedom in fabricating the semiconductor device.

[0251] With respect to the semiconductor device 10G shown in FIG. 13A, the contents described for the semiconductor device 10 shown in FIG. 1A and the like can be referred to for the rest of the description.

[0252] 13B is a plan view of a semiconductor device 10H according to one embodiment of the present invention, which corresponds to the plan view of the semiconductor device 10 shown in FIG.

[0253] In the following, differences from the semiconductor device 10 shown in FIG. 1A etc. will be mainly described, and descriptions of overlapping parts may be omitted.

[0254] The semiconductor device 10H differs from the semiconductor device 10 shown in FIG. 1A, etc., mainly in that, in a plan view, the angle (angle θCH) formed by the two sides constituting the corner CH of the insulating layer 110 and the conductive layer 112b, which are arranged in an island shape, is an acute angle greater than 0 degrees and less than 90 degrees (i.e., the interior angle at the corner CH of the insulating layer 110 and the conductive layer 112b is greater than 270 degrees and less than 360 degrees).

[0255] The semiconductor device 10H having the above-described structure can form a transistor having a channel width longer than that of the transistor 100 included in the semiconductor device 10, thereby increasing the on-state current. Furthermore, the angle θ CH is not limited to 90 degrees, which increases the degree of freedom in fabricating the semiconductor device.

[0256] 13A can also achieve the same effect as above, but the semiconductor device 10H can reduce the area occupied by the transistors because the angle θ CH is smaller than that of the semiconductor device 10G. For example, the widths of the conductive layers 112a and 112b in the Y direction can be reduced. Therefore, the semiconductor device 10H can be made smaller than the semiconductor device 10G.

[0257] With respect to the semiconductor device 10H shown in FIG. 13B, the contents described for the semiconductor device 10 shown in FIG. 1A and the like can be referred to for the rest of the description.

[0258] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0259] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0260] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0261] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0262] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 14A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 14B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0263] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 14B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 14A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 14A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 14A.

[0264] 14A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0265] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0266] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0267] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0268] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 14A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0269] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) a large on-current (in other words, high mobility); (2) a small off-current; (3) a normally-off state; (4) high reliability; and (5) a high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, a small off-current, and is normally-off. The transistor has high mobility and is different from a normally-on transistor.

[0270] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also referred to as microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0271] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0272] The crystallinity of indium oxide can be analyzed by, for example, XRD, TEM, or ED. Alternatively, the analysis may be performed by a combination of these methods.

[0273] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0274] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0275] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0276] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0277] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0278] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 14C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0279] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0280] Furthermore, as shown in FIG. 14C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２) or reacts with the oxygen contained in the film and is released as water molecules.

[0281] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0282] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a transistor using silicon for a semiconductor layer (hereinafter referred to as a Si transistor).

[0283]

[0284] A seed layer is preferably provided so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals that has a small difference in lattice constant with indium oxide (also referred to as lattice mismatch). This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0285] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0286] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0287] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0288] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0289] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0290] 15A to 25C , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of the same parts as those described in Embodiment 1 may be omitted.

[0291] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0292] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or knife coating.

[0293] When processing a thin film constituting a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0294] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0295] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0296] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0297] <Manufacturing Method Example> Here, an example of a manufacturing method of the semiconductor device 10 shown in Figures 1A to 1C will be described with reference to Figures 15A to 25C. In Figures 15 to 25, (A) in each figure corresponds to the plan view shown in Figure 1A. (B) in each figure corresponds to a cross-sectional view taken along dashed line A1-A2 in Figure 1A. (C) in each figure corresponds to a cross-sectional view taken along dashed line B1-B2 in Figure 1A.

[0298] First, a conductive film to be the conductive layer 112a is formed over the substrate 102, and then processed to form the conductive layer 112a (FIGS. 15A to 15C). The conductive film can be preferably formed by sputtering.

[0299] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed in this order on the conductive layer 112a (FIGS. 16A to 16C).

[0300] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf consecutively using the same apparatus.

[0301] The substrate temperature during deposition of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during deposition of the insulating films 110af and 110bf within the above-described range, the amount of impurities (e.g., water and hydrogen) released from the insulating films themselves can be reduced, and diffusion of the impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0302] Since the insulating films 110af and 110bf are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to heat applied during the formation of the insulating films 110af and 110bf.

[0303] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0304] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf (FIGS. 17A to 17C). Examples of methods that can be used to supply oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of oxygen, carbon monoxide, and carbon dioxide. The amount of oxygen supplied can be adjusted by, for example, the power and treatment time in the plasma treatment. In Figures 17B and 17C, arrows schematically show how oxygen (oxygen 180) is supplied to the insulating film 110bf.

[0305] After the insulating film 110bf is formed, nitrogen can be supplied to the insulating film 110bf. The nitrogen supply method can refer to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO ２The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0306] In the insulating layer (here, the insulating film 110bf or the later insulating layer 110b), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ , X is a real number greater than 0). ２ O, NO, and NO ２ In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level where the charge of the indium oxide changes between the 0 state and the -1 state is located within the band gap of the indium oxide. ２ When the metal oxide-containing semiconductor layer is diffused to the interface between the insulating layer and the semiconductor layer or near the interface, the level traps electrons. As a result, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer and the semiconductor layer or near the interface, which can shift the threshold voltage of the transistor in the positive direction. This makes it possible to realize a normally-off transistor (in the case of an n-channel transistor), thereby realizing a semiconductor device with low power consumption.

[0307] Increasing the amount of nitrogen oxide can shift the threshold voltage more to the positive side. However, if the amount of nitrogen oxide is too large, the fluctuation of the threshold voltage when a positive potential (positive bias) is applied to the gate of the transistor may become large, which may reduce reliability. Therefore, it is preferable to keep the amount of nitrogen oxide within a range that does not affect reliability.

[0308] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of released nitrogen oxides in thermal desorption spectroscopy (TDS) or the amount of electron spins in electron spin resonance (ESR). In TDS, NO (mass-to-charge ratio (m / z) = 30), N ２O (m / z=44), and NO ２ (m / z=46) can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２ Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２ Since the molecule has a lone electron, it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４ The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0309] The order of the process of supplying oxygen and the process of supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same process. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N ２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0310] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0311] Subsequently, the film 130 is preferably formed over the insulating film 110bf (FIGS. 18A to 18C). A sputtering method can be suitably used to form the film 130. By forming the film 130 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf.

[0312] The conductivity of the film 130 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 130. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 130.

[0313] The film 130 is preferably made of an oxide material containing one or more of the same elements as those of the semiconductor layer 108. In particular, it is preferably made of an oxide semiconductor that can be used for the semiconductor layer 108.

[0314] During the deposition of the film 130, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the deposition gas introduced into the processing chamber of the deposition apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0315] In this way, by forming the film 130 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 130, and oxygen can be prevented from being desorbed from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be realized that exhibits good electrical characteristics.

[0316] Heat treatment can be performed after the film 130 is formed. By performing heat treatment after the film 130 is formed, oxygen can be effectively supplied from the film 130 to the insulating film 110bf.

[0317] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating film 110af and the insulating film 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0318] After the film 130 is formed or after the heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 130. Oxygen can be supplied by, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. The above description of the plasma treatment can be referred to, and therefore detailed description thereof will be omitted.

[0319] Next, the film 130 is removed (FIGS. 19A to 19C). There is no particular limitation on the method for removing the film 130, but wet etching can be suitably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 130. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0320] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0321] Next, an insulating film 110cf that will become the insulating layer 110c is formed on the insulating film 110bf (FIGS. 20A to 20C). For the formation of the insulating film 110cf, the description of the formation of the insulating film 110af can be referred to.

[0322] When an oxide or oxynitride is used for the insulating layer 110c, the insulating film 110cf can be formed in an oxygen-containing atmosphere to supply oxygen to the insulating film 110bf. A sputtering method can be suitably used to form the insulating film 110cf. For example, the insulating film 110cf can be formed by sputtering using an aluminum target in an oxygen-containing atmosphere. When forming the insulating film 110cf, the higher the oxygen flow rate ratio of the deposition gas introduced into the treatment chamber of the deposition apparatus or the oxygen partial pressure in the treatment chamber, the more oxygen can be supplied to the insulating film 110bf. The oxygen flow rate ratio or the oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, even more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure to as close to 100% as possible.

[0323] By forming the insulating film 110cf in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the insulating film 110cf, and oxygen can be prevented from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be realized that exhibits good electrical characteristics.

[0324] Heat treatment can also be performed after the insulating film 110cf is formed. By performing heat treatment after the insulating film 110cf is formed, oxygen can be effectively supplied from the insulating film 110cf to the insulating film 110bf.

[0325] Next, a conductive film 112bf to be the conductive layer 112b is formed over the insulating film 110cf (FIGS. 21A to 21C). The conductive film 112bf can be formed by sputtering.

[0326] Next, the conductive film 112bf, the insulating film 110cf, the insulating film 110bf, and the insulating film 110af are processed to have a concave polygonal shape in plan view, respectively forming the conductive layer 112b, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a ( FIGS. 22A to 22C ). This results in the formation of the insulating layer 110, which includes the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c. The insulating layer 110 and the conductive layer 112b are formed so that, in plan view, two sides of the concave polygon that form an interior angle exceeding 180 degrees overlap with the conductive layer 112a. For example, wet etching can be suitably used to form the conductive layer 112b. For example, dry etching can be suitably used to form the insulating layer 110.

[0327] The conductive layer 112b and the insulating layer 110 can be formed using, for example, the same resist mask. After forming the insulating films (insulating film 110af, insulating film 110bf, and insulating film 110cf) that will become the insulating layer 110 and the conductive film 112bf, a resist mask is formed over the conductive film 112bf. The conductive film 112bf and the insulating film are processed using the resist mask to form the conductive layer 112b and the insulating layer 110, respectively. By using the same resist mask for forming the conductive layer 112b and the insulating layer 110, productivity can be improved. Furthermore, the top surface shapes of the conductive layer 112b and the insulating layer 110 can be made to match or approximately match. Note that different resist masks can be used for forming the conductive layer 112b and the insulating layer 110.

[0328] Next, a metal oxide film 108f to be the semiconductor layer 108 is formed so as to cover the conductive layer 112a, the conductive layer 112b, and the insulating layer 110 (FIGS. 23A to 23C). The metal oxide film 108f is provided in contact with the top surface of the conductive layer 112a, the top surface and side surfaces of the conductive layer 112b, and the side surface of the insulating layer 110.

[0329] The metal oxide film 108f is preferably formed by sputtering using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by ALD. By using the ALD method, the metal oxide film 108f can be formed with good coverage on the side surfaces of the insulating layer 110 and the conductive layer 112b. Furthermore, the ALD method allows easy control of the film formation rate, and therefore allows thin films to be formed with high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Furthermore, instead of the sputtering method and the ALD method, the metal oxide film 108f can also be formed by CVD.

[0330] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0331] Oxygen gas is preferably used when the metal oxide film 108f is formed. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0332] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 in a later process, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0333] When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film, the higher the crystallinity of the metal oxide film, and thus a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and thus a transistor with a large on-state current can be realized.

[0334] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, grain boundaries may become recombination centers, trapping carriers and reducing the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Because the ease with which a metal oxide film becomes polycrystalline varies depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film 108f. However, one embodiment of the present invention is not limited thereto, and a polycrystalline metal oxide may also be used. When the grain boundaries of a polycrystalline metal oxide film do not affect the transistor characteristics, a transistor using a polycrystalline metal oxide can be realized with higher reliability than a transistor using a metal oxide with low crystallinity.

[0335] The higher the substrate temperature during deposition of a metal oxide film, the higher the crystallinity and density of the resulting metal oxide film, which allows for the realization of a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the resulting metal oxide film, which allows for the realization of a transistor with a large on-state current.

[0336] The substrate temperature during deposition of the metal oxide film 108f is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because productivity is increased. Furthermore, by depositing the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0337] Note that if the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0338] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0339] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0340] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0341] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0342] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0343] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0344] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0345] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0346] Oxidizing agents include, for example, ozone, oxygen, and water.

[0347] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these factors, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these factors, it is possible to form a metal oxide film 108f whose composition changes continuously.

[0348] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0349] In the case where the semiconductor layer 108 has a stacked structure, it is preferable to deposit a metal oxide film first and then deposit a subsequent metal oxide film without exposing the surface of the first metal oxide film to the air.

[0350] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be deposited by the same method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for different layers. For example, a first metal oxide layer can be deposited by sputtering, and a second metal oxide layer on the first metal oxide layer can be deposited by ALD.

[0351] Subsequently, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 (FIGS. 24A to 24C).

[0352] A wet etching method can be suitably used to form the semiconductor layer 108. At this time, the conductive layers 112a and 112b in regions that do not overlap with the semiconductor layer 108 may be partly etched and thinned.

[0353] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108. The heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 or adsorbed on the surface. Furthermore, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, reduce defects or improve crystallinity).

[0354] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0355] Note that the heat treatment may not be performed if it is unnecessary. Alternatively, the heat treatment may be omitted here and may be performed in a subsequent step. Alternatively, a subsequent step in which heat is applied (e.g., a film formation step) may serve as the heat treatment.

[0356] Next, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, and the insulating layer 110 (FIGS. 25A to 25C). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0357] When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing into the conductive layer 104 through the insulating layer 106, thereby suppressing oxidation of the conductive layer 104. As a result, a highly reliable transistor with favorable electrical characteristics can be realized.

[0358] By increasing the temperature during deposition of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during deposition of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108, and oxygen vacancies (V Ｏ ) and V Ｏ H may increase. The substrate temperature during deposition of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during deposition of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a highly reliable transistor can be realized, which exhibits favorable electrical characteristics.

[0359] Before forming the insulating layer 106, plasma treatment can be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0360] Next, a conductive layer 104 is formed over the insulating layer 106 (FIGS. 1A to 1C). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0361] Through the above steps, the semiconductor device 10 of one embodiment of the present invention can be manufactured.

[0362] This embodiment mode can be combined with other embodiment modes as appropriate.

[0363] Embodiment 4 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 26 to 34B. FIG.

[0364] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit of electronic devices having a relatively large screen, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0365] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0366] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0367] The display device of this embodiment can also function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0368] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0369] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0370] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0371] <Display Device 50A> FIG. 26 shows a perspective view of the display device 50A.

[0372] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 26, the substrate 152 is indicated by a dashed line.

[0373] The display device 50A has a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Fig. 26 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 26 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0374] The connection portion 140 is provided outside the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There can be one connection portion 140 or multiple connection portions 140. FIG. 26 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0375] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 can include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0376] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0377] 26 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. The display device 50A and the display module may also be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0378] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. The use of an OS transistor enables a display device with low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device, it is possible to reduce manufacturing costs.

[0379] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0380] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 26 shows an enlarged view of one pixel 201.

[0381] The pixel arrangement in the display device of this embodiment is not particularly limited, and various arrangements can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0382] 26 includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the number of sub-pixels included in one pixel is not particularly limited.

[0383] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0384] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements using microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc. Furthermore, a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials can also be used.

[0385] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0386] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0387] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. In addition, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0388] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs, OLEDs (organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0389] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0390] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0391] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0392] Note that the display device of one embodiment of the present invention can be any of a top-emission type in which light is emitted in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type in which light is emitted toward a substrate on which a light-emitting element is formed, and a dual-emission type in which light is emitted to both sides.

[0393] Figure 27A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0394] 27A includes transistors 205D, 205R, 205G, and 205B, as well as light-emitting elements 130R, 130G, and 130B, between substrates 151 and 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0395] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0396] The display device 50A is a top emission type, which allows transistors and the like to be arranged overlapping the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0397] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured in the same process. Note that the transistors 205D, the transistor 205R, the transistor 205G, and the transistor 205B may each have a different structure.

[0398] In this embodiment, OS transistors are used as the transistors 205D, 205R, 205G, and 205B. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistors according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistors according to one embodiment of the present invention.

[0399] Specifically, the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B each include a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, conductive layers 112a and 112b that function as a source and a drain, a semiconductor layer 108 containing metal oxide, and an insulating layer 110. Here, the same hatched pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 110 is located between the conductive layer 112a and the conductive layer 112b. The insulating layer 106 is located between the conductive layer 104 and the semiconductor layer 108.

[0400] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0401] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, the display device may have a structure in which gates are provided above and below a semiconductor layer in which a channel is formed.

[0402] The display device of this embodiment may also have a Si transistor.

[0403] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher source-drain breakdown voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0404] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage. This allows the amount of current flowing to a light-emitting element to be controlled. This allows for a greater number of gray levels to be achieved in the pixel circuit.

[0405] In terms of the saturation of the current that flows when a transistor operates in the saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0406] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0407] All of the transistors included in the display portion 162 can be OS transistors, all of the transistors included in the display portion 162 can be Si transistors, or some of the transistors included in the display portion 162 can be OS transistors and the rest can be Si transistors.

[0408] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0409] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and the drain of the driving transistor is connected to a pixel electrode of the light-emitting element. An LTPS transistor is preferably used as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0410] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly low (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0411] An insulating layer 218 is provided to cover the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B, and an insulating layer 235 is provided over the insulating layer 218.

[0412] The insulating layer 218 preferably functions as a protective layer for the transistor. The insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 218 to function as a barrier film. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0413] The insulating layer 218 preferably includes one or more inorganic insulating layers. The insulating layer 218 can be made of the same material as that used for the insulating layer 110.

[0414] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 can also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, and the like. Alternatively, the insulating layer 235 can be configured to have recesses formed during processing of the pixel electrodes 111R, 111G, 111B, and the like. The pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrodes 111.

[0415] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0416] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 27A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0417] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 27A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0418] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 27A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0419] 27A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited thereto. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, it is preferable to set the thicknesses of the EL layers 113R, 113G, and 113B so that the optical path length increases the intensity of the light emitted by each layer. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element can be improved.

[0420] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0421] Ends of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the material that can be used for the insulating layer 218 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0422] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. The insulating layer 237 may also be configured to be provided up to the edge of the display device 50A.

[0423] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0424] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0425] A conductive film that transmits visible light can also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can be reflected by the reflective layer and extracted from the display device.

[0426] Materials for forming the pair of electrodes of a light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum alloys, such as an aluminum-nickel-lanthanum alloy (Al-Ni-La), and silver-magnesium alloys and silver-palladium-copper alloys (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0427] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0428] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ It is preferably Ωcm or less.

[0429] The EL layer 113R, the EL layer 113G, and the EL layer 113B are each provided in an island shape. In FIG. 27A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 27A , but this is not limited to this. That is, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both overlapping portions and non-overlapping portions where adjacent EL layers are spaced apart.

[0430] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0431] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0432] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) may be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and high hole-transport properties) or a TADF material may also be used.

[0433] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing efficient emission. This configuration allows the light-emitting element to simultaneously achieve high efficiency, low-voltage operation, and a long life.

[0434] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer). In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0435] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and can also contain an inorganic compound. Each of the layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0436] A light-emitting element can have either a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. A tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows for a light-emitting element capable of emitting high-brightness light. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stacked structure.

[0437] In Figure 27A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0438] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 27A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, thereby applying a solid sealing structure. Alternatively, the space can be filled with an inert gas (such as nitrogen or argon), thereby applying a hollow sealing structure. In this case, the adhesive layer 142 can be provided so as not to overlap with the light-emitting elements. The space can also be filled with a resin different from the frame-shaped adhesive layer 142.

[0439] The protective layer 131 is preferably provided on at least the display portion 162, and is preferably provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162, but also the connection portion 140 and the circuit portion 164. The protective layer 131 is preferably provided up to the edge of the display device 50A. On the other hand, the connection portion 197 has a portion where the protective layer 131 is not provided, in order to connect the FPC 172 and the conductive layer 165.

[0440] By providing the protective layer 131 on the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B, the reliability of the light emitting element can be improved.

[0441] The protective layer 131 can have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0442] The protective layer 131 has an inorganic film, which prevents the common electrode 115 from being oxidized, prevents impurities (water, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0443] The protective layer 131 preferably includes one or more inorganic insulating layers. The protective layer 131 can be made of a material that can be used for the insulating layer 110. In particular, the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.

[0444] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, and more specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0445] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0446] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0447] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0448] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. In this example, the conductive layer 165 is a conductive layer obtained by processing the same conductive film as the conductive layer 112b. In this example, the conductive layer 166 is a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The connection portion between the conductive layer 165 and the conductive layer 166 can have a similar structure to the connection portion between the pixel electrode 111 and the conductive layer 112b. Specifically, FIG. 27A shows an example in which an opening is provided above the conductive layer 165, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 through the opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be connected via the connection layer 242 .

[0449] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0450] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, the circuit section 164, and the like.

[0451] A colored layer such as a color filter can be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0452] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using lithography, or the like.

[0453] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer can also be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0454] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate can also be used for at least one of the substrates 151 and 152.

[0455] Substrates 151 and 152 can be made of polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 can be made of glass having a thickness sufficient to provide flexibility.

[0456] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0457] The adhesive layer 142 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins can also be used. Adhesive sheets, etc., can also be used.

[0458] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0459] <Display Device 50B> Figure 27B shows an example of a cross section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each subpixel of each color. The configuration shown in Figure 27B can be combined with the region including the FPC 172, the circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the end portion configuration shown in Figure 27A. Note that in the following description of the display device, descriptions of parts similar to those of the display device described above may be omitted.

[0460] The display device 50B shown in Figure 27B has a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0461] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0462] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0463] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0464] The light-emitting elements 130R, 130G, and 130B each have a common EL layer 113 and a common electrode 115. The configuration in which the EL layer 113 is common to the subpixels of each color can reduce the number of manufacturing steps compared to the configuration in which different EL layers are provided for the subpixels of each color.

[0465] 27B , light emitting elements 130R, 130G, and 130B each emit white light. The white light emitted by light emitting elements 130R, 130G, and 130B passes through colored layers 132R, 132G, and 132B, respectively, to obtain light of a desired color.

[0466] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers can be selected such that the emission colors of the two light-emitting layers have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer have a complementary color relationship, a configuration in which the light-emitting element as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0467] The EL layer 113 preferably includes, for example, a light-emitting layer having a light-emitting substance that emits blue light and a light-emitting layer having a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0468] A tandem structure is preferably used for the light-emitting element emitting white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and red light, and a light-emitting unit that emits blue light, in this order, or the like can be applied. For example, the number of stacked light-emitting units and the order of their colors can be, from the anode side, a two-layer structure of B and Y (yellow), a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, or a three-layer structure of B, X, and B. The number of stacked light-emitting layers in light-emitting unit X and the order of their colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, a configuration in which another layer is provided between the two light-emitting layers can also be used.

[0469] By applying a microcavity structure, a light emitting element configured to emit white light may emit light of a specific wavelength such as red, green, or blue that is intensified.

[0470] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 27B each emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or the light-emitting element 130G into light with a longer wavelength, thereby extracting red or green light. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A portion of the light emitted by the light-emitting element may be transmitted directly without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0471] <Display Device 50C> A display device 50C shown in FIG. 28 differs from the display device 50B mainly in that it is a bottom-emission display device.

[0472] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0473] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor. Figure 28 shows an example in which the light-shielding layer 117 is provided over the substrate 151, the insulating layer 153 is provided over the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided over the insulating layer 153. Furthermore, the coloring layers 132R, 132G, and 132B are provided over the insulating layer 218, and the insulating layer 235 is provided over the coloring layers 132R, 132G, and 132B.

[0474] The light emitting element 130R overlapping the colored layer 132R includes a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0475] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0476] The light emitting element 130B overlapping the colored layer 132B has a pixel electrode 111B, an EL layer 113 and a common electrode 115.

[0477] The pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal or the like with low electrical resistivity can be used for the common electrode 115, which can suppress voltage drops caused by the electrical resistance of the common electrode 115 and achieve high display quality.

[0478] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the pixel size can be reduced.

[0479] <Display Device 50D> A display device 50D shown in FIG. 29A differs from the display device 50A mainly in that it has a light receiving element 130S.

[0480] The display device 50D has a light-emitting element and a light-receiving element in each pixel. In the display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element.

[0481] In the display device 50D, in which pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so that it is possible to detect contact or proximity of an object while displaying an image. Therefore, the display unit 162 has one or both of an imaging function and a sensing function in addition to an image display function. For example, in addition to displaying an image using all of the sub-pixels of the display device 50D, it is also possible for some sub-pixels to emit light as a light source, other sub-pixels to perform light detection, and the remaining sub-pixels to display an image.

[0482] Therefore, there is no need to provide a light receiving unit and a light source separately from the display device 50D, and the number of components in the electronic device can be reduced. For example, there is no need to provide a separate biometric authentication device or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

[0483] When a light receiving element is used as an image sensor, the display device 50D can capture an image using the light receiving element. For example, the image sensor can capture an image for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, etc.

[0484] The light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor). A touch sensor can detect an object (such as a finger, hand, or pen) when the object comes into direct contact with the display device. A non-contact sensor can detect an object without the object touching the display device.

[0485] The light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0486] The pixel electrode 111S is connected to a conductive layer 112b of the transistor 205S in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.

[0487] The end of the pixel electrode 111S is covered with an insulating layer 237.

[0488] The common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B. The common electrode 115 shared by the light emitting element and the light receiving element is connected to a conductive layer 123 provided in the connection portion 140.

[0489] The functional layer 113S has at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors including organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer will be described. By using an organic semiconductor, the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), which is preferable because a common manufacturing device can be used.

[0490] The functional layer 113S may further include a layer containing a substance with high hole transporting properties, a substance with high electron transporting properties, a bipolar substance, or the like, as a layer other than the active layer. Furthermore, without being limited to the above, the functional layer 113S may further include a layer containing a substance with high hole injection properties, a hole blocking material, a substance with high electron injection properties, an electron blocking material, or the like. For example, the materials that can be used for the light-emitting element described above can be used for the functional layer 113S.

[0491] The light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and can also contain an inorganic compound. The layers constituting the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), a transfer method, a printing method, an inkjet method, or a coating method.

[0492] A display device 50D shown in FIGS. 29B and 29C has, between a substrate 151 and a substrate 152, a layer 353 having a light receiving element, a circuit layer 355, and a layer 357 having a light emitting element.

[0493] The layer 353 includes, for example, the light receiving element 130S. The layer 357 includes, for example, the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B.

[0494] The circuit layer 355 includes a circuit for driving the light receiving element and a circuit for driving the light emitting element. The circuit layer 355 includes, for example, a transistor 205R, a transistor 205G, and a transistor 205B. In addition, the circuit layer 355 may include one or more of a switch, a capacitor, a resistor, a wiring, a terminal, and the like.

[0495] 29B shows an example in which the light receiving element 130S is used as a touch sensor. As shown in FIG. 29B, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that touches the display device 50D, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has touched the display device 50D.

[0496] 29C shows an example in which the light receiving element 130S is used as a non-contact sensor. As shown in FIG. 29C, light emitted by a light emitting element in a layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light receiving element in a layer 353 detects the reflected light.

[0497] 30A is an example of a display device employing an MML (metal maskless) structure. That is, the display device 50E has light-emitting elements fabricated without using a fine metal mask.

[0498] The island-shaped light-emitting layers in the light-emitting elements of a display device employing the MML structure are formed by depositing a light-emitting layer on one surface and then processing it using lithography. This allows for the realization of high-definition display devices or display devices with a high aperture ratio, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be created separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized. For example, if a display device is composed of three types of light-emitting elements, namely, light-emitting elements that emit blue light, light-emitting elements that emit green light, and light-emitting elements that emit red light, the deposition of the light-emitting layers and the processing by lithography can be repeated three times to form the three types of island-shaped light-emitting layers.

[0499] Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution imposed by the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the metal mask cleaning process are unnecessary. Furthermore, since the same or similar equipment as that used for manufacturing transistors can be used for lithography processing, there is no need to introduce special equipment for manufacturing MML structure devices. As such, the MML structure allows for low manufacturing costs, making it suitable for mass production of devices.

[0500] In a display device to which the MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, and therefore it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) using a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.

[0501] By providing a sacrificial layer over the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0502] By employing a film formation step using an area mask and a processing step using a resist mask, a light-emitting element can be manufactured through a relatively simple process.

[0503] The layered structure from the substrate 151 to the insulating layer 235 and the layered structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, and therefore will not be described here.

[0504] In FIG. 30A, a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B are provided on an insulating layer 235.

[0505] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in FIG. 30A emits red light (R). The layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 114 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

[0506] The light-emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in FIG. 30A emits green light (G). The layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 114 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0507] The light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in FIG. 30A emits blue light (B). The layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 114 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

[0508] In this specification and the like, among the EL layers included in the light-emitting elements, layers provided in an island shape for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 114. Note that in this specification and the like, the layers 133R, 133G, and 133B may be referred to as island-shaped EL layers, EL layers formed in an island shape, or the like, without including the common layer 114. Furthermore, a light-emitting element manufactured without using a metal mask may have a structure without a common layer, and may have a structure in which all layers constituting the EL layer are formed in an island shape.

[0509] The layers 133R, 133G, and 133B are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.

[0510] 30A, the layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limitative. The layers 133R, 133G, and 133B may also have different thicknesses.

[0511] The conductive layer 124R is connected to the conductive layer 112b of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the conductive layer 124G is connected to the conductive layer 112b of the transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of the transistor 205B.

[0512] The conductive layers 124R, 124G, and 124B are each formed to cover an opening provided in the insulating layer 235. A layer 128 is buried in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0513] The layer 128 has the function of planarizing the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B. The conductive layers 126R, 126G, and 126B, which are connected to the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, are provided on the conductive layer 124R and the layer 128, on the conductive layer 124G and the layer 128, and on the conductive layer 124B and the layer 128, respectively. Therefore, the regions overlapping with the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixel. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layer 124R and the conductive layer 126R.

[0514] The layer 128 can be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. The layer 128 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 237 can be used for the layer 128.

[0515] 30A shows an example in which the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0516] The height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R can be the same or approximately the same, or can be different from each other. For example, the height of the upper surface of layer 128 can be lower or higher than the height of the upper surface of conductive layer 124R.

[0517] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side surface of the end of the conductive layer 124R. The end of each of the conductive layers 124R and 126R preferably has a tapered shape. Specifically, the end of each of the conductive layers 124R and 126R preferably has a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By tapering the side surface of the pixel electrode, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0518] The conductive layers 124G and 126G, and the conductive layers 124B and 126B are similar to the conductive layers 124R and 126R, respectively, and therefore will not be described in detail.

[0519] The top surface and side surfaces of the conductive layer 126R are covered with the layer 133R. Similarly, the top surface and side surfaces of the conductive layer 126G are covered with the layer 133G, and the top surface and side surfaces of the conductive layer 126B are covered with the layer 133B. Therefore, the entire regions where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting regions of the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B, respectively, thereby increasing the aperture ratio of the pixel.

[0520] Part of the top surface and side surfaces of each of the layers 133R, 133G, and 133B are covered with the insulating layer 125 and the insulating layer 127. A common layer 114 is provided on the layers 133R, 133G, 133B, the insulating layer 125, and the insulating layer 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to a plurality of light-emitting elements.

[0521] In FIG. 30A , the insulating layer 237 shown in FIG. 27A and other figures is not provided between the conductive layer 126R and the layer 133R. That is, the display device 50E does not have an insulating layer (also referred to as a partition wall, bank, spacer, or the like) that contacts the pixel electrode and covers the upper edge of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This allows a high-definition or high-resolution display device to be obtained. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0522] The layers 133R, 133G, and 133B each have a light-emitting layer. The layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer). Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer). Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer, a carrier block layer, and a carrier transport layer on the carrier block layer. It is more preferable that the carrier transport layer be provided on the light-emitting layer. It is more preferable that the carrier block layer be provided on the light-emitting layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer, thereby improving the reliability of the light-emitting element.

[0523] The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0524] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B with the insulating layer 125 interposed therebetween.

[0525] The side surfaces (and even part of the upper surfaces) of the layers 133R, 133G, and 133B are covered with at least one of the insulating layer 125 and the insulating layer 127, which prevents the common layer 114 (or the common electrode 115) from contacting the pixel electrode and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting element, thereby improving the reliability of the light-emitting element.

[0526] The insulating layer 125 preferably has a region in contact with each side surface of the layer 133R, the layer 133G, and the layer 133B. The insulating layer 125 in contact with the layer 133R, the layer 133G, and the layer 133B can prevent the layer 133R, the layer 133G, and the layer 133B from peeling off, thereby improving the reliability of the light-emitting element.

[0527] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0528] By providing the insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, which reduces large unevenness in height on the surface on which a layer (e.g., a carrier injection layer, a common electrode, etc.) is formed on the island-shaped layers, thereby making the surface flatter, thereby improving the coverage of the carrier injection layer, the common electrode, etc.

[0529] The common layer 114 and the common electrode 115 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting elements). In the display device of one embodiment of the present invention, the insulating layer 125 and the insulating layer 127 can flatten the step, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection due to a step disconnection of the common layer 114 or the common electrode 115 can be suppressed. Furthermore, an increase in electrical resistance caused by a local thinning of the common electrode 115 due to the step can be suppressed.

[0530] The upper surface of the insulating layer 127 preferably has a highly flat shape. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a convex curved shape with a large radius of curvature.

[0531] The insulating layer 125 can have a single-layer structure or a stacked structure of two or more layers. The insulating layer 125 preferably has one or more inorganic insulating layers. The insulating layer 125 can be formed using a material that can be used for the insulating layer 110. Aluminum oxide is particularly preferable because it has a high etching selectivity with respect to the EL layer and has a function of protecting the EL layer in the formation of the insulating layer 127. By using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 125, the insulating layer 125 can have few pinholes and an excellent function of protecting the EL layer. The insulating layer 125 can also have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulating layer 125 can also have a stacked structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0532] The insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 preferably has a function of capturing or fixing (gettering) at least one of water and oxygen.

[0533] The insulating layer 125 has a function as a barrier insulating layer, which can suppress the intrusion of impurities (typically, at least one of water and oxygen) that can diffuse into each light-emitting element from the outside. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.

[0534] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. Furthermore, by reducing the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both of them.

[0535] The insulating layer 127 provided on the insulating layer 125 has a function of flattening large unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.

[0536] An insulating layer containing an organic material can be suitably used as the insulating layer 127. A photosensitive resin is preferably used as the organic material, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0537] The insulating layer 127 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins. The insulating layer 127 may also be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. The photosensitive resin may also be a photoresist. Either a positive-type material or a negative-type material may be used as the photosensitive resin.

[0538] The insulating layer 127 can also be made of a material that absorbs visible light. The insulating layer 127 absorbs light emitted from the light-emitting element, thereby preventing light from leaking from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0539] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed can enhance the visible light blocking effect, making it preferable. In particular, mixing three or more color filter materials can make a resin layer that is black or nearly black.

[0540] <Display Device 50F> Figure 30B shows an example of a cross section of the display unit 162 of the display device 50F. The display device 50F differs from the display device 50E mainly in that a colored layer (such as a color filter) is provided in each subpixel of each color. The configuration shown in Figure 30B can be combined with the region including the FPC 172, the circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in Figure 30A.

[0541] The display device 50F shown in Figure 30B has a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0542] The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50F via the colored layer 132R. Similarly, the light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50F via the colored layer 132G. The light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50F via the colored layer 132B.

[0543] The light-emitting elements 130R, 130G, and 130B each have a layer 133. These three layers 133 are formed using the same material and in the same process. Furthermore, these three layers 133 are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.

[0544] 30B emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, to obtain light of a desired color.

[0545] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 30B emit blue light. In this case, the layer 133 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or the light-emitting element 130G into light with a longer wavelength, thereby allowing red or green light to be extracted. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0546] <Display Device 50G> A display device 50G shown in FIG. 31 differs from the display device 50F mainly in that it is a bottom-emission display device.

[0547] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0548] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor. Fig. 31 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, 205B, and the like are provided on the insulating layer 153. Furthermore, the coloring layers 132R, 132G, and 132B are provided on the insulating layer 218, and the insulating layer 235 is provided on the coloring layers 132R, 132G, and 132B.

[0549] The light emitting element 130R overlapping the colored layer 132R includes a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.

[0550] The light emitting element 130G overlapping the colored layer 132G includes a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.

[0551] The light emitting element 130B overlapping the colored layer 132B has a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.

[0552] The conductive layers 124R, 124G, 124B, 126R, 126G, and 126B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal or the like with low electrical resistivity can be used for the common electrode 115, which can suppress voltage drops caused by the electrical resistance of the common electrode 115 and achieve high display quality.

[0553] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the pixel size can be reduced.

[0554] <Display Device 50H> A display device 50H shown in FIG. 32A is a VA mode liquid crystal display device.

[0555] Substrate 151 and substrate 152 are bonded together by adhesive layer 144. Liquid crystal 262 is sealed in the area surrounded by substrate 151, substrate 152, and adhesive layer 144. Polarizing plate 260a is located on the outer surface of substrate 152, and polarizing plate 260b is located on the outer surface of substrate 151. Although not shown, a backlight can be provided outside polarizing plate 260a or polarizing plate 260b.

[0556] The substrate 151 is provided with a transistor 205D, a transistor 205R, a transistor 205G, a connection portion 197, a spacer 224, and the like. The transistor 205D is provided in the circuit portion 164, and the transistors 205R and 205G are provided in the display portion 162. The conductive layer 112b included in the transistor 205R and the transistor 205G functions as a pixel electrode of the liquid crystal element 60.

[0557] The substrate 152 is provided with a colored layer 132R, a colored layer 132G, a light-shielding layer 117, an insulating layer 225, a conductive layer 263, etc. The conductive layer 263 functions as a common electrode for the liquid crystal element 60.

[0558] The transistor 205D, the transistor 205R, and the transistor 205G each include a conductive layer 112a, a semiconductor layer 108, an insulating layer 106, a conductive layer 104, and a conductive layer 112b. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode. The conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer.

[0559] As described above, in this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, and 205G is shown. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, and 205G. That is, the display device 50H includes transistors according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, thereby achieving higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, thereby achieving a narrower frame. For the transistor according to one embodiment of the present invention, refer to the description of the previous embodiment.

[0560] The transistor 205D, the transistor 205R, and the transistor 205G are covered with an insulating layer 218. The insulating layer 218 functions as a protective layer for the transistor 205D, the transistor 205R, and the transistor 205G.

[0561] Each subpixel included in the display unit 162 includes a transistor, a liquid crystal element 60, and a colored layer. For example, a subpixel that emits red light includes a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light. A subpixel that emits green light includes a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light. Although not shown, a subpixel that emits blue light similarly includes a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.

[0562] The liquid crystal element 60 includes a conductive layer 112b, a conductive layer 263, and a liquid crystal 262 sandwiched between them.

[0563] A conductive layer 264 is provided on the substrate 151 and is located on the same plane as the conductive layer 112a. The conductive layer 264 has a portion that overlaps with the conductive layer 112b via the insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c). A storage capacitor is formed by the conductive layer 112b, the conductive layer 264, and the insulating layer 110 therebetween. Note that it is sufficient to have one or more insulating layers between the conductive layer 112b and the conductive layer 264, and a configuration in which one or two of the insulating layers 110 are removed by etching may also be used.

[0564] On the substrate 152 side, an insulating layer 225 is provided to cover the colored layer 132R, the colored layer 132G, and the light-shielding layer 117. The insulating layer 225 can also function as a planarizing layer. The insulating layer 225 can make the surface of the conductive layer 263 approximately flat, thereby making the alignment state of the liquid crystal 262 uniform.

[0565] Note that the conductive layer 263, the insulating layer 218, etc. may have a structure in which an orientation film for controlling the orientation of the liquid crystal 262 is provided on the surface that comes into contact with the liquid crystal 262 (see the orientation film 265 in Figures 34A and 34B).

[0566] The conductive layer 112b and the conductive layer 263 transmit visible light. In other words, a transmissive liquid crystal device can be formed. For example, if a backlight is disposed on the substrate 152 side, light from the backlight polarized by the polarizing plate 260a passes through the substrate 152, the conductive layer 263, the liquid crystal 262, the conductive layer 112b, and the substrate 151, and reaches the polarizing plate 260b. At this time, the orientation of the liquid crystal 262 can be controlled by applying a voltage between the conductive layer 112b and the conductive layer 263, thereby controlling the optical modulation of the light. In other words, the intensity of the light emitted via the polarizing plate 260b can be controlled. Furthermore, the colored layer absorbs light outside a specific wavelength range of the incident light, so that the extracted light exhibits, for example, red light.

[0567] Here, a linear polarizer or a circular polarizer can be used as the polarizer 260b. For example, a linear polarizer and a quarter-wave retardation plate stacked together can be used as the circular polarizer. Using a circular polarizer as the polarizer 260b can suppress reflection of external light.

[0568] When a circular polarizer is used as polarizer 260b, a circular polarizer or a normal linear polarizer can also be used as polarizer 260a. The desired contrast can be achieved by adjusting the cell gap, orientation, drive voltage, etc. of the liquid crystal element used in liquid crystal element 60 according to the type of polarizer used for polarizers 260a and 260b.

[0569] The conductive layer 263 is connected to a conductive layer 166b provided on the substrate 151 side by a connector 223 in the connection portion 140. The conductive layer 166b is connected to the conductive layer 165b through an opening provided in the insulating layer 110 or the like. This allows a potential or a signal to be supplied to the conductive layer 263 from an FPC or an IC arranged on the substrate 151 side. In the configuration shown in Figure 32A, an example is shown in which the conductive layer 165b is formed using the same material and in the same process as the conductive layer 112a, and the conductive layer 166b is formed using the same material and in the same process as the conductive layer 104.

[0570] The connectors 223 may be, for example, conductive particles. Examples of conductive particles include particles of resin or silica coated with a metal material. Nickel or gold is preferable as the metal material because it reduces contact resistance. It is also preferable to use particles coated with two or more layers of metal materials, such as nickel coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the connectors 223. In this case, the conductive particles may be crushed vertically, as shown in FIG. 32A . This increases the contact area between the connectors 223 and the conductive layer to which they are connected, reducing contact resistance and preventing problems such as poor connection. The connectors 223 are preferably arranged so that they are covered by the adhesive layer 144. For example, the connectors 223 are preferably dispersed in the adhesive layer 144 before hardening.

[0571] A connection portion 197 is provided in a region near the end of the substrate 151. In the connection portion 197, the conductive layer 166a is connected to the FPC 172 via a connection layer 242. The conductive layer 166a is connected to the conductive layer 165a via an opening provided in the insulating layer 110 or the like. The configuration shown in FIG. 32A illustrates an example in which the conductive layer 165a is formed using the same material and in the same process as the conductive layer 112a, and the conductive layer 166a is formed using the same material and in the same process as the conductive layer 104.

[0572] 32B shows a configuration example different from the connection portion 197 shown in FIG. 32B shows a configuration in which the insulating layer 110 is not provided on the conductive layer 165a. Furthermore, the conductive layer 166a is not provided, and the conductive layer 165a is in contact with and connected to the connection layer 242. The FPC 172 is connected to the conductive layer 165a via the connection layer 242.

[0573] 32C shows an example of a configuration different from that of the connection portion 140 shown in FIG. 32A. In FIG. 32C, an insulating layer 110 is not provided on the conductive layer 165b. In addition, the conductive layer 166b is not provided, and the conductive layer 165b is in contact with and connected to the connector 223.

[0574] 33 is a liquid crystal display device in the FFS mode. The display device 50I differs from the display device 50H mainly in the configuration of the liquid crystal element 60.

[0575] A conductive layer 263 functioning as a common electrode of the liquid crystal element 60 is provided over the insulating layer 110, and an insulating layer 261 is provided over the conductive layer 263. In addition, a conductive layer 112b which functions as the other of the source electrode and the drain electrode of the transistor and as a pixel electrode of the liquid crystal element 60 is provided over the insulating layer 261. An insulating layer 218 is provided over the conductive layer 112b with the insulating layer 106 interposed therebetween.

[0576] The conductive layer 112b has a comb-like shape or a shape provided with slits in a plan view. The conductive layer 263 is disposed to overlap with the conductive layer 112b. In addition, in a region overlapping with the colored layer, there is a portion on the conductive layer 263 where the conductive layer 112b is not disposed.

[0577] A capacitance is formed by stacking the conductive layer 112b and the conductive layer 263 with the insulating layer 261 interposed therebetween. Therefore, there is no need to separately form a capacitor element, and the aperture ratio of the pixel can be increased.

[0578] In the liquid crystal element 60, both the conductive layer 112b and the conductive layer 263 can be provided so as to have a comb-like upper surface. On the other hand, as shown in a display device 50I, in the liquid crystal element 60, by providing only one of the conductive layer 112b and the conductive layer 263 so as to have a comb-like upper surface, the conductive layer 112b and the conductive layer 263 partially overlap with each other. This allows the capacitance between the conductive layer 112b and the conductive layer 263 to be used as a storage capacitor, eliminating the need for a separate capacitor element and enabling the aperture ratio of the display device to be increased.

[0579] 34A , a portion of the insulating layer 110 that overlaps with the liquid crystal element 60 is removed by etching. The liquid crystal element 60 of the display device 50J has a portion where a conductive layer 264a, an insulating layer 109, and a conductive layer 112b are stacked in this order. By not overlapping the liquid crystal element 60 with the insulating layer 110, not only can the light transmittance be increased but also the number of interfaces located on the path of light from the light source can be reduced, thereby suppressing the effects of interface reflection and interface scattering.

[0580] The conductive layer 112b functions as a pixel electrode of the liquid crystal element 60. The conductive layer 264a functions as a common electrode of the liquid crystal element 60. The conductive layer 264a is provided between the insulating layer 109 and the substrate 151.

[0581] It is preferable that the insulating layer 110 is not provided over the conductive layer 264a. The insulating layer 109 is provided over the conductive layer 264a, and the conductive layer 112b is provided over the insulating layer 109. This increases the capacitance between the conductive layer 112b and the conductive layer 264a. One or both of the insulating layers 106 and 218 may have portions that overlap with the liquid crystal element 60 removed by etching. Alternatively, the insulating layer 218 may not be provided. This allows the electric field of the conductive layer 112b and the conductive layer 264a to be easily transmitted to the liquid crystal 262, thereby enabling high-speed operation of the liquid crystal element 60. Furthermore, not only is the light transmittance in the portion that overlaps with the liquid crystal element 60 increased, but the effects of interface reflection and interface scattering can also be suppressed.

[0582] In the liquid crystal element 60, both the conductive layer 112b and the conductive layer 264a can be provided so as to have a comb-like upper surface. On the other hand, as shown in a display device 50J, in the liquid crystal element 60, by providing only one of the conductive layer 112b and the conductive layer 264a so as to have a comb-like upper surface, the conductive layer 112b and the conductive layer 264a partially overlap with each other. This allows the capacitance between the conductive layer 112b and the conductive layer 264a to be used as a storage capacitor, eliminating the need for a separate capacitor element and enabling the aperture ratio of the display device to be increased.

[0583] 34B is different from the display device 50I mainly in that a common electrode is provided over a pixel electrode. The conductive layer 112b of a transistor (here, the transistor 205R) functions as a pixel electrode in the liquid crystal element 60. The insulating layer 106 and the insulating layer 218 are provided over the conductive layer 112b, and the conductive layer 263 is provided over the insulating layer 218. The conductive layer 263 functions as a common electrode in the liquid crystal element 60. The conductive layer 263 has a comb-like shape or a shape provided with slits in a plan view.

[0584] This embodiment mode can be combined with other embodiment modes as appropriate.

[0585] Embodiment 5 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 35A to 37G.

[0586] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0587] The semiconductor device of one embodiment of the present invention can be applied to a portion other than the display portion of an electronic device. For example, the use of the semiconductor device of one embodiment of the present invention in a control portion of an electronic device is preferable because it enables low power consumption.

[0588] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0589] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0590] The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0591] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0592] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0593] 35A to 35D , examples of wearable devices that can be worn on the head are described. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device with the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion felt by the user.

[0594] The electronic device 700A shown in Figure 35A and the electronic device 700B shown in Figure 35B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0595] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0596] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0597] Each of electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of it as an imaging unit. Furthermore, each of electronic device 700A and electronic device 700B may be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0598] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0599] The electronic device 700A and the electronic device 700B are each provided with a battery (not shown), which can be charged wirelessly and / or wired.

[0600] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can broaden the range of operations. 【060...

Claims

a transistor and a first insulating layer; the transistor has a first conductive layer, a second conductive layer, and a semiconductor layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have respective ends that coincide or substantially coincide with each other in a plan view, and have a concave polygonal shape in a plan view; two sides of the concave polygon that form an interior angle exceeding 180 degrees overlap with the first conductive layer in a plan view; the semiconductor layer is located on the first conductive layer and the second conductive layer so as to have an area overlapping with the two sides in a plan view, and is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, and a top surface of the second conductive layer; Semiconductor device. 　 In claim 1, the semiconductor layer is an oxide semiconductor layer containing indium, the first insulating layer has a second insulating layer, a third insulating layer on the second insulating layer, and a fourth insulating layer on the third insulating layer; the second insulating layer and the fourth insulating layer each contain silicon and nitrogen; the third insulating layer comprises silicon and oxygen; Semiconductor device. 　 In claim 1 or claim 2, The interior angle is 270 degrees. Semiconductor device. 　 In claim 3, The concave polygon has a shape that combines straight lines and curves. Semiconductor device. 　 In claim 1 or claim 2, The interior angle is greater than 180 degrees and less than 270 degrees. Semiconductor device. 　 In claim 5, The concave polygon has a shape that combines straight lines and curves. Semiconductor device. 　 In claim 1 or claim 2, The interior angle is greater than 270 degrees and less than 360 degrees. Semiconductor device. 　 In claim 7, The concave polygon has a shape that combines straight lines and curves. Semiconductor device. 　 In claim 1 or claim 2, the transistor has a fifth insulating layer and a third conductive layer; the fifth insulating layer is located on the semiconductor layer; the third conductive layer is located on the fifth insulating layer and has a region facing a side surface of the first insulating layer with the semiconductor layer and the fifth insulating layer interposed therebetween; Semiconductor device. 　 In claim 9, an end of the third conductive layer coincides or approximately coincides with an end of the fifth insulating layer; Semiconductor device. 　 In claim 10, an edge of the semiconductor layer coincides or approximately coincides with an edge of the third conductive layer and an edge of the fifth insulating layer; Semiconductor device. 　 In claim 1 or claim 2, a sixth insulating layer located below the transistor; an upper surface of the sixth insulating layer contacts the first conductive layer; the sixth insulating layer comprises silicon and hydrogen. Semiconductor device.

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