Memristor, memristor array, neuromorphic device, and memristor control method

Abstract

A memristor according to an embodiment of the present invention comprises a reference layer, a first nonmagnetic layer, a domain wall displacement layer, a second nonmagnetic layer, a first pin layer, and a second pin layer. The first nonmagnetic layer is between the reference layer and the domain wall displacement layer in the stacking direction. The first pin layer is connected to the domain wall displacement layer with the second nonmagnetic layer interposed therebetween. The second pin layer is connected to the domain wall displacement layer at a position different from that of the first pin layer with the second nonmagnetic layer interposed therebetween. The memristor is configured so that a write current smaller than an initial current can be applied between the first pin layer and the second pin layer. The initial current is applied between the first pin layer and the second pin layer when a magnetic domain wall is introduced into the domain wall displacement layer.

Description

Memristor, memristor array, neuromorphic device, and method for controlling memristor

[0001] The present disclosure relates to memristors, memristor arrays, neuromorphic devices, and methods for controlling memristors.

[0002] A neuromorphic device is a device that performs neural network calculations and artificially mimics the relationship between neurons and synapses in the human brain.

[0003] Neuromorphic devices have been proposed that integrate memristors such as phase-change memory (PCM), resistive random access memory (ReRAM), and domain wall motion magnetoresistive effect elements (domain wall motion elements). Memristors output a current that is the product of an input voltage and the memristor's own conductance. The memristor functions as a product operation element in the product-sum operation of the neuromorphic device. For example, Patent Document 1 describes a neuromorphic device that uses domain wall motion elements.

[0004] In a domain wall motion element, the resistance value (conductance) in the stacking direction changes depending on the position of the domain wall. Patent Document 1 discloses that the movement range of the domain wall in the domain wall motion element is controlled using a first magnetization pinned layer and a second magnetization pinned layer. The magnetizations of the first magnetization pinned layer and the second magnetization pinned layer are magnetically coupled with the magnetization of the domain wall motion layer, thereby pinning the magnetization of a portion of the domain wall motion layer. The magnetization of the ferromagnetic layer of the first magnetization pinned layer that is closest to the domain wall motion layer and the magnetization of the ferromagnetic layer of the second magnetization pinned layer that is closest to the domain wall motion layer are oriented in opposite directions.

[0005] International Publication No. 2022 / 185410

[0006] Patent Document 1 controls the magnetization orientation direction of the first and second magnetization pinned layers by utilizing the difference in coercivity between the ferromagnetic layer constituting the first magnetization pinned layer and the ferromagnetic layer constituting the second magnetization pinned layer. Patent Document 1 also fabricates the first and second magnetization pinned layers separately to change their magnetic properties. However, fabricating the first and second magnetization pinned layers separately requires precise control of processing conditions, making manufacturing difficult. Furthermore, fabricating the first and second magnetization pinned layers separately requires a two-step manufacturing process, which lengthens the lead time and increases manufacturing costs.

[0007] The present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a memristor, a memristor array, a neuromorphic device, and a method for controlling a memristor that can introduce a domain wall into a domain wall displacement layer at any timing and are easy to manufacture.

[0008] A memristor according to a first aspect includes a reference layer, a first non-magnetic layer, a domain wall displacement layer, a second non-magnetic layer, a first pinned layer, and a second pinned layer. The reference layer, the domain wall displacement layer, the first pinned layer, and the second pinned layer each include a ferromagnetic material. The first non-magnetic layer is located between the reference layer and the domain wall displacement layer in the stacking direction. The first pinned layer is connected to the domain wall displacement layer with the second non-magnetic layer sandwiched between them. The second pinned layer is connected to the domain wall displacement layer at a position different from the first pinned layer with the second non-magnetic layer sandwiched between them. The memristor according to the first aspect is configured so that a write current smaller than an initial current can be applied between the first pinned layer and the second pinned layer. The initial current is a current applied between the first pinned layer and the second pinned layer when introducing a domain wall into the domain wall displacement layer.

[0009] A method for controlling a memristor according to a second aspect includes the steps of: applying an initial current between a first pinned layer and a second pinned layer of a memristor to introduce a domain wall into a domain wall displacement layer; and applying a write current smaller than the initial current between the first pinned layer and the second pinned layer to move the domain wall. The memristor includes a reference layer, a first non-magnetic layer, the domain wall displacement layer, a second non-magnetic layer, the first pinned layer, and the second pinned layer. The reference layer, the domain wall displacement layer, the first pinned layer, and the second pinned layer each include a magnetic material. The first non-magnetic layer is located between the reference layer and the domain wall displacement layer in the stacking direction. The first pinned layer is connected to the domain wall displacement layer with the second non-magnetic layer sandwiched between them. The second pinned layer is connected to the domain wall displacement layer at a position different from the first pinned layer with the second non-magnetic layer sandwiched between them.

[0010] 1 is a block diagram of an integrated device according to the first embodiment. FIG. 2 is a circuit diagram of a memristor array of the integrated device according to the first embodiment. FIG. 3 is a cross-sectional view of the vicinity of a memristor in the memristor array according to the first embodiment. FIG. 4 is a plan view of a memristor according to the first embodiment. FIG. 5 is a cross-sectional view of a memristor according to the first embodiment. FIG. 6 is a cross-sectional view for explaining a method for manufacturing a memristor according to the first embodiment. FIG. 7 is a cross-sectional view for explaining a method for manufacturing a memristor according to the first embodiment. FIG. 8 is a cross-sectional view for explaining a method for manufacturing a memristor according to the first embodiment. FIG. 9 is a cross-sectional view for explaining a function of a memristor according to the first embodiment. FIG. 10 is a cross-sectional view for explaining a function of a memristor according to the first embodiment. FIG. 11 is a conceptual diagram of a neural network. FIG. 12 is a block diagram showing a system including a neuromorphic device according to the first embodiment. FIG. 13 is a plan view of a memristor according to the second embodiment. FIG. 14 is a cross-sectional view of a memristor according to the second embodiment. FIG. 15 is a cross-sectional view of a memristor according to the third embodiment. FIG. 16 is a cross-sectional view of a memristor according to the fourth embodiment. FIG. 17 is a cross-sectional view of a memristor according to the fifth embodiment. FIG. 18 is a cross-sectional view of a memristor according to the sixth embodiment. FIG. 19 is a cross-sectional view for explaining a function of a memristor according to the sixth embodiment.

[0011] The present embodiment will be described in detail below with reference to the accompanying drawings. The drawings used in the following description may show characteristic portions enlarged for the sake of clarity, and the dimensional ratios of the components may differ from the actual values. The materials, dimensions, and the like exemplified in the following description are merely examples, and the present embodiment is not limited thereto. Appropriate modifications can be made within the scope of the effects of the present embodiment.

[0012] First, the directions will be defined. The x direction and y direction are directions substantially parallel to one surface of the substrate Sub (see FIG. 3 ), which will be described later. The x direction is the direction from the first pinned layer to the second pinned layer along the domain wall displacement layer, which will be described later. The x direction is, for example, the direction in which the domain wall displacement layer, which will be described later, extends. The x direction is an example of a first direction. The y direction is a direction orthogonal to the x direction in the xy plane. The z direction is the direction from the substrate, which will be described later, to the memristor. The z direction is an example of a stacking direction.

[0013] In this specification, the +z direction may be expressed as "up" and the -z direction as "down", but these expressions are for convenience and do not define the direction of gravity. Furthermore, in this specification, "extending in the x direction" means, for example, that the dimension in the x direction is larger than the smallest dimension among the dimensions in the x direction, y direction, and z direction. The same applies to extending in other directions.

[0014] 1 is a block diagram of an integrated device 1 according to a first embodiment. The integrated device 1 includes a memristor array 2 and a control device 3.

[0015] The memristor array 2 has multiple memristors 100 (see FIG. 2 ). The control device 3 controls the operation of each of the memristors 100 in the memristor array 2. The control device 3 may be located, for example, on the periphery of the memristor array 2 as shown in FIG. 1 . The control device 3 may also be located at a position overlapping the memristor array 2 in the z direction.

[0016] The control device 3 includes, for example, a signal input unit 4 , a calculation unit 5 , and an output unit 6 .

[0017] The signal input unit 4 has a control unit 7 and a power supply 8. The control unit 7 has, for example, a processor and a memory. The processor is, for example, a CPU (Central Processing Unit). The processor controls, for example, the address of the element to which a pulse is applied, the potential of the element to which the pulse is applied, the magnitude of the pulse (voltage, pulse length) to be applied to the element, etc. The memory stores the address of the element, a program to operate the processor, etc.

[0018] The calculation unit 5 performs calculations based on the conductance of each element in the memristor array 2 or the output current from each element. The calculation unit 5 includes, for example, a processor. The calculation unit 5, for example, adds up the output currents from multiple elements in the memristor array 2. When the integrated device 1 is applied to a neural network, the calculation unit 5 may add up the output currents from multiple elements and assign the result to an activation function.

[0019] The output unit 6 is connected to the calculation unit 5. The output unit 6 outputs the calculation result of the calculation unit 5 to the outside. The output unit 6 includes, for example, an output capacitor, an amplifier, a converter, etc. The output unit 6 may also feed back the calculation result to the signal input unit 4. The calculation result is stored in, for example, a memory of the signal input unit 4.

[0020] 2 is a circuit diagram of a memristor array 2 according to the first embodiment. The memristor array 2 includes multiple memristors 100, multiple first interconnects L1, multiple second interconnects L2, and multiple third interconnects L3. Each memristor 100 is connected to switch elements SW1, SW2, and SW3 that control the operation of the memristor 100.

[0021] The multiple memristors 100 are arranged in a matrix. The multiple memristors 100 are not limited to those in which actual elements are arranged in a matrix, but may also be those arranged in a matrix in a circuit diagram.

[0022] Each of the first wirings L1 is used when writing data. Each of the first wirings L1 is also called a write wiring. Each of the first wirings L1 connects the memristors 100 belonging to the same row to the signal input unit 4.

[0023] Each of the second wirings L2 is used both when writing and reading data. Each of the second wirings L2 is also referred to as a common wiring. Each of the second wirings L2 is connected to, for example, the calculation unit 5. The second wirings L2 may be provided for each of the multiple memristors 100, or may be provided across the multiple memristors 100.

[0024] Each of the third wirings L3 is used when reading data. Each of the third wirings L3 is also referred to as a read wiring. Each of the third wirings L3 electrically connects, for example, the memristors 100 belonging to the same row to the signal input unit 4. Each of the third wirings L3 may also electrically connect, for example, the memristors 100 belonging to the same column to the signal input unit 4.

[0025] The switch elements SW1, SW2, and SW3 are elements that control the flow of current, and are, for example, elements that utilize a phase change of a crystal layer such as a transistor or an Ovonic Threshold Switch (OTS), elements that utilize a change in band structure such as a metal-insulator transition (MIT) switch, elements that utilize a breakdown voltage such as a Zener diode or an avalanche diode, or elements whose conductivity changes with a change in atomic position.

[0026] The switch element SW1 and the switch element SW2 are, for example, connected one to each memristor 100. The switch element SW1 is, for example, connected between the memristor 100 and the first wiring L1. The switch element SW2 is, for example, connected between the memristor 100 and the second wiring L2. The switch element SW3 is, for example, connected across multiple memristors 100. The switch element SW3 is, for example, connected to the third wiring L3.

[0027] The positional relationship between the switch elements SW1, SW2, and SW3 is not limited to that shown in Figure 2. For example, the switch element SW1 may be connected across multiple memristors 100 and located upstream of the first wiring L1. For another example, the switch element SW2 may be connected across multiple memristors 100 and located upstream of the second wiring L2. For another example, the switch element SW3 may be connected to each memristor 100.

[0028] 3 is a cross-sectional view of the vicinity of a memristor 100 in the memristor array 2 according to the first embodiment. Fig. 3 is a cross-section of one memristor 100 in Fig. 2 taken along the xz plane passing through the center of the width of the domain wall displacement layer 10 in the y direction.

[0029] The memristor array 2 includes, for example, a substrate Sub, a plurality of transistors Tr formed on the substrate Sub, a plurality of memristors 100, a plurality of wirings C1 and C2, and an insulating layer 90.

[0030] The substrate Sub is, for example, a semiconductor substrate. The memristor 100 includes, for example, a domain wall displacement layer 10, a first non-magnetic layer 20, a reference layer 30, a second non-magnetic layer 40, a first pinned layer 50, a second pinned layer 60, a first electrode 71, a second electrode 72, and a third electrode 73. Details of the memristor 100 will be described later.

[0031] The transistor Tr is an example of the above-mentioned switch elements SW1 and SW2. The switch element SW3 is located at a different position in the y direction from the plane shown in FIG. 3. The transistor Tr includes a gate electrode G, an insulating film GI, an active region AA1, and an active region AA2. The active region AA1 and the active region AA2 are formed in the substrate Sub, and serve as a source or a drain depending on the direction of current flow.

[0032] The transistor Tr and the memristor 100 are connected via wiring C1 and wiring C2. The wiring C1 extends in the z direction. The wiring C2 extends in any direction within the xy plane. The wiring C1 and wiring C2 are conductors. The wirings C1 and C2 shown in FIG. 3 electrically connect the first wiring L1 or the second wiring L2 to the transistor Tr, and electrically connect the transistor Tr to the memristor 100.

[0033] The insulating layer 90 provides insulation between the transistor Tr and the memristor 100. The insulating layer 90 is an insulating layer that provides insulation between the wirings of the multilayer wiring and between the elements. The memristor 100 and the transistor Tr are electrically isolated by the insulating layer 90 except for the wirings C1 and C2. The insulating layer 90 is made of, for example, silicon oxide (SiO ｘ ), silicon nitride (SiN ｘ ), silicon carbide (SiC), chromium nitride (CrN), silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al ２ O ３ ), zirconium oxide (ZrO ｘ ), magnesium oxide (MgO), etc.

[0034] Fig. 4 is a plan view of the memristor 100 viewed from the z direction. Fig. 5 is a cross-sectional view of the memristor 100. Fig. 5 is a diagram of the memristor 100 cut along an xz plane passing through the center of the domain wall displacement layer 10 in the y direction. The arrows in the figure represent an example of the orientation direction of the magnetization of a ferromagnetic material.

[0035] The memristor 100 includes, for example, a domain wall displacement layer 10, a first non-magnetic layer 20, a reference layer 30, a second non-magnetic layer 40, a first pinned layer 50, a second pinned layer 60, a first electrode 71, a second electrode 72, and a third electrode 73. The periphery of the memristor 100 is covered with an insulating layer 90.

[0036] The memristor 100 includes a first magnetoresistive effect unit MTJ1, a second magnetoresistive effect unit MTJ2, and a third magnetoresistive effect unit MTJ3. The first magnetoresistive effect unit MTJ1 is composed of a reference layer 30, a first non-magnetic layer 20, and a domain wall displacement layer 10. The second magnetoresistive effect unit MTJ2 is composed of the domain wall displacement layer 10, a second non-magnetic layer 40, and a first pinned layer 50. The third magnetoresistive effect unit MTJ3 is composed of the domain wall displacement layer 10, a second non-magnetic layer 40, and a second pinned layer 60.

[0037] The first magnetoresistive unit MTJ1 has the magnetization M ３０and the magnetization of the domain wall displacement layer 10 changes, the resistance value in the z direction changes. Since conductance is expressed as the reciprocal of the resistance value, the conductance of the first magnetoresistive effect unit MTJ1 changes depending on the position of the domain wall DW in the domain wall displacement layer 10. The second magnetoresistive effect unit MTJ2 and the third magnetoresistive effect unit MTJ3 are used when introducing the domain wall DW into the domain wall displacement layer 10 and when moving the domain wall DW in the domain wall displacement layer 10.

[0038] The reference layer 30 includes a magnetic material. The reference layer 30 includes, for example, a ferromagnetic material. The reference layer 30 is a ferromagnetic layer whose length in the x direction is longer than its width in the y direction. The magnetization M of the reference layer 30 ３０ is oriented in one direction and fixed in the normal environment in which the memristor 100 is used. Here, "the magnetization is fixed" means that the magnetization direction does not reverse during normal operation of the memristor 100 (when no external force exceeding the expected value is applied).

[0039] The reference layer 30 includes, for example, a material that easily provides a coherent tunneling effect between the reference layer 30 and the domain wall displacement layer 10. The reference layer 30 includes, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, or an alloy containing these metals and at least one or more of B, C, and N. The reference layer 30 is, for example, Co—Fe, Co—Fe—B, or Ni—Fe.

[0040] The reference layer 30 may be, for example, a Heusler alloy. Heusler alloys are half-metallic and have high spin polarization. Heusler alloys are either XYZ or X ２ It is an intermetallic compound having a chemical composition of YZ, where X is a transition metal element or a noble metal element of the Co, Fe, Ni, or Cu group on the periodic table, Y is a transition metal element or an element species of X of the Mn, V, Cr, or Ti group, and Z is a typical element of groups III to V. ２ FeSi, Co ２ FeGe, Co ２ FeGa, Co ２ MnSi, Co ２ Mn １－ａ Fe ａ Alｂ Si １－ｂ , Co ２ FeGe １－ｃ Ga ｃ etc.

[0041] The reference layer 30 may have a synthetic antiferromagnetic structure (SAF structure). The synthetic antiferromagnetic structure is composed of two magnetic layers sandwiching a nonmagnetic layer. For example, the reference layer 30 may be a stack of a ferromagnetic layer, a spacer layer, and another ferromagnetic layer. The antiferromagnetic coupling between the two ferromagnetic layers constituting the SAF structure increases the coercive force of the reference layer 30 compared to a non-SAF structure. The magnetic layer constituting the SAF structure includes, for example, a ferromagnetic material and may also include an antiferromagnetic material such as IrMn or PtMn. The spacer layer includes, for example, at least one selected from the group consisting of Ru, Ir, Rh, and Mo.

[0042] The length of the reference layer 30 in the x direction is, for example, longer than the length of a third region A3 of the domain wall displacement layer 10 (described later). By having the reference layer 30 face the entire surface of the third region A3, which is the range in which the domain wall DW can move, it is possible to eliminate a dead region in the conductance of the first magnetoresistive effect unit MTJ1. The dead region refers to a region in which the conductance of the magnetoresistive effect unit does not change even when the position of the domain wall DW changes. Furthermore, the length of the reference layer 30 in the x direction is, for example, longer than the length of the domain wall displacement layer 10 in the x direction. If the area of ​​the reference layer 30 is larger than the area of ​​the domain wall displacement layer 10, the heat capacity of the reference layer 30 increases, improving the efficiency of heat removal from the domain wall displacement layer 10. Furthermore, if the area of ​​the reference layer 30 is larger than the area of ​​the domain wall displacement layer 10, the flatness of the domain wall displacement layer 10 is improved, and the domain wall DW moves more smoothly.

[0043] The first non-magnetic layer 20 is located between the reference layer 30 and the domain wall displacement layer 10 in the z direction. The first non-magnetic layer 20 is, for example, on the reference layer 30. The first non-magnetic layer 20 is a non-magnetic layer whose length in the x direction is longer than its length in the y direction.

[0044] The first nonmagnetic layer 20 is made of, for example, a nonmagnetic insulator, a semiconductor, or a metal. ２ O ３ , SiO ２ , MgO, MgAl ２O ４ , and materials in which a portion of these Al, Si, and Mg is replaced with Zn, Be, Ti, etc. These materials have a large band gap and excellent insulating properties. When the first nonmagnetic layer 20 is made of a nonmagnetic insulator, the first nonmagnetic layer 20 is a tunnel barrier layer. Examples of nonmagnetic metals include Cu, Au, and Ag. Examples of nonmagnetic semiconductors include Si, Ge, and CuInSe. ２ , CuGaSe ２ , Cu(In,Ga)Se ２ etc.

[0045] The thickness t20 of the first non-magnetic layer 20 is, for example, 20 Å or more, and may be 25 Å or more. The area resistance product (RA) of the first magnetoresistive effect unit MTJ1 can be changed by changing the thickness and material of the first non-magnetic layer 20. The area resistance product (RA) is expressed as the product of the element resistance and the element cross-sectional area. The element resistance is the resistance value when the magnetizations of the two ferromagnetic layers sandwiching the non-magnetic layer are parallel. The element cross section of the first magnetoresistive effect unit MTJ1 is a cross section of the first non-magnetic layer 20 cut along the xy plane.

[0046] The domain wall displacement layer 10 is, for example, on the first non-magnetic layer 20. The domain wall displacement layer 10 is sandwiched between the first non-magnetic layer 20 and the second non-magnetic layer 40, for example, in the z direction. The domain wall displacement layer 10 is, for example, a ferromagnetic layer whose length in the x direction is longer than its width in the y direction. The domain wall displacement layer 10 has a domain wall DW therein when the memristor 100 is in use. The domain wall DW is the boundary between different magnetic domains. The domain wall DW moves in the x direction inside the domain wall displacement layer 10. The domain wall DW is also called an analog layer or a magnetic recording layer.

[0047] The domain wall displacement layer 10 has a first region A1, a second region A2, and a third region A3. The first region A1 is a region that overlaps with the first pinned layer 50 when viewed from the z direction. The second region A2 is a region that overlaps with the second pinned layer 60 when viewed from the z direction. The third region A3 is a region other than the first region A1 and the second region A2 of the domain wall displacement layer 10. The third region A3 is sandwiched between the first region A1 and the second region A2 in the x direction, for example.

[0048] In the first region A1, the magnetization M Ａ１is oriented in the first magnetization direction (for example, the +z direction). Ａ２ is oriented in the second magnetization direction (for example, the −z direction). Ａ１ and the magnetization M of the second region A2 Ａ２ The first magnetization direction and the second magnetization direction are, for example, oriented in opposite directions. The first magnetization direction and the second magnetization direction are not limited to the z direction, but may be any direction within the xy plane.

[0049] The third region A3 is a region where the magnetization direction changes and the domain wall DW can move. The third region A3 is called a domain wall movable region. The third region A3 has a first magnetic domain A31 and a second magnetic domain A32. The first magnetic domain A31 and the second magnetic domain A32 have magnetization orientation directions opposite to each other. The boundary between the first magnetic domain A31 and the second magnetic domain A32 is the domain wall DW. The magnetization M of the first magnetic domain A31 Ａ３１ is, for example, the magnetization M of the first region A1 Ａ１ The magnetization M of the second magnetic domain A32 is oriented in the same direction as Ａ３２ is, for example, the magnetization M of the second region A2 Ａ２ In principle, there is only one domain wall DW in the third region A3, and it moves within the third region A3.

[0050] When the volume ratio between the first magnetic domain A31 and the second magnetic domain A32 changes, the domain wall DW moves. The domain wall DW moves, for example, by applying a write current (e.g., a current pulse) in the x direction of the domain wall displacement layer 10 or by applying an external magnetic field to the domain wall displacement layer 10. For example, when a write current is applied between the first electrode 71 and the second electrode 72, the domain wall DW moves. Here, the critical current density of the write current required to move the domain wall DW is referred to as the first critical current density.

[0051] When the domain wall displacement layer 10 is viewed from the z direction, the width in the y direction of the first region A1 and the width in the y direction of the second region A2 may be the same as or wider than the width in the y direction of the third region A3. If the width in the y direction of the first region A1 and the second region A2 is wider than the width in the y direction of the third region A3, the current density of the current flowing through the domain wall displacement layer 10 decreases at the position from the third region A3 to the first region A1 or the second region A2. If the current density of the current flowing through the domain wall displacement layer 10 suddenly decreases, the force moving the domain wall DW weakens, and it is possible to prevent the domain wall DW from entering the first region A1 and the second region A2.

[0052] The thickness of the domain wall displacement layer 10 is, for example, 5 nm or more, and 15 nm or less.

[0053] The domain wall displacement layer 10 includes a magnetic material. The domain wall displacement layer 10 includes, for example, a ferromagnetic material. The domain wall displacement layer 10 can be made of, for example, the same material as the reference layer 30. The domain wall displacement layer 10 may be made of a ferromagnetic material, a ferrimagnetic material, or a combination of these with an antiferromagnetic material whose magnetic state can be changed by a current. The domain wall displacement layer 10 preferably includes at least one element selected from the group consisting of Co, Ni, Fe, Pt, Pd, Gd, Tb, Mn, Ge, and Ga.

[0054] The domain wall displacement layer 10 may be, for example, a laminated film of Co and Ni, a laminated film of Co and Pt, a laminated film of Co and Pd, an MnGa-based material, a GdCo-based material, a TbCo-based material, or the like. Ferrimagnetic materials such as MnGa-based materials, GdCo-based materials, and TbCo-based materials have small saturation magnetization, and the threshold current required to move the domain wall DW is small. Furthermore, a laminated film of Co and Ni, a laminated film of Co and Pt, and a laminated film of Co and Pd have large coercive force, and the displacement speed of the domain wall DW is slow. The antiferromagnetic material may be, for example, Mn ３ X (X is Sn, Ge, Ga, Pt, Ir, etc.), CuMnAs, Mn ２ Au, etc. These antiferromagnetic materials can also be used for the reference layer 30.

[0055] The second non-magnetic layer 40 is, for example, on the domain wall displacement layer 10. The second non-magnetic layer 40 is, for example, located farther from the substrate Sub than the first non-magnetic layer 20. The second non-magnetic layer 40 is, for example, a non-magnetic layer whose length in the x direction is longer than its length in the y direction.

[0056] The second non-magnetic layer 40 is made of, for example, a non-magnetic insulator, semiconductor, or metal. The second non-magnetic layer 40 is preferably made of a non-magnetic insulator. If the second non-magnetic layer 40 is made of an insulator, a portion of the write current flows through the second non-magnetic layer 40, which can prevent a decrease in write efficiency.

[0057] The second non-magnetic layer 40 can be made of the same material as the first non-magnetic layer 20. The second non-magnetic layer 40 may be made of a different material from that of the first non-magnetic layer 20. Since the second magnetoresistive effect unit MTJ2 and the third magnetoresistive effect unit MTJ3 do not require a large resistance change, there are fewer restrictions on the material used for the second non-magnetic layer 40 than on the material used for the first non-magnetic layer 20.

[0058] The second non-magnetic layer 40 has, for example, a first overlapping portion 41, a second overlapping portion 42, and a non-overlapping portion 43. The first overlapping portion 41 is a portion that overlaps with the first pinned layer 50 when viewed from the z direction. The second overlapping portion 42 is a portion that overlaps with the second pinned layer 60 when viewed from the z direction. The non-overlapping portion 43 is a portion that does not overlap with the first pinned layer 50 or the second pinned layer 60 when viewed from the z direction. The second non-magnetic layer 40 may not have the non-overlapping portion 43 and may be composed of two portions, the first overlapping portion 41 and the second overlapping portion 42.

[0059] The thickness t40 of the second non-magnetic layer 40 in the z direction is thinner than the thickness t20 of the first non-magnetic layer 20 in the z direction, for example. The thickness t40 of the second non-magnetic layer 40 in the z direction is the thickness of the first overlapping portion 41 or the second overlapping portion 42. If the thickness t40 of the second non-magnetic layer 40 is thin, the resistance value of the path through which the write current flows can be reduced, and the voltage required for writing can be suppressed. Furthermore, the thickness t40 of the second non-magnetic layer 40 in the z direction may be thicker than the thickness t20 of the first non-magnetic layer 20 in the z direction, for example. If the thickness of the second non-magnetic layer 40 is thick, damage to the domain wall displacement layer 10 can be reduced when milling a portion of the magnetic layer 91 during manufacturing (see FIG. 7 ).

[0060] Furthermore, by changing the thickness t40 of the second nonmagnetic layer 40, the area resistance products (RA) of the second magnetoresistive unit MTJ2 and the third magnetoresistive unit MTJ3 can be changed. For example, the area resistance products (RA) of the second magnetoresistive unit MTJ2 and the third magnetoresistive unit MTJ3 may be smaller than the area resistance product (RA) of the first magnetoresistive unit MTJ1. The small area resistance products (RA) of the second magnetoresistive unit MTJ2 and the third magnetoresistive unit MTJ3 can reduce the voltage required for writing.

[0061] The first pinned layer 50 is connected to the domain wall displacement layer 10 with the second nonmagnetic layer 40 sandwiched therebetween. The first pinned layer 50 is connected to a first end of the domain wall displacement layer 10 with the first overlapping portion 41 sandwiched therebetween.

[0062] The first pinned layer 50 includes a magnetic material. The first pinned layer 50 includes, for example, a ferromagnetic material. For example, the same material as that of the domain wall displacement layer 10 or the reference layer 30 can be applied to the first pinned layer 50. The first pinned layer 50 may have multiple layers. For example, the first pinned layer 50 may have a stacked structure of multiple layers, and may include a mask layer, a cap layer, etc. formed during manufacturing. For example, the first pinned layer 50 may have a synthetic antiferromagnetic structure (SAF structure).

[0063] The magnetization M of the first pinned layer 50 ５０ is the magnetization M of the first region A1 of the domain wall displacement layer 10. Ａ１ The magnetization M of the first pinned layer 50 ５０ is the magnetization M of the first region A1 of the domain wall displacement layer 10. Ａ１ may be in a parallel relationship with

[0064] The magnetization M of the first pinned layer 50 ５０ is the magnetization M of the first region A1 Ａ１ It is not magnetically coupled with the magnetization M ５０ and magnetization M Ａ１ This means that there is no exchange coupling bias acting between the magnetization M Ａ１ and magnetization M ５０ When the magnetization M ５０ When the magnetization is reversed, the magnetization M Ａ１The magnetization also reverses. Ａ１ and magnetization M ５０ When there is no magnetic coupling between ５０ Even if the magnetization is reversed, the magnetization M Ａ１ does not undergo magnetization reversal.

[0065] For example, the cross-sectional area of ​​the first pinned layer 50 in the xy plane perpendicular to the z direction is larger than the cross-sectional area of ​​the domain wall displacement layer 10 in the yz plane perpendicular to the x direction. When this relationship is satisfied, the current density of the write current flowing in the domain wall displacement layer 10 becomes larger than the current density of the write current passing through the first pinned layer 50. By increasing the current density of the write current flowing in the domain wall displacement layer 10, the domain wall DW can be moved stably. Furthermore, by reducing the current density of the write current passing through the first pinned layer 50, the magnetization M of the first region A1 can be reduced. Ａ１ However, it is possible to prevent unintended magnetization reversal due to spin transfer torque. Ａ１ The critical current density required to reverse the magnetization of is preferably greater than the first critical current density.

[0066] The second pinned layer 60 is connected to the domain wall displacement layer 10 with the second nonmagnetic layer 40 sandwiched therebetween. The second pinned layer 60 is connected to a second end of the domain wall displacement layer 10 with the second overlapping portion 42 sandwiched therebetween. The second pinned layer 60 is located at a position spaced apart from the first pinned layer 50 in the x-direction.

[0067] The second pinned layer 60 includes a magnetic material. The second pinned layer 60 includes, for example, a ferromagnetic material. For example, the same material as that of the domain wall displacement layer 10 or the reference layer 30 can be applied to the second pinned layer 60. The second pinned layer 60 may have multiple layers. For example, the second pinned layer 60 may have a stacked structure of multiple layers, and may include a mask layer, a cap layer, etc. formed during manufacturing. For example, the second pinned layer 60 may have a synthetic antiferromagnetic structure (SAF structure).

[0068] The magnetization M of the second pinned layer 60 ６０ is the magnetization M of the second region A2 of the domain wall displacement layer 10 Ａ２ The magnetization M of the second pinned layer 60 is parallel to ６０ is the magnetization M of the first pinned layer 50 ５０ and the magnetization M of the first region A1 Ａ１When the magnetizations M of the second region A2 of the domain wall displacement layer 10 are parallel to each other, Ａ２ may be in an antiparallel relationship with

[0069] The magnetization M of the second pinned layer 60 ６０ is the magnetization M of the second region A2 Ａ２ It is not magnetically coupled with the magnetization M ６０ and magnetization M Ａ２ There is no exchange coupling bias acting between the magnetization M Ａ２ and magnetization M ６０ When the magnetization M ６０ When the magnetization is reversed, the magnetization M Ａ２ The magnetization also reverses. Ａ２ and magnetization M ６０ When there is no magnetic coupling between ６０ Even if the magnetization is reversed, the magnetization M Ａ２ does not undergo magnetization reversal.

[0070] For example, the cross-sectional area of ​​the second pinned layer 60 in the xy plane perpendicular to the z direction is larger than the cross-sectional area of ​​the domain wall displacement layer 10 in the yz plane perpendicular to the x direction. When this relationship is satisfied, the current density of the write current flowing in the domain wall displacement layer 10 becomes larger than the current density of the write current passing through the second pinned layer 60. By increasing the current density of the write current flowing in the domain wall displacement layer 10, the domain wall DW can be moved stably. Furthermore, by reducing the current density of the write current passing through the second pinned layer 60, the magnetization M of the second region A2 can be reduced. Ａ２ However, it is possible to prevent unintended magnetization reversal due to spin transfer torque. Ａ２ The critical current density required to reverse the magnetization of is preferably greater than the first critical current density.

[0071] The film thickness of the first pinned layer 50 is, for example, the same as the film thickness of the second pinned layer 60. Since the first pinned layer 50 and the second pinned layer 60 are processed from the same ferromagnetic layer, their film thicknesses are often the same.

[0072] The first electrode 71 is connected to the first pinned layer 50. The first electrode 71 may be in direct contact with the first pinned layer 50, or may be indirectly connected via a layer in between. The first electrode 71 is, for example, a write electrode used when applying a write current to the memristor 100. The write current flows between the first electrode 71 and the second electrode 72. The first electrode 71 includes a conductive material.

[0073] The second electrode 72 is connected to the second pinned layer 60. The second electrode 72 may be in direct contact with the second pinned layer 60, or may be indirectly connected via a layer in between. The second electrode 72 is a common electrode used when applying a write current to the memristor 100 and when applying a read current to the memristor 100. The second electrode 72 includes a conductive material.

[0074] The third electrode 73 is connected to the reference layer 30. The third electrode 73 may be in direct contact with the reference layer 30, or may be indirectly connected via a layer in between. The third electrode 73 is a read electrode used when applying a read current to the memristor 100. The third electrode 73 includes a conductive material.

[0075] The magnetization direction of each layer of the memristor 100 can be confirmed, for example, by measuring a magnetization curve. The magnetization curve can be measured, for example, using MOKE (Magneto-Optical Kerr Effect). MOKE measurement is a measurement method that uses the magneto-optical effect (magnetic Kerr effect) in which linearly polarized light is incident on a measurement object and the polarization direction rotates.

[0076] Next, a method for manufacturing the memristor 100 will be described. First, a stacked body is formed as shown in Fig. 6. The stacked body is obtained by forming a stacked film on the upper surfaces of the third electrode 73 and the insulating layer 90, and then processing and removing a portion of the stacked film.

[0077] The stacked film is obtained by sequentially stacking the reference layer 30, the first non-magnetic layer 20, the domain wall displacement layer 10, the second non-magnetic layer 40, and the magnetic layer 91. Each layer can be formed using, for example, a sputtering method, a chemical vapor deposition (CVD) method, an electron beam evaporation method (EB evaporation method), an atomic laser deposition method, or the like.

[0078] The laminated film can be processed using photolithography, etching (for example, Ar etching), ion milling, etc. By processing the laminated film, the outer shape of the memristor 100 is formed.

[0079] 7, a first electrode 71 and a second electrode 72 are formed on a part of the magnetic layer 91. The first electrode 71 and the second electrode 72 are formed at positions overlapping the magnetic layer 91 when viewed from the z direction. The first electrode 71 and the second electrode 72 are spaced apart in the x direction.

[0080] Next, using the first electrode 71 and the second electrode 72 as a mask, a part of the magnetic layer 91 is subjected to ion milling. By removing a part of the magnetic layer 91, the first pinned layer 50 and the second pinned layer 60 are formed. The magnetization M of the first pinned layer 50 ５０ and the magnetization M of the second pinned layer 60 ６０ are oriented in the same direction. Ａ１ , M Ａ２ , M Ａ３ are all oriented in the same direction.

[0081] Next, an initial current I ｉｎ is applied to introduce the domain wall DW into the domain wall displacement layer 10. ｉｎ is the current applied between the first pinned layer 50 and the second pinned layer 60 when the domain wall DW is introduced inside the domain wall displacement layer 10 .

[0082] In the second magnetoresistive portion MTJ2, the initial current I ｉｎ flows from the first pinned layer 50 toward the domain wall displacement layer 10. In the third magnetoresistive part MTJ3, the initial current I ｉｎ flows from the domain wall displacement layer 10 toward the second pinned layer 60 .

[0083] Initial current I ｉｎ When the magnetization M of the second region A2 is applied, Ａ２ The magnetization of the first region A1 is reversed by the spin transfer torque. Ａ１ is the initial current I ｉｎThe magnetization M in the second region A2 does not reverse because the flow direction of the magnetization M is different. Ａ２ When the magnetization of the first region A2 is reversed, a domain wall DW is formed between the second region A2 and the third region A3. ｉｎ After applying the initial current I, the domain wall DW remains between the second region A2 and the third region A3. ｉｎ Depending on the magnitude of the initial current I, the domain wall DW may move toward the first region A1. ｉｎ After applying the voltage, the domain wall DW may be between the first region A1 and the third region A3.

[0084] Initial current I ｉｎ The flow direction of the magnetization M of the first region A1 is not limited to the direction shown in FIG. 8, but may be the opposite direction to that shown in FIG. Ａ１ In this case, the initial current I ｉｎ Depending on the magnitude of the magnetic field, the domain wall DW may move toward the second region A2.

[0085] Initial current I ｉｎ When applying the initial current I ｉｎ The magnetization M of the domain wall displacement layer 10 before applying Ａ１ , M Ａ２ , M Ａ３ The external magnetic field may be applied in a direction opposite to the orientation direction of the magnetization M due to the spin transfer torque. Ａ２ Supports magnetization reversal.

[0086] As described above, the memristor 100 is obtained by introducing the domain wall DW into the domain wall displacement layer 10. The introduction of the domain wall DW into the domain wall displacement layer 10 can be performed at any timing. For example, even after the domain wall displacement layer 10 becomes a single magnetic domain during use, the initial current I ｉｎ By applying this voltage, the domain wall DW can be introduced into the domain wall displacement layer 10 .

[0087] Next, a method for controlling the memristor 100 will be described. The memristor 100 operates in two ways: write and read. In the write operation, the position of the domain wall DW of the domain wall displacement layer 10 is changed. In the read operation, the conductance of the memristor 100 or the output current from the memristor 100 is detected.

[0088] First, a write operation to the memristor 100 will be described. In the write operation, a write current is applied to the memristor 100. The write current flows between the first pinned layer 50 and the second pinned layer 60 along the domain wall displacement layer 10. The domain wall DW is moved by applying the write current.

[0089] The write current is the initial current I ｉｎ The signal input section 4 receives an initial current I ｉｎ The write current is configured to be smaller than the initial current I ｉｎ By making it smaller, it is possible to prevent unintended magnetization reversal of the magnetization in the domain wall displacement layer 10 and to suppress the formation of multiple domain walls DW in the domain wall displacement layer 10 .

[0090] For example, the pulse length of the write current is set to the initial current I ｉｎ If the pulse length of the write current is short, it is possible to prevent the magnetization in the domain wall displacement layer 10 from being unintentionally reversed, and to suppress the formation of multiple domain walls DW in the domain wall displacement layer 10.

[0091] The write current is the initial current I ｉｎ A first write current I flows in the same direction as Ｗ１ and the initial current I ｉｎ A second write current I flows in the opposite direction to Ｗ２ FIG. 9 is a cross-sectional view for explaining the function of the memristor according to the first embodiment, in which the first write current I Ｗ１ 10 is a cross-sectional view for explaining the function of the memristor according to the first embodiment, and is a diagram for explaining the second write current I Ｗ２ FIG.

[0092] First write current I Ｗ１When the first write current I is applied, the magnetization of a part of the third region A3 is reversed, and a second magnetic domain A32 is formed. The formation of the second magnetic domain A32 causes the domain wall DW to move. For example, the domain wall DW moves from the boundary between the second region A2 and the third region A3 toward the boundary between the first region A1 and the third region A3. Ｗ１ The magnitude of the initial current I ｉｎ smaller than the size of

[0093] Second write current I Ｗ２ When the second write current I is applied, the magnetization of a part of the second magnetic domain A32 is reversed, and the domain wall DW moves. For example, the domain wall DW moves from the boundary between the first region A1 and the third region A3 toward the boundary between the second region A2 and the third region A3. Ｗ２ The magnitude of the initial current I ｉｎ smaller than the size of

[0094] Also, the second write current I Ｗ２ The magnitude of the first write current I Ｗ１ It is preferable that the second write current I be smaller than the magnitude of the second write current I. Ｗ２ Applying a current in the same direction as the magnetization M Ａ１ There is a risk of magnetization reversal of the magnetization M Ａ１ When the second write current I Ｗ２ Applying a current in the same direction as the magnetization M Ａ２ There is a risk of reversing the magnetization of the magnetized M Ａ２ When the second write current I is unexpectedly reversed, a new domain wall DW is introduced between the second region A2 and the third region A3. Ｗ２ By reducing the value of , it is possible to prevent unintended magnetization reversal and suppress the formation of multiple domain walls DW in the domain wall displacement layer 10 .

[0095] Next, a description will be given of a read operation from the memristor 100. In the read operation, a read current I Ｒ 11 is a cross-sectional view for explaining the function of the memristor according to the first embodiment, and a read current I Ｒ1 is a diagram for explaining a read current I Ｒ is smaller than the write current. Ｒ does not move the domain wall DW.

[0096] The read current flows between the third electrode 73 and the first electrode 71 or the second electrode 72. It is preferable that the read current flows between the third electrode 73 and the second electrode 72. The third magnetoresistive part MTJ3 has a magnetization M ６０ and magnetization M Ａ２ are parallel to each other and have a smaller resistance than the second magnetoresistive effect unit MTJ2. By configuring the read current to flow to the second magnetoresistive effect unit MTJ2 side, the parasitic resistance can be reduced and the effective resistance change amount of the memristor 100 can be increased.

[0097] The memristor according to this embodiment utilizes the spin transfer torque generated in the second magnetoresistive effect unit MTJ2 or the third magnetoresistive effect unit MTJ3 to introduce the domain wall DW into the domain wall displacement layer 10. Therefore, the memristor according to this embodiment can introduce the domain wall DW into the domain wall displacement layer 10 at any timing.

[0098] Furthermore, the memristor 100 according to this embodiment can precisely control the position of the domain wall DW by controlling the magnitude of the write current. By controlling the write current, the memristor 100 according to this embodiment can prevent the domain wall displacement layer 10 from becoming a single magnetic domain or preventing multiple domain walls DW from being formed in the domain wall displacement layer 10.

[0099] Furthermore, in the memristor 100 according to this embodiment, the domain wall DW can be introduced into the domain wall displacement layer 10 at any timing, and therefore the domain wall DW can be introduced again into the domain wall displacement layer 10 even after the domain wall displacement layer 10 has become a single magnetic domain. In other words, the movement range of the domain wall DW is not limited to the third region A3, but can also be expanded to the first region A1 and the second region A2. When the movement range of the domain wall DW in the domain wall displacement layer 10 is expanded, the effective resistance change width (MR ratio) of the first magnetoresistive effect unit MTJ1 can be increased. When the effective resistance change width (MR ratio) of the first magnetoresistive effect unit MTJ1 is large, the memristor 100 can more easily store multi-value data.

[0100] Furthermore, in the memristor 100 according to this embodiment, the first pinned layer 50 and the second pinned layer 60 can be formed simultaneously by processing the magnetic layer 91. The manufacturing method for the memristor 100 according to this embodiment forms the first pinned layer 50 and the second pinned layer 60 in a single milling step, which reduces manufacturing difficulty and shortens the lead time.

[0101] The integrated device 1 according to the first embodiment can be used in, for example, a magnetic memory or a neuromorphic device.

[0102] In the case of a magnetic memory, each memristor 100 functions as an element for storing data. The resistance of the memristor 100 changes depending on the position of the domain wall DW of the memristor 100, and this resistance value is used to store data.

[0103] In the case of a neuromorphic device, each memristor 100 functions as a product operation element. The resistance of the memristor 100 changes depending on the position of the domain wall DW of the memristor, and this resistance value or its inverse, conductance, represents the weight.

[0104] A neuromorphic device is a device that artificially mimics the relationship between neurons and synapses in the human brain. Neuromorphic devices are capable of performing neural network calculations.

[0105] 12 is a schematic diagram of the neural network NN. The neural network NN has an input layer L ｉｎ and the middle layer L ｍ and the output layer L ｏｕｔ In FIG. ｍ presents an example of three layers, but the middle layer L ｍ The number of input layers L ｉｎ and the middle layer L ｍ and the output layer L ｏｕｔ Each of the input layers L has a plurality of chips C, each of which corresponds to a neuron in the brain. ｉｎ and the middle layer L ｍ and the output layer L ｏｕｔ The chips C and the number of transmission means shown in FIG. 12 are merely examples.

[0106] The neural network NN improves the rate of correct answers to questions as its transmission means (synapses) learn. Learning is the process of finding knowledge that may be useful in the future from information. The neural network NN learns by operating while changing the weights of the transmission means. The transmission means performs a multiplication operation to apply a weight to the input signal, and a sum operation to add the result of the multiplication operation. In other words, the transmission means performs a product-sum operation. The memristor 100 according to this embodiment is responsible for this multiplication operation.

[0107] 13 is a block diagram showing a system 300 including the neuromorphic device 200 according to the first embodiment. The system 300 includes a plurality of sensors 201, the neuromorphic device 200, and a communication unit 202.

[0108] Any sensor can be used for each of the multiple sensors 201 depending on the application. For example, a temperature sensor, a humidity sensor, a speed sensor, a pressure sensor, an acceleration sensor, etc. can be used as the multiple sensors 201. The signals from these sensors are input to, for example, the input layer L ｉｎ corresponds to the signal input to

[0109] The neuromorphic device 200 includes, for example, a plurality of integrated devices 1. Each integrated device 1 performs a product-sum operation. Each integrated device 1 performs an operation from each layer of the neural network NN to the next layer.

[0110] The conductance (or resistance) of the memristor 100 changes depending on the position of the domain wall DW. The conductance (or resistance) of the memristor 100 corresponds to the weight of the transmission means in the neural network NN. The memristor 100 has a conductance that changes linearly with respect to the input. For example, if information (e.g., temperature) from a specific sensor 201 among the multiple sensors 201 is important, the conductance (weight) of the memristor 100 that is responsible for propagating the signal from that sensor 201 is increased when the neuromorphic device 200 learns.

[0111] The memristor 100 functions as a product calculation element, outputting a signal that is the product of the input voltage and the conductance (or resistance) of the memristor 100 itself. The memristor array 2 functions as a product-sum calculation unit, combining the outputs from multiple memristors 100. The product-sum calculation using multiple memristors 100 is performed by the calculation unit 5.

[0112] The neuromorphic device 200 performs learning and inference. The conductance of the memristor 100 (corresponding to the weight of the transmission means) is adjusted during learning. Inference is performed using the set conductance of the memristor 100 (corresponding to the weight of the transmission means).

[0113] The neuromorphic device 200 used in the system 300 may be capable of both learning and inference, or may be capable of only inference. When only inference is performed, learning tailored to the task is performed in advance, and weights tailored to the task are installed in the memristors 100 of the neuromorphic device 200. For example, the conductance of each memristor 100 is adjusted to correspond to the weights of the transmission means determined in the advance learning. If the neuromorphic device 200 is capable of only inference, the computational load on the edge device can be reduced.

[0114] The communication unit 202 outputs the calculation results of the neuromorphic device 200 to the outside. For example, an inference result for a predetermined task obtained by the neuromorphic device 200 is input to the communication unit 202, and the communication unit 202 outputs the information to the outside. The communication unit 202 may be wired or wireless.

[0115] Second Embodiment Fig. 14 is a plan view of a memristor 101 according to a second embodiment, viewed from the z direction. Fig. 15 is a cross-sectional view of the memristor 101 according to the second embodiment. Fig. 15 is a view of the memristor 101 cut along an xz plane passing through the center of the domain wall displacement layer 10 in the y direction. The arrows shown in the figure represent an example of the orientation direction of the magnetization of a ferromagnetic material.

[0116] The memristor 101 according to the second embodiment differs from the memristor 100 according to the first embodiment in the shapes of the first pinned layer 50 and the second pinned layer 60. In the memristor 101 according to the second embodiment, the same components as those in the memristor 100 according to the first embodiment are denoted by the same reference numerals. Below, the differences between the memristor 101 according to the second embodiment and the memristor 100 according to the first embodiment will be described.

[0117] The xy cross-sectional area of ​​the second pinned layer 60 perpendicular to the z direction is different from the xy cross-sectional area of ​​the first pinned layer 50 perpendicular to the z direction. The xy cross-sectional area of ​​the second pinned layer 60 is smaller than the xy cross-sectional area of ​​the first pinned layer 50, for example.

[0118] Second write current I Ｗ２ Applying a current in the same direction as the magnetization M Ａ１ or magnetization M Ａ２ There is a risk of magnetization reversal of the magnetization M Ａ１ or magnetization M Ａ２ When the magnetization of the first pinned layer 50 is unexpectedly reversed, a new domain wall DW is introduced between the first region A1 and the third region A3. Ｗ２ By making the xy cross-sectional area of ​​the first pinned layer 50 larger than the xy cross-sectional area of ​​the second pinned layer 60, unintended magnetization reversal can be prevented, and the formation of multiple domain walls DW in the domain wall displacement layer 10 can be suppressed.

[0119] The memristor 101 according to the second embodiment has the same effects as the memristor 100 according to the first embodiment. Furthermore, by increasing the cross-sectional area of ​​the first pinned layer 50, it is possible to further suppress malfunction of the memristor 101. The memristor 101 according to the second embodiment can be substituted for the memristor 100 according to the first embodiment.

[0120] 16 is a cross-sectional view of a memristor 102 according to a third embodiment. Fig. 16 is a diagram of the memristor 102 cut along an xz plane passing through the center of the domain wall displacement layer 10 in the y direction. The arrows in the figure indicate an example of the orientation direction of the magnetization of a ferromagnetic material.

[0121] The memristor 102 according to the third embodiment differs from the memristor 100 according to the first embodiment in the shape of the second nonmagnetic layer 40. In the memristor 102 according to the third embodiment, the same components as those in the memristor 100 according to the first embodiment are denoted by the same reference numerals. Below, the differences between the memristor 101 according to the third embodiment and the memristor 100 according to the first embodiment will be described.

[0122] In the second non-magnetic layer 40 of the memristor 102 according to the third embodiment, the minimum film thickness of the non-overlapping portion 43 is thinner than the film thicknesses of the first overlapping portion 41 and the second overlapping portion 42. When the minimum film thickness of the non-overlapping portion 43 is thin, a write current can be efficiently passed through the domain wall displacement layer 10, and a decrease in write efficiency can be suppressed.

[0123] The memristor 102 according to the third embodiment has the same effects as the memristor 100 according to the first embodiment. Furthermore, the memristor 102 has high write efficiency because the minimum film thickness of the non-overlapping portion 43 is thin. The memristor 102 according to the third embodiment can be substituted for the memristor 100 according to the first embodiment.

[0124] 17 is a cross-sectional view of a memristor 103 according to a fourth embodiment. Fig. 17 is a diagram of the memristor 103 cut along an xz plane passing through the center of the domain wall displacement layer 10 in the y direction. The arrows in the figure indicate an example of the orientation direction of the magnetization of a ferromagnetic material.

[0125] The memristor 103 according to the fourth embodiment differs from the memristor 100 according to the first embodiment in the shapes of the second non-magnetic layer 40 and the domain wall displacement layer 10. In the memristor 103 according to the fourth embodiment, the same components as those in the memristor 100 according to the first embodiment are denoted by the same reference numerals. Below, the differences between the memristor 103 according to the fourth embodiment and the memristor 100 according to the first embodiment will be described.

[0126] The second non-magnetic layer 40 of the memristor 103 according to the fourth embodiment does not have a non-overlapping portion 43, and is composed of a first overlapping portion 41 and a second overlapping portion 42. Because the memristor 103 does not have a non-overlapping portion 43, it is possible to efficiently pass a write current through the domain wall displacement layer 10, and a decrease in write efficiency can be suppressed.

[0127] Furthermore, the upper surface S1 of the portion of the domain wall displacement layer 10 that does not overlap with the first pinned layer 50 and the second pinned layer 60 when viewed from the z direction may be located below the lower surface S2 of the portion of the second non-magnetic layer 40 that overlaps with the first pinned layer 50 or the second pinned layer 60.

[0128] The memristor 103 according to the fourth embodiment has the same effects as the memristor 100 according to the first embodiment. Furthermore, the memristor 103 has high write efficiency because it does not have the non-overlapping portion 43. The memristor 103 according to the fourth embodiment can be substituted for the memristor 100 according to the first embodiment.

[0129] 18 is a cross-sectional view of a memristor 104 according to a fifth embodiment. Fig. 18 is a diagram of the memristor 104 cut along an xz plane passing through the center of the domain wall displacement layer 10 in the y direction. The arrows shown in the figure indicate an example of the orientation direction of the magnetization of a ferromagnetic material.

[0130] The memristor 104 according to the fifth embodiment differs from the memristor 100 according to the first embodiment in that the domain wall displacement layer 10 is composed of two layers, a first layer 11 and a second layer 12. In the memristor 104 according to the fifth embodiment, the same components as those in the memristor 100 according to the first embodiment are denoted by the same reference numerals. Below, the differences between the memristor 104 according to the fifth embodiment and the memristor 100 according to the first embodiment will be described.

[0131] The first layer 11 is, for example, on the first nonmagnetic layer 20. The second layer 12 is, for example, on the first layer 11. The first layer 11 is, for example, between the first nonmagnetic layer 20 and the second layer 12 in the z direction.

[0132] The first layer 11 and the second layer 12 are, for example, ferromagnetic materials. The magnetization of the first layer 11 and the magnetization of the second layer 12 are, for example, magnetically coupled and oriented in the same direction.

[0133] The first layer 11 is preferably made of a material that allows a coherent tunneling effect to be obtained between the reference layer 30 and the first layer 11. The first layer 11 is, for example, CoFeB. In the first magnetoresistive unit MTJ1, a magnetoresistive change occurs based on the difference in the relative angle of magnetization between the two ferromagnetic layers that sandwich the first nonmagnetic layer 20. When the first layer 11 contains the above material, the MR ratio of the first magnetoresistive unit MTJ1 increases.

[0134] The second layer 12 preferably contains a material with a low critical current density. A low critical current density of the second layer 12 slows down the domain wall DW motion speed. A slow domain wall DW motion speed allows the memristor 104 to store more data values. The second layer 12 is, for example, a stacked film of Co and Pd.

[0135] In the domain wall displacement layer 10 of the memristor 104, the first layer 11 is primarily responsible for improving the MR ratio, and the second layer 12 is primarily responsible for displacing the domain wall DW. By dividing the domain wall displacement layer 10 into multiple layers, the functions of each layer can be differentiated, increasing the degree of freedom in material selection.

[0136] The memristor 104 according to the fifth embodiment has the same effects as the memristor 100 according to the first embodiment. Furthermore, by using a multi-layer domain wall displacement layer 10, the memristor 104 has a large MR ratio and can reduce the write current that moves the domain wall DW. The memristor 104 according to the fifth embodiment can be substituted for the memristor 100 according to the first embodiment. Here, the example is given in which the domain wall displacement layer 10 has two layers, but the domain wall displacement layer 10 may have three or more layers.

[0137] 19 is a cross-sectional view of a memristor 105 according to a sixth embodiment. Fig. 19 is a diagram of the memristor 105 cut along an xz plane passing through the center of the domain wall displacement layer 10 in the y direction. The arrows in the figure indicate an example of the orientation direction of the magnetization of a ferromagnetic material.

[0138] The memristor 105 according to the sixth embodiment differs from the memristor 100 according to the first embodiment in that it has a third pinned layer 80 and a fourth electrode 74. In the memristor 105 according to the sixth embodiment, the same components as those in the memristor 100 according to the first embodiment are denoted by the same reference numerals. Below, the differences between the memristor 105 according to the sixth embodiment and the memristor 100 according to the first embodiment will be described.

[0139] The memristor 105 further includes a fourth magnetoresistive unit MTJ4. The fourth magnetoresistive unit MTJ4 is composed of a third pinned layer 80, a second non-magnetic layer 40, and a domain wall displacement layer 10. The area resistance product (RA) of the fourth magnetoresistive unit MTJ4 is, for example, smaller than the area resistance product (RA) of the first magnetoresistive unit MTJ1.

[0140] When viewed from the z direction, the third pinned layer 80 is located between the first pinned layer 50 and the second pinned layer 60 in the x direction. The third pinned layer 80 and the domain wall displacement layer 10 sandwich the second nonmagnetic layer 40 in the z direction. The third pinned layer 80 can be made of the same material as the first pinned layer 50. For example, the xy cross-sectional area of ​​the third pinned layer 80 is smaller than the xy cross-sectional area of ​​the reference layer 30.

[0141] The fourth electrode 74 is in contact with the third pinned layer 80. The fourth electrode 74 is connected to a fourth wiring L4 that is different from the first wiring L1, the second wiring L2, and the third wiring L3. The fourth wiring L4 is connected to the calculation unit 5.

[0142] The third pinned layer 80 can be formed simultaneously with the first pinned layer 50 and the second pinned layer 60. The third pinned layer 80 can be formed by forming the fourth electrode 74 on top of the magnetic layer 91 and milling part of the magnetic layer 91 using the fourth electrode 74 as a mask.

[0143] The memristor 105 differs from the memristor 100 according to the first embodiment in the read operation. FIG. 20 is a diagram for explaining the read operation of the memristor 105. The read current of the memristor 105 is a first read current I Ｒ１ and the second read current I Ｒ２ A read current flows in the memristor 105 by generating a potential difference between the second electrode 72, the third electrode 73, and the fourth electrode 74.

[0144] First read current I Ｒ１ flows between the second electrode 72 and the third electrode 73. A first read current I Ｒ１ may flow from the third electrode 73 to the second electrode 72, or may flow from the second electrode 72 to the third electrode 73. Ｒ１ flows in the z-direction inside the first magnetoresistive unit MTJ1, so that the conductance G1 of the first magnetoresistive unit MTJ1 is obtained. The conductance G1 of the first magnetoresistive unit MTJ1 changes depending on the position of the domain wall DW in the x-direction.

[0145] Second read current I Ｒ２ flows between the second electrode 72 and the fourth electrode 74. A second read current I Ｒ２ The second read current I may flow from the fourth electrode 74 to the second electrode 72, or from the second electrode 72 to the fourth electrode 74. Ｒ２ flows in the z-direction inside the fourth magnetoresistive unit MTJ4, so that the conductance G4 of the fourth magnetoresistive unit MTJ4 is obtained. The conductance G4 of the fourth magnetoresistive unit MTJ4 changes depending on the position of the domain wall DW in the x-direction.

[0146] First read current I Ｒ１ and the second read current I Ｒ２ The difference between (I Ｒ１ -I Ｒ２ ) can detect the difference (G1-G4) between the conductance G1 of the first magnetoresistive effect unit MTJ1 and the conductance G4 of the fourth magnetoresistive effect unit MTJ4. The memristor 105 outputs the difference (G1-G4) between the conductances of the first magnetoresistive effect unit MTJ1 and the fourth magnetoresistive effect unit MTJ4.

[0147] As the domain wall DW moves in the +x direction, the volume ratio of the first magnetic domain A31 in the third region A3 increases. In the first magnetoresistive part MTJ1, as the domain wall DW moves in the +x direction, the magnetization M of the reference layer 30 ３０Therefore, the resistance of the first magnetoresistive unit MTJ1 decreases as the domain wall DW moves in the +x direction, and the conductance G1 of the first magnetoresistive unit MTJ1 increases as the domain wall DW moves in the +x direction.

[0148] The magnetization M of the third pinned layer 80 ８０ is the magnetization M of the reference layer 30 ３０ The resistance of the fourth magnetoresistive unit MTJ4 increases as the domain wall DW moves in the +x direction, and the conductance G4 of the fourth magnetoresistive unit MTJ4 decreases as the domain wall DW moves in the +x direction. The magnetization M of the third pinned layer decreases as the domain wall DW moves in the +x direction. ８０ This is because the volume ratio of the portion (first magnetic domain A31) in which the magnetization is oriented in a direction antiparallel to the first magnetic domain A31 increases.

[0149] The conductance of the memristor 105 is calculated as the difference (G1-G4) between the conductance G1 of the first magnetoresistive unit MTJ1 and the conductance G4 of the fourth magnetoresistive unit MTJ4. By calculating the difference between the conductance G1 of the first magnetoresistive unit MTJ1 and the conductance G4 of the fourth magnetoresistive unit MTJ4, a negative value can also be selected for the conductance of the memristor 105. In other words, the memristor 105 can express a range of conductance from negative to positive values ​​with a single element.

[0150] The memristor 105 according to the sixth embodiment has the same effects as the memristor 100 according to the first embodiment. Furthermore, the memristor 105 has the third pinned layer 80, which allows a single element to express conductance ranging from negative to positive values. The memristor 105 according to the sixth embodiment can be substituted for the memristor 100 according to the first embodiment.

[0151] Although the preferred embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to these embodiments. For example, the characteristic configurations of the respective embodiments may be combined, or some modifications may be made without departing from the spirit of the invention.

[0152] For example, the characteristic configurations of the memristors according to the first to sixth embodiments may be combined.

[0153] REFERENCE SIGNS LIST 1 Integrated device 2 Memristor array 3 Control device 4 Signal input unit 5 Calculation unit 6 Output unit 7 Control unit 8 Power supply 10 Domain wall displacement layer 11 First layer 12 Second layer 20 First non-magnetic layer 30 Reference layer 40 Second non-magnetic layer 41 First overlapping unit 42 Second overlapping unit 43 Non-overlapping unit 50 First pinned layer 60 Second pinned layer 71 First electrode 72 Second electrode 73 Third electrode 74 Fourth electrode 80 Third pinned layer 90 Insulating layer 91 Magnetic layer 100, 101, 102, 103, 104, 105 Memristor 200 Neuromorphic device 201 Sensor 202 Communication unit 300 System DW Domain wall I ｉｎ Initial current I Ｗ１ First write current I Ｗ２ Second write current S1 Upper surface S2 Lower surface

Claims

1. A memristor comprising a reference layer, a first non-magnetic layer, a domain wall displacement layer, a second non-magnetic layer, a first pinned layer, and a second pinned layer, wherein the reference layer, the domain wall displacement layer, the first pinned layer, and the second pinned layer each have a magnetic material, the first non-magnetic layer is between the reference layer and the domain wall displacement layer in the stacking direction, the first pinned layer is connected to the domain wall displacement layer with the second non-magnetic layer sandwiched between them, and the second pinned layer is connected to the domain wall displacement layer at a position different from that of the first pinned layer with the second non-magnetic layer sandwiched between them, and a write current smaller than an initial current can be applied between the first pinned layer and the second pinned layer, and the initial current is a current applied between the first pinned layer and the second pinned layer when a domain wall is introduced inside the domain wall displacement layer.

2. The memristor of claim 1, wherein the magnetization of a first region of the domain wall displacement layer that overlaps with the first pinned layer as viewed from the stacking direction is antiparallel to the magnetization of the first pinned layer, and the magnetization of a second region of the domain wall displacement layer that overlaps with the second pinned layer as viewed from the stacking direction is parallel to the magnetization of the second pinned layer.

3. The memristor according to claim 1, wherein the magnetization of the first pinned layer and the magnetization of the domain wall displacement layer are not magnetically coupled, and the magnetization of the second pinned layer and the magnetization of the domain wall displacement layer are not magnetically coupled.

4. The memristor of claim 1, wherein the cross-sectional areas of the first pinned layer and the second pinned layer perpendicular to the stacking direction are each larger than the cross-sectional area of ​​the domain wall displacement layer perpendicular to a first direction from the first pinned layer to the second pinned layer.

5. The memristor of claim 1, wherein a cross-sectional area of ​​the second pinned layer perpendicular to the stacking direction is different from a cross-sectional area of ​​the first pinned layer perpendicular to the stacking direction.

6. The memristor according to claim 1, wherein the thickness of the second nonmagnetic layer in the stacking direction is thinner than the thickness of the first nonmagnetic layer in the stacking direction.

7. The memristor according to claim 1, wherein the thickness of the second non-magnetic layer in the stacking direction is greater than the thickness of the first non-magnetic layer in the stacking direction.

8. The memristor described in claim 1, wherein the second non-magnetic layer has, when viewed from the stacking direction, an overlapping portion that overlaps with the first pinned layer or the second pinned layer, and a non-overlapping portion that does not overlap with the first pinned layer or the second pinned layer, and the minimum film thickness of the non-overlapping portion is thinner than the film thickness of the overlapping portion.

9. The memristor described in claim 1, wherein the upper surface of the portion of the domain wall displacement layer that does not overlap with the first pinned layer or the second pinned layer when viewed from the stacking direction is lower than the lower surface of the portion of the second nonmagnetic layer that overlaps with the first pinned layer or the second pinned layer.

10. The memristor according to claim 1, further comprising a third pinned layer, wherein the third pinned layer is connected to the domain wall displacement layer, with the second nonmagnetic layer sandwiched between the first pinned layer and the second pinned layer, as viewed from the stacking direction.

11. The memristor of claim 10, wherein a cross-sectional area of ​​the third pinned layer perpendicular to the stacking direction is smaller than a cross-sectional area of ​​the reference layer perpendicular to the stacking direction, and a resistance-area product (RA) of a magnetoresistive effect section consisting of the third pinned layer, the second non-magnetic layer, and the domain wall displacement layer is smaller than a resistance-area product (RA) of a magnetoresistive effect section consisting of the reference layer, the first non-magnetic layer, and the domain wall displacement layer.

12. The memristor of claim 1, wherein the critical current density required to reverse the magnetization of a first region of the domain wall displacement layer that overlaps with the first pinned layer as viewed from the stacking direction, or a second region of the domain wall displacement layer that overlaps with the second pinned layer as viewed from the stacking direction, is greater than the critical current density required to move the domain wall inside the domain wall displacement layer.

13. The memristor of claim 1, wherein the area resistance product (RA) of the magnetoresistive effect section consisting of the first pinned layer, the second non-magnetic layer, and the domain wall displacement layer is smaller than the area resistance product (RA) of the magnetoresistive effect section consisting of the reference layer, the first non-magnetic layer, and the domain wall displacement layer.

14. The memristor of claim 1, wherein the domain wall displacement layer has a first layer and a second layer, the first layer is closer to the first nonmagnetic layer than the second layer, and the material constituting the first layer is different from the material constituting the second layer.

15. The memristor of claim 1, wherein a pulse length of the write current is shorter than a pulse length of the initial current.

16. The memristor of claim 2, configured so that a read current flows between the second pinned layer and the reference layer.

17. The memristor of claim 1, wherein the write current comprises a first write current flowing in the same direction as the initial current and a second write current flowing in the opposite direction to the initial current, and the second write current is configured to be smaller than the first write current.

18. A memristor array comprising a plurality of memristors, at least one of which is the memristor of claim 1.

19. A neuromorphic device comprising the memristor of claim 1.

20. A method for controlling a memristor, comprising: applying an initial current between a first pinned layer and a second pinned layer of a memristor to introduce a domain wall inside a domain wall displacement layer; and applying a write current smaller than the initial current between the first pinned layer and the second pinned layer to move the domain wall, wherein the memristor comprises a reference layer, a first non-magnetic layer, the domain wall displacement layer, a second non-magnetic layer, the first pinned layer, and the second pinned layer, wherein the reference layer, the domain wall displacement layer, the first pinned layer, and the second pinned layer each have a magnetic material, the first non-magnetic layer is between the reference layer and the domain wall displacement layer in the stacking direction, the first pinned layer is connected to the domain wall displacement layer with the second non-magnetic layer sandwiched between them, and the second pinned layer is connected to the domain wall displacement layer at a position different from the first pinned layer, with the second non-magnetic layer sandwiched between them.

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