Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device which improves adhesion between an insulating substrate and a sealing material and achieves a reduction in device size. This semiconductor device includes an insulating substrate, a semiconductor element, and a sealing material. The insulating substrate includes an insulating layer, a front surface circuit pattern provided on the front surface of the insulating layer, and a rear surface circuit pattern provided on the rear surface of the insulating layer. The semiconductor element is bonded to the front surface circuit pattern. The sealing material seals the semiconductor element and the insulating substrate. The sealing material covers the outer peripheral portion of the rear surface circuit pattern such that a portion of the rear surface circuit pattern is exposed from the lower surface of the sealing material.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] The resin-sealed semiconductor device described in Patent Document 1 includes a block-shaped cooling element soldered to the back surface of an insulating substrate, and is resin-sealed with only the back surface of the cooling element exposed. This structure reduces peeling of the sealing resin from the insulating substrate and the generation of sealing resin residue on the back surface of the insulating substrate.

[0003] JP 2014-7294 A

[0004] In the semiconductor device described in Patent Document 1, since a cooling body is built in, the semiconductor device inevitably becomes large in size. In order to reduce the size of the semiconductor device, a structure that does not cause resin peeling even when a cooling body is not provided is required.

[0005] In order to solve the above problems, an object of the present disclosure is to provide a semiconductor device that improves adhesion between an insulating substrate and a sealing material and achieves a reduction in device size.

[0006] The semiconductor device according to the present disclosure includes an insulating substrate, a semiconductor element, and an encapsulant. The insulating substrate includes an insulating layer, a front circuit pattern provided on the front surface of the insulating layer, and a back circuit pattern provided on the back surface of the insulating layer. The semiconductor element is bonded to the front circuit pattern. The encapsulant encapsulates the semiconductor element and the insulating substrate. The encapsulant covers the outer periphery of the back circuit pattern so that a portion of the back circuit pattern is exposed from the underside of the encapsulant.

[0007] According to the present disclosure, a semiconductor device is provided that improves adhesion between an insulating substrate and a sealing material and realizes a reduction in device size.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] FIG. 1 is a diagram showing the configuration of a semiconductor device in a first embodiment. FIG. 2 is a diagram showing the configuration of a semiconductor device in which a sealing material does not cover the outer periphery of a rear surface circuit pattern. FIG. 3 is a diagram showing the configuration of a semiconductor device in a second embodiment. FIG. 4 is a partial cross-sectional view showing the configuration of a semiconductor device in a second embodiment. FIG. 5 is a diagram showing the configuration of a semiconductor device in a second embodiment. FIG. 6 is a diagram showing the configuration of a semiconductor device in a third embodiment. FIG. 7 is a diagram showing the configuration of a semiconductor device in a fourth embodiment. FIG. 8 is a diagram showing the configuration of a semiconductor device in a fourth embodiment. FIG. 9 is a cross-sectional view showing the configuration of a semiconductor device in a fifth embodiment.

[0010] 1A and 1B are diagrams showing the configuration of a semiconductor device 101 according to a first embodiment. Fig. 1A shows the cross-sectional configuration of the semiconductor device 101, and Fig. 1B shows the configuration of the underside of the semiconductor device 101. The semiconductor device 101 includes an insulating substrate 10, a semiconductor element 20, terminals 30, and a sealing material 40.

[0011] The insulating substrate 10 includes a ceramic insulating layer 11, a front circuit pattern 12, and a back circuit pattern 13. The front circuit pattern 12 is provided on the front surface of the ceramic insulating layer 11, and the back circuit pattern 13 is provided on the back surface of the ceramic insulating layer 11. The front surface corresponds to the surface of the ceramic insulating layer 11 on which the semiconductor element 20 is mounted. The front circuit pattern 12 and the back circuit pattern 13 are made of metal such as copper. The insulating substrate 10 in the first embodiment is warped in a convex shape toward the back surface, i.e., downward.

[0012] The semiconductor element 20 is electrically connected to the surface circuit pattern 12 of the insulating substrate 10. The semiconductor element 20 in the first embodiment is joined to the surface circuit pattern 12 via an internal joining material 51 such as solder or silver. The semiconductor element 20 is preferably formed of a wide bandgap semiconductor, and the semiconductor element 20 in the first embodiment is formed of SiC. The semiconductor element 20 is, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a Schottky barrier diode, or the like. Alternatively, the semiconductor element 20 may be a reverse-conducting IGBT (RC-IGBT) in which an IGBT and a free wheel diode are formed within a single semiconductor substrate.

[0013] The terminals 30 are electrically connected to the semiconductor element 20. The terminals 30 are connected to the semiconductor element 20 via metal wires 60 such as aluminum wires. The terminals 30 are also joined to the surface circuit pattern 12 or the semiconductor element 20 via an internal joining material 52 such as solder or silver. Ends of the terminals 30 protrude from the sealing material 40. The surfaces of the terminals 30 may be plated with metal such as Ni or Sn.

[0014] The sealing material 40 seals the insulating substrate 10, the semiconductor element 20, a portion of the terminal 30, the metal wire 60, the internal bonding material 51, and the internal bonding material 52. However, a portion of the rear surface circuit pattern 13 is exposed from the lower surface of the sealing material 40 to form an exposed surface 13A. In addition, in a plan view, the boundary between the sealing material 40 and the exposed surface 13A of the rear surface circuit pattern 13 exposed from the sealing material 40 is located outside the semiconductor element 20. The sealing material 40 is, for example, an epoxy resin.

[0015] A feature of the semiconductor device 101 of the first embodiment is that a sealing material 40 covers the outer periphery of the rear surface circuit pattern 13. Fig. 1(c) is an enlarged cross-sectional view showing the configuration of the sealing material cover 41. Fig. 1(c) shows the configuration of the region P shown in Fig. 1(b). The sealing material 40 extends around to the underside of the rear surface circuit pattern 13 to form a resin burr, i.e., the sealing material cover 41.

[0016] At high temperatures during heating treatment in the manufacturing process of the semiconductor device 101, the difference in linear expansion between the ceramic insulating layer 11, the front circuit pattern 12, and the back circuit pattern 13 causes downward convex warping in the insulating substrate 10. FIG. 1( d ) is a cross-sectional view showing the structure of the insulating substrate 10 with warping. When a sealing material 40 is molded by a resin molding method such as transfer molding in this warped state, the sealing material 40 flows into the gap formed between the mold die and the outer periphery of the back circuit pattern 13. As a result, as shown in FIG. 1( d ), a sealing material cover 41 naturally forms around the outer periphery of the back circuit pattern 13, forming a structure in which the sealing material 40 embraces the back circuit pattern 13.

[0017] 2A and 2B are diagrams showing the configuration of a semiconductor device 100 in which the encapsulant 40 does not cover the outer periphery of the rear surface circuit pattern 13. Fig. 2A shows the cross-sectional configuration of the semiconductor device 100, and Fig. 2B shows the configuration of the underside of the semiconductor device 100. In the semiconductor device 100, the encapsulant 40 does not embrace the rear surface circuit pattern 13, so peeling of the encapsulant 40 is likely to occur.

[0018] On the other hand, in the semiconductor device 101 of the first embodiment, as described above, the encapsulant cover 41 forms a structure in which the encapsulant 40 embraces the rear surface circuit pattern 13. This improves adhesion between the encapsulant 40 and the rear surface circuit pattern 13, reducing the occurrence of peeling. As a result, the reliability of the semiconductor device 101 in durability tests is improved. Furthermore, in the semiconductor device 101 of the first embodiment, the rear surface circuit pattern 13 is directly exposed from the lower surface of the encapsulant 40, and the configuration is simple. This ensures reliability and achieves a reduction in device size. In this way, the semiconductor device 101 achieves both a reduction in device size and high reliability without increasing the number of components.

[0019] In summary, the semiconductor device 101 in the first embodiment includes an insulating substrate 10, a semiconductor element 20, and a sealing material 40. The insulating substrate 10 includes a ceramic insulating layer 11, a front circuit pattern 12 provided on the front surface of the ceramic insulating layer 11, and a back circuit pattern 13 provided on the back surface of the ceramic insulating layer 11. The semiconductor element 20 is bonded to the front circuit pattern 12. The sealing material 40 seals the semiconductor element 20 and the insulating substrate 10. The sealing material 40 covers the outer periphery of the back circuit pattern 13 so that a portion of the back circuit pattern 13 is exposed from the bottom surface of the sealing material 40.

[0020] According to such a semiconductor device 101, the adhesion between the insulating substrate 10 and the sealing material 40 is improved and the size of the device is reduced.

[0021] In addition, in a plan view, the boundary line between the sealing material 40 and the exposed surface 13A of the back surface circuit pattern 13 exposed from the sealing material 40 is located outside the semiconductor element 20. Since the heat dissipation surface is reliably exposed, heat dissipation is improved.

[0022] Furthermore, the semiconductor element 20 is made of SiC, which reduces loss in the semiconductor element 20 and allows the semiconductor device 101 to be fabricated with a high density.

[0023] Second Embodiment FIG. 3 is a diagram illustrating the configuration of a semiconductor device 102A according to a second embodiment. FIG. 3(a) illustrates the cross-sectional configuration of the semiconductor device 102A, and FIG. 3(b) illustrates the configuration of the underside of the semiconductor device 102A. The rear surface circuit pattern 13 includes a step portion 13B provided on the outer periphery of the rear surface circuit pattern 13. The encapsulant 40 wraps around and covers the step portion 13B. The step portion 13B stably forms the encapsulant cover 41. As a result, the occurrence of peeling between the rear surface circuit pattern 13 and the encapsulant 40 is reduced, further improving the reliability of the semiconductor device 102A. The height of the step portion 13B is preferably 100 μm or more. In this case, the encapsulant 40 reliably wraps around the step portion 13B of the rear surface circuit pattern 13 during transfer molding.

[0024] 4 is a partial cross-sectional view showing the configuration of a semiconductor device 102B according to the second embodiment. The rear surface circuit pattern 13 includes an inclined portion, i.e., a tapered portion 13C, provided on the outer periphery of the rear surface circuit pattern 13. The encapsulant 40 wraps around and covers the tapered portion 13C. The encapsulant 40 wraps around the tapered portion 13C more easily than the stepped portion 13B. Therefore, the encapsulant covering 41 is stably formed, reducing the occurrence of peeling between the rear surface circuit pattern 13 and the encapsulant 40. As long as the encapsulant 40 stably wraps around the underside of the rear surface circuit pattern 13, the tapered portion 13C may be provided instead of the stepped portion 13B.

[0025] In these semiconductor devices 102A and 102B, the entire bottom surface of the back surface circuit pattern 13 is exposed from the sealing material 40. A cooler (not shown) is attached to the bottom surface, i.e., exposed surface 13A, of the back surface circuit pattern 13 via a thermally conductive material (not shown). Because the thermal conductivity of the resin forming the sealing material 40 is lower than that of the metal, such as copper, forming the back surface circuit pattern 13, if a thin sealing material 40 is sandwiched between the back surface circuit pattern 13 and the cooler, heat dissipation is hindered. If the entire bottom surface of the back surface circuit pattern 13 is exposed from the sealing material 40, heat dissipation is improved.

[0026] In the manufacturing process of the semiconductor devices 102A and 102B, the exposed surface 13A, in which the entire bottom surface of the rear surface circuit pattern 13 is exposed from the sealing material 40, is formed by using a laser to remove the sealing material 40 attached to the bottom surface of the rear surface circuit pattern 13. The laser removal method reduces damage to the semiconductor devices 102A and 102B compared to mechanical removal methods such as cutting and sandblasting.

[0027] FIG. 5 is a partial cross-sectional view showing the configuration of a semiconductor device 102C according to the second embodiment. The lower surface 42 of the sealing material 40 covering the outer periphery of the rear surface circuit pattern 13 is located below the exposed surface 13A of the rear surface circuit pattern 13 that is exposed through the sealing material 40. Compared to when the lower surface 42 of the sealing material 40 and the exposed surface 13A of the rear surface circuit pattern 13 are flush with each other, the thickness from the rear surface of the ceramic insulating layer 11 to the lower surface 42 of the sealing material 40 is thicker. By providing the sealing material 40 covering the outer periphery of the rear surface circuit pattern 13 further below the exposed surface 13A of the rear surface circuit pattern 13, the sealing material covering 41 is stably formed, reducing the occurrence of peeling between the rear surface circuit pattern 13 and the sealing material 40. Furthermore, this sealing material covering 41 can be stably formed simply by molding using a mold, without requiring laser removal of the sealing material 40. 3 or a tapered portion 13C shown in FIG. 4 may be formed on the outer periphery of the rear surface circuit pattern 13.

[0028] FIG. 6 is a diagram showing the configuration of a semiconductor device 102D according to the second embodiment. FIG. 6(a) shows the cross-sectional configuration of the semiconductor device 102D, and FIG. 6(b) shows the configuration of the underside of the semiconductor device 102D. The outer shape of the backside circuit pattern 13 has long and short sides in a plan view. In this configuration, stress is more likely to occur on the short sides than on the long sides. To alleviate this stress, a step portion 13B is provided only on the short sides, not on the long sides. The sealing material 40 covers the step portion 13B provided on the short sides, forming a sealing material cover 41 only on the short sides.

[0029] In this way, the step portion 13B may be selectively provided depending on the location where the sealing material cover 41 is to be formed for stress relief. By providing the step portion 13B only in the necessary position, the area of ​​the exposed surface 13A of the back surface circuit pattern 13, i.e., the heat dissipation area, is secured. A semiconductor device 102D that achieves both heat dissipation and insulation properties is realized, improving design freedom. Furthermore, the above effect can be obtained even if the tapered portion 13C is provided only on the short side instead of the step portion 13B.

[0030] Furthermore, a general configuration that achieves the above-mentioned effects is as follows: That is, the outer shape of the outer periphery of the rear surface circuit pattern 13 has a plurality of sides (e.g., short sides and long sides) in a plan view, and the presence or absence of a step portion 13B or a tapered portion 13C, or the step shape of the step portion 13B or the tapered shape of the tapered portion 13C, or the step width of the step portion 13B or the tapered width of the tapered portion 13C, is set arbitrarily on each of the plurality of sides.

[0031] FIG. 7 illustrates the configuration of a semiconductor device 102E according to the second embodiment. FIG. 7(a) illustrates the cross-sectional configuration of the semiconductor device 102E, and FIG. 7(b) illustrates the underside configuration of the semiconductor device 102E. In a plan view, the width D1 of the step portions 13B at the corners of the rear surface circuit pattern 13 is wider than the width D2 of the step portions 13B at the sides of the rear surface circuit pattern 13. Because stress tends to concentrate at the corners, widening the width of the step portions 13B at the corners also widens the width of the encapsulant covering 41. As a result, peeling between the rear surface circuit pattern 13 and the encapsulant 40 is reduced, improving the reliability of the semiconductor device 102E. Although not illustrated, the above-described effects can also be achieved when tapered portions 13C are provided at the corners in a similar configuration to that described above, instead of the step portions 13B.

[0032] Furthermore, in a plan view, the boundary line between the sealing material 40 and the exposed surface 13A of the back surface circuit pattern 13 exposed from the sealing material 40 includes rounded portions 43 at positions corresponding to the corners of the back surface circuit pattern 13. The rounded portions 43 are formed by, for example, laser processing. This configuration reduces stress on the corners when the package is mounted with solder, improving the reliability of the semiconductor device 102E.

[0033] 8 is a partial cross-sectional view showing the configuration of a semiconductor device 102F according to the second embodiment. The step portion 13B has a rough surface. The rough surface is formed by laser processing. The rough surface exerts an anchor effect, further improving the adhesion between the rear surface circuit pattern 13 and the sealing material 40. When a tapered portion 13C is provided instead of the step portion 13B, the above-mentioned effect can be obtained by forming a rough surface on the tapered portion 13C.

[0034] Furthermore, although not shown, in either the semiconductor device shown in the first or second embodiment, a rough surface may be formed on the side surface of the rear surface circuit pattern 13. This exerts an anchor effect, further improving the adhesion between the rear surface circuit pattern 13 and the sealing material 40.

[0035] <Third Embodiment> Figure 9 is a diagram showing the configuration of a semiconductor device 103 according to a third embodiment. Figure 9(a) shows the cross-sectional configuration of the semiconductor device 103, and Figure 9(b) shows the configuration of the underside of the semiconductor device 103. The insulating substrate 10 of the semiconductor device 103 is warped in a downwardly convex shape, similar to the semiconductor device 101 of the first embodiment. On the other hand, the semiconductor device 103 of the third embodiment includes, in addition to the configuration of the semiconductor device 101 of the first embodiment, a hole 13D provided in an exposed surface 13A exposed from the sealing material 40. The hole 13D functions as a reference hole for position recognition in the process of removing the sealing material 40.

[0036] In the manufacturing process of the semiconductor device 103, excess sealing material 40 attached to the underside of the rear surface circuit pattern 13, especially the excess sealing material 40 attached to the periphery of the rear surface circuit pattern 13, is removed by a laser. The resin used as the sealing material 40 has a lower thermal conductivity than the metal, such as copper, that forms the rear surface circuit pattern 13. If the sealing material 40 is sandwiched between the rear surface circuit pattern 13 and a cooler, heat dissipation is hindered. Removing the excess sealing material 40 by a laser increases the area of ​​the exposed surface 13A, thereby reducing thermal resistance while maintaining insulation performance.

[0037] When removing the sealing material 40, a laser is irradiated based on the hole 13D provided in the back surface circuit pattern 13. The hole 13D is formed by etching using the same mask as that used when etching the back surface circuit pattern 13. This improves the positional accuracy of the hole 13D in the back surface circuit pattern 13. Since the sealing material 40 is removed based on the hole 13D, the sealing material 40 is removed with high precision. As a result, dimensional variations are reduced, a heat dissipation area is ensured, and heat dissipation performance is improved. A high-output semiconductor device 103 is realized. In this way, improved positional accuracy when removing the sealing material 40 minimizes the thermal resistance from the back surface circuit pattern 13 to the cooler, thereby minimizing the device size.

[0038] The holes 13D may be formed by laser processing instead of etching. This method reduces the reduction in the heat dissipation area compared to processing by etching. It is preferable to provide the holes 13D in two or more locations. The two or more holes 13D also make it possible to correct misalignment of the insulating substrate 10 in the rotational direction.

[0039] <Fourth Embodiment> Figure 10 is a diagram showing the configuration of a semiconductor device 104A according to a fourth embodiment. Figure 10(a) shows the cross-sectional configuration of the semiconductor device 104A, and Figure 10(b) shows the configuration of the underside of the semiconductor device 104A. The rear surface circuit pattern 13 has two holes 13D formed in an exposed surface 13A exposed from the sealing material 40. In addition, the rear surface circuit pattern 13 has a stepped portion 13B formed on its outer periphery. The sealing material 40 wraps around and covers the stepped portion 13B, but a portion of the stepped portion 13B is exposed from the sealing material 40.

[0040] In the manufacturing process of the semiconductor device 104A (for example, the manufacturing process described in the third embodiment can be applied), a portion of the lower surface of the encapsulant 40 is removed. At that time, a portion of the encapsulant cover 41 is also removed to an extent that the reliability of the semiconductor device 104A is ensured, thereby exposing a portion of the step portion 13B. With this configuration, the heat dissipation surface is reliably exposed, improving heat dissipation. In addition, the manufacturing process tolerance and thermal feasibility tolerance are expanded.

[0041] FIG. 11 is a diagram illustrating the configuration of a semiconductor device 104B according to the fourth embodiment. FIG. 11(a) illustrates the cross-sectional configuration of the semiconductor device 104B, and FIG. 11(b) illustrates the configuration of the underside of the semiconductor device 104B. The outer shape of the periphery of the backside circuit pattern 13 has multiple sides, including short and long sides, in a plan view. In the manufacturing process of the semiconductor device 104B (e.g., the manufacturing process described in the third embodiment can be applied), when removing the encapsulant 40, the removal area of ​​the encapsulant 40 is varied depending on the location of each of the multiple sides, including the short and long sides. For example, the removal area is varied depending on the location to relieve stress, such that only the short sides, where stress is likely to occur, are covered with the encapsulant 40 and the long sides are exposed. The removal of the encapsulant cover 41 may be varied depending on the short and long sides. Providing the encapsulant cover 41 in the necessary areas increases the heat dissipation area and improves heat dissipation.

[0042] FIG. 12 is a diagram illustrating the configuration of a semiconductor device 104C according to the fourth embodiment. FIG. 12(a) illustrates the cross-sectional configuration of the semiconductor device 104C, and FIG. 12(b) illustrates the configuration of the underside of the semiconductor device 104C. The outer shape of the periphery of the backside circuit pattern 13 has multiple sides, including short and long sides, in a plan view. In the manufacturing process of the semiconductor device 104C (e.g., the manufacturing process described in the third embodiment can be applied), the sealing material 40 covering the step portions 13B formed on each of the multiple sides, including the short and long sides, is removed according to the location of each of the multiple sides, including the short and long sides, to expose a portion of the step portion 13B. In this manner, the exposure of the step portion 13B may vary depending on the short and long sides. Since the heat dissipation surface is reliably exposed, heat dissipation performance is improved.

[0043] Fifth Embodiment Figure 13 is a cross-sectional view showing the configuration of a semiconductor device 105 according to a fifth embodiment. The encapsulant 40 includes a recess 44 in the center of the upper surface of the encapsulant 40. As the volume of the encapsulant 40 decreases, the rigidity of the encapsulant 40 also decreases. When the semiconductor device 105 is subjected to thermal history, the semiconductor device 105 warps due to expansion and contraction of the encapsulant 40. If the warping is significant, the encapsulant 40 and the rear surface circuit pattern 13 will peel off. In the semiconductor device 105 according to the fifth embodiment, the rigidity of the encapsulant 40 is reduced, thereby reducing warping and peeling. If a step portion 13B is provided in the rear surface circuit pattern 13, reliability is also improved.

[0044] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0045] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0046] 10 insulating substrate, 11 ceramic insulating layer, 12 front surface circuit pattern, 13 rear surface circuit pattern, 13A exposed surface, 13B step portion, 13C tapered portion, 13D hole, 20 semiconductor element, 30 terminal, 40 sealing material, 41 sealing material covering, 42 lower surface of sealing material, 43 R portion, 44 recess, 51 internal bonding material, 52 internal bonding material, 60 metal wire, 100 to 105 semiconductor device, P region.

Claims

1. A semiconductor device comprising: an insulating substrate including an insulating layer, a front circuit pattern provided on the front surface of the insulating layer, and a back circuit pattern provided on the back surface of the insulating layer; a semiconductor element bonded to the front circuit pattern; and a sealing material that seals the semiconductor element and the insulating substrate, wherein the sealing material covers the outer periphery of the back circuit pattern so that a portion of the back circuit pattern is exposed from the underside of the sealing material.

2. The semiconductor device according to claim 1, wherein the rear surface circuit pattern includes a step portion provided on the outer periphery of the rear surface circuit pattern, and the sealing material covers at least a part of the step portion.

3. The semiconductor device according to claim 2, wherein the height of the step portion is 100 μm or more.

4. The semiconductor device according to claim 1, wherein the rear surface circuit pattern includes a tapered portion provided on the outer periphery of the rear surface circuit pattern, and the sealing material covers the tapered portion.

5. The semiconductor device according to claim 1, wherein the lower surface of the sealing material covering the outer periphery of the rear surface circuit pattern is positioned lower than the exposed surface of the rear surface circuit pattern exposed from the sealing material.

6. A semiconductor device according to claim 2 or claim 4, wherein the outer shape of the outer periphery of the rear surface circuit pattern has a plurality of sides in a plan view, and the presence or absence of the step portion or tapered portion, or the step shape of the step portion or the tapered shape of the tapered portion, or the step width of the step portion or the tapered width of the tapered portion, is set arbitrarily on each of the plurality of sides.

7. A semiconductor device according to claim 2 or claim 4, wherein, in a plan view, the width of the step portion or the tapered portion provided at the corner portion of the rear surface circuit pattern is wider than the width of the step portion or the tapered portion provided at the side portion of the rear surface circuit pattern.

8. The semiconductor device according to claim 7, wherein, in a plan view, the boundary line between the exposed surface of the rear surface circuit pattern exposed from the sealing material and the sealing material includes an R portion at a position corresponding to the corner portion of the rear surface circuit pattern.

9. The semiconductor device according to claim 2 or 4, wherein the step portion or the tapered portion has a rough surface.

10. The semiconductor device according to claim 1, wherein the side surface of the rear surface circuit pattern has a rough surface.

11. The semiconductor device according to claim 1, wherein the entire bottom surface of said back surface circuit pattern is exposed from said sealing material.

12. A method for manufacturing a semiconductor device according to claim 1, wherein the excess sealing material adhering to the outer periphery of the rear surface circuit pattern is removed by a laser.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the rear surface circuit pattern includes holes provided on the exposed surface exposed from the sealing material, and the removal by the laser is performed using the holes as recognition holes.

14. A method for manufacturing a semiconductor device according to claim 13, wherein the holes are formed by etching.

15. A method for manufacturing a semiconductor device according to claim 13, wherein the holes are formed by laser processing.

16. The semiconductor device according to claim 2, wherein a portion of the step portion is exposed from the sealing material.

17. The method for manufacturing a semiconductor device according to claim 12, wherein the outer shape of the outer periphery of the rear surface circuit pattern has a plurality of sides in a plan view, and the removal area of ​​the sealing material is changed according to the location of each of the plurality of sides.

18. A method for manufacturing a semiconductor device as described in claim 12, wherein the outer shape of the outer periphery of the back surface circuit pattern has a plurality of sides in a plan view, and the sealing material covering the step portions formed on each of the plurality of sides is removed according to the location of each of the plurality of sides to expose a portion of the step portion.

19. The semiconductor device according to claim 1, wherein the encapsulant includes a recess in the center of the upper surface of the encapsulant.

20. The semiconductor device according to claim 1, wherein, in a plan view, the boundary line between the exposed surface of the back surface circuit pattern exposed from the sealing material and the sealing material is located outside the semiconductor element.

21. The semiconductor device according to claim 1, wherein the semiconductor element is formed of SiC.

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