Multilayer ceramic capacitor

Abstract

 An objective of the present invention is to provide a multilayer ceramic capacitor in which it is possible to suppress the occurrence of cracks during mounting using a mounting machine or the like. A multilayer ceramic capacitor 10 according to the present invention comprises: a laminated body having a first surface and a second surface facing each other in a lamination direction, a third surface and a fourth surface facing each other in a first direction orthogonal to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction orthogonal to the lamination direction and the first direction; and first to fourth external electrodes disposed on the surface of the laminated body. The multilayer body includes first internal electrodes exposed at the third surface and the fourth surface, and second internal electrodes exposed at the third surface and the fourth surface. The first external electrode has a first base plating layer connected to the first internal electrodes. When the dimension of the first base plating layer in the laminating direction is t1, the dimension of the laminated body in the laminating direction is t2, the dimension of the multilayer ceramic capacitor in the first direction is L, and the dimension of the multilayer ceramic capacitor in the second direction is W, the relationships 0.85≤L / W≤1.0 and (t2-5 μm)≤t1≤(t2+2 μm) are satisfied.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, electronic devices such as mobile phones and portable music players have become smaller and thinner. Accordingly, the multilayer ceramic capacitors mounted in these smaller and thinner electronic devices have also become smaller and thinner (see Patent Document 1). In particular, multilayer ceramic capacitors that have become thinner are now being used by being built into wiring boards, or even when mounted on the surface of a wiring board, they are being mounted in very narrow spaces.

[0003] Japanese Patent Application Laid-Open No. 2021-101449

[0004] As a multilayer ceramic capacitor that can accommodate such thinning, a multilayer ceramic capacitor is disclosed in Patent Document 1. For the multilayer ceramic capacitor described in Patent Document 1 and elsewhere, a method is known in which an area other than the external electrodes is masked and an underlayer is formed as a sputtered film using a sputtering method. However, there have been cases where the capacitor cracks during mounting or the mounting height is increased due to excessive solder wetting.

[0005] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks during mounting using a mounting machine or the like.

[0006] A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising a laminate having a first surface and a second surface opposed to each other in a lamination direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the lamination direction and the first direction, and first to fourth external electrodes arranged on a surface of the laminate, wherein the laminate has first internal electrodes exposed on the third surface and the fourth surface, and fifth and sixth external electrodes exposed on the third surface and the first direction. and a second internal electrode exposed at the fourth surface, wherein the first external electrode has a first undercoat plating layer connected to the first internal electrode, and wherein, when the dimension of the first undercoat plating layer in the stacking direction is t, the dimension of the laminate in the stacking direction is T, the dimension of the multilayer ceramic capacitor in the first direction is L, and the dimension of the multilayer ceramic capacitor in the second direction is W, the relationships are 0.85≦L / W≦1.0 and (T−5 μm)≦t≦(T+2 μm).

[0007] According to the multilayer ceramic capacitor of the present invention, by satisfying the condition 0.85≦L / W≦1.00, the laminate has a substantially tetragonal shape, and when the dimension of the first undercoat plating layer in the lamination direction x is t and the dimension of the laminate 12 in the lamination direction x is T, the condition T−5 μm≦t≦T+2 μm is satisfied. This makes it possible to reduce the area where the external electrodes partially protrude in the lamination direction, thereby reducing the probability of cracks occurring in the multilayer ceramic capacitor when mounted.

[0008] According to the present invention, a multilayer ceramic capacitor is provided that can suppress the occurrence of cracks during mounting using a mounting machine or the like.

[0009] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0010] 8A(a) is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 8A(b) is a front view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 8A(c) is a side view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 8A(d) is a schematic cross-sectional view taken along line IV-IV in FIG. 1. FIG. 8A(c) is a schematic cross-sectional view taken along line V-V in FIG. 1. FIG. 8A(c) is a schematic cross-sectional view taken along line VI-VI in FIG. 1. FIG. 8A(d) is a schematic cross-sectional view taken along line VIIIa-VIIIa in FIG. 8A(a). FIG. 8A(b) is an enlarged view of part A in FIG. 8A(b), illustrating a schematic view of the structure of the base plating layer. FIG. 8A(c) is a schematic cross-sectional view taken along line IXA-IXA in FIG. 2. FIG. 8A(d) is a schematic cross-sectional view taken along line IXB-IXB in FIG. 2. FIG. 8A(c) is an exploded perspective view of the laminate shown in FIG. 1. 11A is an external perspective view, from one side, illustrating an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 11B is an external perspective view, from the other side, illustrating an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. 11C is a front view illustrating an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. 11D is a schematic cross-sectional view taken along line XIII-XIII in FIG. 13. 11E is a schematic cross-sectional view taken along line XIV-XIV in FIG. 13. 11F is a schematic cross-sectional view taken along line XV-XV in FIG. 13. 11G is a schematic cross-sectional view taken along line XVI-XVII in FIG. 13. 11H is a schematic cross-sectional view taken along line XVIIA-XVIIA in FIG. 12. 11I is a schematic cross-sectional view taken along line XVIIB-XVIIB in FIG. 12. 11I is an exploded perspective view of the laminate shown in FIG. 11A. 11F is an external perspective view illustrating an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. 11G is a front view illustrating an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. 11H is a schematic cross-sectional view taken along line XXI-XXI in FIG. 19. 11H is a schematic cross-sectional view taken along line XXII-XXII in FIG. 19. 20 is a schematic cross-sectional view taken along line XXIII-XXIII in Fig. 19. FIG. 21 is a schematic cross-sectional view taken along line XXIV-XXIV in Fig. 19.25 is a perspective view showing an example of a multilayer ceramic capacitor according to a fourth embodiment of the present invention. 26 is a schematic cross-sectional view taken along line XXVI-XXVII in Fig. 25. 27 is a schematic cross-sectional view taken along line XXVII-XXVII in Fig. 25. 28 is a schematic cross-sectional view taken along line XXVIII-XXVIII in Fig. 19.

[0011] A. First Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0012] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1. FIG. 8A(a) is an external perspective view showing a state in which a base plating layer is disposed on a laminate, and FIG. 8A(b) is a cross-sectional view taken along line VIIIa-VIIIa in FIG. 8A(a). FIG. 8B is an enlarged view of portion A in FIG. 8A(b), which is an explanatory diagram schematically illustrating the structure of the base plating layer. FIG. 8C is an explanatory diagram schematically illustrating a modified example of the structure of the base plating layer and the thin film layer. Fig. 9A is a schematic cross-sectional view taken along line IXA-IXA in Fig. 2. Fig. 9B is a schematic cross-sectional view taken along line IXB-IXB in Fig. 2. Fig. 10 is an exploded perspective view of the laminate shown in Fig. 1.

[0013] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30 .

[0014] (Laminate) The laminate 12 has a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the stacking direction x.

[0015] Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. Note that the corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on part or all of the third face 12c, the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0016] In addition, either the first surface 12a or the second surface 12b may have a roughened surface.

[0017] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 include a first internal electrode 16a and a second internal electrode 16b.

[0018] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first surface 12a side, and a second outer layer portion 20b located on the second surface 12b side.

[0019] The first outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0020] The second outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0021] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0022] The thickness of the first outer layer portion 20a in the stacking direction x is 1.0 μm or more and 4.0 μm or less, and the thickness of the second outer layer portion 20b in the stacking direction x is 1.0 μm or more and 4.0 μm or less.

[0023] The inner layer portion 18 has a first inner electrode 16a having one end exposed to the third surface 12c and the other end exposed to the fourth surface 12d, a second inner electrode 16b having one end exposed to the third surface 12c and the other end exposed to the fourth surface 12d, and an inner layer dielectric layer 14a.

[0024] The dielectric layer 14 can be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics primarily composed of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these primary components. The inner dielectric layer 14a and the outer dielectric layer 14b are preferably made of the same dielectric material. The inner layer 18 and the outer layer 20a, 20b may be made of different dielectric materials to separate their functions. At least one of Si, Mg, Ba, Mn, and Sn may also be added as an additive.

[0025] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it less likely for dielectric breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited thereto, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable for the layer 14a to be made of a material with a high dielectric constant, such as BaTiO3. It is preferable that the outer dielectric layer 14b be made of the same type of component as the inner dielectric layer 14a.

[0026] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0027] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0028] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 3 to 300, including the first outer layer portion 20 a and the second outer layer portion 20 b. The thickness of the dielectric layer 14 is preferably, for example, 0.4 μm to 2.0 μm.

[0029] When the direction in which the third surface 12c and the fourth surface 12d face each other is defined as a first direction y and the direction in which the fifth surface 12e and the sixth surface 12f face each other is defined as a second direction z, the dimension L of the laminate 12 in the first direction y and the dimension W of the laminate 12 in the second direction z satisfy the condition 0.85≦L / W≦1.00. In other words, the laminate 12 has a substantially tetragonal shape.

[0030] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0031] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0032] The first internal electrode 16a is extended to the third surface 12c of the laminate 12 by a first extension electrode portion 24a, and is extended to the fourth surface 12d of the laminate 12 by a second extension electrode portion 24b. The first extension electrode portion 24a is extended to the fifth surface 12e of the laminate 12, and the second extension electrode portion 24b is extended to the sixth surface 12f of the laminate 12.

[0033] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in a direction connecting the first surface 12a and the second surface 12b.

[0034] The second internal electrode 16b is extended to the third surface 12c of the laminate 12 by a third extension electrode portion 24c, and is extended to the fourth surface 12d of the laminate 12 by a fourth extension electrode portion 24d. The third extension electrode portion 24c is extended to the sixth surface 12f of the laminate 12, and the fourth extension electrode portion 24d is extended to the fifth surface 12e of the laminate 12.

[0035] The first internal electrode 16 a and the second internal electrode 16 b are not exposed on the fifth surface 12 e and the sixth surface 12 f of the laminate 12 .

[0036] Furthermore, when the multilayer ceramic capacitor 10 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0037] As shown in FIG. 7 , the laminate 12 also includes a side portion (W gap) 26 a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22 b of the second internal electrode 16 b and the third surface 12 c, and a side portion (W gap) 26 b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22 a of the first internal electrode 16 a and the fourth surface 12 d.

[0038] Furthermore, as shown in FIG. 6 , the laminate 12 includes an end portion (L gap) 27 a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22 b of the second internal electrode 16 b and the fifth surface 12 e, and a side portion (L gap) 27 b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22 a of the first internal electrode 16 a and the sixth surface 12 f.

[0039] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0040] In addition, by including a Sn layer between the first internal electrode 16a and the second internal electrode 16b and the inner dielectric layer 14a, electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability.

[0041] The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 3 to 300. The thickness of the first internal electrodes 16a and the second internal electrodes 16b is not particularly limited, but is preferably 0.2 μm to 2.0 μm, for example.

[0042] The laminate 12 of the multilayer ceramic capacitor 10 may have the following configuration.

[0043] In the multilayer ceramic capacitor 10, the third surface 12c to the sixth surface 12f of the laminate 12 may be curved so as to form a concave shape toward the center of the laminate 12 when viewed in the stacking direction x. In other words, the third surface 12c to the sixth surface 12f of the laminate 12 may have a warped shape. In this case, it is preferable that the center of the curvature or warpage is near the center of the third surface 12c to the sixth surface 12f. This allows the distance between adjacent external electrodes 30, which will be described later, to be increased, thereby reducing the risk of electrical conduction between the external electrodes 30.

[0044] Furthermore, it is preferable that the laminate 12 has rounded regions where the first surface 12a intersects with the third surface 12c to the sixth surface 12f.

[0045] (External Electrodes) In the multilayer ceramic capacitor 10 according to the first embodiment, the external electrodes 30 are arranged so as to cover the first surface 12a of the laminate 12 but not the second surface 12b.

[0046] 1 to 7, external electrodes 30 are arranged on the laminate 12. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0047] The first external electrode 30a is disposed on the third surface 12c so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0048] The second external electrode 30b is disposed on the fourth surface 12d so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0049] The third external electrode 30c is disposed on the third surface 12c so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first surface 12a. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0050] The fourth external electrode 30d is disposed on the fourth surface 12d so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a portion of the first surface 12a. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0051] Furthermore, as shown in FIG. 1, it is preferable that the external electrode 30 arranged on the fifth surface 12e or the sixth surface 12f from which the internal electrode 16 is not drawn out covers one end side of the side surface from which the internal electrode 16 is not drawn out and a portion from the end of the short side to the middle of the long side.

[0052] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode 16a is connected and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode 16b is connected, thereby realizing the characteristics of a capacitor.

[0053] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d each have an undercoat plating layer 32, a thin film layer 34, and a top plating layer 36.

[0054] In other words, the first external electrode 30a has a first undercoat plating layer 32a, a first thin film layer 34a, and a first top plating layer 36a. The second external electrode 30b has a second undercoat plating layer 32b, a second thin film layer 34b, and a second top plating layer 36b. The third external electrode 30c has a third undercoat plating layer 32c, a third thin film layer 34c, and a third top plating layer 36c. The fourth external electrode 30d has a fourth undercoat plating layer 32d, a fourth thin film layer 34d, and a fourth top plating layer 36d.

[0055] (Plating Base Layer) The plating base layer 32 is disposed on the third surface 12c and the fourth surface 12d. The specific configuration of the plating base layer 32 will be described below.

[0056] The first undercoat plating layer 32a is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the first extraction electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c of the laminate 12.

[0057] The second undercoat plating layer 32b is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the second extraction electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d of the laminate 12.

[0058] The third undercoat plating layer 32c is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the third extraction electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c of the laminate 12.

[0059] The fourth undercoat plating layer 32d is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the fourth extraction electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d of the laminate 12.

[0060] The first undercoat plating layer 32a of the first external electrode 30a is preferably disposed on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12. The upper end of the first undercoat plating layer 32a of the first external electrode 30a may be disposed on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12 so as to overlap the underside of the first thin film layer 34a, or may be disposed separately.

[0061] The second underplating layer 32b of the second external electrode 30b is preferably disposed on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12. The upper end of the second underplating layer 32b of the second external electrode 30b may be disposed on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12 so as to overlap the underside of the second thin film layer 34b, or may be disposed separately.

[0062] The third plating underlayer 32c of the third external electrode 30c is preferably disposed on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12. The upper end of the third plating underlayer 32c of the third external electrode 30c may be disposed on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12 so as to overlap the underside of the third thin film layer 34c, or may be disposed separately.

[0063] The fourth underplating layer 32d of the fourth external electrode 30d is preferably disposed on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12. The upper end of the fourth underplating layer 32d of the fourth external electrode 30d may be disposed on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12 so as to overlap the underside of the fourth thin film layer 34d, or may be disposed separately.

[0064] Here, the structure of the first underplating layer 32a of the first external electrode 30a will be described in detail with reference to FIG. 8B . As shown in FIG. 8B , when the dimension of the first underplating layer 32a in the stacking direction x is t1 and the dimension of the laminate 12 in the stacking direction x is t2, the condition t2 - 5 μm ≦ t1 ≦ t2 + 2 μm is satisfied. Furthermore, the first underplating layer 32a is preferably located 5 μm or less from the point where the laminate 12 has the greatest dimension in the stacking direction x. This minimizes the area where the external electrode 30 partially protrudes in the stacking direction x, thereby reducing the probability of cracks occurring in the multilayer ceramic capacitor 10 during mounting. Preferably, the first underplating layer 32a is located further inward in the stacking direction x than the point where the laminate 12 has the greatest dimension in the stacking direction x. This allows the substantially flat portion to be suctioned with a nozzle during mounting, thereby reducing the likelihood of cracks in the multilayer ceramic capacitor caused by the external electrode 30.

[0065] Furthermore, as shown in FIG. 8B , when a first point P1 where the first underplating layer 32 a and the laminate 12 intersect is taken as a reference point, a second point P2 is taken as the intersection point between the laminate 12 and a line parallel to the stacking direction x that passes through a position 3 μm inward from the first point P1 and the laminate 12, and a third point P3 is taken as the intersection point between the first underplating layer 32 a and a line parallel to the stacking direction x that passes through a position 1 μm outward from the first point P1 and the laminate 12, the angle θ formed by a first straight line x1 connecting the first point P1 and the second point P2 and a second straight line x2 connecting the first point P1 and the third point P3 is preferably 88° or more and 160° or less. The structure of the first underplating layer 32a included in the first external electrode 30a described above is also included in the second underplating layer 32b included in the second external electrode 30b, the third underplating layer 32c included in the third external electrode 30c, and the fourth underplating layer 32d constituting the fourth external electrode 30d. This makes it possible to reduce the amount of solder that wets up from the first surface 12a to the third surface 12c to the sixth surface 12f, and to avoid an increase in mounting height due to suppression of excessive solder wetting up to the second surface 12b.

[0066] The base plating layer 32 contains, for example, Cu as a main metal component. For example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable to use Cu plating as the base plating layer 32, which has good bonding properties with Ni.

[0067] The undercoat plating layer 32 is formed by plating growing from the internal electrode 16 .

[0068] The thickness of each of the undercoat plating layers 32 is preferably 0.5 μm or more and 10.0 μm or less.

[0069] (Thin Film Layer) The thin film layer 34 covers the first surface 12a. Preferably, the thin film layer 34 also covers the underplating layer 32. This makes it possible to suppress the infiltration of moisture from the underplating layer 32. The thin film layer 34 includes a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0070] The first thin film layer 34a is disposed so as to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the fifth surface 12e side, and not cover the second surface 12b, the third surface 12c, and the fifth surface 12e of the laminate 12. The first thin film layer 34a may be disposed separate from the first undercoat plating layer 32a, or may be disposed overlapping the first undercoat plating layer 32a. The surface of the first top plating layer 36a, which will be described later, may be shaped to have a recess.

[0071] The second thin film layer 34b is disposed so as to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side, but not cover the second surface 12b, the fourth surface 12d, and the sixth surface 12f of the laminate 12. The second thin film layer 34b may be disposed separate from the second undercoat plating layer 32b, or may be disposed so as to overlap the second undercoat plating layer 32b. The surface of the second top plating layer 36b, which will be described later, may be shaped to have a recessed portion.

[0072] The third thin film layer 34c is disposed so as to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the sixth surface 12f side, and not to cover the second surface 12b, the third surface 12c, and the sixth surface 12f of the laminate 12. The third thin film layer 34c may be disposed separate from the third undercoat plating layer 32c, or may be disposed so as to overlap the third undercoat plating layer 32c. The surface of the third top plating layer 36c, which will be described later, may be shaped to have a recess.

[0073] The fourth thin film layer 34d is disposed so as to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side, and not cover the second surface 12b, the fourth surface 12d, and the fifth surface 12e of the laminate 12. The fourth thin film layer 34d may be disposed separate from the fourth undercoat plating layer 32d, or may be disposed so as to overlap the fourth undercoat plating layer 32d. The surface of a fourth top plating layer 36d, which will be described later, may be shaped to have a recess.

[0074] 8C, the first thin film layer 34a may cover the first undercoat plating layer 32a without completely covering the end of the first undercoat plating layer 32a. In other words, it is preferable to have a region Sp surrounded by the laminate 12, the undercoat plating layer 32, and the thin film layer. This allows this region Sp to absorb impacts during mounting, etc. Furthermore, the structure of the first thin film layer 34a described above can also be applied to the second through fourth thin film layers 34b through 34d.

[0075] Each of the first to fourth thin film layers 34 a to 34 d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 34 a to 34 d in the direction connecting the first surface 12 a and the second surface 12 b of the laminate 12 to be 1 μm or less, which allows the dimension of the multilayer ceramic capacitor 10 in the stacking direction x to be sufficiently small, thereby allowing the multilayer ceramic capacitor 10 to be made low-profile.

[0076] The dimensions of the first to fourth thin film layers 34a to 34d in the stacking direction x can be measured as follows. That is, when the thin film layers are formed by depositing metal particles, a fluorescent X-ray device can be used to convert the concentration of a predetermined element into a thickness using a calibration curve method for the corresponding metal species. Alternatively, a cross section of the component can be observed using an FIB with a scanning microscope, and the thickness can be measured from the actual observation image.

[0077] Furthermore, when the first to fourth thin film layers 34a to 34d are formed by a thin film forming method, these thin film layers are preferably made of a metal such as Cu or Ni.

[0078] The first to fourth thin film layers 34a to 34d can be configured taking into consideration their respective functions. For example, it is preferable that the main component be NiCr or NiCu in consideration of adhesion to the laminate 12. The first to fourth thin film layers 34a to 34d may be multiple layers or may have a two-layer structure of NiCr and NiCu.

[0079] The thin film layer 34 may be formed by screen printing or the like and contain a dielectric material and a metal component. This allows the thin film layer 34 to adhere to the ceramic of the laminate 12, further improving the adhesion between the laminate 12 and the external electrode 30. In this case, the thin film layer 34 may contain a ceramic component having the same main component as the inner dielectric layer 14a in addition to the metal component. The inclusion of a ceramic component in the thin film layer 34 reduces the difference in thermal expansion coefficient between the laminate 12 and the thin film layer 34, thereby alleviating stress on the thin film layer 34. However, the metal component may be other metal components besides Cu and Ni, or a glass component may be included in addition to the ceramic component. Examples of the glass component include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metal components may include Mg, Cr, Sr, Al, Na, Fe, etc. The thin film layer 34 may also have a discontinuous shape. The term "discontinuous" means that the film is formed discontinuously when viewed in a direction perpendicular to the longitudinal direction.

[0080] For example, when the thin film layer 34 is formed using a material containing ceramic, one method is to polish the cross section, then take a cross section photograph using a digital microscope (Keyence Corporation: VHX-5000), and use the cross section photograph to calculate the thickness, etc. Another method is to measure the thickness, etc. from the actual observation image of the cross section of the part taken by FIB using a scanning microscope.

[0081] (Surface Plated Layer) The surface plated layer 36 includes a first surface plated layer 36a, a second surface plated layer 36b, a third surface plated layer 36c, and a fourth surface plated layer 36d.

[0082] The first surface plating layer 36a is arranged to cover the first thin film layer 34a and the first undercoat plating layer 32a arranged on the third surface 12c of the laminate 12. The second surface plating layer 36b is arranged to cover the second thin film layer 34b and the second undercoat plating layer 32b arranged on the fourth surface 12d of the laminate 12. The third surface plating layer 36c is arranged to cover the third thin film layer 34c and the third undercoat plating layer 32c arranged on the third surface 12c of the laminate 12. The fourth surface plating layer 36d is arranged to cover the fourth thin film layer 34d and the fourth undercoat plating layer 32d arranged on the fourth surface 12d of the laminate 12.

[0083] The surface plating layer 36 preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0084] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0085] The thickness of the surface plating layer 36 is preferably, for example, 0.5 μm or more and 10 μm or less.

[0086] The metal content per unit volume of the surface plating layer is preferably 99% by volume or more.

[0087] The thickness of each surface plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0088] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm or more and 3.2 mm or less, the T dimension in the stacking direction x is 0.04 mm or more and 0.22 mm or less, and the W dimension in the second direction z is 0.2 mm or more and 3.2 mm or less. The dimensions of the multilayer ceramic capacitor 10 preferably satisfy the relationship 0.85≦L / W≦1.00. This allows the laminate 12 to have a substantially tetragonal shape, thereby improving the flexibility of mounting.

[0089] According to the multilayer ceramic capacitor 10 shown in FIG. 1 , by satisfying the condition 0.85≦L / W≦1.00, the laminate 12 has a substantially tetragonal shape, and when the dimension of the first undercoat plating layer 32 a in the stacking direction x is t1 and the dimension of the laminate 12 in the stacking direction x is t2, the condition t2−5 μm≦t1≦t2+2 μm is satisfied. This makes it possible to reduce the area where the external electrodes 30 partially protrude in the stacking direction x, thereby reducing the probability of cracks occurring in the multilayer ceramic capacitor 10 when mounted.

[0090] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to the first embodiment will now be described.

[0091] First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0092] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0093] Furthermore, for example, when forming a printing pattern of an internal electrode by gravure printing, the design of the gravure plate used in the gravure printing is set to the graphic pattern of the first internal electrode, and by changing the structure to correspond to the graphic pattern of the second internal electrode, it is possible to form each of the desired internal electrodes.

[0094] Furthermore, when forming a printing pattern of the internal electrode layer by screen printing, the desired internal electrode can be formed by designing the screen printing mask to the graphic pattern of the first internal electrode and changing the structure to correspond to the graphic pattern of the second internal electrode.

[0095] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0096] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0097] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0098] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0099] At this time, the first lead electrode portion 24a of the first internal electrode 16a and the third lead electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. Furthermore, the second lead electrode portion 24b of the first internal electrode 16a and the fourth lead electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0100] Subsequently, the external electrodes 30 are formed on the laminate 12 .

[0101] First, a base plating layer 32 is formed to cover the internal electrodes 16 exposed on the surface of the laminate 12. The base plating layer 32 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 12 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the base plating layer 32. Furthermore, when forming the base plating layer 32, the angle θ is adjusted by adjusting the amount of rounding of the laminate 12 or the metal ion concentration in the base plating layer 32 to achieve the structure of the present invention.

[0102] Next, the laminate 12 on which the undercoat plating layer 32 has been formed is aligned on a work table, and the thin film layer 34 is formed on the first surface 12a by sputtering. After the thin film layer 34 is formed, a heat treatment is performed at a temperature in the range of 300°C to 600°C, thereby forming the region Sp shown in FIG. 8C .

[0103] Thereafter, a top plating layer 36 is formed on the thin film layer 34 and in the external plating region 40 disposed on the surface of the laminate 12. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 34 as the top plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0104] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 can be manufactured.

[0105] B. Second Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will now be described.

[0106] FIG. 11A is an external perspective view from one side showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 11B is an external perspective view from the other side showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 12 is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 13. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 13. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 13. FIG. 17A is a cross-sectional view taken along line XVIIA-XVIIA in FIG. 12. FIG. 17B is a cross-sectional view taken along line XVIIB-XVIIB in FIG. 12. FIG. 18 is an exploded perspective view of the laminate shown in FIG. 11A. 1 to 7 are given the same reference numerals and detailed description thereof will be omitted.

[0107] The multilayer ceramic capacitor 110 includes a laminate 112 and external electrodes 130 .

[0108] (Laminate) The laminate 12 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layers 114 include an inner dielectric layer 114a and an outer dielectric layer 114b. The internal electrodes 116 include a first internal electrode 116a and a second internal electrode 116b.

[0109] The laminate 112 also has an inner layer portion 118, a first outer layer portion 120a located on the first surface 112a side, and a second outer layer portion 120b located on the second surface 112b side.

[0110] The first outer layer portion 120a is located on the first surface 112a side of the laminate 112 and is an aggregate of multiple outer layer dielectric layers 114b located between the first surface 112a and the internal electrode 116 closest to the first surface 112a.

[0111] The second outer layer portion 120b is located on the second surface 112b side of the laminate 112 and is an aggregate of multiple outer layer dielectric layers 114b located between the second surface 112b and the internal electrode 116 closest to the second surface 112b.

[0112] The region sandwiched between the first outer layer portion 120a and the second outer layer portion 120b is the inner layer portion 118.

[0113] The inner layer portion 118 has a first inner electrode 116a having one end exposed to the third surface 112c and the fifth surface 112e and the other end exposed to the fourth surface 112d and the sixth surface 112f, a second inner electrode 116b having one end exposed to the third surface 112c and the sixth surface 112f and the other end exposed to the fourth surface 112d and the fifth surface 112e, and an inner layer dielectric layer 114a.

[0114] The material of the dielectric layer 114 is the same as that of the dielectric layer 14, and therefore a description thereof will be omitted.

[0115] (Internal Electrode) The internal electrode 116 includes a plurality of first internal electrodes 116a and a plurality of second internal electrodes 116b. The first internal electrodes 116a and the second internal electrodes 116b are alternately stacked with the dielectric layer 114 interposed therebetween.

[0116] The first internal electrode 116a is disposed on the surface of the inner dielectric layer 114a. The first internal electrode 116a faces the first surface 112a and the second surface 112b, has a first opposing electrode portion 122a facing the second internal electrode 116b, and is laminated in the direction connecting the first surface 112a and the second surface 112b.

[0117] The first internal electrode 116a is extended by a first extension electrode portion 124a to the third surface 112c and the fifth surface 112e of the laminate 112, and is extended by a second extension electrode portion 124b to the fourth surface 112d and the sixth surface 112f of the laminate 112. The width of the first extension electrode portion 124a extended to the third surface 112c may be approximately equal to the width of the first extension electrode portion 124a extended to the fifth surface 112e, and the width of the second extension electrode portion 124b extended to the fourth surface 112d may be approximately equal to the width of the second extension electrode portion 124b extended to the sixth surface 112f.

[0118] Furthermore, the first internal electrode 116a is continuously extended to the third surface 112c and the fifth surface 112e of the laminate 112 by the first extension electrode portion 124a, and is continuously extended to the fourth surface 112d and the sixth surface 112f of the laminate 112 by the second extension electrode portion 124b, but this is not limited to this and the electrode may be extended discontinuously.

[0119] The second internal electrode 116b is disposed on a surface of the inner dielectric layer 114a different from the surface of the inner dielectric layer 114a on which the first internal electrode 116a is disposed. The second internal electrode 116b faces the first surface 112a and the second surface 112b, has a second opposing electrode portion 122b facing the first internal electrode 116a, and is laminated in a direction connecting the first surface 112a and the second surface 112b.

[0120] The second internal electrode 116b is extended by a third extension electrode portion 124c to the third surface 112c and the sixth surface 112f of the laminate 112, and is extended by a fourth extension electrode portion 124d to the fourth surface 112d and the fifth surface 112e of the laminate 112. The width of the third extension electrode portion 124c extended to the third surface 112c may be approximately equal to the width of the third extension electrode portion 124c extended to the sixth surface 112f, and the width of the fourth extension electrode portion 124d extended to the fourth surface 112d may be approximately equal to the width of the fourth extension electrode portion 124d extended to the fifth surface 112e.

[0121] Furthermore, the second internal electrode 116b is continuously extended to the third surface 112c and the sixth surface 112f of the laminate 112 by the third extension electrode portion 124c, and is continuously extended to the fourth surface 112d and the fifth surface 112e of the laminate 112 by the fourth extension electrode portion 124d, but this is not limited to this and the second internal electrode 116b may be extended discontinuously.

[0122] Furthermore, when the multilayer ceramic capacitor 110 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 124a and the second extraction electrode portion 124b of the first internal electrode 116a intersects with a straight line connecting the third extraction electrode portion 124c and the fourth extraction electrode portion 124d of the second internal electrode 116b.

[0123] As shown in FIG. 15 , the laminate 112 also includes a side portion (W gap) 126a of the laminate 112 located between one end in the first direction y of the second opposing electrode portion 122b of the second internal electrode 116b and the third surface 112c, and a side portion (W gap) 126b of the laminate 112 located between the other end in the first direction y of the first opposing electrode portion 122a of the first internal electrode 116a and the fourth surface 112d.

[0124] Furthermore, as shown in FIG. 16 , the laminate 112 includes an end portion (L gap) 127a of the laminate 112 located between one end in the second direction z of the second opposing electrode portion 122b of the second internal electrode 116b and the fifth surface 112e, and a side portion (L gap) 127b of the laminate 112 located between the other end in the second direction z of the first opposing electrode portion 122a of the first internal electrode 116a and the sixth surface 112f.

[0125] (External Electrodes) In the multilayer ceramic capacitor 110 according to the second embodiment, the external electrodes 130 are arranged so as to cover the first surface 112a of the laminate 112 but not the second surface 112b.

[0126] 11A to 16, external electrodes 130 are arranged on the laminate 112. The external electrodes 130 include a plurality of external electrodes 130 connected to the first internal electrodes 116a and the second internal electrodes 116b. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0127] The first external electrode 130a is disposed on the third surface 112c and the fifth surface 112e so as to cover the first lead electrode portion 124a of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a. The first external electrode 130a is electrically connected to the first lead electrode portion 124a of the first internal electrode 116a.

[0128] The second external electrode 130b is disposed on the fourth surface 112d and the sixth surface 112f so as to cover the second lead electrode portion 124b of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a. The second external electrode 130b is electrically connected to the second lead electrode portion 124b of the first internal electrode 116a.

[0129] The third external electrode 130c is disposed on the third surface 112c and the sixth surface 112f so as to cover the third lead electrode portion 124c of the second internal electrode 116b, and further so as to cover a portion of the first surface 112a. The third external electrode 130c is electrically connected to the third lead electrode portion 124c of the second internal electrode 116b.

[0130] The fourth external electrode 130d is disposed on the fourth surface 112d and the fifth surface 112e so as to cover the fourth lead electrode portion 124d of the second internal electrode 116b, and further so as to cover a portion of the first surface 112a. The fourth external electrode 130d is electrically connected to the fourth lead electrode portion 124d of the second internal electrode 116b.

[0131] In the laminate 112, the first opposing electrode portion 122a of the first internal electrode 116a and the second opposing electrode portion 122b of the second internal electrode 116b face each other via the inner dielectric layer 114a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 130a and the second external electrode 130b to which the first internal electrode 116a is connected and the third external electrode 130c and the fourth external electrode 130d to which the second internal electrode 116b is connected, thereby realizing the characteristics of a capacitor.

[0132] The first external electrode 130 a , the second external electrode 130 b , the third external electrode 130 c , and the fourth external electrode 130 d each have an undercoat plating layer 132 , a thin film layer 134 , and a top plating layer 136 .

[0133] In other words, the first external electrode 130a has a first underplating layer 132a, a first thin film layer 134a, and a first top plating layer 136a. The second external electrode 130b has a second underplating layer 132b, a second thin film layer 134b, and a second top plating layer 136b. The third external electrode 130c has a third underplating layer 132c, a third thin film layer 134c, and a third top plating layer 136c. The fourth external electrode 130d has a fourth underplating layer 132d, a fourth thin film layer 134d, and a fourth top plating layer 136d.

[0134] (Plating Base Layer) The plating base layer 132 is disposed on the third surface 112c to the sixth surface 112f. The specific configuration of the plating base layer 132 will be described below.

[0135] The first undercoat plating layer 132a is arranged on the surfaces of the third surface 112c and the fifth surface 112e of the laminate 112 so as to cover the first extraction electrode portion 124a of the first internal electrode 116a exposed from the third surface 112c and the fifth surface 112e of the laminate 112.

[0136] The second undercoat plating layer 132b is arranged on the surfaces of the fourth surface 112d and the sixth surface 112f of the laminate 112 so as to cover the second extraction electrode portion 124b of the first internal electrode 116a exposed from the fourth surface 112d and the sixth surface 112f of the laminate 112.

[0137] The third undercoat plating layer 132c is arranged on the surfaces of the third surface 112c and the sixth surface 112f of the laminate 112 so as to cover the third extraction electrode portion 124c of the second internal electrode 116b exposed from the third surface 112c and the sixth surface 112f of the laminate 112.

[0138] The fourth undercoat plating layer 132d is arranged on the surfaces of the fourth surface 112d and the fifth surface 112e of the laminate 112 so as to cover the fourth extraction electrode portion 124d of the second internal electrode 116b exposed from the fourth surface 112d and the fifth surface 112e of the laminate 112.

[0139] The first underplating layer 132a of the first external electrode 130a is preferably disposed on the ridge formed by the first surface 112a, the third surface 112c, and the fifth surface 112e of the laminate 112. The upper end of the first underplating layer 132a of the first external electrode 130a may be disposed so as to overlap or be separated from the underside of the first thin film layer 134a on the ridge formed by the first surface 112a, the third surface 112c, and the fifth surface 112e of the laminate 112. In this case, the first underplating layer 132a may be disposed so as to cover the ridge formed by the third surface 112c and the fifth surface 112e.

[0140] The second underplating layer 132b of the second external electrode 130b is preferably disposed on the ridge formed by the first surface 112a, the fourth surface 112d, and the sixth surface 112f of the laminate 112. The upper end of the second underplating layer 132b of the second external electrode 130b may be disposed so as to overlap or be separated from the lower side of the second thin film layer 134b on the ridge formed by the first surface 112a, the fourth surface 112d, and the sixth surface 112f of the laminate 112. In this case, the second underplating layer 132b may be disposed so as to cover the ridge formed by the fourth surface 112d and the sixth surface 112f.

[0141] The third underplating layer 132c of the third external electrode 130c is preferably disposed on the ridge formed by the first surface 112a, the third surface 112c, and the sixth surface 112f of the laminate 112. The upper end of the third underplating layer 132c of the third external electrode 130c may be disposed so as to overlap or be separated from the lower side of the third thin film layer 134c on the ridge formed by the first surface 112a, the third surface 112c, and the sixth surface 112f of the laminate 112. In this case, the third underplating layer 132c may be disposed so as to cover the ridge formed by the third surface 112c and the sixth surface 112f.

[0142] The fourth underplating layer 132d of the fourth external electrode 130d is preferably disposed on the ridge formed by the first surface 112a, the fourth surface 112d, and the fifth surface 112e of the laminate 112. The upper end of the fourth underplating layer 132d of the fourth external electrode 130d may be disposed so as to overlap or be separated from the lower side of the fourth thin film layer 134d on the ridge formed by the first surface 112a, the fourth surface 112d, and the fifth surface 112e of the laminate 112. In this case, the fourth underplating layer 132d may be disposed so as to cover the ridge formed by the fourth surface 112d and the fifth surface 112e.

[0143] Here, similarly to the first underplating layer 32a of the multilayer ceramic capacitor 10, the first underplating layer 132a of the multilayer ceramic capacitor 110 also satisfies the condition t2 - 5 μm ≦ t1 ≦ t2 + 2 μm, where t1 is the dimension of the first underplating layer 132a in the stacking direction x and t2 is the dimension of the laminate 112 in the stacking direction x. Furthermore, the first underplating layer 132a is preferably located at a distance of 5 μm or less, since this is the largest dimension of the laminate 112 in the stacking direction x.

[0144] Furthermore, with regard to the first underlayer plating layer 132 a of the multilayer ceramic capacitor 110, similarly to the first underlayer plating layer 32 a of the multilayer ceramic capacitor 10, when a first point where the first underlayer plating layer 132 a and the laminate 112 intersect is taken as a reference point, a second point is taken as an intersection point between the laminate 112 and a line parallel to the stacking direction x that passes through a position 3 μm inward from the first point and the laminate 112, and a third point is taken as an intersection point between the first underlayer plating layer 132 a and a line parallel to the stacking direction x that passes through a position 1 μm outward from the first point and the laminate 112, the angle θ formed by a first straight line x1 connecting the first point and the second point and a second straight line x2 connecting the first point and the third point is preferably 88° or more and 160° or less. The structure of the first base plating layer 132a included in the first external electrode 130a described above is also possessed by the second base plating layer 132b included in the second external electrode 130b, the base plating layer 132c included in the third external electrode 130c, and the base plating layer 132d constituting the fourth external electrode 130d.

[0145] (Thin Film Layer) The thin film layer 134 covers the first surface 112a. Preferably, the thin film layer 134 also covers the underplating layer 132. This makes it possible to suppress the intrusion of moisture from the underplating layer 132. The thin film layer 134 includes a first thin film layer 134a, a second thin film layer 134b, a third thin film layer 134c, and a fourth thin film layer 134d.

[0146] The first thin film layer 134a is arranged so as to cover a portion of the first surface 112a of the laminate 112 on the third surface 112c side and the fifth surface 112e side, and not cover the second surface 112b, the third surface 112c, and the fifth surface 112e of the laminate 112. The first thin film layer 134a may be arranged separated from the first undercoat plating layer 132a, or may be arranged so as to overlap the first undercoat plating layer 132a. The surface of the first top plating layer 136a, which will be described later, may be shaped to have a recess.

[0147] The second thin film layer 134b is disposed so as to cover a portion of the first surface 112a of the laminate 112 on the fourth surface 112d side and the sixth surface 112f side, but not cover the second surface 112b, the fourth surface 112d, and the sixth surface 112f of the laminate 112. The second thin film layer 134b may be disposed separate from the second underplating layer 132b, or may be disposed overlapping the second underplating layer 132b. The surface of the second top plating layer 136b, which will be described later, may be shaped to have a recess.

[0148] The third thin film layer 134c is arranged to cover a portion of the first surface 112a of the laminate 112 on the third surface 112c side and the sixth surface 112f side, and not to cover the second surface 112b, the third surface 112c, and the sixth surface 112f of the laminate 112. The third thin film layer 134c may be arranged separate from the third underplating layer 132c, or may be arranged overlapping the third underplating layer 132c. The surface of the third top plating layer 136c, which will be described later, may be shaped to have a recess.

[0149] The fourth thin film layer 134d is disposed so as to cover a portion of the first surface 112a of the laminate 112 on the fourth surface 112d side and the fifth surface 112e side, and not cover the second surface 112b, the fourth surface 112d, and the fifth surface 112e of the laminate 112. The fourth thin film layer 134d may be disposed separate from the fourth underplating layer 132d, or may be disposed overlapping the fourth underplating layer 132d. The surface of the fourth top plating layer 136d, which will be described later, may be shaped to have a recess.

[0150] Each of the first to fourth thin film layers 134 a to 134 d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 134 a to 134 d in the direction connecting the first surface 12 a and the second surface 12 b of the laminate 12 to be 1 μm or less, and the dimension of the multilayer ceramic capacitor 110 in the stacking direction x can be sufficiently reduced, thereby making it possible to reduce the height of the multilayer ceramic capacitor 110.

[0151] (Surface Plated Layer) The surface plated layer 136 includes a first surface plated layer 136a, a second surface plated layer 136b, a third surface plated layer 136c, and a fourth surface plated layer 136d.

[0152] The first surface plating layer 136a is arranged to cover the first thin film layer 134a and the first underplating layer 132a arranged on the third surface 112c and fifth surface 112e of the laminate 112. The second surface plating layer 136b is arranged to cover the second thin film layer 134b and the second underplating layer 132b arranged on the fourth surface 112d and sixth surface 112f of the laminate 112. The third surface plating layer 136c is arranged to cover the third thin film layer 134c and the third underplating layer 132c arranged on the third surface 112c and sixth surface 112f of the laminate 112. The fourth surface plating layer 136d is arranged to cover the fourth thin film layer 134d and the fourth underplating layer 132d arranged on the fourth surface 112d and fifth surface 112e of the laminate 112.

[0153] The surface plating layer 136 preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0154] The surface plating layer 136 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0155] The multilayer ceramic capacitor 110 shown in FIG. 11A has the same effects as the multilayer ceramic capacitor 10 according to the first embodiment.

[0156] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to a second embodiment will now be described.

[0157] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0158] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0159] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 120a on the first surface 112a side. After that, the portion that will become the internal layer portion 118 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the internal layer portion 118 to form the portion that will become the second outer layer portion 120b on the second surface 112b side. In this way, a laminated sheet is produced.

[0160] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0161] Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0162] Next, the laminated chip is fired to produce the laminate 112. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0163] At this time, the first lead electrode portion 124a of the first internal electrode 116a and the third lead electrode portion 124c of the second internal electrode 116b are exposed from the third surface 112c of the laminate 112. Furthermore, the second lead electrode portion 124b of the first internal electrode 116a and the fourth lead electrode portion 124d of the second internal electrode 116b are exposed from the fourth surface 112d of the laminate 112. Furthermore, the first lead electrode portion 124a of the first internal electrode 116a and the fourth lead electrode portion 124d of the second internal electrode 116b are exposed from the fifth surface 112e of the laminate 112. Furthermore, the second lead electrode portion 124b of the first internal electrode 116a and the third lead electrode portion 124c of the second internal electrode 116b are exposed from the sixth surface 112f of the laminate 112.

[0164] Subsequently, the external electrodes 130 are formed on the laminate 112 .

[0165] First, a base plating layer 132 is formed to cover the internal electrodes 116 exposed on the surface of the laminate 112. The base plating layer 132 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 112 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 112 and the base plating layer 132. Furthermore, when forming the base plating layer 132, the angle θ is adjusted by adjusting the amount of rounding of the laminate 112 or the metal ion concentration in the base plating layer 132 to achieve the structure of the present invention.

[0166] Next, the laminate 112 on which the undercoat plating layer 132 has been formed is aligned on a work table, and a thin film layer 134 is formed on the first surface 112a and the second surface 112b by sputtering.

[0167] Thereafter, a top plating layer 136 is formed on the thin film layer 134 and the surface of the laminate 112. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 134 as the top plating layer 136. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0168] At this time, the external electrode 130 placed on the side where the internal electrode 116 is not pulled out is formed in a U-shape by the surface plating layer 136 so as to cover both short sides of the side where the internal electrode 116 is not pulled out and the portions from the ends of both short sides to the middle parts of both long sides.

[0169] In this manner, a multilayer ceramic capacitor 110 as shown in FIG. 11A is manufactured.

[0170] C. Third Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 210 according to a third embodiment of the present invention will now be described.

[0171] FIG. 19 is an external perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. FIG. 20 is a front view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 19. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 19. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 19. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 19. Note that the same reference numerals are used for components that are the same as or correspond to those in FIGS. 1 to 7, and detailed descriptions thereof will be omitted.

[0172] The multilayer ceramic capacitor 210 includes a laminate 12 and a plurality of external electrodes 230 .

[0173] (Laminate) In the multilayer ceramic capacitor 210 according to the third embodiment, the laminate 12 has the same configuration as the laminate 12 according to the first embodiment of the present invention shown in FIG.

[0174] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0175] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0176] The first internal electrode 16a is extended to the third surface 12c of the laminate 12 by a first extension electrode portion 24a, and is extended to the fourth surface 12d of the laminate 12 by a second extension electrode portion 24b. The first extension electrode portion 24a is extended to the fifth surface 12e of the laminate 12, and the second extension electrode portion 24b is extended to the sixth surface 12f of the laminate 12.

[0177] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in a direction connecting the first surface 12a and the second surface 12b.

[0178] The second internal electrode 16b is extended to the third surface 12c of the laminate 12 by a third extension electrode portion 24c, and is extended to the fourth surface 12d of the laminate 12 by a fourth extension electrode portion 24d. The third extension electrode portion 24c is extended to the sixth surface 12f of the laminate 12, and the fourth extension electrode portion 24d is extended to the fifth surface 12e of the laminate 12.

[0179] The first internal electrode 16 a and the second internal electrode 16 b are not exposed on the fifth surface 12 e and the sixth surface 12 f of the laminate 12 .

[0180] Furthermore, when the multilayer ceramic capacitor 210 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0181] Furthermore, on the surfaces 12c, 12d, 12e, and 12f of the laminate 12, it is preferable that the first extraction electrode portion 24a of the first internal electrode 16a and the fourth extraction electrode portion 24d of the second internal electrode 16b are extracted to opposing positions, and that the second extraction electrode portion 24b of the first internal electrode 16a and the third extraction electrode portion 24c of the second internal electrode 16b are extracted to opposing positions.

[0182] As shown in FIG. 24 , the laminate 12 also includes a side portion (W gap) 26 a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22 b of the second internal electrode 16 b and the third surface 12 c, and a side portion (W gap) 26 b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22 a of the first internal electrode 16 a and the fourth surface 12 d.

[0183] Furthermore, as shown in FIG. 23 , the laminate 12 includes an end portion (L gap) 27 a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22 b of the second internal electrode 16 b and the fifth surface 12 e, and a side portion (L gap) 27 b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22 a of the first internal electrode 16 a and the sixth surface 12 f.

[0184] 19 to 24, external electrodes 230 are arranged on the laminate 12. The external electrodes 230 include a plurality of external electrodes 230 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 230 include a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, and a fourth external electrode 230d.

[0185] The first external electrode 230a is disposed on the third surface 12c so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a and a portion of the second surface 12b. The first external electrode 230a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0186] The second external electrode 230b is disposed on the fourth surface 12d so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The second external electrode 230b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0187] The third external electrode 230c is disposed on the third surface 12c so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The third external electrode 230c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0188] The fourth external electrode 230d is disposed on the fourth surface 12d so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The fourth external electrode 230d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0189] Furthermore, as shown in Figure 20, it is preferable that the external electrode 230 arranged on the fifth surface 12e or the sixth surface 12f from which the internal electrode 16 is not drawn out covers, in a U-shape, one of the short sides of the side surface from which the internal electrode 16 is not drawn out and the portion from the end of that short side to the middle of both long sides.

[0190] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 230a and the second external electrode 230b to which the first internal electrode 16a is connected, and the third external electrode 230c and the fourth external electrode 230d to which the second internal electrode 16b is connected, thereby realizing the characteristics of a capacitor.

[0191] Each of the first external electrode 230a, the second external electrode 230b, the third external electrode 230c, and the fourth external electrode 230d preferably has an undercoat plating layer 32, a thin film layer 34, and a top plating layer 36.

[0192] In other words, the first external electrode 230a has a first underplating layer 32a, a first thin film layer 34a, and a first top plating layer 36a. The second external electrode 230b has a second underplating layer 32b, a second thin film layer 34b, and a second top plating layer 36b. The third external electrode 230c has a third underplating layer 32c, a third thin film layer 34c, and a third top plating layer 36c. The fourth external electrode 230d has a fourth underplating layer 32d, a fourth thin film layer 34d, and a fourth top plating layer 36d.

[0193] (Plating Base Layer) The plating base layer 32 is disposed on the third surface 12c and the fourth surface 12d. The specific configuration of the plating base layer 32 will be described below.

[0194] The first undercoat plating layer 32a is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the first extraction electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c of the laminate 12.

[0195] The second undercoat plating layer 32b is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the second extraction electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d of the laminate 12.

[0196] The third undercoat plating layer 32c is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the third extraction electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c of the laminate 12.

[0197] The fourth undercoat plating layer 32d is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the fourth extraction electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d of the laminate 12.

[0198] The first undercoat plating layer 32a of the first external electrode 230a is preferably disposed on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12. The upper end of the first undercoat plating layer 32a of the first external electrode 230a may be disposed so as to overlap or be separated from the underside of the first thin film layer 34a on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12. The same applies to the second surface 12b side.

[0199] The second undercoat plating layer 32b of the second external electrode 230b is preferably disposed on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12. The upper end of the second undercoat plating layer 32b of the second external electrode 230b may be disposed so as to overlap or be separated from the lower side of the second thin film layer 34b on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12. The same applies to the second surface 12b side.

[0200] The third plating underlayer 32c of the third external electrode 230c is preferably disposed on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12. The upper end of the third plating underlayer 32c of the third external electrode 230c may be disposed so as to overlap or be separated from the lower side of the third thin film layer 34c on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12. The same applies to the second surface 12b side.

[0201] The fourth underplating layer 32d of the fourth external electrode 230d is preferably disposed on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12. The upper end of the fourth underplating layer 32d of the fourth external electrode 230d may be disposed so as to overlap or be separated from the lower side of the fourth thin film layer 34d on the ridge formed by the first surface 12a and the fourth surface 12d of the laminate 12. The same applies to the second surface 12b side.

[0202] Here, similarly to the first underlayer plating layer 32a of the multilayer ceramic capacitor 10, the first underlayer plating layer 32a of the multilayer ceramic capacitor 210 also satisfies the condition t2 - 5 μm ≦ t1 ≦ t2 + 2 μm, where t1 is the dimension of the first underlayer plating layer 32a in the stacking direction x and t2 is the dimension of the laminate 12 in the stacking direction x. Furthermore, the first underlayer plating layer 32a is preferably located at a distance of 5 μm or less, since this is the largest dimension of the laminate 12 in the stacking direction x.

[0203] Furthermore, with regard to the first underlayer plating layer 32 a of the multilayer ceramic capacitor 210, similarly to the first underlayer plating layer 32 a of the multilayer ceramic capacitor 10, when a first point where the first underlayer plating layer 32 a and the laminate 12 intersect is taken as a reference point, a second point is taken as an intersection point between the laminate 12 and a line parallel to the stacking direction x that passes through a position 3 μm inward from the first point and the laminate 12, and a third point is taken as an intersection point between the first underlayer plating layer 32 a and a line parallel to the stacking direction x that passes through a position 1 μm outward from the first point and the laminate 12, the angle θ formed by a first straight line x1 connecting the first point and the second point and a second straight line x2 connecting the first point and the third point is preferably 88° or more and 160° or less. The structure of the first base plating layer 32a included in the first external electrode 230a described above is also possessed by the second base plating layer 32b included in the second external electrode 230b, the third base plating layer 32c included in the third external electrode 230c, and the fourth base plating layer 32d constituting the fourth external electrode 230d.

[0204] (Thin Film Layer) The thin film layer 34 is disposed so as to cover the undercoat plating layer 32. The thin film layer 34 includes a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0205] The first thin film layer 34a is disposed so as to cover a portion of the first surface 12a and a portion of the second surface 12b of the laminate 12 on the third surface 12c side and the fifth surface 12e side of the laminate 12, but not cover the third surface 12c and the fifth surface 12e of the laminate 12. The first thin film layer 34a may be disposed separate from the first undercoat plating layer 32a, or may be disposed overlapping the first undercoat plating layer 32a. The surface of the first top plating layer 36a, which will be described later, may be shaped to have a recess.

[0206] The second thin film layer 34b is disposed so as to cover a portion of the first surface 12a and a portion of the second surface 12b of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side, respectively, but not to cover the fourth surface 12d and the sixth surface 12f of the laminate 12. The second thin film layer 34b may be disposed separate from the second undercoat plating layer 32b, or may be disposed so as to overlap the second undercoat plating layer 32b. The surface of the second top plating layer 36b, which will be described later, may be shaped to have a recessed portion.

[0207] The third thin film layer 34c is disposed so as to cover a portion of the first surface 12a and a portion of the second surface 12b of the laminate 12 on the third surface 12c side and the sixth surface 12f side, but not cover the third surface 12c or the sixth surface 12f of the laminate 12. The third thin film layer 34c may be disposed separate from the third underplating layer 32c, or may be disposed so as to overlap the third underplating layer 32c. The surface of a third top plating layer 36c, which will be described later, may be shaped to have a recessed portion.

[0208] The fourth thin film layer 34d is disposed so as to cover a portion of the first surface 12a and a portion of the second surface 12b of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side, but not cover the fourth surface 12d and the fifth surface 12e of the laminate 12. The fourth thin film layer 34d may be disposed separate from the fourth undercoat plating layer 32d, or may be disposed so as to overlap the fourth undercoat plating layer 32d. The surface of a fourth top plating layer 36d, which will be described later, may be shaped to have a recess.

[0209] Each of the first to fourth thin film layers 34 a to 34 d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 34 a to 34 d in the direction connecting the first surface 12 a and the second surface 12 b of the laminate 12 to be 1 μm or less, which allows the dimension of the multilayer ceramic capacitor 10 in the stacking direction x to be sufficiently small, thereby allowing the multilayer ceramic capacitor 10 to be made low-profile.

[0210] (Surface Plated Layer) The surface plated layer 36 includes a first surface plated layer 36a, a second surface plated layer 36b, a third surface plated layer 36c, and a fourth surface plated layer 36d.

[0211] The first surface plating layer 36a is arranged to cover the first thin film layer 34a and the first undercoat plating layer 32a arranged on the third surface 12c of the laminate 12. The second surface plating layer 36b is arranged to cover the second thin film layer 34b and the second undercoat plating layer 32b arranged on the fourth surface 12d of the laminate 12. The third surface plating layer 36c is arranged to cover the third thin film layer 34c and the third undercoat plating layer 32c arranged on the third surface 12c of the laminate 12. The fourth surface plating layer 36d is arranged to cover the fourth thin film layer 34d and the fourth undercoat plating layer 32d arranged on the fourth surface 12d of the laminate 12.

[0212] The surface plating layer 36 preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0213] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0214] The multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 19 provides the same effects as the multilayer ceramic capacitor 10 described above.

[0215] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to the third embodiment will now be described.

[0216] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0217] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0218] In printing the patterns using each conductive paste, first, the patterns using the conductive paste for the internal electrodes are printed.

[0219] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0220] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0221] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0222] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0223] At this time, the first lead electrode portion 24a of the first internal electrode 16a and the third lead electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. Furthermore, the second lead electrode portion 24b of the first internal electrode 16a and the fourth lead electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0224] Subsequently, the external electrodes 230 are formed on the laminate 12 .

[0225] First, a base plating layer 32 is formed to cover the internal electrodes 16 exposed on the surface of the laminate 12. The base plating layer 32 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 12 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the base plating layer 32. Furthermore, when forming the base plating layer 32, the angle θ is adjusted by adjusting the amount of rounding of the laminate 12 or the metal ion concentration in the base plating layer 32 to achieve the structure of the present invention.

[0226] Next, the laminate 12 on which the undercoat plating layer 32 has been formed is aligned on a work table, and a thin film layer 34 is formed on the first surface 12a and the second surface 12b by sputtering.

[0227] Thereafter, a top plating layer 36 is formed on the thin film layer 34 and the surface of the laminate 12. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 34 as the top plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0228] In this manner, the multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 19 can be manufactured.

[0229] D. Fourth Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 310 according to a fourth embodiment of the present invention will now be described.

[0230] Fig. 25 is an external perspective view showing an example of a multilayer ceramic capacitor according to a fourth embodiment of the present invention. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI in Fig. 25. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 25. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII in Fig. 19.

[0231] The multilayer ceramic capacitor 310 according to the fourth embodiment of the present invention has a laminate 312 having a configuration similar to that of the multilayer ceramic capacitor 10 according to the first embodiment, and external electrodes 330. The multilayer ceramic capacitor 310 has a W dimension greater than an L dimension.

[0232] The multilayer ceramic capacitor 310 according to the fourth embodiment includes a rectangular parallelepiped laminate 312 and external electrodes 330 disposed on both ends of the laminate 312 .

[0233] The laminate 112 has a plurality of stacked dielectric layers 314. Furthermore, the laminate 312 has a first surface 312a and a second surface 312b facing in a stacking direction x, a third surface 312c and a fourth surface 312d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 312e and a sixth surface 312f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0234] The multilayer ceramic capacitor 310 has a W dimension greater than an L dimension.

[0235] The multilayer ceramic capacitor 310 includes a laminate 312 and external electrodes 330 .

[0236] (Laminate) The laminate 312 includes a plurality of dielectric layers 314 and a plurality of internal electrodes 316. The dielectric layers 314 include an inner dielectric layer 314a and an outer dielectric layer 314b. The internal electrodes 316 include a first internal electrode 316a and a second internal electrode 316b.

[0237] The laminate 312 also has an inner layer portion 318, a first outer layer portion 320a located on the first surface 312a side, and a second outer layer portion 320b located on the second surface 312b side.

[0238] The first outer layer portion 320a is located on the first surface 312a side of the laminate 312 and is a collection of multiple outer layer dielectric layers 314b located between the first surface 312a and the internal electrode 316 closest to the first surface 312a.

[0239] The second outer layer portion 320b is located on the second surface 312b side of the laminate 12 and is an aggregate of multiple outer layer dielectric layers 314b located between the second surface 312b and the internal electrode 316 closest to the second surface 312b.

[0240] The region sandwiched between the first outer layer portion 320 a and the second outer layer portion 320 b is the inner layer portion 318 .

[0241] The inner layer portion 318 has a first internal electrode 316a having one end exposed to the third surface 312c and the fifth surface 312e and the other end exposed to the fourth surface 312d and the sixth surface 312f, a second internal electrode 316b having one end exposed to the third surface 312c and the sixth surface 312f and the other end exposed to the fourth surface 312d and the fifth surface 312e, and an inner layer dielectric layer 314a.

[0242] The material of the dielectric layer 314 is the same as that of the dielectric layer 14, and therefore a description thereof will be omitted.

[0243] (Internal Electrode) The internal electrode 316 includes a plurality of first internal electrodes 316a and a plurality of second internal electrodes 316b. The first internal electrodes 316a and the second internal electrodes 316b are alternately stacked with the dielectric layer 314 interposed therebetween.

[0244] The first internal electrode 316a is disposed on the surface of the inner dielectric layer 314a. The first internal electrode 316a faces the first surface 312a and the second surface 312b, has a first opposing electrode portion 322a facing the second internal electrode 316b, and is laminated in the direction connecting the first surface 312a and the second surface 312b.

[0245] The first internal electrode 316a is led out to the third surface 312c of the laminate 312 by a first lead electrode portion 324a.

[0246] The second internal electrode 316b is disposed on a surface of the inner dielectric layer 314a different from the surface of the inner dielectric layer 314a on which the first internal electrode 316a is disposed. The second internal electrode 316b faces the first surface 312a and the second surface 312b, has a second opposing electrode portion 322b facing the first internal electrode 316a, and is laminated in the direction connecting the first surface 312a and the second surface 312b.

[0247] The second internal electrode 316b is led out to the fourth surface 312d by a second lead electrode portion 324b.

[0248] As shown in FIG. 27 , the laminate 312 also includes a side portion (W gap) 326a of the laminate 312 located between one end in the second direction z of the second opposing electrode portion 322b of the second internal electrode 316b and the fifth surface 312e, and a side portion (W gap) 326b of the laminate 312 located between the other end in the first direction y of the first opposing electrode portion 322a of the first internal electrode 316a and the sixth surface 312f.

[0249] Furthermore, as shown in FIG. 26 , the laminate 312 includes an end portion (L gap) 327a of the laminate 312 located between one end in the second direction z of the second opposing electrode portion 322b of the second internal electrode 316b and the fourth surface 312d, and a side portion (L gap) 327b of the laminate 312 located between the other end in the first direction y of the first opposing electrode portion 322a of the first internal electrode 316a and the third surface 312c.

[0250] (External Electrodes) In the multilayer ceramic capacitor 310 according to the fourth embodiment, the external electrodes 330 are arranged so as to cover the first surface 312 a and the second surface 312 b of the laminate 312 .

[0251] 25 to 28, external electrodes 330 are arranged on the laminate 312. The external electrodes 330 include a plurality of external electrodes 330 connected to the first internal electrodes 316a and the second internal electrodes 316b. The external electrodes 330 include a first external electrode 330a and a second external electrode 330b.

[0252] The first external electrode 330a is disposed on the third surface 312c so as to cover the first lead electrode portion 324a of the first internal electrode 316a, and further so as to cover a portion of the first surface 312a and a portion of the second surface 312b. The first external electrode 330a is electrically connected to the first lead electrode portion 324a of the first internal electrode 316a.

[0253] The second external electrode 330b is disposed on the fourth surface 312d so as to cover the second lead electrode portion 324b of the first internal electrode 316a, and further so as to cover a portion of the first surface 312a and a portion of the second surface 312b. The second external electrode 330b is electrically connected to the second lead electrode portion 124b of the first internal electrode 316a.

[0254] In the laminate 312, the first opposing electrode portion 322a of the first internal electrode 316a and the second opposing electrode portion 322b of the second internal electrode 316b face each other via the inner dielectric layer 314a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 330a and the second external electrode 330b to which the first internal electrode 316a is connected, thereby realizing the characteristics of a capacitor.

[0255] The first external electrode 330 a and the second external electrode 330 b each have an undercoat plating layer 332 , a thin film layer 334 and a top plating layer 336 .

[0256] In other words, the first external electrode 330a has a first underplating layer 332a, a first thin film layer 334a, and a first top plating layer 336a, and the second external electrode 330b has a second underplating layer 332b, a second thin film layer 334b, and a second top plating layer 336b.

[0257] (Plating Base Layer) The plating base layer 332 is disposed on the third surface 312c and the fourth surface 312d. The specific configuration of the plating base layer 332 will be described below.

[0258] The first undercoat plating layer 332a is disposed on the surface of the third surface 312c of the laminate 312 so as to cover the first extraction electrode portion 324a of the first internal electrode 316a exposed from the third surface 312c of the laminate 312.

[0259] The second undercoat plating layer 332b is disposed on the surface of the fourth surface 312d of the laminate 312 so as to cover the second extraction electrode portion 324b of the first internal electrode 316a exposed from the fourth surface 312d of the laminate 312.

[0260] The first underplating layer 332a of the first external electrode 330a is preferably disposed on the ridge line formed by the first surface 312a and the third surface 312c of the laminate 312 and on the ridge line formed by the second surface 312b and the third surface 312c. The upper end of the first underplating layer 332a of the first external electrode 330a may be disposed so as to overlap or be separated from the underside of the first thin film layer 334a on the ridge line formed by the first surface 312a and the third surface 312c of the laminate 312. The same applies to the second surface 312b side.

[0261] The second plating underlayer 332b of the second external electrode 330b is preferably disposed on the ridge formed by the first surface 312a and the fourth surface 312d of the laminate 312 and on the ridge formed by the second surface 312b and the fourth surface 312d of the laminate 312. The upper end of the second plating underlayer 332b of the second external electrode 330b may be disposed so as to overlap or be separated from the lower side of the second thin film layer 334b ​​on the ridge formed by the first surface 312a and the fourth surface 312d of the laminate 312. The same applies to the second surface 312b side.

[0262] Here, similarly to the first underplating layer 32a of the multilayer ceramic capacitor 10, the first underplating layer 332a of the multilayer ceramic capacitor 310 also satisfies the condition t2 - 5 μm ≦ t1 ≦ t2 + 2 μm, where t1 is the dimension of the first underplating layer 332a in the stacking direction x and t2 is the dimension of the laminate 312 in the stacking direction x. Furthermore, the first underplating layer 332a is preferably located at a distance of 5 μm or less, since this is the largest dimension of the laminate 312 in the stacking direction x.

[0263] Furthermore, with regard to the first underlayer plating layer 132a of the multilayer ceramic capacitor 310, similarly to the first underlayer plating layer 32a of the multilayer ceramic capacitor 10, when a first point where the first underlayer plating layer 332a and the laminate 312 intersect is taken as a reference point, a second point is taken as an intersection point between the laminate 312 and a line parallel to the stacking direction x that passes through a position 3 μm inward from the first point and the laminate 312, and a third point is taken as an intersection point between the first underlayer plating layer 332a and a line parallel to the stacking direction x that passes through a position 1 μm outward from the first point and the laminate 312, the angle θ formed by a first straight line x1 connecting the first point and the second point and a second straight line x2 connecting the first point and the third point is preferably 88° or more and 160° or less.

[0264] (Thin Film Layer) The thin film layer 334 covers the first surface 312a. Preferably, the thin film layer 334 also covers the underplating layer 332. This makes it possible to suppress the infiltration of moisture from the underplating layer 332. The thin film layer 334 has a first thin film layer 334a and a second thin film layer 334b.

[0265] The first thin film layer 334a is disposed so as to cover a portion of the first surface 312a and a portion of the second surface 312b of the laminate 312 on the third surface 312c side, but not cover the third surface 312c through sixth surface 312f of the laminate 312. The first thin film layer 334a may be disposed separate from the first underplating layer 332a, or may be disposed overlapping the first underplating layer 332a. The surface of the first top plating layer 336a, which will be described later, may be shaped to have a recessed portion.

[0266] The second thin film layer 334b ​​is disposed so as to cover a portion of the first surface 312a and a portion of the second surface 312b of the laminate 312 on the side of the fourth surface 312d, but not to cover the third surface 312c to the sixth surface 312f of the laminate 312. The second thin film layer 334b ​​may be disposed separate from the second underplating layer 332b, or may be disposed so as to overlap the second underplating layer 332b. The surface of the second top plating layer 336b, which will be described later, may be shaped to have a recessed portion.

[0267] Each of the first thin film layer 334 a and the second thin film layer 334 b is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first thin film layer 334 a and the second thin film layer 334 b in the direction connecting the first surface 312 a and the second surface 312 b of the laminate 312 to be 1 μm or less, which allows the dimension of the multilayer ceramic capacitor 310 in the stacking direction x to be sufficiently small, and therefore allows the multilayer ceramic capacitor 310 to be made low-profile.

[0268] (Surface Plated Layer) The surface plated layer 336 includes a first surface plated layer 336a and a second surface plated layer 336b.

[0269] The first surface plating layer 336a is disposed so as to cover the first thin film layer 334a and the first underplating layer 332a disposed on the third surface 312c of the laminate 312. The second surface plating layer 336b is disposed so as to cover the second thin film layer 334b ​​and the second underplating layer 332b disposed on the fourth surface 312d of the laminate 312.

[0270] The surface plating layer 336 preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0271] The surface plating layer 336 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0272] The multilayer ceramic capacitor 310 shown in FIG. 25 has the same effects as the multilayer ceramic capacitor 10 according to the first embodiment.

[0273] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Hereinafter, a method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to the fourth embodiment, will be described. Hereinafter, a method for manufacturing a multilayer ceramic capacitor according to the first embodiment will be described.

[0274] First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0275] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0276] Furthermore, for example, when forming a printing pattern of an internal electrode by gravure printing, the design of the gravure plate used in the gravure printing is set to the graphic pattern of the first internal electrode, and by changing the structure to correspond to the graphic pattern of the second internal electrode, it is possible to form each of the desired internal electrodes.

[0277] Furthermore, when forming a printing pattern of the internal electrode layer by screen printing, the desired internal electrode can be formed by designing the screen printing mask to the graphic pattern of the first internal electrode and changing the structure to correspond to the graphic pattern of the second internal electrode.

[0278] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 320a on the first surface 312a side. Thereafter, the portion that will become the internal layer portion 318 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the internal layer portion 318 to form the portion that will become the second outer layer portion 320b on the second surface 312b side. In this way, a laminated sheet is produced.

[0279] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0280] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0281] Next, the laminated chip is fired to produce the laminate 312. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0282] At this time, the first lead electrode portion 324a of the first internal electrode 316a is exposed from the third surface 312c of the laminate 312. Furthermore, the second lead electrode portion 324b of the second internal electrode 316b is exposed from the fourth surface 312d of the laminate 312.

[0283] Subsequently, an external electrode 330 is formed on the laminate 312 .

[0284] First, a base plating layer 332 is formed to cover the internal electrodes 316 exposed on the surface of the laminate 312. The base plating layer 332 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 312 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 312 and the base plating layer 332. Furthermore, when forming the base plating layer 332, the angle θ is adjusted by adjusting the amount of rounding of the laminate 312 or the metal ion concentration in the base plating layer 332 to achieve the structure of the present invention.

[0285] Next, the laminate 312 on which the undercoat plating layer 332 has been formed is aligned on a work table, and a thin film layer 334 is formed on the first surface 312a and the second surface 312b by sputtering.

[0286] Thereafter, a top plating layer 336 is formed on the thin film layer 334 and the surface of the laminate 312. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 334 as the top plating layer 336. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0287] In this manner, the multilayer ceramic capacitor 310 according to the embodiment shown in FIG. 25 can be manufactured.

[0288] E. Experimental Examples 1. Experimental Example 1 Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were fabricated as experimental samples according to the manufacturing method described above, in which the difference between the dimension t1 of the undercoat plating layer in the stacking direction and the dimension t2 of the laminate in the stacking direction was varied. A mounting resistance test was then performed, and each sample was evaluated.

[0289] (1) Specifications of the multilayer ceramic capacitors fabricated as samples of experimental examples Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors were fabricated as samples of Comparative Example 1 and Examples 1 to 5. Structure of multilayer ceramic capacitor: multilayer ceramic capacitor shown in Fig. 11A Dimensions of multilayer ceramic capacitor (L): 480 µm Dimensions of multilayer ceramic capacitor (W): 480 µm Dimensions of multilayer ceramic capacitor (T): 60 µm Ceramic material: BaTiO3 Material of internal electrodes: Ni Structure of external electrodes Undercoat plating layer: Cu plating Thin film layer: sputtered film containing at least one of Ni, Cr, and Cu Top plating layer: two-layer structure of Ni plating layer and Sn plating layer

[0290] (2) Impact Resistance Test Method: The chip was fixed to a metal plate with double-sided tape. A 5 g Zr nozzle was then prepared and allowed to freely drop from a position approximately 2 mm above the chip surface. The Zr nozzle had an outer diameter φ of 0.6 mm and an inner diameter φ of 0.4 mm. Chips whose capacitance decreased by 20% or more compared to the average capacitance of 1,000 samples of each type before the test were judged to be defective (NG). The number of chips judged to be NG was then counted. The number of samples for each type was 1,000.

[0291] (3) Results The evaluation results are shown in Table 1. Table 1 shows the evaluation results for multilayer ceramic capacitor samples in which the difference between the dimension t1 of the undercoat plating layer in the stacking direction and the dimension t2 of the laminate in the stacking direction was varied. Note that cases in which the dimension of the undercoat plating layer in the stacking direction was larger than the dimension of the laminate in the stacking direction are indicated by a minus sign, and cases in which the dimension of the undercoat plating layer in the stacking direction was smaller than the dimension of the laminate are indicated by a plus sign.

[0292]

[0293] According to Table 1, in Examples 1 to 5, the difference between the dimension t1 of the undercoat plating layer in the stacking direction and the dimension t2 of the laminate in the stacking direction satisfied the condition t2 - 5 μm ≦ t1 ≦ t2 + 2 μm, and therefore, as a result of the mounting resistance test, good results were obtained, with 10 or less out of 1,000 samples for each sample being evaluated as defective (NG).

[0294] On the other hand, in Comparative Example 1, the difference between the dimension t1 of the undercoat plating layer in the stacking direction and the dimension t2 of the laminate in the stacking direction did not satisfy the condition t2 - 5 μm≦t1≦t2 + 2 μm, and as a result of the mounting resistance test, 24 out of 1000 samples were evaluated as defective (NG), resulting in an increase in the number of defects.

[0295] 2. Experimental Example 2 In order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitor samples were fabricated according to the manufacturing method described above, with the angle between the first line x1 and the second line x2 being varied, and the wetting of the solder for each sample was evaluated.

[0296] (1) Specifications of multilayer ceramic capacitors fabricated as samples for experimental examples Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors were fabricated as samples for Comparative Examples 2 and 3 and Examples 6 to 9. Structure of multilayer ceramic capacitor: multilayer ceramic capacitor shown in Fig. 11A Dimensions of multilayer ceramic capacitor (L): 480 µm Dimensions of multilayer ceramic capacitor (W): 480 µm Dimensions of multilayer ceramic capacitor (T): 60 µm Ceramic material: BaTiO3 Material of internal electrode: Ni Structure of external electrode Undercoat plating layer: Cu plating Thin film layer: sputtered film containing at least one of Ni, Cr, and Cu Top plating layer: two-layer structure of Ni plating layer and Sn plating layer

[0297] (2) Evaluation Method for Solder Wetting: A test board was prepared with a 500 μm square land pad and a 100 μm spacing between land electrodes. A 300 μm square solder paste was applied to the test board to a thickness of 40 μm. The solder ball particle size of the solder paste was 5 μm to 15 μm. After mounting, the board was heat-treated at 230°C or higher for 30 minutes. Cross-sections were then polished at 1 / 2 W of the laminate and 1 / 2 of the external electrodes from the direction connecting the fifth and sixth surfaces of the laminate. The distance from the top surface of the laminate to the top surface of the solder was measured using an optical microscope or the like. A distance greater than 10 μm was evaluated as defective (NG).

[0298] (3) Results The evaluation results are shown in Table 2. Table 2 shows the evaluation results for multilayer ceramic capacitors, which are samples in which the angle between the first line x1 and the second line x2 is changed.

[0299]

[0300] According to Table 2, in Examples 6 to 9, the angle between the first straight line x1 and the second straight line x2 was greater than or equal to 88° and less than 160°, so it was confirmed that wetting of the solder onto the second surface was suppressed.

[0301] On the other hand, in Comparative Examples 2 and 3, since the angle formed by the first line x1 and the second line x2 was outside the range of 88° or more and 160° or less, it was confirmed that the wettability rose to a depth of 10 μm or more from the outermost surface of the laminate.

[0302] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0303] 10, 110, 210, 310 Multilayer ceramic capacitor 12 Laminate 12a, 112a, 312a First surface 12b, 112b, 312b Second surface 12c, 112c, 312c Third surface 12d, 112d, 312d Fourth surface 12e, 112e, 312e Fifth surface 12f, 112f, 312f Sixth surface 14, 114, 314 Dielectric layer 14a, 114a, 314a Inner dielectric layer 14b, 114b, 314b Outer dielectric layer 16, 116, 316 Internal electrode 16a, 116a, 316a First internal electrode 16b, 116b, 316b Second internal electrode 18, 118, 318 Inner layer portion 20a, 120a, 320a First outer layer portion 20b, 120b, 320b Second outer layer portion 22a, 122a, 322a First opposing electrode portion 22b, 122b, 322b Second opposing electrode portion 24a, 124a, 324a First extracted electrode portion 24b, 124b, 324b Second extracted electrode portion 24c, 124c Third extracted electrode portion 24d, 124d Fourth extracted electrode portion 26a, 26b, 126a, 126b, 326a, 326b Side portion of laminate (W gap) 27a, 27b, 127a, 127b, 327a, 327b End portion of laminate (L gap) 30, 130, 230, 330 External electrodes 30a, 130a, 230a, 330a First external electrode 30b, 130b, 230b, 330b Second external electrode 30c, 130c, 230c Third external electrode 30d, 130d, 230d Fourth external electrode 34, 134, 334 Thin film layer 34a, 134a, 334a First thin film layer 34b, 134b, 334b ​​Second thin film layer 34c, 134c Third thin film layer 34d, 134d Fourth thin film layer 36, 136, 336 Surface plating layer 36a, 136a, 336a First surface plating layer 36b, 136b, 336b Second surface plating layer 36c, 136c Third surface plating layer 36d, 136d Fourth surface plating layer x Stacking direction y First direction z Second direction L Dimension of multilayer ceramic capacitor in the first direction W Dimension of multilayer ceramic capacitor in the second direction T Dimension of multilayer ceramic capacitor in the stacking direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate having first and second surfaces opposed to each other in a stacking direction, third and fourth surfaces opposed to each other in a first direction perpendicular to the stacking direction, and fifth and sixth surfaces opposed to each other in a second direction perpendicular to the stacking direction and the first direction; and first to fourth external electrodes arranged on a surface of the laminate, wherein the laminate includes a first internal electrode exposed on the third and fourth surfaces, and a second internal electrode exposed on the third and fourth surfaces, and the first external electrode has a first undercoat plating layer connected to the first internal electrode, wherein, when a dimension of the first undercoat plating layer in the stacking direction is t, a dimension of the laminate in the stacking direction is T, a dimension of the multilayer ceramic capacitor in the first direction is L, and a dimension of the multilayer ceramic capacitor in the second direction is W, A multilayer ceramic capacitor, wherein 0.85≦L / W≦1.0 and (T−5 μm)≦t≦(T+2 μm).

2. The multilayer ceramic capacitor according to claim 1, wherein (T-5 μm)≦t≦T.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the dimension of the multilayer ceramic capacitor in the lamination direction is 220 μm or less.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the first external electrode has a first thin film layer, and the first thin film layer is disposed on the first surface of the laminate and on the first undercoat plating layer.

5. The multilayer ceramic capacitor according to claim 4, wherein the first external electrode has an area surrounded by the laminate, the first underplating layer, and the first thin film layer.

6. A multilayer ceramic capacitor comprising: a laminate having first and second surfaces opposed to each other in a stacking direction, third and fourth surfaces opposed to each other in a first direction perpendicular to the stacking direction, and fifth and sixth surfaces opposed to each other in a second direction perpendicular to the stacking direction and the first direction; and first external electrodes and second external electrodes arranged on surfaces of the laminate, wherein the laminate includes a first internal electrode exposed on the third surface and a second internal electrode exposed on the fourth surface, and the first external electrode has a first undercoat plating layer connected to the first internal electrode, wherein, when the dimension of the first undercoat plating layer in the stacking direction is t, the dimension of the laminate in the stacking direction is T, the dimension of the multilayer ceramic capacitor in the first direction is L, and the dimension of the multilayer ceramic capacitor in the second direction is W, then 0.85≦L / W≦1.0 and (T−5μm)≦t≦(T+2μm). That is, a multilayer ceramic capacitor.

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