Insulated-gate semiconductor device

Abstract

The present invention further improves an insulated-gate semiconductor device. An insulated-gate semiconductor device comprises: a first-conductivity-type semiconductor substrate (15); a trench (9a) provided to the semiconductor substrate, the trench having a first side wall surface (S1), a second side wall surface (S2), and a lower surface (S3); an insulated-gate electrode structure embedded in the trench; a second-conductivity-type base region (6a) provided in contact with the first side wall surface; a first-conductivity-type source region (7a) provided to the upper-surface side of the base region so as to be in contact with the first side wall surface; a second-conductivity-type gate bottom protection region (4a) provided in contact with the lower surface of the trench; a second-conductivity-type connection region (5a) provided to the upper-surface side of the gate bottom protection region so as to be in contact with the second side wall surface; and a second-conductivity-type contact region (8a) provided to the upper-surface side of the connection region. Along the direction in which the first side wall surface (S1) and the second side wall surface (S2) face each other, a first end (41) of the gate bottom protection region protrudes in a direction away from the insulated-gate electrode structure with reference to the position of the first side wall surface.

Description

Insulated gate semiconductor device

[0001] The present invention relates to an insulated gate semiconductor device having an insulated gate electrode structure in a trench.

[0002] Power semiconductor devices are semiconductor elements that can withstand high voltages and control large currents. By using silicon carbide (SiC) substrates for power semiconductor devices, it is possible to realize transistors with high voltage blocking capabilities.

[0003] Patent Document 1 describes that each device cell of the semiconductor device includes a pn junction between a diode region and a drift region, and a trench having a first sidewall, a second sidewall opposing the first sidewall, and a bottom, and that the diode region is adjacent to the second sidewall, the pn junction is adjacent to the bottom of the trench, and the diode regions of the device cells are spaced apart in the lateral direction of the semiconductor body.

[0004] Patent Document 2 describes a trench and a protective diffusion layer of a second conductivity type provided in the drift layer in contact with the bottom of the trench.

[0005] Patent Document 3 describes - It is described that a p-type buried region is selectively provided within the p-type drift layer and contacts the deposited insulating layer at the bottom of the trench.

[0006] Patent No. 5907940 Patent No. 7241848 Patent No. 7156425

[0007] Even if a transistor has a high voltage blocking capability due to the use of a silicon carbide (SiC) substrate, if the dielectric strength of the gate insulating film is insufficient for the voltage blocking capability of the transistor, voltage breakdown may occur at an early stage.

[0008] Furthermore, Patent Document 1 employs a one-sided channel structure in which only the a-plane, which has high carrier mobility, is used as the channel. In the one-sided channel structure, the plane not used as the channel is covered with a p-type semiconductor region, resulting in a lower channel density and a higher on-resistance compared to the double-sided channel structure.

[0009] In view of the above problems, an object of the present invention is to provide an insulated gate semiconductor device with further improved performance.

[0010] (g) a connection region of the second conductivity type provided on the upper surface of the gate bottom protection region in contact with the second sidewall surface; and (h) a contact region of the second conductivity type provided on the upper surface of the connection region, wherein (i) a first end portion of the gate bottom protection region on the first sidewall surface side protrudes in a direction away from the insulated gate electrode structure, based on the position of the first sidewall surface.

[0011] The first end may protrude along the first direction in a direction away from the insulated gate electrode structure, with the position of the lower end of the first sidewall surface as a reference.

[0012] The semiconductor substrate may include a drift layer, and a high concentration region of the first conductivity type having a higher impurity concentration than the drift layer may be provided on the lower surface side of the base region.

[0013] The protrusion amount of the first end portion may be 0.05 μm or more and 0.15 μm or less.

[0014] The high concentration region may be located deeper than the base region and shallower than the gate bottom protection region.

[0015] The semiconductor substrate may also include a current diffusion layer provided on the upper surface side of the drift layer and having a higher impurity concentration than the drift layer, and the high concentration region may have a higher impurity concentration than the current diffusion layer.

[0016] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0017] According to the present invention, it is possible to provide an insulated gate semiconductor device with further improved performance.

[0018] 11 is a cross-sectional schematic diagram showing a longitudinal sectional configuration of an insulated gate semiconductor device according to a first embodiment; FIG. 12 is a cross-sectional schematic diagram for explaining the plane orientation of a sidewall surface of a trench; FIG. 13 is a graph showing simulation results; FIG. 14 is a cross-sectional schematic diagram showing a longitudinal sectional configuration of an insulated gate semiconductor device according to a comparative example; FIG. 15 is a cross-sectional schematic diagram showing a longitudinal sectional configuration of an insulated gate semiconductor device according to a comparative example; FIG. 16 is a cross-sectional schematic diagram showing a longitudinal sectional configuration of a trench according to a first modification of the first embodiment; FIG. 17 is a cross-sectional schematic diagram showing a longitudinal sectional configuration of an insulated gate semiconductor device according to a second embodiment; FIG. 18 is a graph showing simulation results; FIG. 19 is a cross-sectional schematic diagram showing a process for explaining an example of a method for manufacturing an insulated gate semiconductor device according to the second embodiment; FIG. 19 is a cross-sectional schematic diagram following FIG. 11; FIG. 12 is a cross-sectional schematic diagram following FIG. 13; FIG. 14 is a cross-sectional schematic diagram showing a longitudinal sectional configuration of an insulated gate semiconductor device according to a first modification of the second embodiment; FIG. 19 is a cross-sectional schematic diagram showing a longitudinal sectional configuration of an insulated gate semiconductor device according to a second modification of the second embodiment;

[0019] Hereinafter, first and second embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0020] In this specification, the term "first main electrode region" refers to a semiconductor region that serves as either the source region or the drain region in a field-effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), the term "first main electrode region" refers to a semiconductor region that serves as either the emitter region or the collector region. In a static induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO), the term "first main electrode region" refers to a semiconductor region that serves as either the anode region or the cathode region. In an FET or SIT, the term "second main electrode region" refers to a semiconductor region that serves as the other of the source region or the drain region. In an IGBT, the term "second main electrode region" refers to the region that serves as the other of the emitter region or the collector region. In an SI thyristor or GTO, the term "second main electrode region" refers to a semiconductor region that serves as the other of the anode region or the cathode region. Thus, if the "first main electrode region" is the source region, the "second main electrode region" refers to the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. In an FET or the like, the functions of the "first main electrode region" and the "second main electrode region" can be interchanged by exchanging the bias relationship. Furthermore, in this specification, when the term "main electrode region" is simply used, it comprehensively means either the first main electrode region or the second main electrode region.

[0021] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are read as being converted to left and right, and if it is rotated 180 degrees and observed, up and down are read as being reversed. Furthermore, the following description will exemplarily describe a case where the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, the "+" and "-" attached to "n" and "p" indicate a semiconductor region with a relatively higher or lower impurity density, respectively, compared to a semiconductor region without the "+" and "-" attached. However, even if the same "n" and "n" are attached to semiconductor regions, this does not mean that the impurity densities of the respective semiconductor regions are strictly the same. Furthermore, it is technically and logically self-evident that the components and regions to which the limitations of "first conductivity type" and "second conductivity type" are added in the following description mean components and regions made of semiconductor materials even if there is no particular explicit limitation. Also, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0022] [First Embodiment] <Structure of Insulated Gate Semiconductor Device> As shown in Fig. 1, an insulated gate semiconductor device according to a first embodiment includes a trench-gate MOSFET as an active element. While Fig. 1 illustrates two unit cells, namely, unit cell 17a including an insulated gate electrode structure (10a, 11a) embedded in trench 9a and unit cell 17b including an insulated gate electrode structure (10b, 11b) embedded in trench 9b, in practice, many more unit cells are periodically arranged in parallel. The insulated gate semiconductor device according to the first embodiment can be configured as a power semiconductor device that can pass a large current by arranging a plurality of these unit cells to form a multi-channel structure.

[0023] As shown in FIG. 1, the insulated gate semiconductor device according to the first embodiment includes a semiconductor substrate 15. The semiconductor substrate 15 is made of, for example, a silicon carbide (SiC) substrate. When the semiconductor substrate 15 is made of a SiC substrate, the insulated gate semiconductor device according to the first embodiment is a SiC semiconductor device. The semiconductor substrate 15 is not limited to a SiC substrate, and may be made of, for example, gallium nitride (GaN), gallium oxide (Ga ２ O ３ ), diamond (C) or aluminum nitride (AlN) or other wide band gap semiconductor, or a silicon (Si) semiconductor substrate.

[0024] The semiconductor substrate 15 is of the first conductivity type (n － The drift layer 2 has an impurity concentration of, for example, 5×10 １５ cm －３ That's it, 2 x 10 １６ cm －３ The thickness of the drift layer 2 is, for example, about 1 μm or more and 100 μm or less. The impurity concentration and thickness of the drift layer 2 can be adjusted appropriately depending on the withstand voltage specifications and the like.

[0025] A current spreading layer (CSL) 3 of a first conductivity type (n-type) having a higher impurity concentration than the drift layer 2 is selectively provided on the upper surface side of the drift layer 2. The lower surface of the current spreading layer 3 is in contact with the upper surface of the drift layer 2. The impurity concentration of the current spreading layer 3 is, for example, 1×10 １６ cm －３ That's it, 1 x 10 ２１ cm －３ The current diffusion layer 3 does not necessarily have to be provided, and if the current diffusion layer 3 is not provided, the drift layer 2 may be provided so as to extend to the region of the current diffusion layer 3.

[0026] Base regions 6a, 6b, and 6c of the second conductivity type (p-type) are provided on the upper surface side of the current diffusion layer 3. The lower surfaces of the base regions 6a and 6b are in contact with the upper surface of the current diffusion layer 3. When the current diffusion layer 3 is not provided, the lower surfaces of the base regions 6a, 6b, and 6c are in contact with the upper surface of the drift layer 2.

[0027] The upper surface of the base regions 6 a, 6 b, and 6 c is provided with a first conductivity type (n ＋ First main regions (source regions) 7a, 7b, and 7c of the MOSFET type are selectively provided. The lower surface of the source region 7a is in contact with the upper surface of the base region 6a. The lower surface of the source region 7b is in contact with the upper surface of the base region 6b. The lower surface of the source region 7c is in contact with the upper surface of the base region 6c.

[0028] Within the current spreading layer 3 and at the bottom of the trenches 9a and 9b, a second conductivity type (p ＋ Gate bottom protection regions 4a and 4b (type) are provided. The gate bottom protection region 4a contacts the bottom surface of the trench 9a. The gate bottom protection region 4b contacts the bottom surface of the trench 9b. The impurity concentration of the gate bottom protection regions 4a and 4b is, for example, 5×10 １５ cm －３ That's it, 2 x 10 ２１ cm －３ When the current diffusion layer 3 is not provided, the gate bottom protection regions 4 a and 4 b are provided inside the drift layer 2 .

[0029] The upper surface of the gate bottom protection regions 4a and 4b is provided with a second conductivity type (p ＋ The gate-side gate insulating film 4 has connection regions 5a and 5b (type) formed thereon. The lower surface of the connection region 5a contacts the upper surface of the gate bottom protection region 4a. The lower surface of the connection region 5b contacts the upper surface of the gate bottom protection region 4b. One side surface of the connection region 5a contacts the current spreading layer 3 and the base region 6c. One side surface of the connection region 5b contacts the current spreading layer 3 and the base region 6a. If the current spreading layer 3 is not provided, one side surface of each of the connection regions 5a and 5b contacts the drift layer 2 instead of the current spreading layer 3.

[0030] On the upper surface side of the connection regions 5a and 5b, a second conductivity type (p ＋＋Contact regions 8a and 8b (type) are provided. The contact regions 8a and 8b may have a higher impurity concentration than the gate bottom protection regions 4a and 4b. The lower surface of the contact region 8a is in contact with the upper surface of the connection region 5a. The lower surface of the contact region 8b is in contact with the upper surface of the connection region 5b. As a result, the contact regions 8a and 8b are electrically connected to the gate bottom protection regions 4a and 4b with the connection regions 5a and 5b interposed therebetween. The connection regions 5a and 5b are connection regions that connect the contact regions 8a and 8b to the gate bottom protection regions 4a and 4b. One side surface of the contact region 8a is in contact with the source region 7c. One side surface of the contact region 8b is in contact with the source region 7a.

[0031] Trenches 9a and 9b are provided from the upper surface of the semiconductor substrate 15 toward the normal direction (depth direction) of the upper surfaces of the source regions 7a and 7b and the contact regions 8a and 8b. The trench 9a penetrates the source region 7a, the base region 6a, and the contact region 8a, and its lower surface S3 reaches the gate bottom protection region 4a. The trench 9b penetrates the source region 7b, the base region 6b, and the contact region 8b, and its lower surface reaches the gate bottom protection region 4b. The trenches 9a and 9b may have a planar pattern extending in a stripe shape in the depth direction and forward direction of the paper in FIG. 1, or may have a dotted planar pattern.

[0032] A gate insulating film 10a is provided along the bottom surface S3 of the trench 9a and along both sidewall surfaces S1 and S2. A gate electrode 11a is buried inside the trench 9a with the gate insulating film 10a interposed therebetween. The gate insulating film 10a and the gate electrode 11a form a trench-gate type insulated gate electrode structure (10a, 11a). Similarly, a trench-gate type insulated gate electrode structure (10b, 11b) is formed within the trench 9b.

[0033] The gate insulating films 10a and 10b are made of silicon oxide (SiO ２ In addition to silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si ３ N ４ ) film, aluminum oxide (Al ２ O３ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ２ O ３ ) film, hafnium oxide (HfO ２ ) film, zirconium oxide (ZrO ２ ) film, tantalum oxide (Ta ２ O ５ ) film, bismuth oxide (Bi ２ O ３ The gate electrodes 11 a and 11 b may be made of a single layer of any one of the above films or a laminated film of a plurality of these films. The gate electrodes 11 a and 11 b may be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of p-type or n-type impurities, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni).

[0034] The unit cell 17a including the insulated gate electrode structures (10a, 11a) and the unit cell 17b including the insulated gate electrode structures (10b, 11b) have the same configuration. Therefore, the following description will mainly focus on the configuration of the unit cell 17a. As shown in FIG. 2 , the chip structure of the semiconductor substrate 15 in which the trench 9a is formed has an off-axis angle θ1 of, for example, approximately 4° to 8° in the <11-20> direction relative to the <0001> (c-axis) direction. The off-axis angle θ1 is the angle between the reference plane of the chip structure and a plane (basal plane) perpendicular to the c-axis, which is the (0001) plane (SiC plane) or the (000-1) plane (C-plane). The straight lines L1 shown by multiple solid lines on the side of the chip structure schematically represent the SiC plane.

[0035] Consider providing a trench 9a in this chip structure. The opposing sidewall surfaces S1 and S2 of the trench 9a both use the a-plane, which is the (11-20) plane. In FIG. 2, dashed lines L2 and L3 parallel to the a-plane are shown schematically. In this case, because the semiconductor wafer has an off-angle θ1, the inclination angle θ2 of one sidewall surface S1 of the trench 9a relative to the a-plane is different from the inclination angle θ3 of the other sidewall surface S2 relative to the a-plane. For example, if the off-angle θ1 is 4°, the inclination angle θ2 of the SiC surface side of the sidewall surface S1 of the trench 9a relative to the a-plane is 5°, and the inclination angle θ3 of the SiC surface side of the sidewall surface S2 of the trench 9a relative to the a-plane is 13°. Thus, the inclination angle θ2 is smaller than the inclination angle θ3. Generally, the smaller the inclination angle from the a-plane, the higher the electron mobility.

[0036] In the insulated gate semiconductor device according to the first embodiment, the sidewall surface S1, which is one of the sidewall surfaces S1 and S2 and has a higher electron mobility, is utilized as a current path. The sidewall surface S1 is defined as a "first sidewall surface." As shown in FIG. 1 , the current diffusion layer 3, the base region 6a, and the source region 7a contact the sidewall surface S1. Note that if the current diffusion layer 3 is not provided, the drift layer 2 contacts the sidewall surface S1 instead of the current diffusion layer 3.

[0037] As shown in FIG. 2 , the sidewall surface S2, which is the sidewall surface with lower electron mobility out of the sidewall surfaces S1 and S2, is designed not to be used as a current path. The sidewall surface S2 is defined as a "second sidewall surface." As shown in FIG. 1 , the connection region 5a and the contact region 8a contact the sidewall surface S2. More specifically, the other side surface of the connection region 5a and the other side surface of the contact region 8a contact the sidewall surface S2. The direction in which the sidewall surfaces S1 and S2 face each other is defined as a first direction.

[0038] As shown in FIG. 1 , the bottom surface S3 of the trench 9a is a surface that connects the bottom end of the sidewall surface S1 to the bottom end of the sidewall surface S2. As shown in FIG. 1 , the gate bottom protection region 4a is in contact with the bottom surface S3. Of the ends of the gate bottom protection region 4a along the first direction (the direction in which the sidewall surfaces S1 and S2 face each other), the end located on the sidewall surface S1 side is defined as a first end 41. The first end 41 protrudes along the first direction. More specifically, the first end 41 protrudes in a direction away from the insulated gate electrode structure (10a, 11a) based on the position of the sidewall surface S1 in the first direction.

[0039] FIG. 3 shows simulation results illustrating the relationship between the value of the protrusion amount d of the first end 41 and the electric field generated in the gate insulating film 10a. In the simulation results shown in FIG. 3, the value of the protrusion amount d is varied from negative to positive values ​​to determine the electric field generated in the gate insulating film 10a. A positive value of the protrusion amount d indicates that the first end 41 protrudes to the right of the sidewall surface S1 in the first direction, as shown in FIG. 1, for example. A value of zero of the protrusion amount d indicates that the first end 41 is located at the same position as the sidewall surface S1 in the first direction, as shown in the comparative example of FIG. 4. A negative value of the protrusion amount d indicates that the first end 41 is located to the left of the sidewall surface S1 in the first direction, as shown in the comparative example of FIG. 5. The simulation results show that the larger the value of the protrusion amount d, the smaller the electric field generated in the gate insulating film 10a. Furthermore, within the range of protrusion amount d from -0.3 μm to 0 μm, the larger the protrusion amount d, the smaller the electric field generated in the gate insulating film 10a, but the decrease in the electric field is gradual. In contrast, when the protrusion amount d is a positive value (d1 > 0), the electric field generated in the gate insulating film 10a is significantly reduced. Simulation results show that when the protrusion amount d = 0.4 μm, the electric field generated in the gate insulating film 10a is reduced to about one-third of that when the protrusion amount d = -0.3 μm. Thus, by setting the protrusion amount d of the first end 41 to a positive value, the electric field generated in the gate insulating film 10a can be suppressed.

[0040] Interlayer insulating films 12a and 12b are selectively provided on the upper surfaces of the gate electrodes 11a and 11b. The interlayer insulating films 12a and 12b may be, for example, a silicon oxide film (BPSG film) doped with boron (B) and phosphorus (P), a silicon oxide film (PSG film) doped with phosphorus (P), a non-doped silicon oxide film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film (BSG film) doped with boron (B), or a silicon nitride film (Si ３ N ４ The film may be a single layer such as a monolayer film, or a laminated film made up of multiple layers of these.

[0041] A first main electrode (source electrode) 13 is provided to cover the upper surfaces of the source regions 7a, 7b, and 7c and the contact regions 8a and 8b exposed between the interlayer insulating films 12a and 12b. The lower surface of the source electrode 13 contacts the upper surfaces of the source regions 7a, 7b, and 7c and the contact regions 8a and 8b, providing electrical conduction. The source electrode 13 is provided separately from gate wiring electrodes (not shown) electrically connected to the gate electrodes 11a and 11b. The source electrode 13 is made of a metal such as aluminum (Al), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or copper (Cu). The source electrode 13 may also have a barrier metal layer on its lower surface.

[0042] The lower surface of the drift layer 2 is provided with a first conductivity type (n ＋ A second main region (drain region) 1 of n-type (SiC type) is provided. The drain region 1 is configured of a semiconductor substrate (SiC substrate) made of SiC. Note that a dislocation conversion layer or a recombination promotion layer, which is an n-type buffer layer having a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0043] A second main electrode (drain electrode) 14 is provided on the lower surface side of the drain region 1. The drain electrode 14 may be, for example, a single layer film made of gold (Au), or a metal film laminated in this order from the drain region 1 side, titanium (Ti), nickel (Ni), and Au, and may further have a metal film of molybdenum (Mo), tungsten (W), or the like laminated on the bottom layer. In addition, nickel silicide (NiSi) may be provided between the drain region 1 and the drain electrode 14 for ohmic contact. ｘ A drain contact layer such as a SiO 2 film may be provided. Note that when simply referred to as a “main electrode,” it comprehensively refers to either the first main electrode (source electrode) 13 or the second main electrode (drain electrode) 14.

[0044] During operation of the insulated gate semiconductor device according to the first embodiment, when the source electrode 13 is grounded, a positive voltage is applied to the drain electrode 14, and a positive voltage equal to or greater than a threshold is applied to the gate electrodes 11a and 11b, an inversion layer (channel) is formed in the base regions 6a and 6b on the sidewall surface S1 of the trench 9a, resulting in an ON state. In the ON state, current flows from the drain electrode 14 to the source electrode 13 via the drain region 1, the drift layer 2, the current spreading layer 3, the inversion layer in the base regions 6a and 6b, and the source regions 7a and 7b. On the other hand, when the voltage applied to the gate electrodes 11a and 11b is less than the threshold, no inversion layer is formed in the base regions 6a and 6b, resulting in an OFF state, and no current flows from the drain electrode 14 to the source electrode 13. Note that the insulated gate electrode structure (10a, 11a) of the insulated gate semiconductor device according to the first embodiment is a one-sided channel structure, so no inversion layer (channel) is formed on the sidewall surface S2 of the trench 9a.

[0045] <<Major Effects of the First Embodiment>> According to the insulated gate semiconductor device of the first embodiment, the first end 41 of the gate bottom protection region 4a protrudes from the position of the sidewall surface S1 in a direction away from the insulated gate electrode structure (10a, 11a) in the direction in which the sidewall surface S1 and the sidewall surface S2 face each other. This makes it possible to suppress the electric field generated in the gate insulating film 10a. This makes it possible to make the gate insulating film 10a less susceptible to dielectric breakdown. For example, dielectric breakdown of the gate insulating film 10a can be suppressed.

[0046] Although the width of the trench 9a is substantially constant in the depth direction and the sidewall surfaces S1 and S2 are parallel in FIG. 1 , the present technology is not limited thereto. As shown in Variation 1 of FIG. 6 , the width of the trench 9a may be narrower as it deepens. More specifically, the sidewall surfaces S1 and S2 are formed obliquely toward the bottom surface S3. In this case, the first end 41 of the gate bottom protection region 4a protrudes in a direction away from the insulated gate electrode structure (10a, 11a) based on the position of the lower end S11 of the sidewall surface S1 in the first direction. If there is an arc-shaped curved portion at the corner between the bottom surface S3 and the sidewall surfaces S1 and S2 as shown in FIG. 6 , the lower end S11 is the lower end of the linear portion of the sidewall surface S1. Although the contact regions 8a and 8b are in contact with the sidewall surfaces S2 of the trenches 9a and 9b in FIG. 1 , they do not necessarily need to be in contact. 1, the gate bottom protection regions 4a and 4b are in contact with the lower surfaces of the trenches 9a and 9b, respectively, but the gate bottom protection regions 4a and 4b do not have to be in contact with the lower surfaces of the trenches 9a and 9b, respectively, as shown in Modification 2 of Fig. 17. In this case, if the distance between the lower surfaces of the trenches 9a and 9b and the gate bottom protection regions 4a and 4b is within 0.1 µm, the depletion layer extending from the gate bottom protection regions 4a and 4b toward the trenches 9a and 9b can reach them.

[0047] 7, the insulated gate semiconductor device according to the second embodiment differs from the insulated gate semiconductor device according to the first embodiment in that it includes first conductivity type (n-type) high concentration regions 16a, 16b, and 16c provided on the underside of base regions 6a, 6b, and 6c. The high concentration regions 16a, 16b, and 16c have the same configuration. Therefore, the following description will mainly focus on the configuration of high concentration region 16a.

[0048] The high-concentration region 16a is a counter-doped region (high-concentration portion of the JFET region) provided to suppress on-resistance. The high-concentration region 16a has a higher impurity concentration than the drift layer 2 and the current diffusion layer 3. The impurity concentration of the high-concentration region 16a is about one order of magnitude higher than that of the drift layer 2. The impurity concentration of the high-concentration region 16a is, for example, 5×10 １６ cm－３ That's it, 1 x 10 ２１ cm －３ The high-concentration region 16a is located deeper than the bottom surface of the base region 6a and shallower than the top surface of the gate bottom protection region 4a in the vertical direction. In the example shown in FIG. 7 , the top surface of the high-concentration region 16a does not contact the bottom surface of the base region 6a, and the bottom surface of the high-concentration region 16a does not contact the top surface of the gate bottom protection region 4a. Current diffusion layers 3 are interposed between the high-concentration region 16a and the base region 6a and between the high-concentration region 16a and the gate bottom protection region 4a. Therefore, n-type semiconductor regions are arranged in the order of the current diffusion layer 3, the high-concentration region 16a, and the current diffusion layer 3 in the vertical direction, and the impurity concentration peaks in the high-concentration region 16a in the vertical direction. If the current diffusion layer 3 is not provided, a drift layer 2 is interposed between the high-concentration region 16a and the base region 6a and between the high-concentration region 16a and the gate bottom protection region 4a. The high-concentration region 16a extends in the first direction. One end of the high concentration region 16a in the first direction contacts the trench 9a, and the other end contacts the connection region 5b. In this embodiment, the connection regions 5a and 5b include a part of the base region. For example, the connection region 5b is a region of the second conductivity type (p ＋ The semiconductor device includes a connection region 5b1 of a semiconductor type (semiconductor type) and a region 5b2 which is a part of the base region.

[0049] The simulation results shown in Figures 8 and 9 will be described below. In the graph of the simulation results shown in Figure 8, the horizontal axis represents the drain-source breakdown voltage (V) and the vertical axis represents the transistor on-resistance (mΩ cm ２) is shown. In the graph of the simulation results shown in FIG. 9, the horizontal axis represents the drain-source breakdown voltage (V) and the vertical axis represents the maximum electric field strength (V / cm) generated in the gate insulating film 10a. The drain-source breakdown voltage (BVdss) indicates the breakdown voltage performance of the transistor. FIGS. 8 and 9 show the results of simulations performed while changing the value of the protrusion amount d for a case where the high-concentration region 16a is provided (Group A) and a case where the high-concentration region 16a is not provided (Group B). The protrusion amount d of plot A1 in Group A is −0.1 (μm), the protrusion amount d of plot A2 is 0 (μm), the protrusion amount d of plot A3 is 0.05 (μm), the protrusion amount d of plot A4 is 0.1 (μm), the protrusion amount d of plot A5 is 0.15 (μm), and the protrusion amount d of plot A6 is 0.4 (μm). The amount of protrusion d of plot B1 included in group B is −0.3 (μm), the amount of protrusion d of plot B2 is −0.1 (μm), the amount of protrusion d of plot B3 is 0 (μm), the amount of protrusion d of plot B4 is 0.2 (μm), and the amount of protrusion d of plot B5 is 0.4 (μm). Note that in Figures 8 to 10, the numerical values ​​in parentheses for each plot indicate the value of the amount of protrusion d.

[0050] As shown in FIG. 8 , when the high-concentration region 16a is not provided (Group B), the on-resistance of the transistor increases with increasing protrusion amount d. In Group B, the on-resistance of plot B3 increases to approximately 2.5 times that of plot B1. In contrast, when the high-concentration region 16a is provided (Group A), a large increase in the on-resistance of the transistor can be suppressed even when the protrusion amount d is increased. This is because the high-concentration region 16a allows more carriers to accumulate on the underside of the base region 6a. The on-resistance of plots A1 to A5 is almost constant and lower than that of plot B1. The on-resistance of plot A6 is suppressed to approximately the same level as that of plot B1. By providing the high-concentration region 16a, the on-resistance can be suppressed even when the protrusion amount d is increased (more specifically, when it is set to a positive value). Furthermore, in Group A, the drain-source breakdown voltage increases as the protrusion amount d increases. By providing the high concentration region 16a and setting the protrusion amount d to approximately 0.05 μm or more and 0.15 μm or less (0.05 μm≦d≦0.15 μm), it is possible to achieve a breakdown voltage performance equivalent to that of plot B1 and an on-resistance lower than that of plot B1.

[0051] 9, when plots having the same protrusion amount d are compared, the maximum electric field strength generated in the gate insulating film 10a tends to be higher in the plots of Group A than in the plots of Group B. However, as the value of the protrusion amount d is increased in Group A, the maximum electric field strength decreases from plot A3 onwards. Furthermore, when the high concentration region 16a is provided and the protrusion amount d is in the range of about 0.05 μm or more and 0.15 μm or less (0.05 μm≦d≦0.15 μm), an electric field strength similar to that of plot B1 can be obtained.

[0052] Next, with reference to FIG. 10, the results of a simulation in which the electric field generated in the gate insulating film 10a was obtained while changing the impurity concentration of the n-type semiconductor region on the lower surface side of the base region 6a will be described. The n-type semiconductor region on the lower surface side of the base region 6a corresponds to the region in which the high concentration region 16a is provided. The simulation results shown in FIG. 10 are plotted against the impurity concentration (cm －３ 10 ) and the vertical axis represents the electric field (V / cm) generated in the gate insulating film 10a. The simulation results shown in FIG. 10 were obtained for the case where the protrusion amount d was −0.3 (μm) (Group C) and for plot A4 where the protrusion amount d was 0.1 (μm). Plot B1 of Group C corresponds to plot B1 in FIG. 8 .

[0053] As shown in Figure 10, it can be seen that in Group C, the higher the impurity concentration of the n-type semiconductor region, the stronger the electric field generated in the gate insulating film 10a. In the case of Group C, increasing the impurity concentration of the n-type semiconductor region increases the electric field generated in the gate insulating film 10a, which may cause dielectric breakdown. In contrast, in the case of plot A4, the electric field generated in the gate insulating film 10a is kept low compared to the plots of Group C with the same impurity concentration. When the protrusion amount d is set to a positive value, dielectric breakdown in the gate insulating film 10a can be made less likely to occur even if a high-concentration region 16a is provided.

[0054] <<Method of Manufacturing an Insulated Gate Semiconductor Device>> Next, an example of a method of manufacturing an insulated gate semiconductor device according to the second embodiment will be described. Note that the method of manufacturing an insulated gate semiconductor device described below is just one example, and it goes without saying that various other manufacturing methods, including this embodiment, can be implemented within the scope of the spirit of the claims. Furthermore, in the description of the method of manufacturing an insulated gate semiconductor device according to the second embodiment, the unit cell 17b shown in FIG. 7 will be used as an example.

[0055] First, as shown in FIG. 11, an n-type impurity such as nitrogen (N) is added. ＋An n-type semiconductor substrate (SiC substrate) 1 is prepared. The top surface of the SiC substrate 1 has an off-angle of, for example, 3 to 8 degrees from the {0001} plane. The top surface of the SiC substrate 1 is doped with n-type impurities such as N, and an n-type impurity having a lower impurity concentration than the SiC substrate 1 is formed. － The drift layer 2 made of n-type SiC is epitaxially grown. Next, n-type impurities such as nitrogen are added to the upper surface of the drift layer 2, and the current spreading layer 3 made of n-type SiC with a higher impurity concentration than the drift layer 2 is epitaxially grown. The current spreading layer 3 may be formed by ion implantation of n-type impurities such as nitrogen (N) into the upper part of the drift layer 2. Then, a mask pattern formed on the upper surface of the current spreading layer 3 is used as an ion implantation mask to selectively ion-implant p-type impurities such as aluminum (Al). By implanting the p-type impurities into a deep position in the current spreading layer 3, the p ＋ A gate bottom protection region 4b of the mold is selectively formed. The mask pattern may be a photoresist pattern formed using photolithography and dry etching techniques, or an oxide film pattern formed using CVD, lithography, and dry etching techniques. The mask pattern can be removed after use. In each of the following steps, a mask pattern having a pattern appropriate for the step is used.

[0056] 12, n-type impurities such as nitrogen (N) are selectively ion-implanted into the upper portion of the current diffusion layer 3. By implanting the n-type impurities into a shallow position in the current diffusion layer 3, an n-type high concentration region 16b is selectively formed. Then, using the mask pattern formed on the upper surface of the current diffusion layer 3 as an ion implantation mask, p-type impurities such as aluminum (Al) are selectively ion-implanted into the upper surface side of the current diffusion layer 3 and the upper surface side of the gate bottom protection region 4b. By implanting the p-type impurities into a shallow position in the current diffusion layer 3, a p-type high concentration region 16b is selectively formed. ＋ A mold connection region 5b1 is selectively formed.

[0057] 13, a base region 6 made of p-type SiC is epitaxially grown on the upper surface of the current spreading layer 3. Then, as shown in FIG. 14, n-type impurities such as nitrogen (N) and p-type impurities such as aluminum (Al) are selectively ion-implanted into the upper part of the base region 6. As a result, n ＋ type source region 7b and p ＋＋ A mold contact region 8b is selectively formed.

[0058] Next, as shown in FIG. 15, using the mask pattern as an etching mask, trenches 9b are selectively formed in the depth direction from the top surfaces of the source region 7b and contact region 8b by dry etching techniques such as reactive ion etching (RIE). The trenches 9b penetrate the source region 7b, contact region 8b, and base region 6, and further dig into the upper portion of the current spreading layer 3 to reach the gate bottom protection region 4b. The base region 6 is divided into base regions 6a and 6b. Next, as shown in FIG. 7, insulated gate electrode structures (10b, 11b), an interlayer insulating film 12b, a source electrode 13, a drain electrode 14, etc. are formed. Heat treatment to activate the ion-implanted impurities is performed at an appropriate timing.

[0059] <<Major Effects of Second Embodiment>> According to the insulated gate semiconductor device of the second embodiment, the high-concentration regions 16a, 16b, and 16c of the first conductivity type, which have a higher impurity concentration than the drift layer 2, are provided on the lower surfaces of the base regions 6a, 6b, and 6c, and therefore the on-resistance value can be suppressed. More specifically, when the high-concentration regions 16a, 16b, and 16c are provided, the on-resistance value of the transistor can be suppressed even if the value of the protrusion amount d is large (for example, even if it is set to a positive value).

[0060] Furthermore, in the insulated gate semiconductor device according to the second embodiment, the protrusion amount d of the first end portion is set to 0.05 μm or more and 0.15 μm or less, and therefore, it is possible to achieve a breakdown voltage performance equivalent to that of plot B1, in which the protrusion amount d is −0.3 μm and no high-concentration region is provided, and also to achieve an on-resistance lower than that of plot B1.

[0061] Furthermore, in the insulated gate semiconductor device according to the second embodiment, high concentration regions 16 a, 16 b, and 16 c are located deeper than base regions 6 a, 6 b, and 6 c and shallower than gate bottom protection regions 4 a and 4 b, allowing carriers to be efficiently accumulated on the underside of base regions 6 a, 6 b, and 6 c, thereby suppressing the on-resistance of the transistor.

[0062] As shown in Modification 1 of FIG. 16 , the upper surface of the high-concentration region 16 a may be in contact with the lower surface of the base region 6 a, and the lower surface may be in contact with the gate bottom protection region 4 a and the current diffusion layer 3. Similarly, the upper surface of the high-concentration region 16 b may be in contact with the lower surface of the base region 6 b, and the lower surface may be in contact with the gate bottom protection region 4 b and the current diffusion layer 3. If the current diffusion layer 3 is not provided, the lower surfaces of the connection regions 5 a and 5 b are in contact with the drift layer 2 instead of the current diffusion layer 3. Furthermore, as shown in Modification 2 of FIG. 18 , the gate bottom protection regions 4 a and 4 b do not have to be in contact with the lower surfaces of the trenches 9 a and 9 b, respectively. In this case, as long as the distance between the lower surfaces of the trenches 9 a and 9 b and the gate bottom protection regions 4 a and 4 b is within 0.1 μm, the depletion layers extending from the gate bottom protection regions 4 a and 4 b toward the trenches 9 a and 9 b can reach them.

[0063] Although the first and second embodiments of the present disclosure have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0064] For example, although a MOSFET is exemplified as the semiconductor device according to the first and second embodiments, ＋ Instead of the drain region 1 of type p ＋ The present invention can also be applied to an insulated gate bipolar transistor (IGBT) having a collector region of a type similar to that of a reverse-conducting IGBT (RC-IGBT) or a reverse-blocking insulated gate bipolar transistor (RB-IGBT).

[0065] Furthermore, the configurations disclosed in the first and second embodiments can be combined as appropriate within the scope of not causing any contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description.

[0066] REFERENCE SIGNS LIST 1 Drain region 2 Drift layer 3 Current diffusion layer 4a, 4b Gate bottom protection region 5a, 5b Connection region 6a, 6b, 6c Base region 7a, 7b, 7c Source region 8a, 8b Contact region 9a, 9b Trench 10a, 10b Gate insulating film (insulated gate electrode structure) 11a, 11b Gate electrode (insulated gate electrode structure) 12a, 12b Interlayer insulating film 13 Source electrode 14 Drain electrode 15 Semiconductor substrate 16a, 16b, 16c Highly doped region 17a, 17b Unit cell 41 First end d Protrusion amount S1 Side wall surface S2 Side wall surface S3 Bottom surface S11 Bottom end

Claims

a first conductivity type semiconductor substrate; a trench provided in the semiconductor substrate and having a first sidewall surface, a second sidewall surface opposing the first sidewall surface along a first direction, and a bottom surface; an insulated gate electrode structure embedded in the trench; a second conductivity type base region provided in contact with the first sidewall surface; a first conductivity type main electrode region provided on an upper surface side of the base region in contact with the first sidewall surface; a second conductivity type gate bottom protection region provided in contact with the bottom surface of the trench; a second conductivity type connection region provided on an upper surface side of the gate bottom protection region in contact with the second sidewall surface; and a second conductivity type contact region provided on an upper surface side of the connection region; 2. The insulated gate semiconductor device according to claim 1, wherein said first end portion protrudes along said first direction in a direction away from said insulated gate electrode structure, with the position of the lower end of said first sidewall surface as a reference.

3. The insulated gate semiconductor device according to claim 1 or 2, wherein the semiconductor substrate includes a drift layer, and a high concentration region of the first conductivity type having a higher impurity concentration than the drift layer is provided on the lower surface side of the base region.

4. The insulated gate semiconductor device according to claim 3, wherein the protrusion amount of said first end is not less than 0.05 μm and not more than 0.15 μm.

5. The insulated gate semiconductor device according to claim 3, wherein the high concentration region is provided at a position deeper than the base region and shallower than the gate bottom protection region.

6. The insulated gate semiconductor device according to claim 3, wherein the semiconductor substrate includes a current diffusion layer provided on an upper surface side of the drift layer and having a higher impurity concentration than the drift layer, and the high concentration region has a higher impurity concentration than the current diffusion layer.

Images