Multilayer ceramic capacitor

Abstract

An objective of the present invention is to provide a highly reliable multilayer ceramic capacitor by suppressing migration caused by moisture penetrating to an external electrode. A multilayer ceramic capacitor (1) comprises a laminated body that includes an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers that are alternately laminated in a lamination direction, the laminated body having two main surfaces facing each other in the lamination direction and two end surfaces facing each other in a length direction, and a pair of external electrodes connected to the internal electrode layers at the two end surfaces, wherein, at an end portion in the length direction of a main surface external electrode portion (40T) extending on at least one of the two main surfaces, a reinforcing resin (40S) is disposed between the external electrodes and a main surface (TS1).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have traditionally been used as small, high-capacity electronic components not only in precision instruments but are also finding wider applications in fields such as electric vehicles and medical equipment. However, there is a growing demand for these multilayer ceramic capacitors to be even smaller, have larger capacitance, and are more reliable.

[0003] In recent years, in order to absorb stress generated by sudden thermal changes and the like, a multilayer ceramic capacitor has become known, as disclosed in Patent Document 1, which is provided with external electrodes in which a resin electrode layer is formed on the surface of a base electrode layer and a plating layer is further formed on the surface of that resin electrode layer.

[0004] JP 2024-83200 A

[0005] However, when a current is passed through an external electrode that includes a resin electrode layer as a constituent member, the infiltration of moisture can cause metal to precipitate, resulting in migration, which can cause electrical conduction between the external electrodes.

[0006] An object of the present invention is to provide a highly reliable multilayer ceramic capacitor that suppresses migration caused by moisture penetration into external electrodes.

[0007] The inventor discovered that the occurrence of migration can be suppressed by placing a reinforcing resin between the main surface and the end of the main surface external electrode portion of the external electrode extending on the main surface of the laminate, and thereby completed the present invention.

[0008] That is, the present invention is a multilayer ceramic capacitor comprising: an inner layer portion including a plurality of inner layer dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction; and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposing each other in the stacking direction, two side surfaces opposing each other in a width direction perpendicular to the stacking direction, and two end faces opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes connected to the internal electrode layers at the two end faces, wherein a reinforcing resin is arranged between the external electrodes and the main surfaces at the lengthwise ends of the main surface external electrode portions extending on at least one of the two main surfaces.

[0009] According to the present invention, it is possible to provide a highly reliable multilayer ceramic capacitor that suppresses migration caused by the penetration of moisture into the external electrodes.

[0010] 1 is a perspective view showing the appearance of a multilayer ceramic capacitor of the present invention. 2 is a cross-sectional view of the multilayer ceramic capacitor of the present invention taken along line II-II shown in FIG. 1. 3 is a cross-sectional view of the multilayer ceramic capacitor of the present invention taken along line III-III shown in FIG. 1. 4 is an enlarged view of region IV shown in FIG. 2. 5 is an enlarged view of another embodiment of region IV shown in FIG. 2. 6 is a cross-sectional view of another embodiment of the multilayer ceramic capacitor of the present invention taken along line II-II shown in FIG.

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] (Multilayer Ceramic Capacitor) FIG. 1 is a perspective view showing a multilayer ceramic capacitor 1, FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1 taken along line II-II, and FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1 taken along line III-III. FIG. 4 is an enlarged view of region IV shown in FIG. 2. FIG. 5 is an enlarged view of another embodiment of region IV shown in FIG. 2. FIG. 6 is a cross-sectional view of another embodiment of the multilayer ceramic capacitor 1 shown in FIG. 1. FIG. 7 is an enlarged view of region VII shown in FIG. 6. FIG. 8 is an enlarged view of another embodiment of region VII shown in FIG. 6. Note that line II-II in FIG. 1 passes through the center in the width direction W of the multilayer ceramic capacitor 1, which will be described later.

[0013] 1 to 3 and 6 show an xyz Cartesian coordinate system. The x direction is the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10, the y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the z direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also referred to as an LT cross section, and the cross section shown in FIG. 3 is also referred to as a WT cross section. Note that the length direction L, the width direction W, and the stacking direction T do not necessarily have to be orthogonal to each other, and may intersect each other.

[0014] The size of the multilayer ceramic capacitor is preferably such that the length L is 0.2 mm to 10 mm, the width W is 0.1 mm to 10 mm, and the stacking direction T is 0.1 mm to 10 mm.

[0015] (Laminate) The laminate 10 has a substantially rectangular parallelepiped shape and has a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L. The surface of each surface may be uneven or may be roughened. Note that when there is no need to particularly distinguish between the first main surface TS1 and the second main surface TS2, they will be collectively referred to as the main surface TS; when there is no need to particularly distinguish between the first end surface LS1 and the second end surface LS2, they will be collectively referred to as the end surface LS; and when there is no need to particularly distinguish between the first side surface WS1 and the second side surface WS2, they will be collectively referred to as the side surface WS.

[0016] It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.

[0017] 2 and 3 , the laminate 10 has a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100. Note that, when there is no need to particularly distinguish between the first outer layer portion 201 and the second outer layer portion 202, they will be collectively described as the outer layer portion 200.

[0018] The inner dielectric layer 20i constituting the inner layer portion 100 and the outer dielectric layer 20o constituting the outer layer portion 200 may have different component compositions because the inner layer portion 100 and the outer layer portion 200 are required to have different functions. For example, the inner dielectric layer 20i is required to have a high dielectric constant, while the outer dielectric layer 20o is required to have high moisture resistance, weather resistance, and strength. The dielectric layer constituting the inner layer portion 100 will be referred to as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer portion 200 will be referred to as the outer dielectric layer 20o. However, when there is no need to particularly distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they will be collectively referred to as the dielectric layer 20.

[0019] (Inner Layer Portion) The inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged opposite each other with the inner dielectric layers 20i interposed therebetween. The inner layer portion 100 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0020] The material of the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as a secondary component to the material of the dielectric layer 20.

[0021] The thickness of the inner dielectric layer 20i is not particularly limited, but is preferably, for example, 0.2 μm or more and 15 μm or less. By reducing the thickness of the inner dielectric layer 20i, the capacitance can be improved.

[0022] (Outer Layer Portions) The first outer layer portion 201 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 202 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 201 is disposed between the first main surface TS1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 202 is disposed between the second main surface TS2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 201 and the second outer layer portion 202 do not include the internal electrode layer 30.

[0023] The outer layer portion 200 is formed of an insulating material. The first outer layer portion 201 and the second outer layer portion 202 can each be composed of a plurality of outer dielectric layers 20o, or may be composed of a single outer dielectric layer 20o. The outer dielectric layer 20o can be composed of the same type of dielectric material as the inner dielectric layer 20i, or may contain a different component from the inner dielectric layer 20i depending on the desired function.

[0024] (Internal Electrode Layers) The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0025] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0026] The opposing electrode portions 311 and 321 face each other via the inner dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the opposing electrode portions 311 and 321 are not particularly limited and may be, for example, approximately rectangular. The opposing electrode portions 311 and 321 are portions that generate electrostatic capacitance and essentially function as capacitors.

[0027] The lead electrode portion 312 extends from the counter electrode portion 311 toward the first end surface LS1 of the laminate 10 and is exposed at the first end surface LS1. The lead electrode portion 322 extends from the counter electrode portion 321 toward the second end surface LS2 of the laminate 10 and is exposed at the second end surface LS2. The lengths in the width direction W of the counter electrode portion 311 and the lead electrode portion 312 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed first end surface LS1. The lengths in the width direction W of the counter electrode portion 321 and the lead electrode portion 322 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed second end surface LS2.

[0028] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end surface LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end surface LS1 of the laminate 10, i.e., the first external electrode 41.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 contain metallic Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a main component, or as a component other than the main component, at least one selected from metals such as Cu, Ag, Pd, Sn, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the inner dielectric layer 20i. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0030] Furthermore, Sn regions containing Sn may be formed at the interfaces between the first and second internal electrode layers 31, 32 and the internal dielectric layer 20i.

[0031] The thicknesses of the first internal electrode layers 31 and the second internal electrode layers 32 are not particularly limited, but are preferably, for example, 0.2 μm or more and 2.0 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layers 31 and the second internal electrode layers 32 is also not particularly limited.

[0032] The thicknesses of the inner dielectric layers 20i and the internal electrode layers 30 may be measured by, for example, observing the LT cross section of the laminate exposed by polishing near the center in the width direction with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0033] 2 , the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end gap LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the inner dielectric layer 20i, while the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the inner dielectric layer 20i. The first end gap LG1 is a portion that functions as a lead electrode portion to the first end surface LS1 of the first internal electrode layer 31, and the second end gap LG2 is a portion that functions as a lead electrode portion to the second end surface LS2 of the second internal electrode layer 32. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0034] The electrode opposing portion L30 is located with the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is located with the lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is located with the lead-out electrode portion 322 of the second internal electrode layer 32.

[0035] As shown in Fig. 3, the laminate 10 has, in the width direction W, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap WG1 and a second side gap WG2 arranged to sandwich the electrode facing portion W30. The first side gap WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side gap WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side gap WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap WG1 and the second side gap WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also called W gaps.

[0036] (External Electrodes) The external electrodes 40 are connected to the internal electrode layers 30 at the two end faces LS of the laminate 10. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0037] The first external electrode 41 is disposed on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 extends from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. The first external electrode 41 also extends from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2. In this manner, the first external electrode 41 is composed of an end face external electrode portion 41L covering the end face LS of the laminate 10, a main surface external electrode portion 41T covering a portion of the main surface TS of the laminate 10, and a side face external electrode portion 41W covering a portion of the side surface WS of the laminate 10.

[0038] The second external electrode 42 is disposed on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 extends from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2. The second external electrode 42 also extends from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2. In this manner, the second external electrode 42 is composed of an end face external electrode portion 42L covering the end face LS of the laminate 10, a main face external electrode portion 42T covering a portion of the main face TS of the laminate 10, and a side face external electrode portion 42W covering a portion of the side face WS of the laminate 10.

[0039] In addition, when there is no need to particularly distinguish between the first external electrode 41 and the second external electrode 42, the first external electrode 41 and the second external electrode 42 will be collectively referred to as the external electrode 40, the end surface external electrode portion 41L of the first external electrode 41 and the end surface external electrode portion 42L of the second external electrode 42 will be collectively referred to as the end surface external electrode portion 40L of the external electrode 40, the side surface external electrode portion 41W of the first external electrode 41 and the side surface external electrode portion 42W of the second external electrode 42 will be collectively referred to as the side surface external electrode portion 40W of the external electrode 40, and the main surface external electrode portion 41T of the first external electrode 41 and the main surface external electrode portion 42T of the second external electrode 42 will be collectively referred to as the main surface external electrode portion 40T of the external electrode 40.

[0040] As shown in Figure 2, the first external electrode 41 is composed of a base electrode layer 411 arranged on the surface of the laminate 10, a resin electrode layer 412 arranged on the surface of the base electrode layer 411, and a plating layer 413 arranged on the surface of the resin electrode layer 412.

[0041] In addition, the second external electrode 42 is composed of a base electrode layer 421 arranged on the surface of the laminate 10, a resin electrode layer 422 arranged on the surface of the base electrode layer 421, and a plating layer 423 arranged on the surface of the resin electrode layer 422.

[0042] As shown in FIG. 6 , the first external electrode 41 may have a structure in which a resin electrode layer 412 is disposed directly on the surface of the laminate 10 and a plating layer 413 is disposed on the surface of the resin electrode layer 412 .

[0043] The second external electrode 42 may also be configured such that a resin electrode layer 422 is directly disposed on the surface of the laminate 10 and a plating layer 413 is disposed on the surface of the resin electrode layer 422 .

[0044] (Base Electrode Layer) The base electrode layer 411 and the base electrode layer 421 can be fired layers containing metal and glass. Examples of the glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, Li, and the like. Specific examples include borosilicate glass. The metal contains Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, and Au, or alloys such as Ag-Pd alloys, as a main component, or may contain at least one selected from the group consisting of Ni, Ag, Pd, and Au, as a main component, or as a component other than the main component.

[0045] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0046] The thickness of each of the base electrode layer 411 and the base electrode layer 421 is not particularly limited, and may be 2 μm or more and 220 μm or less.

[0047] (Resin Electrode Layer) The resin electrode layer 412 and the resin electrode layer 422 contain a resin and a conductive filler, and preferably contain a thermosetting resin and a metal filler. Examples of the thermosetting resin include epoxy resin, phenolic resin, and acrylic resin. Examples of elements constituting the metal filler include Ag and Cu, and these may be combined.

[0048] The resin electrode layer 412 and the resin electrode layer 422 can be formed by applying a conductive paste containing a resin and a conductive filler to the laminate 10. The resin electrode layer may be a multi-layered layer.

[0049] The thickness of each of the resin electrode layers 412 and 422 is not particularly limited, and may be 2 μm or more and 220 μm or less.

[0050] (Plating Layer) The plating layer 413 covers the surface of the resin electrode layer 412, and the plating layer 423 covers the surface of the resin electrode layer 422. The plating layer 413 and the plating layer 423 can contain at least one selected from, for example, metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag—Pd alloys.

[0051] The plating layer 413 and the plating layer 423 may each be formed of multiple layers. FIGS. 4, 5, 7, and 8 show an embodiment in which the plating layer 423 is formed of a Ni plating layer 423a and a Sn plating layer 423b. Preferably, the plating layer has a two-layer structure formed of different components. The Ni plating layer 423a prevents the base electrode layer 421 from being eroded by solder when mounting ceramic electronic components, and the Sn plating layer 423b improves the wettability of the solder when mounting ceramic electronic components, facilitating mounting. The plating layer 413 and the plating layer 423 may each have a three-layer structure, for example, by stacking Cu plating, Ni plating, and Sn plating. The outermost layer may be an Au plating layer.

[0052] The thickness of each of the plating layers 413 and 423 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0053] (Reinforcing Resin) The reinforcing resin 40S is disposed between the main surface external electrode portion 40T and the main surface TS at the end of the main surface external electrode portion 40T in the length direction L. By disposing the reinforcing resin 40S in this manner, the intrusion of moisture from the end of the external electrode 40 is suppressed, and the deposition (migration) of metal ions on the surface of the laminate 10 can be suppressed.

[0054] 4 and 5 show the state of the reinforcing resin 40S in the main surface external electrode portion 40T of the external electrode 40 on which the base electrode layer 421 is arranged. Also, Fig. 7 and Fig. 8 show the state of the reinforcing resin 40S in the external electrode 40 on which the base electrode layer 421 is not arranged.

[0055] 4 and 7 , the reinforcing resin 40S can be disposed at the end of the main surface external electrode portion 40T in the length direction L, between the first main surface TS1 and the plating layer 423. By disposing the reinforcing resin 40S between the first main surface TS1 and the plating layer 423, it is possible to prevent moisture from penetrating into the main surface external electrode portion 40T through a path between the first main surface TS1 and the plating layer 423, and to suppress migration caused by deposition of metal of the internal electrode layer 30 on the surface of the laminate 10.

[0056] 5 and 8 , the reinforcing resin 40S can be disposed at the end of the main surface external electrode portion 40T in the length direction L, between the first main surface TS1 and the resin electrode layer 422. By disposing the reinforcing resin 40S between the first main surface TS1 and the resin electrode layer 422, it is possible to prevent moisture from penetrating into the main surface external electrode portion 40T through a path between the first main surface TS1 and the resin electrode layer 422, and it is possible to suppress migration caused by deposition of metal of the internal electrode layer 30 on the surface of the laminate 10.

[0057] By placing reinforcing resin 40S between the first main surface TS1 and the plating layer 423, as well as between the first main surface TS1 and the resin electrode layer 422, it is possible to reliably suppress the intrusion of moisture from the end of the external electrode 40, thereby effectively preventing migration.

[0058] In a cross section LT parallel to the length direction L and the stacking direction T at the center of the width direction W of the multilayer ceramic capacitor, the length L1 of the reinforcing resin 40S disposed between the main surface external electrode portion 40T and the main surface TS is defined as follows: if L1 is too large, stress is applied to the main surface external electrode portion 40T, making the external electrode 40 more likely to crack. Furthermore, the bonding area between the main surface external electrode portion 40T and the main surface TS is reduced, increasing the equivalent series resistance (ESR). On the other hand, if L1 is too small, it is not possible to prevent moisture from entering from the outside, and migration cannot be suppressed. Therefore, in a multilayer ceramic capacitor 15 size (L: 1.0 mm, W, T: 0.5 mm), the length L1 of the reinforcing resin 40S is preferably 2 μm or more and 80 μm or less.

[0059] The reinforcing resin 40S shown in the embodiment is disposed between the main surface TS and the main surface TS at the end in the length direction L of the main surface external electrode portion 40T extending on the two main surfaces TS, but the present invention is not limited to disposing the reinforcing resin 40S at the end of the main surface external electrode portion 40T extending on the two main surfaces TS in this manner. In other words, the reinforcing resin 40S can also be effective by disposing it between the main surface TS and the end of the main surface external electrode portion 40T extending along one of the two main surfaces TS.

[0060] The reinforcing resin 40S shown in the embodiment is provided in the main surface external electrode portions 40T of both the first external electrode 41 and the second external electrode 42, but it may also be provided in the main surface external electrode portion 40T of either the first external electrode 41 or the second external electrode 42.

[0061] Similarly, the reinforcing resin 40S can be disposed between the side surface external electrode portion 40W and the side surface WS at the end portion in the length direction L of the side surface external electrode portion 40W extending on the surfaces of the two side surfaces WS. The reinforcing resin 40S may also be disposed between the end portion of the side surface external electrode portion 40W extending along one of the two side surfaces WS and the main surface TS.

[0062] The reinforcing resin 40S can be provided in the side external electrode portions 40W of both the first external electrode 41 and the second external electrode 42, but may also be provided in the side external electrode portion 40W of either the first external electrode 41 or the second external electrode 42.

[0063] The reinforcing resin 40S can be arranged on the main surface external electrode portion 40T on either of the two main surfaces TS, which will be the mounting surface when the multilayer ceramic capacitor is mounted, or on the side surface external electrode portion 40W on either of the two side surfaces WS, but is not limited to this and may be arranged on all of the main surface external electrode portions 40T on the two main surfaces TS and the side surface external electrode portions 40W on the two side surfaces WS.

[0064] The reinforcing resin 40S may be primarily composed of a thermosetting resin, such as an epoxy resin or an acrylic resin, and may further contain a silane coupling agent, a pigment, or an imidazole as a secondary component.

[0065] The reinforcing resin 40S preferably has a suitable flexibility, and the Young's modulus of the reinforcing resin 40S is preferably 2 GPa or more and 10 GPa or less.

[0066] In a cross section LT parallel to the length direction L and the stacking direction T at the center of the width direction W of the multilayer ceramic capacitor 1, the length L of the reinforcing resin 40S disposed between the main surface external electrode portion 40T and the main surface TS is defined as L1, and the length L from the tip of the main surface external electrode portion 40T to the end surface LS of the laminate 10 is defined as L2. The ratio L1 / L2 of L1 to L2 is preferably 0.011 or greater and 0.749 or less. Adjusting the length L of the reinforcing resin 40S in this way can prevent moisture from penetrating the external electrode 40 and suppress migration. If the L1 / L2 ratio is less than 0.011, the length L1 of the reinforcing resin 40S is insufficient, making it impossible to suppress migration. Furthermore, if the L1 / L2 ratio exceeds 0.749, the adhesive area between the main surface external electrode portion 40T and the main surface TS decreases, resulting in an increased equivalent series resistance (ESR).

[0067] The reinforcing resin 40S can also be disposed on the portions of the main surface TS that are not covered by the main surface external electrode portions 40T. When the reinforcing resin 40S is disposed on the entire main surface TS that is not covered by the main surface external electrode portions 40T, the metal of the internal electrode layer 30 does not precipitate on the surface of the laminate 10, and migration can be reliably suppressed.

[0068] A pedestal (not shown) containing a conductive metal as a main component may be disposed on the surface of the main surface external electrode portion 40T in the stacking direction T. By disposing the pedestal, it is possible to reduce vibration noise (ringing) of the wiring board that occurs due to the electrostrictive effect of the multilayer ceramic capacitor 1.

[0069] The pedestal may be arranged, for example, by attaching a block-shaped spacer mainly composed of a conductive metal to the surface of the main surface external electrode portion 40T. Alternatively, the pedestal may be formed by applying a paste mainly composed of a conductive metal to the surface of the main surface external electrode portion 40T and drying it.

[0070] (Manufacturing of Multilayer Ceramic Capacitor) Next, an example of a method for manufacturing a multilayer ceramic capacitor will be described.

[0071] First, a ceramic green sheet and a conductive paste for the internal electrodes are prepared by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto the surface of a carrier film using a die coater, gravure coater, microgravure coater, or the like. The conductive paste for the internal electrodes contains a binder and a solvent, and known organic binders and organic solvents can be used. The conductive paste for the internal electrodes forms the internal electrode layer 30.

[0072] Next, a conductive paste for internal electrodes is printed in a predetermined pattern on the ceramic green sheets by, for example, screen printing or gravure printing, thereby forming an internal electrode pattern.

[0073] Next, a predetermined number of ceramic green sheets for outer layers, which do not have internal electrode patterns formed thereon, are stacked on top of which ceramic green sheets with internal electrodes formed thereon are stacked in order, and a predetermined number of ceramic green sheets for outer layers are stacked on top of these to produce a laminate sheet. The ceramic green sheets form the dielectric layers 20 that constitute the multilayer ceramic capacitor 1.

[0074] The resulting laminated sheet is pressed in the lamination direction using a means such as a hydrostatic press to produce a laminated block. The laminated block is then cut to a predetermined size to produce laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0075] The laminated chip is then fired to produce the laminate 10. The firing temperature at this time depends on the materials of the dielectric and the internal electrodes, but is preferably 900° C. or higher and 1300° C. or lower.

[0076] A conductive paste for external electrodes is applied to both end surfaces of the obtained laminate 10 and baked to form base electrode layers 411, 421. The baking temperature at this time is preferably 700° C. or higher and 900° C. or lower. Thereafter, resin electrode layers 412, 422 are formed, and then plating layers 413, 423 are formed.

[0077] (Formation of Reinforcing Resin) The reinforcing resin 40S can be formed by dissolving a thermosetting resin in a solvent such as diethylene glycol monobutyl ether and adjusting the viscosity.

[0078] When the end portions in the length direction L of the principal surface external electrode portions 40T are peeled off from the principal surface TS of the laminate 10 and a low-viscosity thermosetting resin solution is applied onto the principal surface external electrode portions 40T or onto the laminate 10, the thermosetting resin solution spreads between the principal surface external electrode portions 40T and the principal surface TS, and the thermosetting resin solution can be disposed between the end portions of the principal surface external electrode portions 40T and the principal surface TS. Note that application may be performed under reduced pressure in order to efficiently dispose the thermosetting resin solution between the end portions of the principal surface external electrode portions 40T and the principal surface TS.

[0079] Thereafter, a heat treatment is performed to harden the thermosetting resin, thereby forming the reinforcing resin 40S.

[0080] Each evaluation test was carried out on the multilayer ceramic capacitors. In each evaluation test, multilayer ceramic capacitors having different ratios L1 / L2 (where L1 is the length L of the reinforcing resin 40S in the length direction L and L2 is the length L from the tip of the main surface external electrode portion 40T to the end surface LS of the laminate 10 in the length direction L) were used as samples.

[0081] (Measurement of Crack Occurrence Rate) A sample multilayer ceramic capacitor was mounted on a 1.6 mm thick JIS substrate (glass epoxy substrate) using solder. A pressing tool was pressed against the substrate from the side of the substrate where the multilayer ceramic capacitor was not mounted, bending the substrate and applying mechanical stress. The pressing tool was pressed for 5 seconds, and the substrate was bent by 10 mm. The multilayer ceramic capacitor was then removed from the substrate and polished perpendicular to the substrate surface. The cross section of the ceramic body was observed for cracks, and the percentage of samples with cracks was calculated. Thirty samples were collected for each level of the ratio L1 / L2 of length L1 to length L2.

[0082] (Measurement of Migration Defect Rate) To evaluate the state of migration, a multilayer ceramic capacitor was mounted on a substrate as a sample, and a high-temperature load test was performed in which a voltage of 1.5 WV was applied between the external electrodes at 140°C and maintained for 2000 hours. The state of migration on the sample surface was then observed with a digital microscope, and the migration defect rate was calculated using the following formula from the number of samples in which Ag migration was observed and the number of samples used for evaluation. The number of samples for each level of the ratio L1 / L2 of length L1 to length L2 was 30. Migration defect rate (%) = (number of samples in which Ag migration was observed / number of samples used for evaluation) × 100

[0083] (Measurement of Equivalent Series Resistance (ESR)) The equivalent series resistance (ESR) was measured at a frequency of 10 MHz. The number of samples for each level of the ratio L1 / L2 of the length L1 to the length L2 was 10.

[0084] The evaluation criteria were as follows: a crack occurrence rate of 10% or more was rated as × (fail); a crack occurrence rate of less than 10% and a migration defect rate of less than 5% was rated as ○ (acceptable pass); and a crack occurrence rate of less than 10%, a migration defect rate of less than 3%, and an ESR of less than 16 mΩ was rated as ⊚ (pass).

[0085]

[0086] As shown in Table 1, good results were confirmed in Examples 1 to 6, in which the ratio L1 / L2 of the length L1 to the length L2 was 0.011 or more and 0.749 or less. Particularly good results were confirmed in Examples 2 to 5, in which the ratio L1 / L2 of the length L1 to the length L2 was 0.025 or more and 0.578 or less.

[0087] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and can be embodied in various forms without departing from the gist of the present invention.

[0088] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 Counter electrode portion 312 Lead electrode portion 32 Second internal electrode layer 321 Counter electrode portion 322 Lead electrode portion 40 External electrode 40S Reinforcing resin 40T Main surface external electrode portion 41 First external electrode 411 Base electrode layer 412 Resin electrode layer 413 Plating layer 42 Second external electrode 421 Base electrode layer 422 Resin electrode layer 423 Plating layer 100 Internal layer portion 200 External layer portion 201 First external layer portion 202 Second external layer portion L30 Electrode opposing portion LG1 First end gap portion LG2 Second end gap portion W30 Electrode opposing portion WG1 First side gap portion WG2 Second side gap portion L: Length direction T: Stacking direction W: Width direction LS: End face LS1: First end face LS2: Second end face TS: Main face TS1: First main face TS2: Second main face WS: Side face WS1: First side face WS2: Second side face

Claims

1. A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction; and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposing each other in the stacking direction, two side surfaces opposing each other in a width direction perpendicular to the stacking direction, and two end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes connected to the internal electrode layers at the two end surfaces, wherein a reinforcing resin is disposed between the external electrodes and the main surfaces at the lengthwise ends of the main surface external electrode portions extending on at least one of the two main surfaces.

2. A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction; and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposing each other in the stacking direction, two side surfaces opposing each other in a width direction perpendicular to the stacking direction, and two end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes connected to the internal electrode layers at the two end surfaces, wherein a reinforcing resin is disposed between the external electrodes and the side surfaces at the lengthwise ends of side surface external electrode portions extending on at least one of the two side surfaces.

3. The multilayer ceramic capacitor according to claim 1, wherein the external electrodes comprise: a resin electrode layer disposed on the laminate and containing a metal and a resin; and a plating layer disposed on the resin electrode layer; and the reinforcing resin is disposed between the main surface and the plating layer at the end of the main surface external electrode portion in the longitudinal direction.

4. The multilayer ceramic capacitor according to claim 2, wherein the external electrode comprises: a resin electrode layer disposed on the laminate and containing a metal and a resin; and a plating layer disposed on the resin electrode layer; and the reinforcing resin is disposed between the side surface and the plating layer at the end of the side surface external electrode portion in the longitudinal direction.

5. The multilayer ceramic capacitor according to claim 3, wherein the reinforcing resin is disposed between the main surface and the resin electrode layer at the end portions in the length direction of the main surface external electrode portions.

6. The multilayer ceramic capacitor according to claim 4, wherein the reinforcing resin is disposed between the side surface and the resin electrode layer at the end of the side surface external electrode portion in the length direction.

7. A multilayer ceramic capacitor according to claim 3 or 4, wherein the external electrodes have a base electrode layer containing metal and glass between the laminate and the resin electrode layer.

8. The multilayer ceramic capacitor according to claim 1 or 2, wherein the reinforcing resin contains a thermosetting resin as a main component.

9. The multilayer ceramic capacitor according to claim 1, wherein, in a cross section at the center in the width direction parallel to the length direction and the stacking direction, when the length in the length direction of the reinforcing resin arranged between the main surface and the main surface external electrode portion is L1, and the length in the length direction from the tip of the main surface external electrode portion to the end face of the laminate is L2, the ratio L1 / L2 of L1 to L2 is 0.011 or more and 0.749 or less.

10. The multilayer ceramic capacitor according to claim 2, wherein, in a cross section parallel to the length direction and the width direction at the center of the stacking direction, when the length in the length direction of the reinforcing resin arranged between the side surface and the side surface external electrode portion is L1 and the length in the length direction from the tip of the side surface external electrode portion to the end face of the laminate is L2, the ratio L1 / L2 of L1 to L2 is 0.011 or more and 0.749 or less.

11. The multilayer ceramic capacitor according to claim 1, wherein the reinforcing resin is also disposed on portions of the main surfaces that are not covered by the main surface external electrode portions.

12. The multilayer ceramic capacitor according to claim 2, wherein the reinforcing resin is also disposed on the side surfaces in areas not covered by the side surface external electrode portions.

13. The multilayer ceramic capacitor according to claim 1 or 2, wherein the Young's modulus of the reinforcing resin is 2 GPa or more and 10 GPa or less.

14. The multilayer ceramic capacitor according to claim 1, wherein a base containing a conductive metal as a main component is disposed on the surface of the main surface external electrode portion in the lamination direction.

15. The multilayer ceramic capacitor according to claim 2, wherein a base containing a conductive metal as a main component is disposed on the surface in the width direction of the side surface external electrode portion.

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