Three-terminal in-sensor memory device and operation method thereof

Abstract

The present invention relates to a three-terminal in-sensor memory device capable of adaptively adjusting the degree of controlling a source-drain current, and an operation method thereof. The three-terminal in-sensor memory device according to an embodiment of the present invention comprises: a first electrode; a second electrode; and an insulating layer forming a conductive filament while interposed between the first electrode and the second electrode.

Description

Three-terminal inductive memory device and method of operating the three-terminal inductive memory device

[0001] The present invention relates to a three-terminal inductive memory device and an operating method of the three-terminal inductive memory device.

[0002] As interest in artificial neural networks has increased recently, research on neuromorphic devices that implement them in hardware is actively underway.

[0003] Neuromorphic devices mimic the structure of neurons and synapses that make up the human brain's nervous system. They typically consist of a pre-neuron, a synapse, and a post-neuron. A typical neuromorphic device consists of an input section, a synapse array, and an output section. The input section functions as a pre-neuron, the output section as a post-neuron, and the synapse array functions as a synapse.

[0004] However, since the neuromorphic devices known in the past have a hardware-fixed structure, they cannot properly control the various structures of neural networks that are being studied recently.

[0005] Conventional sensing and neuromorphic synaptic devices utilize a three-terminal memory element with a transistor structure consisting of a source electrode, a drain electrode, and a gate electrode to control the storage level size. The electric field of the gate is used to control the source-drain current flowing between the source and drain electrodes. However, this method has the drawback of only being able to finely adjust the degree of source-drain current control.

[0006] Accordingly, a technology needs to be proposed that can adaptively control the degree of source-drain current control.

[0007] The background technology described above is technology that the inventor possessed or acquired in the process of deriving the disclosure of the present invention, and cannot necessarily be said to be publicly known technology disclosed to the general public prior to the present application.

[0008] The present invention provides a three-terminal insensing memory device and an operating method thereof capable of adaptively adjusting the degree of controlling source-drain current.

[0009] At this time, the present invention not only controls the value of the source-drain current, but also provides a three-terminal insensing memory device and its operating method capable of controlling the retention time when the source-drain current is a photoexcitation current.

[0010] However, the problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0011] A three-terminal inductive memory device according to one embodiment of the present invention may include a first electrode; a second electrode; and an insulating layer interposed between the first electrode and the second electrode to form a conductive filament.

[0012] In one embodiment, the three-terminal sensing memory element may control a source-drain current between a source electrode and a drain electrode included in the first electrode using the conductive filament.

[0013] In one embodiment, the three-terminal inductive memory element may control the source-drain current by supplying or removing carriers through the conductive filament.

[0014] In one embodiment, the three-terminal sensing memory element may control the value of the source-drain current by supplying or removing the carrier through the conductive filament according to a voltage applied to the second electrode.

[0015] In one embodiment, the three-terminal inductive memory element may control the additional formation and maintenance time of the source-drain current when the source-drain current is a photoexcitation current generated in response to light being incident on the three-terminal inductive memory element.

[0016] In one embodiment, the source-drain current may be generated by a voltage applied to the source electrode and the drain electrode.

[0017] In one embodiment, the insulating layer may be formed of a material that forms the conductive filament by a voltage applied to the first electrode and the second electrode.

[0018] In one embodiment, the insulating layer may be formed of a material that generates a source-drain current between the source electrode and the drain electrode included in the first electrode as a photoexcitation current in response to incident light.

[0019] In one embodiment, the three-terminal sensing memory element may further include a semiconductor layer interposed between the first electrode and the insulating layer.

[0020] A method of operating a three-terminal inductive memory device including a first electrode, a second electrode, and an insulating layer interposed between the first electrode and the second electrode according to one embodiment of the present invention may include a step of controlling a source-drain current between a source electrode and a drain electrode included in the first electrode by using a conductive filament formed inside the insulating layer.

[0021] In one embodiment, the controlling step may further include controlling the source-drain current by supplying or removing carriers through the conductive filament.

[0022] In one embodiment, the controlling step may be a step of controlling the value of the source-drain current by supplying or removing the carrier through the conductive filament according to a voltage applied to the second electrode.

[0023] In one embodiment, the source-drain current may be a photoexcitation current generated in response to light being incident on the three-terminal incident memory element.

[0024] In one embodiment, the controlling step may include a step of controlling additional formation and maintenance time of the source-drain current, which is the photoexcitation current.

[0025] In one embodiment, the source-drain current may be generated by a voltage applied to the source electrode and the drain electrode.

[0026] The present invention can achieve the technical effect of providing a three-terminal insensing memory device and an operating method thereof capable of adaptively adjusting the degree of controlling the source-drain current.

[0027] At this time, the present invention can achieve a technical effect of not only controlling the value of the source-drain current, but also controlling the retention time when the source-drain current is a photoexcitation current.

[0028] FIG. 1 and FIG. 2 are schematic drawings showing a three-terminal insensing memory device according to one embodiment of the present invention.

[0029] FIG. 3a and FIG. 3b are diagrams showing a three-terminal insensing memory device according to Example 1 of the present invention and current-voltage graphs before and after a set process.

[0030] FIG. 4a and FIG. 4b are drawings for explaining when voltage is applied to the second electrode in a three-terminal inductive memory device according to Embodiment 1 of the present invention.

[0031] FIG. 5a and FIG. 5b are diagrams for explaining when a photoexcitation current is generated in a three-terminal insensing memory device according to Example 1 of the present invention.

[0032] FIGS. 6A to 6E are diagrams for explaining the control of the retention time of the photoexcitation current in a three-terminal inductive memory device according to Embodiment 1 of the present invention.

[0033] FIG. 7a and FIG. 7b are drawings showing a three-terminal insensing memory element according to Embodiment 2 of the present invention.

[0034] FIGS. 8A to 8D are diagrams showing current-voltage graphs before and after a set process of a three-terminal insensing memory device according to Example 2 of the present invention.

[0035] FIGS. 9A to 9C are graphs and schematic diagrams for explaining the source-drain current when voltage is applied to the second electrode in a three-terminal inductive memory device according to Embodiment 2 of the present invention.

[0036] FIGS. 10A to 10E are diagrams for explaining when a photoexcitation current is generated in a three-terminal insensing memory device according to Embodiment 2 of the present invention.

[0037] Hereinafter, embodiments are described in detail with reference to the attached drawings. However, the embodiments may be modified in various ways, and the scope of the patent application is not limited or restricted by these embodiments. It should be understood that all modifications, equivalents, or alternatives to the embodiments are included within the scope of the patent application.

[0038] The terms used in the examples are for illustrative purposes only and should not be construed as limiting. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood to not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0039] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the embodiments pertain. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0040]

[0041] In addition, when describing with reference to the attached drawings, identical components will be assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted. When describing embodiments, if a detailed description of a related known technology is judged to unnecessarily obscure the gist of the embodiment, the detailed description will be omitted.

[0042] Additionally, in describing components of an embodiment, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0043] Components included in one embodiment and components with common functions will be described using the same names in other embodiments. Unless otherwise stated, the descriptions given in one embodiment may also apply to other embodiments, and detailed descriptions will be omitted to the extent of overlap.

[0044]

[0045] Hereinafter, the three-terminal inductive memory device and the operating method of the three-terminal inductive memory device of the present invention will be described in detail with reference to examples and drawings. However, the present invention is not limited to these examples and drawings.

[0046]

[0047] A three-terminal inductive memory device according to one embodiment of the present invention includes a first electrode; a second electrode; and an insulating layer interposed between the first electrode and the second electrode and forming a conductive filament.

[0048] In one embodiment, a three-terminal sensing memory device can control a source-drain current between a source electrode and a drain electrode included in a first electrode using a conductive filament.

[0049] At this time, the degree of control of the source-drain current can be adjusted depending on the presence or absence of a conductive filament, and in particular, a three-terminal insensing memory device can finely control the value of the source-drain current when a conductive filament is formed.

[0050] Additionally, the three-terminal inductive memory device can control not only the value of the source-drain current, but also the retention time of the source-drain current when the source-drain current is a photoexcitation current.

[0051] As the source-drain current is controlled using the conductive filament in this way, the resistance state of the insulating layer can be set to a different value than before.

[0052]

[0053] FIG. 1 and FIG. 2 are schematic drawings showing a three-terminal insensing memory device according to one embodiment of the present invention.

[0054] Referring to the drawings, a three-terminal insensing memory element (100) according to one embodiment may include a first electrode (110), a second electrode (120), and an insulating layer (130).

[0055] Although the drawing shows a structure in which the first electrode (110) is at the top and the second electrode (120) is at the bottom, a top gate structure in which the second electrode (110) is at the top and the first electrode (120) is at the bottom may also be possible.

[0056] The first electrode (110) and the second electrode (120) may each include at least one selected from the group consisting of platinum (Pt), silver (Ag), aluminum (Al), iridium (Ir), gold (Au), ruthenium (Ru), tungsten (W), titanium (Ti), nickel (Ni), hafnium (Hf), iridium oxide (IrO2), ruthenium oxide (RuO2), titanium nitride (TiN), and tantalum nitride (TaN).

[0057] The first electrode (110) and the second electrode (120) may be made of the same material or different materials, respectively. Preferably, the first electrode (110) and the second electrode (120) may be made of silver (Ag) or platinum (Pt), respectively.

[0058] The insulating layer (130) is a component that exhibits a high resistance state in a crystalline or amorphous structure and is converted to a low resistance state in response to the formation of conductive filaments, and can generate a source-drain current between the source electrode (112) and the drain electrode (114) included in the first electrode (110) by a voltage applied to the source electrode (112) and the drain electrode (114) or by incident light.

[0059] To this end, the insulating layer (130) may include a conductive channel formed by a controllable metal ion, a point defect, or both according to a voltage that allows electron movement. For example, the point defect may include an oxygen vacancy. The oxygen vacancy may electrically connect the first electrode (110) and the second electrode (120) to change the resistance state in a local region of the device (100), between the source electrode (112) included in the first electrode (110) and the second electrode (120), or between the drain electrode (114) included in the first electrode and the second electrode (120), thereby exhibiting a switching characteristic between the first electrode (110) and the second electrode (120). As another example, the metal ion may be a metal cation having a positive charge or a metal anion having a negative charge.

[0060] In particular, the insulating layer (130) can form conductive filaments (132) therein in response to voltage being applied between the first electrode (110) and the second electrode (120).

[0061] These conductive filaments (132) can be used to control the source-drain current between the source electrode (112) and the drain electrode (114) included in the first electrode (110).

[0062] More specifically, the three-terminal inductive memory element (100) can control the source-drain current by supplying or removing carriers (e.g., electrons) through the conductive filament (132).

[0063] For example, the three-terminal insensing memory element (100) can control the value of the source-drain current by supplying or removing carriers through the conductive filament (132) according to the voltage applied to the second electrode (120). For a more specific example, the three-terminal insensing memory element (100) can increase the value of the source-drain current by supplying carriers from the second electrode (120) to the insulating layer (130) through the conductive filament (132) formed in the insulating layer (130) in response to a negative voltage being applied to the second electrode (120), and can decrease the value of the source-drain current by moving carriers from the insulating layer (130) to the second electrode (120) through the conductive filament (132) formed in the insulating layer (130) in response to a positive voltage being applied to the second electrode (120) to reduce carriers in the insulating layer (130). For another more specific example, in the case where a semiconductor layer (140) made of an n-type semiconductor exists between the source and the drain, the three-terminal insensing memory device (100) can increase the source-drain current value in the semiconductor layer (140) between the source and the drain by supplying carriers from the second electrode (120) to the insulating layer (130) through the conductive filaments (132) formed in the insulating layer (130) in response to a negative voltage being applied to the second electrode (120), and can decrease the source-drain current value in the semiconductor layer (140) between the source and the drain by reducing the carriers in the insulating layer (130) by moving carriers from the insulating layer (130) to the second electrode (120) through the conductive filaments (132) formed in the insulating layer (130) in response to a positive voltage being applied to the second electrode (120).As another more specific example, in a three-terminal insensing memory device (100), when a semiconductor layer (140) made of a p-type semiconductor exists between the source and the drain, when a positive voltage is applied to the second electrode (120), carriers are supplied from the second electrode (120) to the insulating layer (130) through the conductive filaments (132) formed in the insulating layer (130), thereby increasing the source-drain current value in the semiconductor layer (140) between the source and the drain, and when a negative voltage is applied to the second electrode (120), carriers are moved from the insulating layer (130) to the second electrode (120) through the conductive filaments (132) formed in the insulating layer (130), thereby decreasing the carriers in the insulating layer (130), thereby decreasing the source-drain current value in the semiconductor layer (140) between the source and the drain.

[0064] At this time, the three-terminal insensing memory device (100) can roughly control the value of the source-drain current to a preset unit or more for the low-resistance insulating layer (130) on which the set process has been performed, and can finely control the value of the source-drain current to a preset unit or less for the high-resistance insulating layer (130) on which the reset process has been performed. That is, while the existing three-terminal insensing memory device using an electric field can only finely control the source-drain current, the three-terminal insensing memory device (100) according to one embodiment can adaptively control the source-drain current, such as roughly controlling it to a preset unit or more or finely controlling it to a preset unit or less.

[0065] Controlling the value of the source-drain current means controlling the amount of source-drain current, i.e. the amount of carriers.

[0066] Here, the source-drain current may be generated by the voltage applied to the source electrode (112) and the drain electrode (114). Accordingly, the insulating layer (130) may be formed of a material that forms a conductive filament (132) by the voltage applied to the first electrode (110) and the second electrode (120). For example, the insulating layer (130) may include at least one selected from the group consisting of a metal oxide, a metal nitride, and a semiconductor oxide.

[0067] In one embodiment, the metal oxide may include at least one selected from the group consisting of Ga2O3, ZnO, Al2O3, CaO, CdO, Co3O5, CoO2, CuO2, MoO3, WO3, MnO2, RuO2, TiO2, SnO2, Nb2O5, NiO, CrO2, Fe3O4, ZrO2, HfO2, and V2O5.

[0068] In one embodiment, the metal nitride may include at least one selected from the group consisting of GaN, InN, AlN, Ti2N, Ti3N2, Ti4N3, Zr2N, V2N, and Cr2N.

[0069] In one embodiment, SiO2 may be used as the semiconductor oxide.

[0070] In addition, when the source-drain current is a photoexcitation current generated in response to light being incident on the three-terminal in-sensing memory element (100), the three-terminal in-sensing memory element (100) can control the maintenance time of the source-drain current.

[0071] For example, a three-terminal inductive memory device (100) can increase the retention time of the source-drain current in response to a negative voltage being applied to the second electrode (120), and can decrease the retention time of the source-drain current in response to a positive voltage being applied to the second electrode (120).

[0072] For a more specific example, when a semiconductor layer (140) made of an n-type semiconductor exists between the source and the drain, in response to a negative voltage being applied to the second electrode (120), photoexcited carriers (electrons) generated in the semiconductor layer (140) between the source and the drain and electrons supplied from the second electrode (120) form more carriers (electrons) in the semiconductor layer (140) between the source and the drain, and accordingly, the three-terminal insensing memory device (100) can increase the retention time of the source-drain current, thereby increasing the retention time required for forgetting and reducing the forgetting speed at which forgetting occurs. On the other hand, the three-terminal insensing memory device (100) can reduce the retention time of the source-drain current in the semiconductor layer (140) between the source and the drain in response to a positive voltage being applied to the second electrode (120), thereby reducing the retention time required for forgetting and increasing the forgetting speed at which forgetting occurs.

[0073] For another more specific example, when a semiconductor layer (140) made of a p-type semiconductor exists between the source and the drain, in response to a positive voltage being applied to the second electrode (120), photoexcited carriers (electrons) generated in the semiconductor layer (140) between the source and the drain and electrons supplied from the second electrode (120) form more carriers (electrons) in the semiconductor layer (140) between the source and the drain, and accordingly, the three-terminal insensing memory device (100) can increase the retention time of the source-drain current, thereby increasing the retention time required for forgetting and reducing the forgetting speed at which forgetting occurs. On the other hand, the three-terminal insensing memory device (100) can reduce the retention time of the source-drain current in the semiconductor layer (140) between the source and the drain in response to a negative voltage being applied to the second electrode (120), thereby reducing the retention time required for forgetting and increasing the forgetting speed at which forgetting occurs.

[0074] To this end, the insulating layer (130) may be formed of a material that generates a source-drain current between the source electrode (112) and the drain electrode (114) included in the first electrode (110) as a photoexcitation current in response to light incident thereon. For example, the insulating layer (130) may be formed of a material including at least one selected from the group consisting of a metal oxide, a metal nitride, and a semiconductor oxide as described above.

[0075] When a semiconductor layer (140) is included in a three-terminal inductive memory element (100), the semiconductor layer (140) may be formed of a material that generates a source-drain current between the source electrode (112) and the drain electrode (114) included in the first electrode (110) as a photoexcitation current in response to incident light. The semiconductor layer (140) may include at least one selected from the group consisting of carbon nanotubes (CNT), graphene, reduced graphene oxide (RGO), indium oxide (In2O3), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), titanium oxide (TiO2), indium tin oxide (ITO), hafnium indium zinc oxide (HfIZO), and tin oxide (SnO2), and may be doped as n-type or p-type.

[0076] When the semiconductor layer (140) is used as a carbon nanotube (CNT) channel, it can help improve performance in areas such as wearable devices and neuromorphic computing due to the high mobility and flexibility of the carbon nanotube.

[0077] This insulating layer (130) may be positioned on a substrate (150). The substrate (150) may be, for example, a conductive substrate on which a lower electrode (120) is formed and on which a carrier can be supplied, and may be, in particular, a semiconductor substrate such as a silicon substrate or germanium; or an SOI substrate (silicon on insulator).

[0078] In the above drawing, the second electrode (120) is positioned on a surface facing one side of the substrate (150) on which the first electrode (110) and the insulating layer (130) are disposed, but is not limited thereto, and may be positioned on a surface facing one side of the insulating layer (130) on which the first electrode (110) is disposed. In this case, a structure having the order of “first electrode (110) - insulating layer (130) - second electrode (120) - substrate (150)” in the direction from top to bottom can be implemented. A detailed description thereof will be described below.

[0079] In this way, as the source-drain current is controlled using the conductive filament (132), when the source-drain is composed only of the insulating layer (130) without the semiconductor layer (140) between the source and drain, the resistance state of the insulating layer (130) can be set to be more variable than before by being directly connected to the insulating layer (130) which is the source-drain.

[0080] For example, a three-terminal insensing memory element (100) exhibits a first resistance state of an insulating layer (130) in a high resistance state, a second resistance state in which light is incident while supplying carriers to the insulating layer (130) in a low resistance state through a conductive filament (132), a third resistance state in which light is not incident while supplying carriers to the insulating layer (130) in a low resistance state through a conductive filament (132), a fourth resistance state in which light is incident while removing carriers to the insulating layer (130) in a low resistance state, and a fifth resistance state in which light is not incident while removing carriers to the insulating layer (130) in a low resistance state, thereby implementing the behavior of a memristor and can be used as an optoelectronic synapse element.

[0081] The first resistance state, the second resistance state, the third resistance state, the fourth resistance state, and the fifth resistance state can represent signals of stages '0, 1, 2, 3, 4', respectively, and the logic states of '0, 1, 2, 3, 4' can implement quinary data storage and display. Therefore, the three-terminal insensing memory device (100) has three or more logic states to implement multi-value, and is expected to contribute to the high-speed, miniaturization, and low-power consumption of next-generation semiconductors by being more advantageous in power consumption and large-capacity information processing compared to conventional binary-based semiconductors that have reached their technical limits in terms of power consumption. In addition, the three-terminal insensing memory device (100) can be used as a device that can simultaneously perform image sensing and memory through electrical stimulation and optical stimulation. In addition, the three-terminal inductive memory device (100) is a memristor-based synaptic device that can be expanded into a high-speed, high-density next-generation resistive three-terminal inductive memory device capable of multi-step processing beyond the conventional computer structure.

[0082] The light incident on the three-terminal insensing memory element (100) described above may have a wavelength in the ultraviolet band, infrared band, or visible light band.

[0083]

[0084] The operating method described below is assumed to be performed by a three-terminal insensing memory element (100) of the aforementioned structure.

[0085] A three-terminal sensing memory element (100) can control the source-drain current between the source electrode (112) and the drain electrode (114) included in the first electrode (110) by using a conductive filament (132) formed inside the insulating layer (130).

[0086] More specifically, the three-terminal inductive memory element (100) can control the source-drain current by supplying or removing carriers (e.g., electrons) through the conductive filament (132). When the three-terminal inductive memory element (100) further includes a semiconductor layer (140), the three-terminal inductive memory element (100) can control the source-drain current in the semiconductor layer (140) between the source and drain by supplying or removing carriers (e.g., electrons) through the conductive filament (132).

[0087] For example, the three-terminal insensing memory element (100) can control the value of the source-drain current by supplying or removing carriers through the conductive filament (132) according to the voltage applied to the second electrode (120). For a more specific example, the three-terminal insensing memory element (100) can increase the value of the source-drain current by supplying carriers from the second electrode (120) to the insulating layer (130) through the conductive filament (132) formed in the insulating layer (130) in response to a negative voltage being applied to the second electrode (120), and can decrease the value of the source-drain current by moving carriers from the insulating layer (130) to the second electrode (120) through the conductive filament (132) formed in the insulating layer (130) in response to a positive voltage being applied to the second electrode (120) to reduce carriers in the insulating layer (130).

[0088] For another example, when a semiconductor layer (140) made of an n-type semiconductor is included in a three-terminal in-sensing memory element (100), the three-terminal in-sensing memory element (100) can increase the source-drain current value in the semiconductor layer (140) between the source and drain by supplying carriers from the second electrode (120) to the insulating layer (130) through the conductive filaments (132) formed in the insulating layer (130) in response to a negative voltage being applied to the second electrode (120), and can decrease the source-drain current value in the semiconductor layer (140) between the source and drain by moving carriers from the insulating layer (130) to the second electrode (120) through the conductive filaments (132) formed in the insulating layer (130) in response to a positive voltage being applied to the second electrode (120), thereby reducing carriers in the insulating layer (130). For another more specific example, when a semiconductor layer (140) made of a p-type semiconductor is included in a three-terminal in-sensing memory element (100), the three-terminal in-sensing memory element (100) can increase the source-drain current value in the semiconductor layer (140) between the source and drain by supplying carriers from the second electrode (120) to the insulating layer (130) through the conductive filaments (132) formed in the insulating layer (130) in response to a positive voltage being applied to the second electrode (120), and can decrease the source-drain current value in the semiconductor layer (140) between the source and drain by reducing the carriers in the insulating layer (130) by moving carriers from the insulating layer (130) to the second electrode (120) through the conductive filaments (132) formed in the insulating layer (130) in response to a negative voltage being applied to the second electrode (120).

[0089] Here, the source-drain current may be generated by a voltage applied to the source electrode (112) and the drain electrode (114).

[0090] However, without being limited or restricted thereto, the source-drain current may be a photoexcited current generated in response to light being incident on the three-terminal incident memory element (100).

[0091] In this case, the three-terminal insensing memory element (100) can control the retention time of the source-drain current, which is the photoexcitation current.

[0092] For example, the three-terminal in-sensing memory device (100) can increase the holding time of the source-drain current in response to a negative voltage being applied to the second electrode (120), and can decrease the holding time of the source-drain current in response to a positive voltage being applied to the second electrode (120). For a more specific example, when a semiconductor layer (140) made of an n-type semiconductor exists between the source and the drain, in response to a negative voltage being applied to the second electrode (120), more carriers (electrons) are formed in the semiconductor layer (140) between the source and the drain by photoexcited carriers (electrons) generated in the semiconductor layer (140) between the source and the drain and electrons supplied from the second electrode (120), and accordingly, the three-terminal in-sensing memory device (100) can increase the holding time of the source-drain current, thereby increasing the forgetting time required for forgetting and decreasing the forgetting speed at which forgetting occurs. On the other hand, the three-terminal insensing memory element (100) can reduce the retention time of the source-drain current in response to a positive voltage being applied to the second electrode (120), thereby reducing the forgetting time required for forgetting and increasing the forgetting speed at which forgetting occurs.

[0093] For another more specific example, when a semiconductor layer (140) made of a p-type semiconductor exists between the source and the drain, in response to a positive voltage being applied to the second electrode (120), photoexcited carriers (electrons) generated in the semiconductor layer (140) between the source and the drain and electrons supplied from the second electrode (120) form more carriers (electrons) in the semiconductor layer (140) between the source and the drain, and accordingly, the three-terminal insensing memory device (100) can increase the retention time of the source-drain current, thereby increasing the retention time required for forgetting and reducing the forgetting speed at which forgetting occurs. On the other hand, the three-terminal insensing memory device (100) can reduce the retention time of the source-drain current in the semiconductor layer (140) between the source and the drain in response to a negative voltage being applied to the second electrode (120), thereby reducing the retention time required for forgetting and increasing the forgetting speed at which forgetting occurs.

[0094]

[0095] Hereinafter, the present invention will be described in detail with reference to the following examples and comparative examples. However, the technical concept of the present invention is not limited or restricted thereby.

[0096]

[0097] Example 1

[0098] FIG. 3a and FIG. 3b are diagrams showing a three-terminal insensing memory device according to Example 1 of the present invention and current-voltage graphs before and after a set process.

[0099] In more detail, FIG. 3a shows a three-terminal sensing memory device (100; hereinafter, Ag / CNT / Ag device) in which a p-type semiconductor layer (140; hereinafter, CNT) is deposited on a 100 nm insulating layer (130; hereinafter, SiO2)) / substrate (150; hereinafter, Si substrate) by spin coating, and then Ag is deposited on the CNT as a first electrode (110) and Ag is deposited on the Si substrate as a second electrode (120).

[0100] When a voltage was applied to this device by connecting the Ag electrode on the CNT and the Ag electrode on the Si substrate, a low current of less than nA was flowing at 1.0 V before the set process due to the SiO2 insulating layer, but as the set voltage increased, a current of several hundred μA was confirmed to flow, as shown in Fig. 3b. This is due to the set process in which a conductive filament (132) channel is formed within the SiO2 insulating layer according to the voltage application, connecting the upper and lower parts.

[0101] At this time, by applying voltage to the first electrode (110) of Ag and the second electrode (120) of Si on top of CNT / SiO2, a conductive filament (132) is formed as shown in the drawings, so that a high current can flow between the first electrode (110) and the second electrode (120).

[0102] FIG. 4a and FIG. 4b are drawings for explaining when voltage is applied to the second electrode in a three-terminal inductive memory device according to Embodiment 1 of the present invention.

[0103] Referring to the drawings, since the CNT is p-type, the current flowing between the first electrode (110) and the second electrode (120) increases as the voltage increases. Accordingly, when a positive voltage and a negative voltage are applied to the second electrode (120), the source-drain current may decrease and increase, respectively.

[0104] For example, when a positive voltage is applied to the second electrode (120), electrons injected from the source electrode (111; hereinafter, the left source Ag electrode) move along the conductive filament (132) of the insulating layer (130) to the second electrode (120), and as a result, the number of electrons moving to the drain electrode (112; hereinafter, the right drain Ag electrode) decreases, thereby decreasing the total current.

[0105] For another example, when a negative voltage is applied to the second electrode (120), more electrons are injected from the second electrode (120) and combine with the electrons injected from the left source Ag electrode, thereby generating more current, which may cause the current to increase. This indicates that, as shown in FIG. 2 above, the source-drain current can be increased or decreased by additionally supplying or removing carriers through the conductive filament (132) channel of the insulating layer (130) rather than the electric field from the second electrode (120).

[0106] FIG. 5a and FIG. 5b are diagrams for explaining when a photoexcitation current is generated in a three-terminal insensing memory device according to Example 1 of the present invention.

[0107] In addition, the three-terminal in-sensing memory device (100) can be used as an in-sensing memory device capable of a photoexcited long-term memory device, as the photoexcited current is provided as a source-drain current in response to the application of light (hereinafter referred to as UV) to the CNT, and the photoexcited current is maintained for a long time due to the persistent photoconductivity (PPC) effect.

[0108] First, when a 365 nm UV light source is applied to the Ag / CNT / SiO2 / Si device as shown in FIG. 5a to increase the photoexcited carriers, if the voltage direction of the second electrode (120; Ag electrode of the lower Si) is positive (+), the photoexcited carriers formed in the p-type CNTs escape toward the second electrode (120; lower Si) along the conductive filament (132), so a low current is formed at the drain Ag electrode. Conversely, if the voltage direction of the second electrode (120; Ag electrode of the lower Si) is negative (-), a higher current flows due to the supply of electrons from the second electrode (120) to the photoexcited carriers. This means that the amount of photocurrent flowing from the source electrode (112) to the drain electrode (114) can also be controlled by adding the conductive filament (132) within the insulating layer (130) as a very small current path.

[0109] FIGS. 6A to 6E are diagrams for explaining the control of the retention time of the photoexcitation current in a three-terminal inductive memory device according to Embodiment 1 of the present invention.

[0110] In addition, based on the result that the 3-terminal insensing memory element (100) can increase or decrease the photoexcitation current depending on the voltage (hereinafter, gate voltage) applied to the second electrode (120), the depression characteristics of the EPSC (Excitatory postsynaptic current) generated in the optical synapse element according to the gate voltage by repeatedly applying the photoexcitation are shown in the drawings. As shown in FIG. 6a, after performing the optical set process to form a high EPSC by applying UV for 5 seconds, the decreasing depression characteristics of the EPSC were confirmed while changing the gate voltage to -0.05, 0, and +0.05 V. As shown in FIG. 6b, when the gate voltage increases to a positive voltage, a lower current is formed during depression, so that the EPSC increases more to a negative value than the reference (Vg = 0 V) ​​and then decreases from a high value, and when the gate voltage decreases to a negative voltage, a higher current is formed during depression, so that the EPSC increases to a positive value than the reference (Vg = 0 V) ​​and then decreases and then decreases more quickly. This suggests that as the gate voltage increases toward a positive voltage (+), EPSCs generated by photoexcitation persist longer, enabling long-term memory. Conversely, as the gate voltage decreases toward a negative voltage (-), the forgetting rate can be increased through faster EPSCs. This implies that long-term memory and forgetting characteristics can be freely controlled by controlling EPSCs during the forgetting process with the gate voltage.

[0111] Through the drawings, the PPF characteristics that can be used to confirm the long-term memory characteristics of the optoelectronic synapse device using the photoexcitation carrier were confirmed. Compared to A1 obtained by applying the first UV, A2 due to the change in gate voltage after the second UV application increases more greatly when a positive voltage (+) is applied to the lower gate. Therefore, the PPF, which is A2 / A1, shows a phenomenon in which it greatly increases with increasing voltage, and it was confirmed that the PPF value decreases as a negative voltage (-) is applied. This indicates that a higher memory is possible when a positive voltage (+) is applied to the lower gate electrode. In particular, although △t, which is when UV is turned off between the first and second photoexcitation stimuli, decreases, it shows a phenomenon in which it increases overall as the gate voltage increases.

[0112]

[0113] Example 2

[0114] FIG. 7a and FIG. 7b are drawings showing a three-terminal insensing memory element composed only of an insulating layer (130) without a semiconductor (140) layer according to Example 2 of the present invention.

[0115] Example 2 shows a three-terminal insensing memory device (100; hereinafter referred to as a Pt / Ga2O3 / Pt device) using Pt as a first electrode (110), Ga2O3 as an insulating layer (130), and Pt as a second electrode (120).

[0116] FIG. 7a is a schematic diagram showing the flow of carriers (electrons) in a metal / oxide / metal two-terminal structure, and FIG. 7b is a schematic diagram showing the movement of carriers in a three-terminal device after a set process of forming a conductive filament (132) channel in an insulating layer (130) using the first electrode (110) and the second electrode (120) is performed, showing a three-terminal structure in which a voltage is added to the second electrode (120) at the bottom. As in the previously described embodiment 1, since a microscopic current path is added to the second electrode (120), carriers are divided into those moving from the source electrode (111; hereinafter, upper Pt) included in the first electrode (110) to the drain electrode (112; hereinafter, another upper Pt) and those moving to the second electrode (120; lower gate electrode) through the conductive filament (132) channel. Accordingly, the amount of carriers moving between the source electrode (112) and the drain electrode (114) may decrease, thereby reducing the source-drain current. Conversely, when the lower gate voltage applied to the second electrode (120; lower gate) is formed in the opposite direction, additional carriers may flow to the drain electrode (114) through the second electrode (120; lower gate), thereby forming more source-drain current. This is a similar characteristic to that in FIGS. 1 and 2.

[0117] FIGS. 8A to 8D are diagrams showing current-voltage graphs before and after a set process of a three-terminal insensing memory device according to Example 2 of the present invention.

[0118] FIGS. 8a and 8b are schematic diagrams showing the flow of current when current is applied to the Ga2O3 insulating layer (130) through the first electrode (110) and the second electrode (120) and after the set process in which a conductive filament (132) channel is formed in the device. As in FIG. 8c, when the conductive filament is not formed, a high resistance state is maintained, but when a conductive filament is formed in the Ga2O3 insulating layer (130) at 7 V or higher, a set process may occur in which the resistance state suddenly switches to a low resistance state in which a large amount of current flows. Therefore, as in FIG. 8d, very different IV curves may appear before and after the set process.

[0119] FIGS. 9A to 9C are graphs and schematic diagrams for explaining the source-drain current when voltage is applied to the second electrode in a three-terminal insensing memory device according to Embodiment 2 of the present invention.

[0120] FIG. 9a and FIG. 9b show the IV characteristics between the source electrode (111; upper Pt electrode) and the drain electrode (112; another upper Pt electrode) included in the first electrode (110) after forming a conductive filament (132) through a set process in the Ga2O3 insulating layer (130) according to the gate voltage applied to the second electrode (120; lower Pt electrode (gate). As the negative voltage (-) to the second electrode (120) increases, electrons are additionally supplied from the second electrode (120) to the conductive filament (132) channel, and the current further increases as the gate voltage increases to a negative voltage (-) (FIG. 9a). On the contrary, when a positive voltage (+) is applied to the second electrode (120), electrons moving from the source electrode (112) to the drain electrode (114) move to the second electrode (120; lower Pt electrode which is the gate) and are transferred to the source electrode (112) and A characteristic of decreasing current is exhibited as the electrons moving between the drain electrodes (114) decrease. This indicates that the direction and magnitude of the voltage (lower gate voltage) applied to the second electrode (120) are controlled, enabling additional amplification and reduction of carriers through the conductive filament (132) channel rather than the electric field. Fig. 9c indicates that the source-drain current is well controlled as the gate voltage is varied to 0 V, 5 mV, -5 mV, 0 V, -5 mV, 5 mV, 10 mV, -10 mV, and 0 V under a constant Vds of 0.5 V.

[0121] FIGS. 10A to 10E are diagrams for explaining when a photoexcitation current is generated in a three-terminal insensing memory device according to Embodiment 2 of the present invention.

[0122] The described three-terminal insensing memory device (100), which is a Pt / Ga2O3 / Pt three-terminal device, can be applied to improve long-term memory characteristics and control forgetting speed. Fig. 10a shows the results of depression using different gate voltages after forming optical potentiation by repeating UV 10 times with a pulse width of 0.5 seconds and a 50% duty cycle. As a negative voltage (-) is applied to the second electrode (120; lower gate), the EPSC increases during depression, and can decrease as a positive voltage (+) is applied. Figs. 10b and 10c show electrical depression as the gate voltage is increased (+) or increased (-) during depression after optical potentiation under the same UV pulse conditions. It is confirmed in Fig. 10b that the electrical depression decreases more quickly as the (+) gate voltage increases, and it is confirmed that the electrical depression does not occur but rather increases as the (-) gate voltage increases. This means that the forgetting speed can be controlled by the direction and magnitude of the gate voltage.

[0123] FIG. 10d is a graph showing the forgetting and secondary learning / secondary forgetting processes under different gate voltages after the first learning was performed by applying 100 UV photostimulations (0.5 s pulse width, duty cycle 50%) while applying gate voltages of +3 mV, 0 mV, and -3 mV to a 3-terminal insensing memory device (100), which is a 3-terminal Pt / Ga2O3 / Pt device, and then removing the photoexcitation. The highest EPSC value was observed when the gate voltage was -3 mV during the first learning through photoexcitation stimulation, and a relatively low EPSC value was observed when it was +3 mV. This means that the generation of EPSC due to photoexcitation depending on the gate voltage can be affected, which can control the learning speed. After the end of the light stimulus, the depression over time was observed, and the forgetting time until the point where the maximum EPSC, which is defined as forgetting, reached 70% decreased from 90 seconds to 55 seconds as the gate voltage increased from -3 mV to +3 mV. This means that the time required for forgetting increases as the gate voltage increases to a negative voltage, which means that long-term memory characteristics are improved. In addition, a higher EPSC value was shown at a negative gate voltage even in the second learning, and a higher EPSC value was shown in the second forgetting than in the first regardless of the gate voltage. In addition, as in the first forgetting, a longer forgetting time and a higher EPSC value were shown when the gate voltage changed from +3 mV to -3 mV. This means that, as mentioned above, a higher EPSC is obtained due to the additional electron supply from the second electrode (120), and thus a longer long-term memory characteristic is shown.

[0124] Figure 10e shows the remaining EPSCs after 25 and 50 seconds of the learning process by applying gate voltages of +3 mV, 0 mV, and -3 mV to nine Pt / Ga2O3 / Pt three-terminal devices 100 times with light stimulation (0.5 s pulse width, duty cycle 50%), and maintaining each gate voltage. It also shows the visual memory through the secondary learning and forgetting process according to different gate voltages. After the first 100 times of light stimulation, five devices were put into a learning state and are shown in dark color. Afterwards, the forgetting process was performed while maintaining different gate voltages. When the gate voltage was +3 mV, a light color was shown due to a rapid decrease in EPSC, whereas a darker color was shown when the gate voltage was -3 mV. This indicates that the long-term memory characteristics of each device can be improved depending on the gate voltage. Additionally, by performing the second learning, we were able to obtain the same color by learning in all the same ways, and after that, as the forgetting process increased to 25 seconds and 50 seconds, the color became lighter, but when the gate voltage was +3 mV, it showed a lighter color, whereas when it was -3 mV, it showed a darker color. In addition, the colors of all these devices showed a result of showing a darker color than the forgetting process after the first learning. This means that as the number of learning times increased, a higher EPSC was shown during forgetting, and when the gate voltage was maintained at -3 mV, electrons were injected from the gate through the conductive filament channel into the Ga2O3 channel, so a higher EPSC value could be shown and maintained for a long time. In addition, this means that additional carrier supply and removal occurred by controlling the direction and size of the gate voltage by using the conductive filament channel within the insulating film rather than the existing electric field, making it possible to increase and maintain the EPSC.

[0125]

[0126] Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the above. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0127] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. First electrode; a second electrode; and An insulating layer formed between the first electrode and the second electrode and forming a conductive filament; including, 3-terminal insensing memory device.

2. In paragraph 1, The above three-terminal insensing memory element, Using the conductive filament, the source-drain current between the source electrode and the drain electrode included in the first electrode is controlled. 3-terminal insensing memory device.

3. In paragraph 2, The above three-terminal insensing memory element, Controlling the source-drain current by supplying or removing carriers through the conductive filament; 3-terminal insensing memory device.

4. In paragraph 3, The above three-terminal insensing memory element, Controlling the value of the source-drain current by supplying or removing the carrier through the conductive filament according to the voltage applied to the second electrode. 3-terminal insensing memory device.

5. In paragraph 2, The above three-terminal insensing memory element, When the source-drain current is a photoexcitation current generated in response to light being incident on the three-terminal incident memory element, the additional formation and maintenance time of the source-drain current is controlled. 3-terminal insensing memory device.

6. In paragraph 2, The above source-drain current is, It is generated by the voltage applied to the source electrode and the drain electrode, 3-terminal insensing memory device.

7. In paragraph 1, The above insulating layer is, It is formed of a material that forms the conductive filament by a voltage applied to the first electrode and the second electrode. 3-terminal insensing memory device.

8. In paragraph 7, The above insulating layer is, It is formed of a material that generates a source-drain current between the source electrode and the drain electrode included in the first electrode as a photoexcitation current in response to incident light. 3-terminal insensing memory device.

9. In paragraph 1, The above three-terminal insensing memory element, A semiconductor layer interposed between the first electrode and the insulating layer; including more, 3-terminal insensing memory device.

10. In a method of operating a three-terminal insensing memory element including a first electrode, a second electrode, and an insulating layer interposed between the first electrode and the second electrode, A step of controlling the source-drain current between the source electrode and the drain electrode included in the first electrode by using a conductive filament formed inside the insulating layer. including, Method of operation of a three-terminal inductive memory device.

11. In paragraph 10, The above controlling step is, A step of controlling the source-drain current by supplying or removing carriers through the conductive filament; including more, Method of operation of a three-terminal inductive memory device.

12. In paragraph 11, The above controlling step is, A step of controlling the value of the source-drain current by supplying or removing the carrier through the conductive filament according to the voltage applied to the second electrode. Method of operation of a three-terminal inductive memory device.

13. In paragraph 10, The above source-drain current is, The photoexcitation current generated in response to light being incident on the above three-terminal incident memory element is Method of operation of a three-terminal inductive memory device.

14. In paragraph 13, The above controlling step is, A step of controlling the additional formation and maintenance time of the source-drain current, which is the photoexcitation current. including, Method of operation of a three-terminal inductive memory device.

15. In paragraph 10, The above source-drain current is, It is generated by the voltage applied to the source electrode and the drain electrode, Method of operation of a three-terminal inductive memory device.

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