Method for significantly reducing contact resistance of two-dimensional semiconductor device

Abstract

Disclosed is a method for significantly reducing contact resistance of a two-dimensional semiconductor device. According to one aspect of the present embodiment, a method for reducing contact resistance of a two-dimensional semiconductor device is provided, the method comprising: an arrangement process for arranging a preset material on an electrode in the two-dimensional semiconductor device; and an exposure process for exposing the two-dimensional semiconductor device having undergone the arrangement process to a preset environment.

Description

A method for significantly reducing the contact resistance of a two-dimensional semiconductor device

[0001] The present embodiment relates to a method for significantly reducing the contact resistance of a two-dimensional semiconductor device.

[0002]

[0003] This patent is the result of research conducted with the support of the National Research Foundation of Korea (NRF) with funding from the Korean government (Ministry of Science and ICT) in 2022 (Project ID: 1711175688, Subproject ID: 2022M3H4A1A04096396, Project Name: Nanomaterial Technology Development, Project Name: Development of Two-Dimensional Boron Nitride-Based Room-Temperature Operation Quantum Light Source Technology).

[0004] The content described in this section merely provides background information for the present embodiment and does not constitute prior art.

[0005] As the size of semiconductor devices decreases, the number of semiconductor devices that can be integrated onto a single wafer increases, leading to faster device operation. Accordingly, active research is underway to reduce the size of semiconductor devices.

[0006] Recently, research is being conducted on the use of two-dimensional materials to reduce the size of semiconductor devices. Two-dimensional materials exhibit stable and superior properties even at thicknesses of less than 1 nm. Therefore, two-dimensional materials are attracting attention as a potential solution to overcome the performance degradation associated with shrinking semiconductor devices.

[0007] Two-dimensional materials are placed between metal electrodes within semiconductor devices, enabling them to function as semiconductor elements. However, the biggest problem that arises when using two-dimensional materials in semiconductor devices is contact resistance. When a two-dimensional material is placed between metal electrodes to connect them, a phenomenon called Fermi level pinning occurs. This forms a Schottky barrier between the two-dimensional material and the metal electrode, significantly increasing the contact resistance of the semiconductor element and degrading its electrical performance.

[0008] Accordingly, despite the aforementioned advantages of two-dimensional materials, there are difficulties in commercializing two-dimensional semiconductor devices.

[0009] One embodiment of the present invention aims to provide a two-dimensional semiconductor device with significantly reduced contact resistance and a method for reducing the same.

[0010] According to one aspect of the present embodiment, a method for reducing the contact resistance of a two-dimensional semiconductor device is provided, characterized in that it includes a placement process of arranging a predetermined material on an electrode in a two-dimensional semiconductor device, and an exposure process of exposing a two-dimensional semiconductor device that has undergone the placement process to a predetermined environment.

[0011] According to one aspect of the present embodiment, the predetermined material is characterized by being composed of bismuth (Bi), indium (In) and tin (Sn).

[0012] According to one aspect of the present embodiment, the preset material is characterized in that each component is composed in a preset ratio.

[0013] According to one aspect of the present embodiment, the two-dimensional semiconductor device is characterized by including a substrate, an electrode disposed on the substrate, and a two-dimensional material disposed between the electrodes.

[0014] According to one aspect of the present embodiment, the two-dimensional material is characterized by being TMD (Transition Metal Dichalcogenide), black phosphorus, or graphene.

[0015] According to one aspect of the present embodiment, the preset environment is characterized by having a preset temperature in a vacuum state.

[0016] According to one aspect of the present embodiment, the preset temperature is characterized in that it is higher than the melting point of the preset material.

[0017] According to one aspect of the present embodiment, a two-dimensional semiconductor device is provided, characterized in that it includes a substrate, an electrode disposed on the substrate, a two-dimensional material disposed between the electrodes, and a predetermined material bonded only to the electrodes.

[0018] According to one aspect of the present embodiment, the predetermined material is characterized by being composed of bismuth (Bi), indium (In) and tin (Sn).

[0019] According to one aspect of the present embodiment, the electrode is characterized in that it is implemented with gold (Au) or chromium (Cr).

[0020] According to one aspect of the present embodiment, the two-dimensional material is characterized by being TMD (Transition Metal Dichalcogenide), black phosphorus, or graphene.

[0021] According to one aspect of the present embodiment, a two-dimensional semiconductor device is provided, comprising a substrate, an electrode disposed on the substrate, a two-dimensional material disposed between the electrodes, and a preset material bonded only on the electrodes, wherein the preset material is disposed on the electrodes, and the two-dimensional semiconductor device on which the preset material is disposed is exposed to a preset environment and bonded only on the electrodes.

[0022] According to one aspect of the present embodiment, the preset material is characterized in that it is placed on the electrode or placed in contact with the electrode.

[0023] As described above, according to one aspect of the present embodiment, there is an advantage of significantly low contact resistance even though it includes a two-dimensional material.

[0024] FIG. 1 is a flowchart illustrating a method for reducing contact resistance of a two-dimensional semiconductor element according to one embodiment of the present invention.

[0025] FIGS. 2 and 3 are drawings illustrating a process for reducing the contact resistance of a two-dimensional semiconductor device according to one embodiment of the present invention.

[0026] FIG. 4 is a graph illustrating the band structure of a conventional two-dimensional semiconductor device and a two-dimensional semiconductor device according to an embodiment of the present invention.

[0027] FIG. 5 is a graph showing the current size according to the gate voltage of a conventional two-dimensional semiconductor device and a two-dimensional semiconductor device according to an embodiment of the present invention.

[0028] FIG. 6 is a graph showing the current size according to the applied voltage of a conventional two-dimensional semiconductor device and a two-dimensional semiconductor device according to an embodiment of the present invention.

[0029] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the invention to specific embodiments, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Similar reference numerals have been used for similar components in the description of each drawing.

[0030] Terms such as first, second, A, and B may be used to describe various components, but these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0031] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0032] The terminology used in this application is solely for the purpose of describing specific embodiments and is not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. It should be understood that terms such as "comprise" or "have" in this application do not preclude the presence or possibility of addition of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification.

[0033] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0034] Terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0035] In addition, each configuration, process, procedure or method included in each embodiment of the present invention may be shared within a scope that is not technically inconsistent with each other.

[0036] FIG. 1 is a flowchart illustrating a method for reducing contact resistance of a two-dimensional semiconductor element according to one embodiment of the present invention.

[0037] A two-dimensional semiconductor device manufactured using a method according to one embodiment of the present invention may not have a high contact resistance as in the prior art, despite containing a two-dimensional material. Accordingly, a two-dimensional semiconductor device manufactured using a method according to one embodiment of the present invention may possess the advantages of containing a two-dimensional material, while also having superior electrical performance due to a relatively significantly lower contact resistance.

[0038] A predetermined material is placed on an electrode within a two-dimensional semiconductor device (S110). The predetermined material is placed on the electrode within the two-dimensional semiconductor device or in contact with the electrode within the two-dimensional semiconductor device. Here, the predetermined material is composed of bismuth (Bi), indium (In), and tin (Sn), and is composed in a ratio of 30 to 35 wt%: 49 to 53 wt%: 15 to 18 wt%, respectively. A material composed of such components and ratios is placed on the electrode or in contact with the electrode.

[0039] A two-dimensional semiconductor device having a preset material disposed thereon is exposed to a preset environment (S120). Here, the preset environment may be an environment having a vacuum state and a temperature higher than the melting point of the preset material. Since the melting point of the preset material is around 62°C, the preset environment may be an environment having a vacuum state and a temperature higher than 62°C, and more preferably, an environment having a vacuum state and a temperature of 200 to 300°C. When the preset material is exposed to the above-described environment, it liquefies and, as illustrated in FIG. 3, propagates only along the electrodes within the two-dimensional semiconductor device and bonds with the electrodes.

[0040] FIGS. 2 and 3 are drawings illustrating a process for reducing contact resistance of a two-dimensional semiconductor device according to an embodiment of the present invention, and FIG. 4 is a graph illustrating a band structure of a conventional two-dimensional semiconductor device and a two-dimensional semiconductor device according to an embodiment of the present invention.

[0041] Referring to FIG. 2, a two-dimensional semiconductor device includes a substrate (210), an electrode (220) disposed on the substrate (210), and a two-dimensional material (230) disposed between the electrodes (220). The electrode (220) may be formed of a metal, for example, gold (Au) or chromium (Cr). Here, the two-dimensional material (230) may be a transition metal dichalcogenide (TMD), black phosphorus, or graphene. Since the two-dimensional semiconductor device includes the above-described configuration, it has an energy band structure as illustrated in FIG. 4a.

[0042] As a two-dimensional material (230) is placed between electrodes (220), a Schottky barrier is formed, significantly increasing the contact resistance of the semiconductor element.

[0043] In recognition of this problem, a material (240) is placed on or in contact with the electrode (220).

[0044] When the two-dimensional semiconductor element on which the preset material is placed is exposed to a preset environment, as illustrated in FIG. 3, the preset material is liquefied and bonded only on the electrodes along the electrodes (220). Accordingly, the preset material forms an ohmic bond as illustrated in FIG. 4b, so that even if the two-dimensional material is placed between the electrodes (220), it can have a significantly low contact resistance.

[0045] Because the preset material is liquefied and bonded only to the electrode along the electrode surface, it can be implemented with great precision. Even if the electrode is implemented on the order of hundreds of nanometers or even a few micrometers, the preset material can be precisely bonded only to the electrode surface. Consequently, the electrode can be implemented simply while ensuring excellent performance. This significant reduction in contact resistance can be confirmed in Figures 5 and 6.

[0046] FIG. 5 is a graph showing the current size according to the gate voltage of a conventional two-dimensional semiconductor device and a two-dimensional semiconductor device according to an embodiment of the present invention, and FIG. 6 is a graph showing the current size according to the applied voltage of a conventional two-dimensional semiconductor device and a two-dimensional semiconductor device according to an embodiment of the present invention.

[0047] Referring to FIG. 5a or FIG. 5b, it can be seen that, compared to conventional two-dimensional semiconductor devices, a two-dimensional semiconductor device according to an embodiment of the present invention flows a significantly larger current even when the same gate voltage is applied. It can be seen that several to several tens of times more current flows.

[0048] This can also be confirmed in Fig. 6. In a situation where a constant gate voltage is applied, the same source-drain voltage (V DS ) is applied, it can be confirmed that a current several to several tens of times greater flows in the two-dimensional semiconductor device according to an embodiment of the present invention compared to a conventional two-dimensional semiconductor device (the current magnitude values ​​in FIG. 6(a) and FIG. 6(b) are different). Referring to this, it can be confirmed that the two-dimensional semiconductor device according to an embodiment of the present invention has a significantly smaller contact resistance compared to a conventional two-dimensional semiconductor device.

[0049] Although each process is described as being executed sequentially in FIG. 1, this is merely an illustrative description of the technical idea of ​​one embodiment of the present invention. In other words, a person of ordinary skill in the art to which one embodiment of the present invention pertains may modify and apply various modifications and variations, such as changing the order described in each drawing and executing the process, or executing one or more of the processes in parallel, without departing from the essential characteristics of one embodiment of the present invention. Therefore, FIG. 1 is not limited to a chronological order.

[0050] Meanwhile, the processes illustrated in FIG. 1 can be implemented as computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes all types of recording devices that store data that can be read by a computer system. That is, a computer-readable recording medium includes storage media such as magnetic storage media (e.g., ROM, floppy disks, hard disks, etc.) and optical readable media (e.g., CD-ROMs, DVDs, etc.). In addition, a computer-readable recording medium can be distributed across network-connected computer systems, so that the computer-readable code can be stored and executed in a distributed manner.

[0051] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art to which the present embodiment pertains may make various modifications and variations without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The protection scope of the present embodiment should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

[0052]

[0053] CROSS-REFERENCE TO RELATED APPLICATION

[0054] This patent application claims priority under 35 USC § 119(a) to Korean Patent Application No. 10-2024-0119200, filed in Korea on September 3, 2024, the entire contents of which are incorporated by reference herein. Furthermore, this patent application claims priority in countries other than the United States for the same reasons, the entire contents of which are incorporated by reference herein.

Claims

1. A method for reducing the contact resistance of a two-dimensional semiconductor device, A placement process for placing a predetermined material on an electrode within a two-dimensional semiconductor device; and Exposure process of exposing a two-dimensional semiconductor device that has gone through the above arrangement process to a preset environment A method for reducing resistance of a two-dimensional semiconductor device, characterized by including:

2. In Paragraph 1, The above-mentioned established material is, A method for reducing the resistance of a two-dimensional semiconductor device characterized by being composed of bismuth (Bi), indium (In), and tin (Sn).

3. In paragraph 2, The above-mentioned established material is, A method for reducing resistance of a two-dimensional semiconductor device, characterized in that each component is composed of a preset ratio.

4. In paragraph 1, The above two-dimensional semiconductor device is, Substrate; Electrode disposed on the above substrate; and A method for reducing resistance of a two-dimensional semiconductor device, characterized in that it includes a two-dimensional material disposed between the electrodes.

5. In paragraph 4, The above two-dimensional material is, A method for reducing resistance of a two-dimensional semiconductor device characterized by being TMD (Transition Metal Dichalcogenide), black phosphorus or graphene.

6. In paragraph 1, The above-mentioned configured environment is, A method for reducing resistance of a two-dimensional semiconductor device characterized by having a preset temperature in a vacuum state.

7. In paragraph 6, The above-mentioned preset temperature is, A method for reducing resistance of a two-dimensional semiconductor device, characterized in that the melting point of the above-described material is higher than that of the above-described material. In an 8.2-dimensional semiconductor device, Substrate; Electrode disposed on the above substrate; A two-dimensional material disposed between the electrodes; and A predetermined material bonded only to the above electrode A two-dimensional semiconductor device characterized by including:

9. In Paragraph 8, The above-mentioned established material is, A two-dimensional semiconductor device characterized by being composed of bismuth (Bi), indium (In), and tin (Sn).

10. In paragraph 8, The above electrodes are, A two-dimensional semiconductor device characterized by being implemented with gold (Au) or chromium (Cr).

11. In Paragraph 8, The above two-dimensional material is, A two-dimensional semiconductor device characterized by being TMD (Transition Metal Dichalcogenide), black phosphorus, or graphene. In 12.2-dimensional semiconductor devices, Substrate; Electrode disposed on the above substrate; A two-dimensional material disposed between the electrodes; and It includes a preset material bonded only to the above electrode, and The above-mentioned established material is, A two-dimensional semiconductor device characterized by being disposed on the electrode, having a preset material disposed thereon, being exposed to a preset environment, and being bonded only on the electrode.

13. In paragraph 12, The above-mentioned established material is, A two-dimensional semiconductor device characterized by being disposed on the electrode or disposed in contact with the electrode.

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