Chirped all-pass group delay filter in coupled stripline

Abstract

A chirped all-pass group delay filter includes one or more layers of substrate and cascading coupled dispersive delay lines configured to cancel ripples, wherein the cascading coupled dispersive delay lines use a stripline configuration, thereby controlling phase offsets in each stage.

Description

[0001]CHIRPED ALL-PASS GROUP DELAY FILTER IN COUPLED STRIPLINE Related Applications This application claims the benefit of U.S. Provisional Patent Application Serial No.63 / 691,356 (filed September 6, 2024), which is hereby incorporated herein by reference in its entirety. Federally-Sponsored Research and Development This invention was made with United States Government support from the National Institute of Standards and Technology (NIST), an agency of the United States Department of Commerce. The Government has certain rights in this invention. Copyright Notice This patent disclosure may contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves any and all copyright rights. Field of Invention The present invention relates generally to frequency sweeping in radio frequency circuits, and more particularly to chirped group-delay filter for fast frequency sweeps. Background Fast analog wideband frequency sweeping has many potential use cases in field measurements of the radio spectrum. The speed of the sweep should be faster than the shortest transmission events in the frequency range of interest, while long enough to achieve reasonable frequency resolution. As an example, consider field monitoring of widely deployed cellular and local-area networks. Since these support transmission bursts as short as a few tens of μs across 600MHz - 7 GHz, an ideal wideband measurement would span the full bandwidth in a few μs. Summary of Invention Conventional instruments have limitations with respect to this type of measurement. High-performance heterodyne spectrum analyzer instruments that are commercially available support sweep times on the order of 10 ms, about three orders of magnitude longer than the goal. While real-time instruments can meet this time resolution requirement, wideband digitization is required, which comes at significant cost of dynamic range. Presented herein is an exemplary printed circuit board that implements a type of radio frequency all-pass filter known as a chirped group-delay filter and a method of designing such a board. Compared to conventional designs, exemplary designs reduce the gain ripple by a factor of 14, producing chirp duration of 25.75 ns swept across the radio frequencies of 2 - 3.95 GHz. Exemplary embodiments include cascading coupled dispersive delay lines using design parameters that are modulated to cancel ripples, and the use of stripline technology to control phase offsets in each stage. Applications include the generation of ultra-fast carrier frequency sweeps (>= 1 THz / sec) for laboratory testing or radio spectrum monitoring. According to one aspect of the invention, a method for designing and optimizing an exemplary N-stage cascaded filter system includes the steps of synthesizing each nthfilter stage into coupled stripline circuit board trace geometry, wherein each filter stage has respective independent values for center frequency fn, bandwidth Bn, and a spatial phase parameter φn; and varying the respective independent values across different stages to achieve overall design targets of overall center frequency fcand overall bandwidth B with reduced ripple in both loss and group delay. Optionally, the method includes the step of optimizing the respective independent variables in sub-groups of size Ns,and cascading these sub-groups until total loss meets a target maximum amount of loss. Optionally, the method includes the step of maximizing Δτ as part of a delay loop by minimizing gain ripple figure of merit δG / Δτ. Optionally, the step of minimizing the gain ripple figure of merit includes leveraging degrees of freedom available in a cascaded design by quadratic- phase spatial modulation. Optionally, the method includes the step of adjacently cascading a plurality of coupled non-uniform transmission lines. Optionally, the method includes the step of enforcing a maximum trace separation by clipping Z0e,nto a minimum limit, wherein Z0e,n(x) is the modulated coupled-mode impedances along the length of each nthnon-uniform transmission line and is defined further herein. Optionally, the method includes the step of suppressing coupling with via fencing placed along a centerline between traces where Z0e,n(x) < Z0e,min, thereby reducing separation between filter stages and thus total width of the filter system. Optionally, the method includes the step of optimizing A(x) that is applied to all stages, and then the set of {fn, Bn, ϕn}. Optionally, the method includes the steps of encapsulating chirp fidelity metrics like ripple, monotonicity, and chirping efficiency into a single cost, kcdefined further herein and wherein weighting coefficients are set based on application-driven design goals and different units, the passband delay efficiency, is a proportion of group delay response time that is chirped; and defining a loss cost kL. According to another aspect of the invention, a chirped all-pass group delay filter includes one or more layers of substrate; and cascading coupled dispersive delay lines configured to cancel ripples, wherein the cascading coupled dispersive delay lines use a stripline configuration, thereby controlling phase offsets in each stage. Optionally, the cascading coupled dispersive delay lines comprises coupled Bragg gratings. Optionally, stage of the cascaded filter has different spatial modulation. Optionally, filter includes a printed transmission topology using offset broadside-coupled stripline. Optionally, the filter includes via fencing along a centerline between traces where Z0e,n(x) < Z0e,min, thereby reducing separation between filter stages and thus total width of the filter system by suppressing coupling, wherein Z0e,n(x) is the modulated coupled-mode impedances along the length of each nthnon- uniform transmission line and is defined further herein. Optionally, the filter includes a first conductive layer; a first dielectric layer adjacent to the first conductive layer; a second conductive layer adjacent to the first dielectric layer and separated from the first conductive layer by the first dielectric layer; a second dielectric layer adjacent to the second conductive layer and separated from the first dielectric layer by the second conductive layer; a third conductive layer adjacent to the second dielectric layer and separated from the second conductive layer by the second dielectric layer; a third dielectric layer adjacent to the third conductive layer and separated from the second dielectric layer by the third conductive layer; and a fourth conductive layer adjacent to the third dielectric layer and separated from the third conductive layer by the third dielectric layer; wherein coupled center conductors are located on either side of the second dielectric layer, in the second and third conductive layers, and wherein first and fourth conductive layers are configured as shielding layers, and are electrically coupled to each other. Optionally, the second dielectric layer is relatively thin compared to the first and third dielectric layers. Optionally, the conductive layers are printed layers of chemically-etched rolled copper. The foregoing and other features of the invention are hereinafter described in greater detail with reference to the accompanying drawings. Brief Description of the Drawings FIG.1 shows an exemplary cascaded multi-stage filter, illustrated by (a), that achieves low ripple in gain and group delay by varying spatial modulation parameters in coupled NUTL across the stages, as shown in (b). FIG.2 shows discontinuities in trace layout synthesis: an asymptote in separation distance s(x) arises when Z0e(x) is near 50Ω, as shown in (a). A conventional solution is to truncate the separation between the coupled lines, as in (b). An exemplary approach is to suppress coupling with a shorting wall for Z0e(x) < Z0e,min, as in (c). FIG.3 shows an offset broadside-coupled stripline transmission structure used to implement each stage of the filter as cross-section (left) and from above (right). Grounding vias are illustrated in solid black. FIG.4 shows the Z0 = 50Ω matching condition (solid line) trace dimension contour and its intersection with achievable even-mode impedances (dashed lines) for the stripline structure of Fig.3. The range of even-mode impedances used in the design was Z0e,max= 52Ω to Z0e,max= 123Ω. FIG.5 shows an exemplary layout of the two interior stripline layers (orange shades) and vias (black) of an exemplary 14-stage filter. Microstrip transitions on the left side of the board lead to coaxial adapters, as marked, while those on the right side are terminated with 50Ω resistors. The dimensions of the board are 305mm×107mm×2 mm. FIG.6 shows a partial zoomed-in version of FIG.5. FIG.7 shows an exemplary method for designing and optimizing an exemplary N-stage cascaded filter system. Detailed Description There are several benefits to fast sweeping in spectrum sensing and monitoring applications. For instance, fast wideband sweeps could flag out-of- band overload events in narrowband receivers. In other cases, measurement acquisition times could be cut significantly by increasing the probability of intercept with relaxed digitization requirements. As one example, statistical distribution of gap times between rare burst events is extremely long-tailed; measurements based on slow narrowband sweeps are forced to linger in a single channel for seconds at a time. A faster sweep could allow a dramatic improvement by monitoring many channels simultaneously. To measure occupancy rate statistics, it is necessary to capture many occupancy events. This becomes time-consuming for infrequently-used channels, which has been observed even in commonplace residential environments. Fast local oscillator (LO) sweeps may be used to set the center frequency in ultra-fast scans of the radio spectrum, allowing near-simultaneous visibility into transmissions across widely spaced frequency bands. This capability helps to guarantee that even extremely short transmissions can be captured and observed. Receivers that use this type of filter to manipulate input pulses are sometimes known as compressive receivers. The all-pass linear group-delay filter is the core microwave component needed for one approach to generating these fast LO sweeps for spectrum sensing or monitoring. In this context, the filter is used to spread the frequency components of a short input pulse into a fast LO sweep. This is the opposite of their original purpose in radar receivers, which perform detection by compressing frequency-modulated continuous wave (FMCW) chirps into short pulses, allowing noise to be removed by time-gating. Still, receivers that use linear group-delay filters to manipulate input pulses are sometimes known as compressive receivers. This name has held in the context of LO sweeping by pulse expansion for observing the radio spectrum. Therefore, presented herein is a precision filter capable of studying practical applications of fast sweeping in laboratory or fixed installation settings. It may be applied as part of a delay loop in order to multiply the achievable sweep time. Thus, in contrast with conventional systems, which constrained the filter size and cost by assuming low-gain amplifiers, exemplary systems permit a large circuit board and loss as large as 30 dB. In exchange, exemplary systems minimize gain ripple with similar loss per chirp duration. This is achieved by varying the spatial modulation in each stage of a cascaded filter composed of coupled Bragg gratings, as shown by Fig.1. To overcome large line losses, implementing LO sweeps longer than 1 μs with these filters at microwave frequencies requires a technique known as delay looping. As examples, the loss figure of merit −G / Δτ achieved in prior passive designs has been as low as 0.12 dB / ns at 1 GHz, while printed circuit designs centering at a few GHz have tended closer to 1 dB / ns. The delay loop avoids losses of hundreds of dBs (or more) by embedding the filter in an amplified feedback loop. To design a filter that can maximize Δτ as part of a delay loop, one may minimize the gain ripple figure of merit δG / Δτ, because M feedback cycles in the loop multiply not just the sweep time as M × Δτ (as desired) but also gain ripple over frequency, M × δG. Since the multiplied gain ripple needs to be small enough to maintain the LO drive level across the full frequency sweep range, there is an upper limit on M and thus also the achievable sweep time. In exemplary designs, in order to minimize δG / Δτ, the main strategy is not to improve the single stages in isolation, but to leverage the degrees of freedom available in a cascaded design. To this end, quadratic-phase spatial modulation is particularly appealing, since the truncation and Fresnel ripple may cancel across multiple stages. Further, while these coupled NUTLs are long, they can be cascaded and laid out adjacently. The modulated coupled-mode impedances along the length of each nthNUTL are Z0e,n(x) (even) and Z0o,n(x) (odd). A common port input impedance Z0 is set for all 4 ports of every stage. The formula for Z0e,n(x) takes the form, Following the convention in prior work, we specify Z0e,n(x) and Z0, since they then determine Z0o,n(x). The modulation function, χn(x), implements the quadratic phase in coupling with respect to x and frequency that produces chirped group delay. Within the scope of each stage, χn(x) is parameterized by its own design center frequency fn, bandwidth Bn, and for multi-layer structures, spatial modulation phase offset The phase offset creates a new degree of freedom for design in broadside-coupled structures; otherwise, for edge-coupled structures, = π / 2. The modulation formulas also account for maximum line length (Lmax) and bounds on achievable Z0e,n(Z0e,minand Z0e,max), which are fixed across all stages. The coupling profile function, A(x), is applied in common across all stages. This is a slow monotonic function that gives us some fine-tuning control over gain, bandwidth, and flatness, which we can leverage in a similar way to a Fourier window function. In fact, prior work set these based on the left half of Fourier window functions, including Gaussian and modified Kaiser half-windows. The intuitive appeal of this approach lies with an approximation that relates S21,n(f) and Z0e,n(x) through a Fourier transform relationship. However, the quantitative errors in this approach are not well understood in the context of group delay filters. As a result, spectral window functions may be used only as an initial starting point before optimization. The remaining coefficient, An, sets the maximum value of Z0e,n(x). For automated optimization, we need to determine this given Z0e,maxand arbitrary A(x) and χn(x), but did not find an expression in prior work. By solving (1) for Z0e,n(x) → Z0e,max, we get This enforces Z0e,n(x) ∈ [Z0,Z0e,max] before we apply further adjustments to accommodate a discontinuity at low coupling. When Z0e,n(x) → Z0, the realization of Z0e,ntends toward a discontinuity in planar layout dimensions. An example of this phenomenon is shown by FIG. 2(a), where coupling is controlled by trace separation distance. In this case, since the even-mode impedance can only reach Z0when all coupling is suppressed, the layout synthesis would have to prescribe infinite separation distance. For electrical performance, the risk in increasing separation distance is the excitation of higher-order modes, which distort the gain and group delay response by in the structure. In order to preserve the transverse electromagnetic (TEM) line propagation required by some simulation methods, one may accept slight distortion in the modulation where Z0e,n(x) < Z0e,min. The filter designer has options in the nature of the distortion. The approach taken in FIG.2(b) is to enforce a maximum trace separation by clipping Z0e,nto a minimum limit. In stripline-like structures, we propose suppression of coupling with via fencing, as shown by FIG.2(c). The fence placement is along the centerline between traces where Z0e,n(x) < Z0e,min. The impact is to set Z0e,n= Z0, with some corresponding adjustment in the trace width. As with clipping, this reduces the separation between filter stages and thus the total width of the filter. In empirical and simulation experience centered on stripline designs more ripple suppression is seen when using the center-line fencing technique. This is not significant on the scale of each stage alone, in terms of ripple in gain and group delay. Instead, the benefit arises in the cascaded design, where ripple cancellation is more effective. Further, this approach has tended to give closer agreement between finite element method (FEM) modeling and the piecewise NUTL simulation, and greater return loss. A multi-stage filter leverages many degrees of freedom in the design for minimized ripple and loss. Besides the choice of A(x), each nthstage can be synthesized with its own independent parameters {fn,Bn, ϕn}, which together define the design space that is available to a shared board stack-up. In what follows, we develop a multi-stage synthesis procedure that minimizes loss and ripple through A(x) and further reduces ripple through the selection of stage parameters. The approach is detailed by first selecting the algorithm and establishing multi-objective cost functions before describing the design procedures for the A(x) and the stage parameters. Our strategy pursues optimization methods, because of the lack of closed-form expressions for the loss and ripple responses of these designs. In this application, the optimization can be viewed as a fine-tuning step, improving on replicated cascaded copies of a single-stage design. To select an appropriate algorithm for this purpose, one may look for the following: 1) support for bounding constraints on all design input parameters; 2) support for a large parameter spaces; 3) global scope across the full range of bounds in design space; 4) a non-differentiable solution space, because cost function discontinuities arise from the quantized stage lengths Ln; and, 5) maturity and prior study in multi-objective microwave and filter design problems. Evolution-based optimizers have found wide use in electromagnetic applications and filter design. Within this class of algorithms, one may use differential evolution in its original form. Besides wide use in antenna arrays and inverse scattering problems, it has been applied to multi-objective optimization of microwave filters given constraints. However, other algorithms could also work in this context. An approach is to first optimize the A(x) that is applied to all stages, and then the set of {fn, Bn, ϕn}. In each tuning iteration, one may synthesize each NUTL in the cascade and then evaluate the resulting response. Cost heuristics should be chosen that evaluate the design fitness in terms of ripple and loss. The costs are defined and evaluated only within the passband, and normalized by Δτ where needed, so that design fitness can be compared across different Lnand N. First, one may encapsulate chirp fidelity metrics like ripple, monotonicity, and chirping efficiency into a single cost, kc: The need for the weighting coefficients Wn here comes from the application- driven design goals, and also the different units among the kn. The passband delay efficiency, ητ= Δτ / τmax, is the proportion of the group delay response time that is chirped. Next, a loss cost kLneeds to be defined. The understanding here is that external gain equalization will be added to correct the design afterward. At best, a passive equalizer can only flatten the gain to the lowest uncorrected passband gain. Therefore, therefore set the loss cost as With the cost functions defined, we move on to apply them in optimization procedures used to determine each of W(x) and the stage coefficients. Our primary purpose in the design of A(x) is to minimize the maximum loss across the passband. A secondary goal is to reduce ripple, though this is mainly addressed through the stage parameters in the cascaded design. The optimizer may only accept a vector of discrete values, so A(x) may need to be discretized. To do this, one may represent A(x) as a piecewise linear interpolation at points A(xk), for a fixed number of xkspread uniformly across x. The optimizer may then treat the A(xk) as free variables. • Number of stages: 1 • Cost heuristic: kc× kL• Variables: discretized points in A(x), f1, B1, ϕ1• Initial conditions: {A(x) ∼ Triangular half-window, f1 = fc, B1 = B, ϕ1 = π / 2} The cost heuristic calculations are given by (3) and (4). Empirical experience so far shows that it is important to optimize not only A(x) here, but also f1, B1, and ϕ1. The purpose is to establish the coupling profile under best-case conditions, even if only optimized for 1 stage. The reasoning behind this is to use this as a rough first-pass at minimizing δG and δτ. Now that A(x) has been designed, one can move on to reducing ripple further by optimization of fn, Bn, The first step is to select the total number of stages in the design, N. An assumption is that the goal is to maximize Δτ given a fixed loss budget, which might be determined based on the gain of an input amplifier. Therefore, the number of stages can be estimated based on the optimized A(x). The tuning procedure may be applied separately to each cascaded subsection in design. Limiting the number of stages being optimized at any one time becomes necessary for large N, when the optimizer starts differential evolution struggled to converge. Thus, to tune each subset of NSstages, our procedure is as follows: • Number of stages: NS∈ {2, ... ,N} • Cost heuristic: kc• Variables: {f1, ..., fNS}, {B1, ...,BNS}, {ϕ1, ..., ϕNS} • Initial conditions: all {fn= fc,Bn= B, ϕn= π / 2} The cost heuristic calculations are given by (3). In this procedure, we do not penalize for loss, with the idea that this was already optimized through A(x). The numerical performance of the synthesized design depends heavily on all three parameters in each stage. To optimize the full N stages in cascade, we repeat the procedure in each section, where each has a different number of stages, NS. The optimized vectors that result from each iteration of the procedure are concatenated together. As a final cascaded design, the resulting vectors are {f1, ..., fN}, {B1, ...,BN}, and {ϕ1, ..., ϕN}. An exemplary printed transmission topology is offset broadside-coupled stripline, illustrated by Fig.3. This allows use of the full range of approaches detailed above. Compared with edge-coupled microstrip, shielding may be gained by via fencing, and the ability to vary An exemplary layer stackup consists of 4 printed layers of chemically- etched rolled copper, that are separated by 3 dielectric layers. In this design we chose ^r= 3 substrate to avoid a thick layer stackup at Z0= 50Ω. The coupled center conductors 310, 312 are printed on either side of the center dielectric layer 320, which was set to the thinnest available to maximize coupling at s = 0. The outer dielectric slabs 322, 324 are much thicker, which was necessary to achieve Z0 = 50Ω at reasonable w when s = 0. These inner traces are embedded in respective thin 87 μm bonding layers 330, 332 between the 3 dielectric slabs. Shielding is provided by the outer copper layers 340, 342 on the top and bottom, which are stitched together with plated vias 350, 352 where shown. The approximate size of the circuit board panel is 300mm × 450 mm. The design formulas for conventional coupled-trace dimensions do not account for the trace thickness or the via fence “side-wall.” To include their effects in the mappings (Z0e,n(x) ↔ sn(x), Z0e,n(x) ↔ wn(x)), one may use full- wave electromagnetic simulations. The approach is to sweep across a uniform sampling grid on s and w with, for example, a commercial FEM solver. The bounds on this sweep may be determined with a first-order model known in the art. The simulations produced the coupled impedance mappings shown by the contour plots in Fig.4. The interpolated contour at Z0= 50Ω is the numerical mapping that we used to synthesize printed traces from Z0e,n(x). Some additional simulation was needed before setting Z0e,min = 52Ω to minimize synthesis discontinuity. By hand-tuning in simulation, this was identified as the threshold for which s could be left the same either with center-line shielding Z0e(x) → Z0 or (Z0e(x) → Z0e,min). Where center-line shielding was applied, only a slight adjustment to w was needed to maintain matching, since coupling between the trace and the center-line shielding was weak. Turning now to FIG.5, an exemplary layout of two interior stripline layers 510, 512 and vias 550 of an exemplary 14-stage filter is shown at 500. Microstrip transitions 560, 562 on the bottom of the figure lead to coaxial adapters or ports, as marked, while those on the top of the figure are terminated with 50Ω resistors 570. The dimensions of the exemplary board as shown are 305mm×107mm×2 mm. To synthesize the layout artwork from Z0e,n(x), one may apply the inverted trace dimension mappings from Fig.4 to determine wn(x) and sn(x). With these parameters, one may synthesize geometry on each of the inner stripline layers on a 5 μm grid using a set-theoretic planar geometry engine, e.g. This tool allows placing grounded via fence shielding along a curved path conforming to 1.2mm clearance around each coupled NUTL and where needed for center-line shielding. The exemplary via fences comprise plated 0.3mm drill holes with 0.55mm center-to-center spacing. Stripline to microstrip transitions may be used to connect the cascaded filter with coaxial connectors, and to create footprints for surface-mount terminations to ground. The layout of the two inner layers are illustrated with vias in FIG.6, a zoomed-in partial view of FIG.5. The large via holes 650 near the edge of the board provide mounting points for the board and the coaxial adapters. Transitions to microstrip and surface mount pads are located where marked. A fullwave FEM modeler may be used to validate the design and to conduct filter evaluation and optimization procedures. Because the model may be too large to evaluate for all 14 stages, it may simulated at smaller increments, e.g., only for the NS = 4 section of the filter, replacing the via fences with ideally conductive sheets. When coupling suppression was applied instead of truncation, the closest cross-validation between the full-wave simulation and chain-matrix evaluation may be achieved. Exemplary embodiments may use the center-line grounding vias where Z0e,n ≤ Z0e,min. A method according to the descriptions above for designing and optimizing an exemplary N-stage cascaded filter system is shown at FIG.7. The taper function A(x), which is a slow ramp needed to reduce ripple, is designed through an optimization procedure, rather than by using sub-optimal choices as in conventional systems. Each nthfilter stage is synthesized into coupled stripline circuit board trace geometry using a procedure similar to that known in the art, for example, in A. Lujambio, I. Arnedo et al., “Dispersive Delay Line with Effective Transmission-Type Operation in Coupled-Line Technology,” IEEE Microw. Wireless Compon. Lett., vol.21, pp.459–461, 2011. Each has its own independent values for center frequency fn and bandwidth Bn, and a new spatial phase parameter φn. These are varied across the different stages of the design to achieve the overall design targets fcand B with reduced ripple in both loss and group delay. Large designs are optimized in smaller groups that have size Ns. The final synthesized design is achieved by cascading these sub-groups of sizes {2, 3, …} until the total loss meets the target maximum amount of loss. The processes described herein may be embodied in, and fully automated via, software code modules executed by a computing system that includes one or more general purpose computers or processors. The code modules may be stored in any type of non-transitory computer-readable medium or other computer storage device. Some or all the methods may alternatively be embodied in specialized computer hardware. In addition, the components referred to herein may be implemented in hardware, software, firmware, or a combination thereof. Many other variations than those described herein will be apparent from this disclosure. For example, depending on the embodiment, certain acts, events, or functions of any of the algorithms described herein can be performed in a different sequence, can be added, merged, or left out altogether (e.g., not all described acts or events are necessary for the practice of the algorithms). Moreover, in certain embodiments, acts or events can be performed concurrently, e.g., through multi-threaded processing, interrupt processing, or multiple processors or processor cores or on other parallel architectures, rather than sequentially. In addition, different tasks or processes can be performed by different machines and / or computing systems that can function together. Any logical blocks, modules, and algorithm elements described or used in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, and elements have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The described functionality can be implemented in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure. The various illustrative logical blocks and modules described or used in connection with the embodiments disclosed herein can be implemented or performed by a machine, such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, but in the alternative, the processor can be a controller, microcontroller, or state machine, combinations of the same, or the like. A processor can include electrical circuitry configured to process computer- executable instructions. In another embodiment, a processor includes an FPGA or other programmable device that performs logic operations without processing computer-executable instructions. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Although described herein primarily with respect to digital technology, a processor may also include primarily analog components. For example, some or all of the signal processing algorithms described herein may be implemented in analog circuitry or mixed analog and digital circuitry. A computing environment can include any type of computer system, including, but not limited to, a computer system based on a microprocessor, a mainframe computer, a digital signal processor, a portable computing device, a device controller, or a computational engine within an appliance, to name a few. The elements of a method, process, or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module stored in one or more memory devices and executed by one or more processors, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of non-transitory computer-readable storage medium, media, or physical computer storage known in the art. An example storage medium can be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The storage medium can be volatile or nonvolatile. While one or more embodiments have been shown and described, modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustrations and not limitation. Embodiments herein can be used independently or can be combined. All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other. The ranges are continuous and thus contain every value and subset thereof in the range. Unless otherwise stated or contextually inapplicable, all percentages, when expressing a quantity, are weight percentages. The suffix (s) as used herein is intended to include both the singular and the plural of the term that it modifies, thereby including at least one of that term (e.g., the colorant(s) includes at least one colorants). Option, optional, or optionally means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where the event occurs and instances where it does not. As used herein, combination is inclusive of blends, mixtures, alloys, reaction products, collection of elements, and the like. As used herein, a combination thereof refers to a combination comprising at least one of the named constituents, components, compounds, or elements, optionally together with one or more of the same class of constituents, components, compounds, or elements. All references are incorporated herein by reference. The use of the terms “a,” “an,” and “the” and similar referents in the context of describing the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. It can further be noted that the terms first, second, primary, secondary, and the like herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. For example, a first current could be termed a second current, and, similarly, a second current could be termed a first current, without departing from the scope of the various described embodiments. The first current and the second current are both currents, but they are not the same condition unless explicitly stated as such. The modifier about used in connection with a quantity is inclusive of the stated value and has the meaning dictated by the context (e.g., it includes the degree of error associated with measurement of the particular quantity). The conjunction or is used to link objects of a list or alternatives and is not disjunctive; rather the elements can be used separately or can be combined together under appropriate circumstances. Although the invention has been shown and described with respect to a certain embodiment or embodiments, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described elements (components, assemblies, devices, compositions, etc.), the terms (including a reference to a "means") used to describe such elements are intended to correspond, unless otherwise indicated, to any element which performs the specified function of the described element (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiment or embodiments of the invention. In addition, while a particular feature of the invention may have been described above with respect to only one or more of several illustrated embodiments, such feature may be combined with one or more other features of the other embodiments, as may be desired and advantageous for any given or particular application.

Claims

Claims What is claimed is:

1. A method for designing and optimizing an exemplary N-stage cascaded filter system, the method comprising the steps of: synthesizing each nthfilter stage into coupled stripline circuit board trace geometry, wherein each filter stage has respective independent values for center frequency fn, bandwidth Bn, and a spatial phase parameter φn; and varying the respective independent values across different stages to achieve overall design targets of overall center frequency fcand overall bandwidth B with reduced ripple in both loss and group delay.

2. The method of claim 1, further comprising the step of: optimizing the respective independent variables in sub-groups of size Ns,and cascading these sub-groups until total loss meets a target maximum amount of loss.

3. The method of claim 1, further comprising the step of: maximizing Δτ as part of a delay loop by minimizing gain ripple figure of merit δG / Δτ.

4. The method of claim 3, wherein the step of minimizing the gain ripple figure of merit includes leveraging degrees of freedom available in a cascaded design by quadratic-phase spatial modulation.

5. The method of claim 1, further comprising the step of: adjacently cascading a plurality of coupled non-uniform transmission lines.

6. The method of claim 1, further comprising the step of: enforcing a maximum trace separation by clipping Z0e,nto a minimum limit, wherein Z0e,n(x) is the modulated coupled-mode impedances along the length of each nthnon-uniform transmission line and wherein:

7. The method of claim 6, further comprising the step of: suppressing coupling with via fencing placed along a centerline between traces where Z0e,n(x) < Z0e,min, thereby reducing separation between filter stages and thus total width of the filter system.

8. The method of claim 1, further comprising the step of: optimizing A(x) that is applied to all stages, and then the set of {fn, Bn, ϕn}.

9. The method of claim 1, further comprising the step of: encapsulating chirp fidelity metrics like ripple, monotonicity, and chirping efficiency into a single cost, kcwherein weighting coefficients Wnare set based on application-driven design goals and different units among the kn, the passband delay efficiency, ητ= Δτ / τmax, is a proportion of group delay response time that is chirped; and defining a loss cost kL10. A chirped all-pass group delay filter comprising: one or more layers of substrate; andcascading coupled dispersive delay lines configured to cancel ripples, wherein the cascading coupled dispersive delay lines use a stripline configuration, thereby controlling phase offsets in each stage.

11. The chirped all-pass group delay filter of claim 10, wherein the cascading coupled dispersive delay lines comprises coupled Bragg gratings.

12. The chirped all-pass group delay filter of claim 10, wherein each stage of the cascaded filter has different spatial modulation.

13. The chirped all-pass group delay filter of claim 10, further comprising a printed transmission topology using offset broadside-coupled stripline.

14. The chirped all-pass group delay filter of claim 10, further comprising: via fencing along a centerline between traces where Z0e,n(x) < Z0e,min, thereby reducing separation between filter stages and thus total width of the filter system by suppressing coupling, wherein Z0e,n(x) is the modulated coupled-mode impedances along the length of each nthnon-uniform transmission line and wherein:

15. The chirped all-pass group delay filter of claim 10, further comprising: a first conductive layer; a first dielectric layer adjacent to the first conductive layer; a second conductive layer adjacent to the first dielectric layer and separated from the first conductive layer by the first dielectric layer; a second dielectric layer adjacent to the second conductive layer and separated from the first dielectric layer by the second conductive layer; a third conductive layer adjacent to the second dielectric layer and separated from the second conductive layer by the second dielectric layer;a third dielectric layer adjacent to the third conductive layer and separated from the second dielectric layer by the third conductive layer; and a fourth conductive layer adjacent to the third dielectric layer and separated from the third conductive layer by the third dielectric layer; wherein coupled center conductors are located on either side of the second dielectric layer, in the second and third conductive layers, and wherein first and fourth conductive layers are configured as shielding layers, and are electrically coupled to each other.

16. The chirped all-pass group delay filter of claim 16, wherein the second dielectric layer is relatively thin compared to the first and third dielectric layers.

17. The chirped all-pass group delay filter of claim 16, wherein the conductive layers are printed layers of chemically-etched rolled copper.

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