Switched capacitor circuit, driving method for switched capacitor circuit, and electronic device

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide a switched capacitor circuit, a driving method for a switched capacitor circuit, and an electronic device, used for reducing the loss of the switched capacitor circuit. The switched capacitor circuit comprises an inductor network connected in series to an output end and / or a capacitor. The inductor network can suppress a sudden change in current, and protects the circuit from a sudden current impact. Therefore, the sudden change in current can be suppressed in a branch connected in series to the inductor network. The branch does not have an impact current, and likewise does not generate a current impact on other branches, which can reduce, to a certain extent, the impact current in branches where the capacitor and the output end are located, reduce the loss of the switched capacitor circuit, and improve the efficiency of the switched capacitor circuit. The impact current can also be suppressed by adjusting a driving timing or a capacitance value of the switched capacitor circuit, thereby reducing the loss of the switched capacitor circuit.

Description

Switched capacitor circuit, driving method of switched capacitor circuit, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411307282.X, filed on September 14, 2024, and entitled "Switched capacitor circuit, driving method of switched capacitor circuit, and electronic device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronics, and in particular to a switched capacitor circuit, a driving method of the switched capacitor circuit, and an electronic device. BACKGROUND

[0003] Electronic devices such as mobile phones, watches, and tablet computers achieve wired or wireless fast charging by outputting a high voltage of 2 (or 4) times the battery voltage through a power adapter or a wireless charging circuit, and then reducing the high voltage to 1 / 2 (or 1 / 4) through a switched capacitor circuit (SC) in the electronic device to charge the battery. In this way, under the same power, using high voltage to transmit power can reduce the transmission current and reduce line loss. In addition, the switched capacitor circuit SC has the characteristics of open-loop high efficiency, and combining the charging protocol to control the adapter or the wireless charging circuit to adjust the voltage or current can make the entire charging system of the electronic device efficient and reduce heat consumption, thereby achieving super-fast charging.

[0004] Currently, the loss of the switched capacitor circuit itself is an important reason for limiting the efficiency of the switched capacitor circuit. SUMMARY

[0005] The present application provides a switched capacitor circuit, a driving method of the switched capacitor circuit, and an electronic device including the switched capacitor circuit, for reducing the loss of the switched capacitor circuit.

[0006] In a first aspect, the present application provides a switched capacitor circuit, which includes a switched capacitor sub-circuit, an inductor network, an input terminal, and an output terminal. The switched capacitor sub-circuit includes a first capacitor, a first-stage switch network, and a switched capacitor network, and the switched capacitor network includes a second capacitor, a third capacitor, and a second-stage switch network. The first-stage switch network is coupled to the input terminal and the first capacitor, respectively, and is configured to adjust the on-off relationship between the first capacitor and the input terminal. The second-stage switch network is coupled to the first capacitor, the second capacitor, and the third capacitor, respectively, and is configured to adjust the series-parallel relationship among the first capacitor, the second capacitor, and the third capacitor. The first end of the inductor network is coupled to the switched capacitor network, and the second end of the inductor network is coupled to the output terminal.

[0007] The switch capacitor circuit provided by the embodiments of the present application has an inductive network in series at the output end. The inductive network can suppress current mutation and protect the circuit from sudden current impact. Therefore, after the inductive network is connected in series at the branch where the output end is located, the mutation of the total output current can be limited, the total output current will not contain impact current, and the branch where the output end is located will not impact the branches where the first capacitor, the second capacitor and the third capacitor are located. The impact current of the branches where the first capacitor, the second capacitor and the third capacitor are located can be reduced to a certain extent, the loss of the switch capacitor circuit is reduced, and the efficiency of the switch capacitor circuit is improved.

[0008] In a first possible implementation, the switch capacitor sub-circuit includes a plurality of switch capacitor networks coupled in series, and the last stage switch capacitor network is coupled to the first end. The switch capacitor circuit includes a plurality of second switch capacitor networks coupled in series, and the ratio of the input voltage of the input end VI to the output voltage Vvo is 2 N+1 :1, so as to realize high conversion ratio and meet different use requirements.

[0009] In a second possible implementation, the switch capacitor circuit includes at least one switch capacitor group, and the switch capacitor group includes two-phase switch capacitor sub-circuits coupled in interleaved parallel between the input end and the inductive network. By arranging two-phase switch capacitor sub-circuits in the switch capacitor circuit, the switch capacitor circuit can meet a larger charging power.

[0010] In a third possible implementation, the switch capacitor circuit includes a plurality of switch capacitor groups coupled in parallel between the input end and the inductive network. By arranging a plurality of switch capacitor groups in the switch capacitor circuit, the ripple of the charging voltage can be reduced, and the stability of the charging voltage can be improved.

[0011] In a possible implementation, the capacitance of the first capacitor is greater than the capacitance of the second capacitor, and the capacitance of the second capacitor is equal to the capacitance of the third capacitor. In the case that the capacitance of the first capacitor is greater than the capacitance of the second capacitor, and the capacitance of the second capacitor is equal to the capacitance of the third capacitor, the first capacitor can be equivalent to a voltage source, the capacitance of the first capacitor is large and the impedance is small, and the influence of the first capacitor on the voltage drop on the branch can be ignored. In this way, the influence of the first capacitor on the voltage drop on the branch during switching between series connection with the second capacitor and series connection with the third capacitor can be ignored, so as to reduce the impact current of the switch capacitor circuit during mode switching.

[0012] In a possible implementation, the capacitance of the first capacitor is more than twice the capacitance of the second capacitor. In this way, almost no impact current is generated between the branch where the second capacitor is located and the branch where the third capacitor is located, so as to effectively suppress the impact current between the second capacitor and the third capacitor.

[0013] In a possible implementation, the second-stage switch network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; a first electrode of the first transistor is coupled with a negative electrode of a first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of a second capacitor respectively; a second electrode of the second transistor is coupled with the first terminal and a first electrode of the third transistor respectively; a second electrode of the third transistor is coupled with a negative electrode of the second capacitor and a first electrode of the fourth transistor respectively; a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of a third capacitor respectively; a second electrode of the sixth transistor is coupled with the first terminal and a first electrode of the seventh transistor respectively; a second electrode of the seventh transistor is coupled with a negative electrode of the third capacitor and a first electrode of the eighth transistor respectively; and a second electrode of the eighth transistor is coupled with the reference ground voltage terminal. This is a topology with simple structure.

[0014] In a possible implementation, the switch capacitor circuit comprises two-phase switch capacitor sub-circuits; the seventh transistor in one phase switch capacitor sub-circuit and the third transistor in the other phase switch capacitor sub-circuit are the same transistor; or the eighth transistor in one phase switch capacitor sub-circuit and the fourth transistor in the other phase switch capacitor sub-circuit are the same transistor.

[0015] In a possible implementation, the switch capacitor sub-circuit comprises a plurality of switch capacitor networks coupled in series. The second switch network in each of the switch capacitor networks comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. In each of the switch capacitor networks, a first electrode of the fourth transistor is coupled to a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled to a reference ground voltage terminal. A first electrode of the eighth transistor is coupled to a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled to the reference ground voltage terminal. In the first switch capacitor network, a first electrode of the first transistor is coupled to a negative electrode of a first capacitor, and a second electrode of the first transistor is coupled to a first electrode of the second transistor and a positive electrode of a second capacitor. A first electrode of the fifth transistor is coupled to a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor and a positive electrode of a third capacitor. In the switch capacitor network other than the first switch capacitor network, a first electrode of the first transistor is coupled to a second electrode of the second transistor in the previous switch capacitor network, and a second electrode of the first transistor is coupled to a first electrode of the second transistor and a positive electrode of the second capacitor. A first electrode of the fifth transistor is coupled to a second electrode of the sixth transistor in the previous switch capacitor network, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor and a positive electrode of the third capacitor. In the last switch capacitor network, a second electrode of the second transistor, a first electrode of the third transistor, a second electrode of the sixth transistor and a first electrode of the seventh transistor are all coupled to an output terminal. In the switch capacitor network other than the last switch capacitor network, a second electrode of the second transistor is coupled to a first electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to a first electrode of the third transistor. This is a simple topology.

[0016] In a possible implementation, the seventh transistor in the last switch capacitor network in the switch capacitor sub-circuit of one phase is the same transistor as the third transistor in the last switch capacitor network in the switch capacitor sub-circuit of another phase, or the eighth transistor in the last switch capacitor network in the switch capacitor sub-circuit of one phase is the same transistor as the fourth transistor in the last switch capacitor network in the switch capacitor sub-circuit of another phase. In this way, the number of transistors in the switch capacitor circuit can be reduced, and the area occupied by the switch capacitor circuit can be reduced.

[0017] In a second aspect, the application provides a driving method for a switched-capacitor circuit, the switched-capacitor circuit comprising the switched-capacitor circuit in the second and third possible implementation manners of the first aspect. The second-stage switching network comprises a second transistor, a third transistor, a sixth transistor and a seventh transistor; the second transistor and the third transistor are connected in series and are connected in parallel with a second capacitor; the sixth transistor and the seventh transistor are connected in series and are connected in parallel with a third capacitor; the first capacitor, the second capacitor and the third capacitor have equal capacitance values; the switched-capacitor circuit comprises a first-phase switched-capacitor sub-circuit; the driving method comprises: for the first-phase switched-capacitor sub-circuit, in a first mode, the third transistor and the sixth transistor are turned on, and the second transistor and the seventh transistor are turned off; in a second mode, the sixth transistor is turned off, the third transistor is turned on, and the second transistor and the seventh transistor are turned off; in a third mode, the third transistor and the sixth transistor are turned off, and the second transistor and the seventh transistor are turned on; in a fourth mode, the third transistor and the sixth transistor are turned off, the seventh transistor is turned on, and the second transistor is turned off.

[0018] The driving method provided by the application is used to drive the switched-capacitor circuit, the second mode and the fourth mode are added, and a branch with a capacitor is turned off in the two modes, so as to eliminate the current impact between the two branches with capacitors. Therefore, the impact current between the first capacitor, the second capacitor and the third capacitor can be suppressed without increasing the capacitance value of the first capacitor, so as to reduce the loss of the switched-capacitor circuit and improve the efficiency of the switched-capacitor circuit. That is, after the new control logic is introduced, the capacitance value relationship of the first capacitor, the second capacitor and the third capacitor can be broken, and the first capacitor with a smaller capacitance value can be used to suppress the impact current.

[0019] In a possible implementation manner, the switched-capacitor circuit comprises two-phase switched-capacitor sub-circuits; the two-phase switched-capacitor sub-circuits operate in a phase difference of 180°. For the switched-capacitor circuit comprising the two-phase switched-capacitor sub-circuits, the driving method can also suppress the impact current.

[0020] In a possible implementation manner, the duty cycles of the first mode and the third mode are 3 / 8 respectively, and the duty cycles of the second mode and the fourth mode are 1 / 8 respectively. In this duty cycle, the voltage drops of the branches in each mode can be equal, and the impact current between the first capacitor, the second capacitor and the third capacitor can be better suppressed, and the loss of the switched-capacitor circuit can be reduced.

[0021] In a possible implementation, the switch capacitor circuit further comprises a second phase switch capacitor sub-circuit; for the second phase switch capacitor sub-circuit, in the first mode, the second transistor and the seventh transistor are turned on, and the third transistor and the sixth transistor are turned off; in the second mode, the second transistor and the seventh transistor are turned on, and the third transistor and the sixth transistor are turned off; in the third mode, the second transistor and the seventh transistor are turned off, and the third transistor and the sixth transistor are turned on; and in the fourth mode, the second transistor and the seventh transistor are turned off, and the third transistor and the sixth transistor are turned on. The driving method further comprises: in the fifth mode, the third transistor and the sixth transistor of the first phase switch capacitor sub-circuit are turned on, and the second transistor and the seventh transistor are turned off; the second transistor of the second phase switch capacitor sub-circuit is turned off, the seventh transistor is turned on, and the third transistor and the sixth transistor are turned off; and in the sixth mode, the third transistor and the sixth transistor of the first phase switch capacitor sub-circuit are turned off, and the second transistor and the seventh transistor are turned on; the sixth transistor of the second phase switch capacitor sub-circuit is turned off, the third transistor is turned on, and the second transistor and the seventh transistor are turned off. By turning off or delaying turning on one transistor in advance in the second mode, the fifth mode, the fourth mode, and the sixth mode, the input and output current ripples can be reduced, the voltage ripples can be reduced, and the charging voltage stability can be improved.

[0022] In a possible implementation, the duty cycles of the first mode and the third mode are 3 / 14 respectively, and the duty cycles of the second mode, the fourth mode, the fifth mode, and the sixth mode are 1 / 7 respectively. In this duty cycle, the voltage drops of the branches in each mode can be equal, the impact current between the first capacitor, the second capacitor, and the third capacitor can be better inhibited, and the loss of the switch capacitor circuit can be reduced.

[0023] In a possible implementation, the switch capacitor circuit comprises n switch capacitor groups coupled in parallel; and the switch capacitor sub-circuits in adjacent switch capacitor groups operate in a staggered phase of 180° / n. For the switch capacitor circuit comprising n switch capacitor groups, the driving method can also inhibit the impact current.

[0024] In a third aspect, the embodiment of the present application provides a driving method of the switched-capacitor circuit, the switched-capacitor circuit comprising the switched-capacitor circuit in the first possible implementation manner of the first aspect.The second-stage switch network comprises a second transistor, a third transistor, a sixth transistor and a seventh transistor; the second transistor and the third transistor are connected in series and are connected in parallel with a second capacitor; the sixth transistor and the seventh transistor are connected in series and are connected in parallel with a third capacitor; the first capacitor, the second capacitor and the third capacitor have equal capacitance values; the driving method comprises: in a first mode, the third transistor and the sixth transistor in the first-stage switch capacitor network are turned on, and the second transistor and the seventh transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the second transistor and the seventh transistor in the last-stage switch capacitor network are turned on, and the third transistor and the sixth transistor are turned off; in a second mode, the third transistor in the first-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the second transistor and the seventh transistor in the last-stage switch capacitor network are turned on, and the third transistor and the sixth transistor are turned off; in a third mode, the second transistor and the seventh transistor in the first-stage switch capacitor network are turned on, and the third transistor and the sixth transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the third transistor and the sixth transistor in the last-stage switch capacitor network are turned on, and the second transistor and the seventh transistor are turned off; in a fourth mode, the seventh transistor in the first-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the third transistor and the sixth transistor in the last-stage switch capacitor network are turned on, and the second transistor and the seventh transistor are turned off; in a fifth mode, the third transistor and the sixth transistor in the first-stage switch capacitor network are turned on, and the second transistor and the seventh transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the seventh transistor in the last-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; in a sixth mode, the second transistor and the seventh transistor in the first-stage switch capacitor network are turned on, and the sixth transistor and the third transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the third transistor in the last-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off; in a seventh mode, the third transistor in the first-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the seventh transistor in the last-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; in an eighth mode, the seventh transistor in the first-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; adjacent-stage switch capacitor networks operate in a 180° out-of-phase manner; the third transistor in the last-stage switch capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off. For a switch capacitor circuit comprising a plurality of switch capacitor networks connected in series, the driving method can still suppress the impact current.

[0025] In a possible implementation, the duty cycles of the first and third modes are 1 / 4 respectively, the duty cycles of the second and fourth modes are 1 / 8 respectively, the duty cycles of the fifth and sixth modes are 3 / 32 respectively, and the duty cycles of the seventh and eighth modes are 1 / 32 respectively. In this case, the voltage drops of the branches in each mode can be equalized, and the impact current among the first, second and third capacitors can be better suppressed, and the loss of the switched-capacitor circuit can be reduced.

[0026] In a possible implementation, the switched-capacitor circuit includes two-phase switched-capacitor sub-circuits, and the two-phase switched-capacitor sub-circuits operate in a phase difference of 180°. In the case that each switched-capacitor sub-circuit includes a plurality of switched-capacitor networks coupled in series, the driving method can still suppress the impact current.

[0027] In a possible implementation, the switched-capacitor circuit includes n switched-capacitor groups coupled in parallel, and the switched-capacitor sub-circuits in adjacent switched-capacitor groups operate in a phase difference of 180° / n. In the case that each switched-capacitor sub-circuit includes a plurality of switched-capacitor networks coupled in series, the driving method can still suppress the impact current.

[0028] In a fourth aspect, the embodiment of the present application provides a switched-capacitor circuit, which includes at least one switched-capacitor sub-circuit. The switched-capacitor sub-circuit includes a first capacitor, a first switch network and a switched-capacitor network. The switched-capacitor network includes a second capacitor, a third capacitor, a second switch network and a third switch network. The first switch network is coupled to an input terminal and the first capacitor respectively, and is configured to adjust the on-off relationship between the first capacitor and the input terminal. The second switch network is coupled to the first capacitor, the second capacitor and the third capacitor respectively, and is configured to adjust the series-parallel relationship among the first capacitor, the second capacitor and the third capacitor. The first inductor network is coupled to the first capacitor in series. The second inductor network is coupled to the second capacitor in series. The third inductor network is coupled between the second switch network and a first node. The fourth inductor network is coupled between the third switch network and the first node. The fifth inductor network is coupled between the first node and an output terminal. The sixth inductor network is coupled to the third capacitor in series. The switched-capacitor sub-circuit includes one or more of the first inductor network, the second inductor network, the third inductor network, the fourth inductor network, the fifth inductor network or the sixth inductor network.

[0029] The switch capacitor circuit provided by the embodiment of the present application sets an inductive network at one position or multiple positions, so that the inductive network is in series with the capacitor or the output terminal. The branch provided with the inductive network can suppress the current mutation of the branch due to the inductive network, thereby improving the efficiency of the switch capacitor circuit.

[0030] In a possible implementation, the switch capacitor sub-circuit comprises at least two of the first inductive network, the second inductive network, the third inductive network, the fourth inductive network, the fifth inductive network or the sixth inductive network; the switch capacitor sub-circuit does not simultaneously comprise the second inductive network and the third inductive network; or the switch capacitor sub-circuit does not simultaneously comprise the fourth inductive network and the sixth inductive network. When the switch capacitor sub-circuit comprises two inductive networks, the effect of suppressing the impact current of the first capacitor, the second capacitor, the third capacitor and the output terminal can be achieved. When the switch capacitor sub-circuit comprises three inductive networks and the first capacitor, the second capacitor and the third capacitor are respectively in series with an inductive network, the inductive network and the capacitor can be complementary paired, thereby facilitating accurate adjustment of the resonance state of the switch capacitor sub-circuit.

[0031] In a possible implementation, the switch capacitor sub-circuit comprises a plurality of switch capacitor networks coupled in series, and the last switch capacitor network is coupled to the first node; the second capacitor of at least some of the switch capacitor networks is coupled in series with a second inductive network; or the third capacitor of at least some of the switch capacitor networks is coupled in series with a sixth inductive network. The switch capacitor circuit comprises a plurality of (N) switch capacitor networks coupled in series, so that the ratio of the input voltage and the output voltage of the input terminal Vvi:Vvo is 2 N+1 :1, thereby realizing high conversion ratio and meeting different use requirements.

[0032] In a possible implementation, the switch capacitor circuit comprises at least one switch capacitor group, and the switch capacitor group comprises two-phase switch capacitor sub-circuits; the two-phase switch capacitor sub-circuits are coupled in parallel between the input terminal and the first node. The switch capacitor circuit comprises a plurality of switch capacitor sub-circuits, so that the switch capacitor circuit can meet a larger charging power on the basis of realizing high conversion ratio.

[0033] In a possible implementation, the switch capacitor circuit comprises a plurality of switch capacitor groups coupled in parallel between the input terminal and the first node. By arranging a plurality of switch capacitor groups in the switch capacitor circuit, the ripple of the charging voltage can be reduced, and the stability of the charging voltage can be improved.

[0034] In a possible implementation, the switched-capacitor circuit includes two-phase switched-capacitor sub-circuits; the second switch network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a first electrode of the first transistor is coupled with a negative electrode of a first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of a second capacitor respectively; a second electrode of the second transistor is coupled with the first node and a first electrode of the third transistor respectively; a second electrode of the third transistor is coupled with a negative electrode of the second capacitor and a first electrode of the fourth transistor respectively; a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of a third capacitor respectively; a second electrode of the sixth transistor is coupled with the first node and a first electrode of the seventh transistor respectively; a second electrode of the seventh transistor is coupled with a negative electrode of the third capacitor and a first electrode of the eighth transistor respectively; and a second electrode of the eighth transistor is coupled with the reference ground voltage terminal. This is a simple topology structure.

[0035] In a possible implementation, the seventh transistor in the one-phase switched-capacitor sub-circuit and the third transistor in the other-phase switched-capacitor sub-circuit are the same transistor; and the eighth transistor in the one-phase switched-capacitor sub-circuit and the fourth transistor in the other-phase switched-capacitor sub-circuit are the same transistor. In this way, the number of transistors in the switched-capacitor circuit can be reduced, and the area occupied by the switched-capacitor circuit can be reduced.

[0036] In a possible implementation, the switch capacitor sub-circuit comprises a plurality of switch capacitor networks coupled in series. The second switch network in each of the switch capacitor networks comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. In each of the switch capacitor networks, a first electrode of the fourth transistor is coupled to a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled to a reference ground voltage terminal. A first electrode of the eighth transistor is coupled to a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled to the reference ground voltage terminal. In the first switch capacitor network, a first electrode of the first transistor is coupled to a negative electrode of a first capacitor, and a second electrode of the first transistor is coupled to a first electrode of the second transistor and a positive electrode of a second capacitor. A first electrode of the fifth transistor is coupled to a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor and a positive electrode of a third capacitor. In the switch capacitor network other than the first switch capacitor network, a first electrode of the first transistor is coupled to a second electrode of the second transistor in the previous stage switch capacitor network, and a second electrode of the first transistor is coupled to a first electrode of the second transistor and a positive electrode of the second capacitor. A first electrode of the fifth transistor is coupled to a second electrode of the sixth transistor in the previous stage switch capacitor network, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor and a positive electrode of the third capacitor. In the last stage switch capacitor network, a second electrode of the second transistor, a first electrode of the third transistor, a second electrode of the sixth transistor and a first electrode of the seventh transistor are all coupled to an output terminal. In the switch capacitor network other than the last stage switch capacitor network, a second electrode of the second transistor is coupled to a first electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to a first electrode of the third transistor. This is a simple topology.

[0037] In a possible implementation, the seventh transistor in the last stage switch capacitor network in one phase switch capacitor sub-circuit is the same transistor as the third transistor in the last stage switch capacitor network in another phase switch capacitor sub-circuit, or the eighth transistor in the last stage switch capacitor network in one phase switch capacitor sub-circuit is the same transistor as the fourth transistor in the last stage switch capacitor network in another phase switch capacitor sub-circuit. In this way, the number of transistors in the switch capacitor circuit can be reduced, and the area occupied by the switch capacitor circuit can be reduced.

[0038] In a fifth aspect, the present application provides an electronic device comprising the switch capacitor circuit and the battery according to any one of the first aspect or the fourth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is an architecture diagram of an electronic device according to an embodiment of the present application;

[0040] FIG. 2 is a connection relationship diagram of a switch capacitor circuit according to an embodiment of the present application;

[0041] Fig. 3 is a topological schematic diagram of a switched-capacitor circuit according to an embodiment of the present application;

[0042] Fig. 4A is a diagram of an intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0043] Fig. 4B is an equivalent diagram of the intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0044] Fig. 5A is a diagram of another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0045] Fig. 5B is an equivalent diagram of the another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0046] Fig. 6 is a diagram of a simulated current waveform of a capacitor according to an embodiment of the present application;

[0047] Fig. 7 is a topological schematic diagram of another switched-capacitor circuit according to an embodiment of the present application;

[0048] Fig. 8A is a diagram of yet another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0049] Fig. 8B is an equivalent diagram of the yet another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0050] Fig. 9A is a diagram of yet another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0051] Fig. 9B is an equivalent diagram of the yet another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0052] Fig. 10A and Fig. 10B are timing diagrams of driving a switched-capacitor circuit according to an embodiment of the present application;

[0053] Fig. 11A is a diagram of yet another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0054] Fig. 11B is an equivalent diagram of the yet another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0055] Fig. 11C is a diagram of yet another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0056] Fig. 11D is an equivalent diagram of the yet another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0057] Fig. 12A and Fig. 12B are diagrams of simulation results under three conditions according to an embodiment of the present application;

[0058] FIG. 12C is a comparison chart of effects brought by a driving method according to an embodiment of the present application;

[0059] FIG. 13A is a topological schematic diagram of another switched-capacitor circuit according to an embodiment of the present application;

[0060] FIG. 13B and FIG. 13C are driving timing diagrams of a switched-capacitor circuit according to an embodiment of the present application;

[0061] FIG. 14A, FIG. 14C, FIG. 14E, FIG. 14G are another intermediate mode diagrams of a switched-capacitor circuit according to an embodiment of the present application;

[0062] FIG. 14B, FIG. 14D, FIG. 14F, FIG. 14H are equivalent diagrams of another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0063] FIG. 15 is a topological schematic diagram of another switched-capacitor circuit according to an embodiment of the present application;

[0064] FIG. 16A-FIG. 16D are driving timing diagrams of a switched-capacitor circuit according to an embodiment of the present application;

[0065] FIG. 17A, FIG. 17C, FIG. 17E, 17G are another intermediate mode diagrams of a switched-capacitor circuit according to an embodiment of the present application;

[0066] FIG. 17B, FIG. 17D, FIG. 17F, FIG. 17H are equivalent diagrams of another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0067] FIG. 18A is a schematic diagram of another architecture of a switched-capacitor circuit according to an embodiment of the present application;

[0068] FIG. 18B and FIG. 18C are topological schematic diagrams of another switched-capacitor circuit according to an embodiment of the present application;

[0069] FIG. 19 is a topological schematic diagram of another switched-capacitor circuit according to an embodiment of the present application;

[0070] FIG. 20 is a driving timing diagram of a switched-capacitor circuit according to an embodiment of the present application;

[0071] FIG. 21A, FIG. 21C, FIG. 21E, FIG. 21G, FIG. 21I, FIG. 21K, FIG. 21M, FIG. 21O are another intermediate mode diagrams of a switched-capacitor circuit according to an embodiment of the present application;

[0072] FIG. 21B, FIG. 21D, FIG. 21F, FIG. 21H, FIG. 21J, FIG. 21L, FIG. 21N, FIG. 21P are equivalent diagrams of another intermediate mode of a switched-capacitor circuit according to an embodiment of the present application;

[0073] FIG. 22A and FIG. 22B are schematic diagrams of another topology of a switched-capacitor circuit according to embodiments of the application;

[0074] FIG. 23 is a schematic diagram of an architecture of a switched-capacitor circuit according to embodiments of the application;

[0075] FIG. 24 is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the application;

[0076] FIG. 25A and FIG. 25B are schematic diagrams of another intermediate mode of a switched-capacitor circuit according to embodiments of the application;

[0077] FIG. 26A is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the application;

[0078] FIG. 26B and FIG. 26C are schematic diagrams of another intermediate mode of a switched-capacitor circuit according to embodiments of the application;

[0079] FIG. 26D is a schematic diagram of simulation results of a capacitor current at different inductance values according to embodiments of the application;

[0080] FIG. 27A is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the application;

[0081] FIG. 27B and FIG. 27C are schematic diagrams of another intermediate mode of a switched-capacitor circuit according to embodiments of the application;

[0082] FIG. 28A is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the application;

[0083] FIG. 28B and FIG. 28C are schematic diagrams of another intermediate mode of a switched-capacitor circuit according to embodiments of the application;

[0084] FIG. 29-FIG. 34 are schematic diagrams of another topology of a switched-capacitor circuit according to embodiments of the application;

[0085] FIG. 35A is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the application;

[0086] FIG. 35B and FIG. 35C are schematic diagrams of another intermediate mode of a switched-capacitor circuit according to embodiments of the application;

[0087] FIG. 36-FIG. 40 are schematic diagrams of another topology of a switched-capacitor circuit according to embodiments of the application;

[0088] FIG. 41A is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the application;

[0089] FIG. 41B is a schematic diagram of another intermediate mode of a switched-capacitor circuit according to embodiments of the application;

[0090] FIG. 41C is an equivalent diagram of another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0091] FIG. 41D is a diagram of another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0092] FIG. 41E is an equivalent diagram of another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application;

[0093] FIG. 42A and FIG. 42B are topological schematic diagrams of another switched-capacitor circuit according to an embodiment of the present application;

[0094] FIG. 43A and FIG. 43B are topological schematic diagrams of another switched-capacitor circuit according to an embodiment of the present application;

[0095] FIG. 44 is a topological schematic diagram of another switched-capacitor circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0096] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0097] Hereinafter, the terms "second", "first", and the like are only used for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "second", "first", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0098] In addition, in the embodiments of the present application, the orientation terms such as "upper", "lower", "left", "right", and the like can include but not limited to the orientation defined by the relative placement of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the placement of the components in the drawings.

[0099] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through an intermediate medium. In addition, the term "coupling" can be direct electrical connection, or indirect electrical connection through an intermediate medium. The term "contact" can be direct contact, or indirect contact through an intermediate medium.

[0100] In the embodiments of this application, "and / or" describes the association relationship of associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0101] The electronic device provided in the embodiments of this application is not specially limited in form, and the following embodiments are exemplarily described by taking a mobile phone as an example.

[0102] The electronic device provided in the embodiments of this application is not specially limited in form, and the following embodiments are exemplarily described by taking a mobile phone as an example.

[0103] FIG. 1 is an architecture diagram of an electronic device provided in the embodiments of this application.

[0104] The electronic device 100 provided in the embodiments of this application can include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 01, an antenna 02, a mobile communication module 150, a wireless communication module 160, an audio module 170, a loudspeaker 170A, a receiver 170B, a microphone 170C, a headset interface 170D, a sensor module 180, a camera 193, and a display screen 194, and the like.

[0105] It can be understood that the structural schematic of the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 can include more or fewer components than the schematic, or combine certain components, or split certain components, or different arrangement of components. The components shown can be implemented in hardware, software or a combination of software and hardware.

[0106] The wireless communication function of the electronic device 100 can be realized by the antenna 01, the antenna 02, the mobile communication module 150, the wireless communication module 160, the modem processor, and the baseband processor, etc.

[0107] The processor 110 can include one or more processing units, for example, the processor 110 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc.

[0108] The electronic device 100 realizes the display function through the GPU, the display screen 194, and the application processor, etc. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering.

[0109] The electronic device 100 can realize the shooting function through the ISP, the camera 193, the video codec, the GPU, the display screen 194, and the application processor, etc.

[0110] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to realize the expansion of the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to realize the data storage function.

[0111] The internal memory 121 can be used to store one or more computer programs including instructions. The processor 110 can execute the above-mentioned instructions stored in the internal memory 121, so as to make the electronic device 100 execute the methods provided in some embodiments of the present application, and various functional applications and data processing, etc.

[0112] The electronic device 100 can implement audio functions through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor, etc. For example, music playing, recording, etc.

[0113] The sensor module 180 can include a pressure sensor, a gyro sensor, a barometric sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc.

[0114] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives the input of the battery 142 and / or the charging management module 140, and supplies power for the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160, etc. The power management module 141 can also be used to monitor the parameters such as the battery capacity, the battery cycle number, the battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be arranged in the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 can also be arranged in the same device.

[0115] The charging management module 140 is used to receive the charging input from the charger. The charger can be a wireless charger or a wired charger (or an adapter). In some wired charging embodiments, the charging management module 140 can receive the charging input of the wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive the wireless charging input through the wireless charging coil of the electronic device 100.

[0116] FIG. 2 is a schematic diagram of a connection relationship of a switched-capacitor circuit according to an embodiment of the present application.

[0117] As shown in FIG. 2, the charging management module 140 can be connected to the USB interface 130 by an over voltage protection (OVP) protection circuit 131, wherein when the OVP protection circuit 131 detects that the voltage accessed to the USB interface 130 is too high (exceeding a threshold voltage), the charging management module 140 can be actively disconnected from the USB interface 130. For example, as shown in FIG. 2, the charging management module 140 is specifically connected to the wireless charging coil 132 by a receive integrated circuit (Rx IC) 133. In addition, in order to realize ordinary charging or fast charging of the battery, as shown in FIG. 2, the charging management module 140 can include a switched capacitor converter (SC) for fast charging of the battery and a buck converter (BUCK) for ordinary normal charging of the battery. The switched capacitor converter SC and the BUCK are connected to the USB interface 130 through the OVP protection circuit 131, and are connected to the wireless charging coil 132 through the Rx IC 133.

[0118] The processor 110 or the charging management module 140 can detect the charging of the battery by the buck converter BUCK or the switched capacitor converter SC according to the charging protocol. Generally, the switched capacitor converter SC and the buck converter BUCK are buck converters with a fixed buck ratio. For example, when the processor 110 or the charging management module 140 detects that the voltage at the input side of the switched capacitor converter SC and the buck converter BUCK is 5V according to the charging protocol, the processor 110 or the charging management module 140 controls the buck converter BUCK to convert the voltage of 5V to a voltage slightly higher than the voltage of the battery (for example, 2V) and then charges the battery. Alternatively, when the processor 110 or the charging management module 140 detects that the voltage at the input side of the switched capacitor converter SC and the buck converter BUCK is 20V according to the charging protocol, the processor 110 or the charging management module 140 determines that this is a fast charging scenario, and then controls the switched capacitor converter SC to convert the voltage of 20V to a voltage near the voltage of the battery and then charges the battery.

[0119] When the voltage or capacity of the battery rises to a certain stage, or the heat consumption is too large, the charging power needs to be controlled to be switched down to a lower charging power (for example, 40W). The voltage output by the switched capacitor converter SC of the adapter or the wireless charger will be reduced to about 10V. At this time, in order to maintain the original charging current and maintain fast charging, the charging protocol will control the switched capacitor converter SC to reduce the input voltage of 10V to about 5V in a 2:1 buck mode to continue charging the battery. Of course, when the charging protocol controls the adapter or the wireless charger to further reduce the voltage, the switched capacitor converter SC needs to be further switched to a buck mode to ensure that the output voltage is continuously maintained at about 5V, thereby ensuring the effect of fast charging.

[0120] That is, the switched-capacitor circuit SC can receive an input voltage through an input terminal and provide an output voltage through an output terminal. The input voltage can be a voltage provided from a charger outside the electronic device 100 or a voltage provided from any node in a power network inside the electronic device 100. The switched-capacitor circuit SC can generate an output voltage having a certain ratio with the input voltage and output to the outside of the system or any node in the power network inside the system.

[0121] FIG. 3 is a topological diagram of a switched-capacitor circuit according to an embodiment of the present application.

[0122] In some embodiments, as shown in FIG. 3, the switched-capacitor circuit SC includes a first switched-capacitor network 1 and a second switched-capacitor network 2. The first switched-capacitor network 1 includes a first capacitor Cf1 and a first-stage switch network 10. The second switched-capacitor network 2 includes a second capacitor Cf2, a third capacitor Cf3, and a second-stage switch network 20.

[0123] The first-stage switch network 10 includes a first switch network. The first capacitor Cf1 is coupled to the first-stage switch network 10 (i.e., the first switch network). The first-stage switch network 10 is configured to adjust the on-off relationship between the first capacitor Cf1 and the input terminal VI.

[0124] The second-stage switch network 20 is coupled to the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3, respectively. The second-stage switch network 20 is configured to adjust the series-parallel relationship among the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3.

[0125] For example, the second-stage switch network 20 includes a second switch network 21 and a third switch network 22. The second switch network 21 is coupled to the second capacitor Cf2 and the first-stage switch network 10, respectively. The second switch network 21 is configured to adjust the series-parallel relationship between the second capacitor Cf2 and the first capacitor Cf1. The third switch network 22 is coupled to the third capacitor Cf3 and the first-stage switch network 10, respectively. The third switch network 22 is configured to adjust the series-parallel relationship between the third capacitor Cf3 and the first capacitor Cf1. The second switch network 21 and the third switch network 22 are coupled to the output terminal VO and configured to output a reduced charging voltage.

[0126] For example, the second switch network 21 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. The third switch network 22 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8. The first-stage switch network 10 includes a ninth transistor Q9 and a tenth transistor Q10.

[0127] The first electrode of the first transistor Q1 is coupled with the negative electrode of the first capacitor Cf1, and the second electrode of the first transistor Q1 is coupled with the first electrode of the second transistor Q2 and the positive electrode of the second capacitor Cf2 respectively. The second electrode of the second transistor Q2 is coupled with the output terminal VO and the first electrode of the third transistor Q3 respectively. The second electrode of the third transistor Q3 is coupled with the negative electrode of the second capacitor Cf2 and the first electrode of the fourth transistor Q4 respectively. The second electrode of the fourth transistor Q4 is coupled with the reference ground voltage terminal GND.

[0128] The first electrode of the fifth transistor Q5 is coupled with the positive electrode of the first capacitor Cf1, and the second electrode of the fifth transistor Q5 is coupled with the first electrode of the sixth transistor Q6 and the positive electrode of the third capacitor Cf3 respectively. The second electrode of the sixth transistor Q6 is coupled with the output terminal VO and the first electrode of the seventh transistor Q7 respectively. The second electrode of the seventh transistor Q7 is coupled with the negative electrode of the third capacitor Cf3 and the first electrode of the eighth transistor Q8 respectively. The second electrode of the eighth transistor Q8 is coupled with the reference ground voltage terminal GND.

[0129] The first electrode of the ninth transistor Q9 is coupled with the input terminal VI, and the second electrode of the ninth transistor Q9 is coupled with the positive electrode of the first capacitor Cf1 and the first electrode of the fifth transistor Q5 respectively. The first electrode of the tenth transistor Q10 is coupled with the negative electrode of the first capacitor Cf1 and the first electrode of the first transistor Q1 respectively, and the second electrode of the tenth transistor Q10 is coupled with the reference ground voltage terminal GND.

[0130] The first transistor Q1 to the tenth transistor Q10 each include a control electrode, and under the control of the control electrode, the switch can switch the first electrode and the second electrode between the on state and the off state. In the embodiments of the present application, the transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET). In addition, in the example shown in FIG. 3, only one transistor is shown at each position of the transistor, and it can be understood that two or more transistors in parallel can be used at each position of the transistor to reduce the resistance of the switch when turned on. In the embodiments of the present application, the transistor is divided into two types: a negative (N) type transistor and a positive (P) type transistor. The transistor includes a source, a drain, and a gate, and the conduction (turn on) or disconnection (turn off, cutoff, open circuit) of the transistor can be controlled by controlling the level of the gate of the transistor. When the transistor is turned on, the source and the drain are conductive, and an on current is generated, and when the gate level of the transistor is different, the size of the on current generated between the source and the drain is also different. When the transistor is turned off, the source and the drain are not conductive, and no current is generated. In the embodiments of the present application, the gate of the transistor is also referred to as the control electrode, the source is referred to as the first electrode, and the drain is referred to as the second electrode; or the gate is referred to as the control electrode, the drain is referred to as the first electrode, and the source is referred to as the second electrode. In addition, the N type transistor is turned on when the level of the control electrode is high, the first electrode and the second electrode are conductive, and the on current is generated between the first electrode and the second electrode. The N type transistor is turned off when the level of the control electrode is low, the first electrode and the second electrode are not conductive, and no current is generated. The P type transistor is turned on when the level of the control electrode is low, the first electrode and the second electrode are conductive, and the on current is generated. The P type transistor is turned off when the level of the control electrode is high, the first electrode and the second electrode are not conductive, and no current is generated. The transistors used in the following schemes can be referred to the description herein.

[0131] FIG. 4A is a kind of intermediate mode diagram of a switched capacitor circuit provided by an embodiment of the present application, and FIG. 4B is an equivalent diagram of a kind of intermediate mode of a switched capacitor circuit provided by an embodiment of the present application.

[0132] As shown in FIG. 4A, in the first mode D1, the first transistor Q1, the third transistor Q3, the sixth transistor Q6, the eighth transistor Q8, and the ninth transistor Q9 are controlled to be turned on, and the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7, and the tenth transistor Q10 are controlled to be turned off, and the capacitors are connected to form the equivalent circuit shown in FIG. 4B.

[0133] In the 4:1 step-down mode, in the first time period of a cycle, as shown in Fig. 4A, the first switch network 10 connects the input terminal VI to the positive terminal of the first capacitor Cf1. The second switch network 21 connects the negative terminal of the first capacitor Cf1 to the positive terminal of the second capacitor Cf2, and connects the negative terminal of the second capacitor Cf2 to the output terminal VO. The third switch network 22 connects the negative terminal of the third capacitor Cf3 to the reference ground voltage terminal GND, and connects the positive terminal of the third capacitor Cf3 to the output terminal VO. The capacitors are connected to form the equivalent circuit as shown in Fig. 4B, in which the first capacitor Cf1 and the second capacitor Cf2 are connected in series, and the first capacitor Cf1 and the second capacitor Cf2 are connected in parallel with the third capacitor Cf3 and the output terminal VO respectively. When the system is stable, Vvi = Vcf1 + Vcf2 + Vvo, and Vcf3 = Vvo, where Vvi is the input voltage, Vcf1 is the voltage across the first capacitor Cf1, Vcf2 is the voltage across the second capacitor Cf2, Vcf3 is the voltage across the third capacitor Cf3, and Vvo is the output voltage.

[0134] Fig. 5A is another intermediate mode diagram of a switched capacitor circuit according to an embodiment of the present application, and Fig. 5B is an equivalent circuit of the switched capacitor circuit according to an embodiment of the present application.

[0135] As shown in Fig. 5A, in the second mode D2, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7 and the tenth transistor Q10 are controlled to be turned on, and the first transistor Q1, the third transistor Q3, the sixth transistor Q6, the eighth transistor Q8 and the ninth transistor Q9 are controlled to be turned off. The capacitors are connected to form the equivalent circuit as shown in Fig. 5B.

[0136] In the second time period of a cycle, as shown in Fig. 5A, the first switch network 10 connects the negative terminal of the first capacitor Cf1 to the reference ground voltage terminal GND. The second switch network 21 connects the positive terminal of the second capacitor Cf2 to the output terminal VO, and connects the negative terminal of the second capacitor Cf2 to the reference ground voltage terminal GND. The third switch network 22 connects the positive terminal of the third capacitor Cf3 to the positive terminal of the first capacitor Cf1, and connects the negative terminal of the third capacitor Cf3 to the output terminal VO. The capacitors are connected to form the equivalent circuit as shown in Fig. 5B, in which the first capacitor Cf1 and the third capacitor Cf3 are connected in series, and the first capacitor Cf1 and the third capacitor Cf3 are connected in parallel with the second capacitor Cf2 and the output terminal VO respectively. When the system is stable, Vcf2 = Vvo, and Vcf1 = Vcf2 + Vvo.

[0137] In summary, Vvi=4Vvo, Vcf1=2Vvo, Vcf2=Vvo, Vcf3=Vvo can be obtained, and thus a voltage conversion ratio of 4:1 can be achieved. That is, since the input voltage Vvi is four times the output voltage Vvo, a voltage conversion ratio of 4:1 can be achieved when the switch capacitor circuit SC shown in FIG. 3 operates in the mode shown in FIG. 4A and FIG. 5A. At this time, the voltage Vcf1 of the first capacitor Cf1 is twice the output voltage Vvo, and each of the voltage Vcf2 of the second capacitor Cf2 and the voltage Vcf3 of the third capacitor Cf3 is equal to the output voltage Vvo.

[0138] Therefore, the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 all have lower voltage stress. Since the effective capacitance of a capacitor is greatly affected by the DC bias voltage, lower voltage stress means that less capacitance is required, and thus the single board area of the switch capacitor circuit SC shown in FIG. 3 is smaller.

[0139] FIG. 6 is a simulation current waveform diagram of a capacitor provided in an embodiment of the present application.

[0140] Since the principle of a switch capacitor is mutual charging and discharging between capacitors, the turn-off current of any transistor in the switch capacitor circuit SC shown in FIG. 3 is small (the tail of the inrush current is close to zero current), and the loss of turn-off is small. However, there is a large inrush current at the moment of turn-on of any transistor in the switch capacitor circuit SC. Especially in the case where a capacitor is connected in a loop in the switch capacitor circuit SC shown in FIG. 3, as shown in FIG. 6, the above-mentioned dual-mode operation mode including the first mode D1 and the second mode D2, at the moment of entering the first mode D1, there is a large inrush current between the branch where the third capacitor Cf3 is located and the branches where the first capacitor Cf1 and the second capacitor Cf2 are located (at circle W1, about 20A). At the moment of entering the second mode D2, there is a large inrush current between the branch where the second capacitor Cf2 is located and the branches where the first capacitor Cf1 and the third capacitor Cf3 are located (at circle W2, about 20A), which affects the efficiency of the switch capacitor circuit SC. In FIG. 6, under the first mode D1, the current icf1 of the first capacitor Cf1 and the current icf2 of the second capacitor Cf2 have coinciding curves. At the moment of entering the first mode D1, the current icf1 of the first capacitor Cf1, the current icf2 of the second capacitor Cf2, and the current icf3 of the third capacitor Cf3 have coinciding curves.

[0141] FIG. 7 is a topological schematic diagram of another switch capacitor circuit provided in an embodiment of the present application.

[0142] An embodiment of the present application provides a switch capacitor circuit, as shown in FIG. 7, which includes a first-phase switch capacitor circuit SC1, an inductor network L, an input end VI, and an output end VO.

[0143] For example, the first phase switched capacitor circuit SC1 has the same structure as the switched capacitor circuit SC shown in FIG. 3. For example, the first phase switched capacitor circuit SC1 is a single first interleaved second stage (SFIPS) circuit.

[0144] The first end of the inductive network L is coupled to the second switched capacitor network 2, and the second end of the inductive network L is coupled to the output terminal VO.

[0145] FIG. 8A is another intermediate mode diagram of a switched capacitor circuit according to an embodiment of the present application, and FIG. 8B is an equivalent diagram of the intermediate mode of the switched capacitor circuit according to an embodiment of the present application.

[0146] As shown in FIG. 8A, in the first mode, the first transistor Q1, the third transistor Q3, the sixth transistor Q6, the eighth transistor Q8, and the ninth transistor Q9 are controlled to be turned on, and the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7, and the tenth transistor Q10 are controlled to be turned off, so as to connect the capacitors to form the equivalent circuit shown in FIG. 8B.

[0147] FIG. 9A is another intermediate mode diagram of a switched capacitor circuit according to an embodiment of the present application, and FIG. 9B is an equivalent diagram of the intermediate mode of the switched capacitor circuit according to an embodiment of the present application.

[0148] As shown in FIG. 9A, in the second mode, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7, and the tenth transistor Q10 are controlled to be turned on, and the first transistor Q1, the third transistor Q3, the sixth transistor Q6, the eighth transistor Q8, and the ninth transistor Q9 are controlled to be turned off, so as to connect the capacitors to form the equivalent circuit shown in FIG. 9B.

[0149] As shown in FIG. 8B and FIG. 9B, since the inductive network L can suppress current mutation, the circuit is protected from sudden current impact. Therefore, after the inductive network L is connected in series on the branch where the output terminal VO is located, the mutation of the total output current can be limited, the total output current will not contain impact current, and the branch where the output terminal VO is located will not impact the branches where the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 are located, so as to reduce the impact current of the branches where the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 are located to a certain extent, reduce the loss of the switched capacitor circuit SC, and improve the efficiency of the switched capacitor circuit SC.

[0150] In the first implementation, the capacitance of the first capacitor Cf1 is greater than the capacitance of the second capacitor Cf2, and the capacitance of the second capacitor Cf2 is equal to the capacitance of the third capacitor Cf3. For example, Cf1 >> Cf2 = Cf3.

[0151] During the operation of the switched capacitor circuit SC, half of the time is in the first mode shown in Fig. 8A, and half of the time is in the second mode shown in Fig. 9A. As shown in Figs. 8B and 9B, during the operation of the switched capacitor circuit SC, the first capacitor Cf1 switches between the first branch S1 in Fig. 8B and the second branch S2 in Fig. 9B. If the switched capacitor circuit SC switches from the first state in Fig. 8B to the second state in Fig. 9B or switches from the second state in Fig. 9B to the first state in Fig. 8B, the voltage drops across the first branch S1 and the second branch S2 are always equal, and thus there is no inrush current during the mode switching of the switched capacitor circuit SC.

[0152] In the case where the capacitance of the first capacitor Cf1 is greater than the capacitance of the second capacitor Cf2, and the capacitance of the second capacitor Cf2 is equal to the capacitance of the third capacitor Cf3, the first capacitor Cf1 can be equivalent to a voltage source, the capacitance of the first capacitor Cf1 is large and the impedance of the first capacitor Cf1 is small, and the influence of the first capacitor Cf1 on the voltage drop across the branches can be ignored. In this way, during the switching of the first capacitor Cf1 between the first branch S1 in Fig. 8B and the second branch S2 in Fig. 9B, the influence of the first capacitor Cf1 on the voltage drops across the first branch S1 and the second branch S2 can be ignored, thereby reducing the inrush current during the mode switching of the switched capacitor circuit SC.

[0153] For example, the capacitance of the first capacitor Cf1 is more than twice the capacitance of the second capacitor Cf2. For example, the withstand voltage of the first capacitor Cf1 is 2 times the output voltage Vvo, and the withstand voltage of the second capacitor Cf2 is 1 times the output voltage Vvo.

[0154] In the case where the capacitance of the first capacitor Cf1 is more than twice the capacitance of the second capacitor Cf2, there is almost no inrush current between the parallel first branch S1 and the second branch S2, thereby effectively suppressing the inrush current between the second capacitor Cf2 and the third capacitor Cf3.

[0155] In the second implementation, the capacitance of the first capacitor Cf1, the capacitance of the second capacitor Cf2, and the capacitance of the third capacitor Cf3 are equal, i.e., Cf1 = Cf2 = Cf3. The inrush current is reduced by changing the driving timing of the switched capacitor circuit SC. In this way, the capacitance of the first capacitor Cf1 can be reduced, and the area occupied by the first capacitor Cf1 can be reduced.

[0156] FIG. 10A and FIG. 10B are driving timing diagrams of a switched-capacitor circuit according to an embodiment of the present application. FIG. 11A is another intermediate mode diagram of a switched-capacitor circuit according to an embodiment of the present application, and FIG. 11B is an equivalent diagram of the another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application; FIG. 11C is another intermediate mode diagram of a switched-capacitor circuit according to an embodiment of the present application, and FIG. 11D is an equivalent diagram of the another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application.

[0157] The embodiment of the present application further provides a driving method of a switched-capacitor circuit SC, the switched-capacitor circuit SC comprising the switched-capacitor circuit SC shown in FIG. 7. As shown in FIG. 10A and FIG. 10B, the driving method of the switched-capacitor circuit SC comprises:

[0158] As shown in FIG. 8A, in the first mode D1, the sixth transistor Q6 and the third transistor Q3 are turned on, and the seventh transistor Q7 and the second transistor Q2 are turned off. In the first mode D1, the ninth transistor Q9, the first transistor Q1, and the eighth transistor Q8 are also turned on, and the tenth transistor Q10, the fourth transistor Q4, and the fifth transistor Q5 are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 8B, and both the first branch S1 and the second branch S2 are turned on.

[0159] As shown in FIG. 11A, in the second mode D1A, the sixth transistor Q6 is turned off, the third transistor Q3 is turned on, and the seventh transistor Q7 and the second transistor Q2 are turned off. In the second mode D1A, the ninth transistor Q9, the first transistor Q1, and the eighth transistor Q8 are also turned on, and the tenth transistor Q10, the fourth transistor Q4, and the fifth transistor Q5 are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 11B, and the first branch S1 is turned on, and the second branch S2 loop is blocked.

[0160] As shown in FIG. 9A, in the third mode D2, the seventh transistor Q7 and the second transistor Q2 are turned on, and the sixth transistor Q6 and the third transistor Q3 are turned off. In the third mode D2, the tenth transistor Q10, the fourth transistor Q4, and the fifth transistor Q5 are also turned on, and the ninth transistor Q9, the first transistor Q1, and the eighth transistor Q8 are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 9B, and both the first branch S1 and the second branch S2 are turned on.

[0161] As shown in FIG. 11C, in the fourth mode D2A, the seventh transistor Q7 is turned on, and the sixth transistor Q6, the third transistor Q3 and the second transistor Q2 are turned off. In the fourth mode D2A, the tenth transistor Q10, the fourth transistor Q4 and the fifth transistor Q5 are also turned on, and the ninth transistor Q9, the first transistor Q1 and the eighth transistor Q8 are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 11D, in which the first branch S1 is blocked, and the second branch S2 is turned on.

[0162] In the embodiments of the present application, as shown in FIG. 10A, the second mode D1A can be located after the first mode D1. For example, after the ninth transistor Q9, the first transistor Q1, the third transistor Q3, the sixth transistor Q6 and the eighth transistor Q8 are turned on to enter the first mode D1, the sixth transistor Q6 is turned off in advance to enter the second mode D1A. The fourth mode D2A can be located after the third mode D2. For example, after the tenth transistor Q10, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5 and the seventh transistor Q7 are turned on to enter the third mode D2, the second transistor Q2 is turned off in advance to enter the fourth mode D2A.

[0163] As shown in FIG. 10B, the second mode D1A can be located before the first mode D1. For example, after the ninth transistor Q9, the first transistor Q1 and the third transistor Q3 are turned on, the sixth transistor Q6 is turned on in advance to enter the second mode D1A. Then the sixth transistor Q6 is turned on to enter the first mode D1. The fourth mode D2A can be located before the third mode D2. For example, after the tenth transistor Q10, the fourth transistor Q4, the fifth transistor Q5 and the seventh transistor Q7 are turned on, the second transistor Q2 is turned on in advance to enter the fourth mode D2A. Then the second transistor Q2 is turned on to enter the third mode D2.

[0164] The order of the modes is not limited in the embodiments of the present application. The first mode D1 can be located before the third mode D2, the second mode D1A can be located before the first mode D1, or the second mode D1A can be located after the first mode D1. The fourth mode D2A can be located before the second mode D2, or the fourth mode D2A can be located after the second mode D2.

[0165] FIGS. 12A and 12B are simulation results under three conditions provided by the embodiments of the present application. FIG. 12C is a comparison diagram of effects brought by a driving method provided by the embodiments of the present application.

[0166] Fig. 12A is a simulation diagram of the inrush current when Cf1=Cf2=Cf3 and the driving method is not used, and only the first mode D1 and the third mode D2 exist in the driving process of the SC. Fig. 6 is a simulation diagram of the inrush current when Cf1=Cf2=Cf3 and the driving method is not used, and only the first mode (the first mode) D1 and the second mode (the third mode) D2 exist in the driving process of the SC. Fig. 12B is a simulation diagram of the inrush current when Cf1=Cf2=Cf3 and the driving method is used. In the driving process of the SC, the first mode D1, the second mode D1A, the third mode D3 and the fourth mode D2A exist. In order to facilitate the description, the driving control of the SC without the driving method provided by the embodiments of the present application is called "non-split phase control", and the driving control of the SC with the driving method provided by the embodiments of the present application is called "split phase control".

[0167] As shown in Fig. 12A, when the output terminal VO is in series with the inductance and the non-split phase control is used, if Cf1>>Cf2=Cf3, at the moment of entering the first mode D1, there is no large inrush current between the branch where the third capacitor Cf3 is located and the branches where the first capacitor Cf1 and the second capacitor Cf2 are located (at the circle W1, less than 5A). At the moment of entering the second mode D2, there is no large inrush current between the branch where the second capacitor Cf2 is located and the branches where the first capacitor Cf1 and the third capacitor Cf3 are located (at the circle W2, less than 5A). There is almost no inrush current on the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3. As shown in Fig. 6, when the capacitance of the first capacitor Cf1 decreases, even if the output terminal VO has the inductance, there will be a certain inrush current (the maximum current is 20A) between the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3.

[0168] As shown in FIG. 12B, when the capacitance of the first capacitor Cf1 is reduced and the split-phase control is added, even if Cf1 = Cf2 = Cf3 is maintained, the impact current on the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3 can be greatly reduced. As shown in FIG. 12C, when Cf1 = Cf2 = Cf3, at the moment of entering the first mode D1, there is no large impact current between the branch where the third capacitor Cf3 is located and the branch where the first capacitor Cf1 and the second capacitor Cf2 are located (at circle W1, less than 12A). At the moment of entering the second mode D2, there is no large impact current between the branch where the second capacitor Cf2 is located and the branch where the first capacitor Cf1 and the third capacitor Cf3 are located (at circle W2, less than 12A). As can be seen from the comparison chart, after the split-phase control is added, the current peak value on the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3 is obviously reduced (less than 12A), and the reduction effect of the first capacitor Cf1 is particularly obvious.

[0169] Based on this, the driving method provided by the embodiments of the present application is used to drive the switched capacitor circuit SC, by adding the second mode D1A and the fourth mode D2A, and turning off a branch with a capacitor in the switched capacitor circuit SC in the above two modes, the current impact between the two branches including the capacitor is eliminated. Thus, without increasing the capacitance of the first capacitor Cf1, the impact current between the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3 is suppressed, thereby reducing the loss of the switched capacitor circuit SC and improving the efficiency of the switched capacitor circuit SC. That is, after the split-phase control is introduced, the capacitance relationship of the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3 can be broken, and the first capacitor Cf1 with a smaller capacitance can be used to suppress the impact current.

[0170] In some embodiments, as shown in FIGS. 10A and 10B, the duty cycles of the first mode D1 and the third mode D2 are 3 / 8 respectively, and the duty cycles of the second mode D1A and the fourth mode D2A are 1 / 8 respectively.

[0171] In this way, the voltage drops of the branches in each mode can be equalized, the impact current between the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3 can be better suppressed, the loss of the switched capacitor circuit SC can be reduced, and the efficiency of the switched capacitor circuit SC can be improved.

[0172] FIG. 13A is a topological schematic diagram of another switched capacitor circuit provided by the embodiments of the present application.

[0173] In some embodiments, as shown in FIG. 13A, the switched-capacitor circuit SC includes at least one switched-capacitor group, and the switched-capacitor group includes two-phase switched-capacitor sub-circuits, which are respectively a first-phase switched-capacitor sub-circuit SCI and a second-phase switched-capacitor sub-circuit SC2. By arranging two-phase switched-capacitor sub-circuits in the switched-capacitor circuit SC, the switched-capacitor circuit SC can meet a larger charging power.

[0174] The first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 are coupled in parallel in an interleaved manner between the input terminal VI and the inductive network L. During the driving of the switched-capacitor circuit SC, the first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 operate in a phase difference of 180°. That is, at the same time, the transistors turned on in the second-stage switch network 20A in the first-phase switched-capacitor sub-circuit SCI and the transistors turned on in the second-stage switch network 20B in the second-phase switched-capacitor sub-circuit SC2 are completely different. For example, the first-phase switched-capacitor sub-circuit SCI enters the first mode D1 shown in FIG. 4A, and the second-phase switched-capacitor sub-circuit SC2 enters the second mode D2 shown in FIG. 5A. The first-phase switched-capacitor sub-circuit SCI enters the second mode D2 shown in FIG. 5A, and the second-phase switched-capacitor sub-circuit SC2 enters the first mode D1 shown in FIG. 4A.

[0175] For example, the first-phase switched-capacitor circuit SCI includes a first switched-capacitor network 1A and a second switched-capacitor network 2A. The first switched-capacitor network 1A includes a first capacitor Cf1A and a first-stage switch network 10A, and the second switched-capacitor network 2A includes a second capacitor Cf2A, a third capacitor Cf3A, and a second-stage switch network 20A. The first-stage switch network 10A is coupled with the input terminal VI and the second-stage switch network 20A, respectively, and the second-stage switch network 20A is coupled with the output terminal VO. The first capacitor Cf1A is coupled with the first-stage switch network 10A, and the first-stage switch network 10A is used to adjust the on-off between the first capacitor Cf1A and the input terminal VI. The second capacitor Cf2A and the third capacitor Cf3A are coupled with the second-stage switch network 20A, respectively, and the second-stage switch network 20A is used to adjust the series-parallel connection between the second capacitor Cf2A and the first capacitor Cf1A, and the second-stage switch network 20A is also used to adjust the series-parallel connection between the third capacitor Cf3A and the first capacitor Cf1A. The first-stage switch network 10A includes the above-mentioned first switch network, for example, and the second-stage switch network 20A includes the above-mentioned second switch network 21 and the third switch network 22, for example.

[0176] In some embodiments, the second-stage switching network 20A of the first-phase switched-capacitor circuit SC1 includes a first transistor Q1A, a second transistor Q2A, a third transistor Q3A, a fourth transistor Q4A, a fifth transistor Q5A, a sixth transistor Q6A, a seventh transistor Q7A, and an eighth transistor Q8A, and the first-stage switching network 10A includes a ninth transistor Q9A and a tenth transistor Q10A. The connection relationship of each transistor can refer to the description of FIG. 3.

[0177] For example, the second-phase switched-capacitor circuit SC2 also includes a first switched-capacitor network 1B and a second switched-capacitor network 2B, the first switched-capacitor network 1B includes a first capacitor Cf1B and a first-stage switching network 10B, and the second switched-capacitor network 2B includes a second capacitor Cf2B, a third capacitor Cf3B, and a second-stage switching network 20B. The first-stage switching network 10B is coupled with the input terminal VI and the second-stage switching network 20B, respectively, and the second-stage switching network 20B is coupled with the output terminal VO. The first capacitor Cf1B is coupled with the first-stage switching network 10B, and the first-stage switching network 10B is used to adjust the connection and disconnection between the first capacitor Cf1B and the input terminal VI. The second capacitor Cf2B and the third capacitor Cf3B are coupled with the second-stage switching network 20B, respectively, and the second-stage switching network 20B is used to adjust the series-parallel connection between the second capacitor Cf2B and the first capacitor Cf1B, and the second-stage switching network 20B is also used to adjust the series-parallel connection between the third capacitor Cf3B and the first capacitor Cf1B. The first-stage switching network 10B includes, for example, the first switching network described above, and the second-stage switching network 20B includes, for example, the second switching network 21 and the third switching network 22 described above.

[0178] In some embodiments, the second-stage switching network 20B of the second-phase switched-capacitor circuit SC2 includes a first transistor Q1B, a second transistor Q2B, a third transistor Q3B, a fourth transistor Q4B, a fifth transistor Q5B, a sixth transistor Q6B, a seventh transistor Q7B, and an eighth transistor Q8B, and the first-stage switching network 10B includes a ninth transistor Q9B and a tenth transistor Q10B. The connection relationship of each transistor can refer to the description of FIG. 3.

[0179] The transistors in the first-phase switched-capacitor circuit SC1 and the second-phase switched-capacitor circuit SC2 in the interleaved parallel connection are in a complementary relationship, which can be understood as a corresponding relationship between the on and off states. For example, when the ninth transistor Q9A in the first-phase switched-capacitor circuit SC1 is turned on, the ninth transistor Q9B in the second-phase switched-capacitor circuit SC2 is turned off.

[0180] In the first implementation, in the first-phase switched-capacitor circuit SC1, the capacitance of the first capacitor Cf1A is greater than the capacitance of the second capacitor Cf2A, and the capacitance of the second capacitor Cf2A is equal to the capacitance of the third capacitor Cf3A. For example, Cf1A >> Cf2A = Cf3A.

[0181] For example, the capacitance of the first capacitor Cf1A is more than twice the capacitance of the second capacitor Cf2A. For example, the withstand voltage of the first capacitor Cf1A is 2 times the output voltage Vvo, and the withstand voltage of the second capacitor Cf2A is 1 times the output voltage Vvo.

[0182] In the second-phase switched-capacitor circuit SC2, the capacitance of the first capacitor Cf1B is greater than the capacitance of the second capacitor Cf2B, and the capacitance of the second capacitor Cf2B is equal to the capacitance of the third capacitor Cf3B. For example, Cf1B >> Cf2B = Cf3B.

[0183] For example, the capacitance of the first capacitor Cf1B is more than twice the capacitance of the second capacitor Cf2B. For example, the withstand voltage of the first capacitor Cf1B is 2 times the output voltage Vvo, and the withstand voltage of the second capacitor Cf2B is 1 times the output voltage Vvo.

[0184] The transistors in the first-phase switched-capacitor circuit SC1 and the second-phase switched-capacitor circuit SC2 are in a complementary relationship, and the capacitances can satisfy the following relationship: Cf1A = Cf1B >> Cf2A = Cf2B = Cf3A = Cf3B.

[0185] This can suppress the inrush current among the first capacitor Cf1A, the second capacitor Cf2A, and the third capacitor Cf3A in the first-phase switched-capacitor circuit SC1, and suppress the inrush current among the first capacitor Cf1B, the second capacitor Cf2B, and the third capacitor Cf3B in the second-phase switched-capacitor circuit SC2, thereby reducing the loss of the switched-capacitor circuit SC and improving the efficiency of the switched-capacitor circuit SC.

[0186] In the second implementation, in the first-phase switched-capacitor circuit SC1, the capacitance of the first capacitor Cf1A, the capacitance of the second capacitor Cf2A, and the capacitance of the third capacitor Cf3A are equal, i.e., Cf1A = Cf2A = Cf3A. In the second-phase switched-capacitor circuit SC2, the capacitance of the first capacitor Cf1BA, the capacitance of the second capacitor Cf2B, and the capacitance of the third capacitor Cf3B are equal, i.e., Cf1B = Cf2B = Cf3B. For example, Cf1A = Cf1B = Cf2A = Cf2B = Cf3A = Cf3B. By changing the driving timing of the switched-capacitor circuit SC, the inrush current is reduced. In this way, the capacitance of the first capacitor Cf1A and the first capacitor Cf1B can be reduced, and the area occupied by the first capacitor Cf1A and the first capacitor Cf1B can be reduced.

[0187] FIG. 13B and FIG. 13C are driving timing diagrams of a switched-capacitor circuit according to an embodiment of the present application. FIG. 14A, FIG. 14C, FIG. 14E, FIG. 14G are another intermediate mode diagrams of a switched-capacitor circuit according to an embodiment of the present application, and FIG. 14B, FIG. 14D, FIG. 14F, FIG. 14H are equivalent diagrams of the another intermediate mode of the switched-capacitor circuit according to an embodiment of the present application.

[0188] In some embodiments, the switched-capacitor circuit SC comprises the switched-capacitor circuit SC shown in FIG. 13A. As shown in FIG. 13B and FIG. 13C, the driving method of the switched-capacitor circuit SC comprises:

[0189] As shown in FIG. 14A, in the first mode D1, the sixth transistor Q6A and the third transistor Q3A in the first phase switched-capacitor circuit SC1 are turned on, and the seventh transistor Q7A and the second transistor Q2A are turned off. In the first mode D1, the ninth transistor Q9A, the first transistor Q1A, and the eighth transistor Q8A are also turned on, and the tenth transistor Q10A, the fourth transistor Q4A, and the fifth transistor Q5A are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14B, and both the first branch S1A and the second branch S2A are turned on.

[0190] In the first mode D1, the sixth transistor Q6B and the third transistor Q3B in the second phase switched-capacitor circuit SC2 are turned off, and the seventh transistor Q7B and the second transistor Q2B are turned on. In the first mode D1, the ninth transistor Q9B, the first transistor Q1B, and the eighth transistor Q8B are also turned off, and the tenth transistor Q10B, the fourth transistor Q4B, and the fifth transistor Q5B are turned on. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14B, and both the first branch S1B and the second branch S2B are turned on.

[0191] As shown in FIG. 14C, in the second mode D1A, the third transistor Q3A in the first phase switched-capacitor circuit SC1 is turned on, and the sixth transistor Q6A, the seventh transistor Q7A, and the second transistor Q2A are turned off. In the second mode D1A, the ninth transistor Q9A, the first transistor Q1A, and the eighth transistor Q8A are also turned on, and the tenth transistor Q10A, the fourth transistor Q4A, and the fifth transistor Q5A are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14D, and the first branch S1A is turned on, and the second branch S2A loop is blocked.

[0192] In the second mode D1A, the second transistor Q2B, the third transistor Q3B, the sixth transistor Q6B in the second phase switched-capacitor circuit SC2 are turned off, and the seventh transistor Q7B is turned on. In the second mode D1B, the ninth transistor Q9B, the first transistor Q1B, the eighth transistor Q8B are also turned off, and the tenth transistor Q10B, the fourth transistor Q4B, the fifth transistor Q5B are turned on. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14D, the first branch S1B is turned on, and the second branch S2B loop is blocked.

[0193] At this time, although the first branch S1A is turned on, and the first branch S1B is turned on, since the capacitance values on the two branches are equal, there is no impact current between the two branches.

[0194] As shown in FIG. 14E, in the third mode D2, the seventh transistor Q7A and the second transistor Q2A in the first phase switched-capacitor circuit SC1 are turned on, and the sixth transistor Q6A and the third transistor Q3A are turned off. In the third mode D2, the tenth transistor Q10A, the fourth transistor Q4A, the fifth transistor Q5A are also turned on, and the ninth transistor Q9A, the first transistor Q1A, the eighth transistor Q8A are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14F, the first branch S1A and the second branch S2A are both turned on.

[0195] In the third mode D2, the seventh transistor Q7B and the second transistor Q2B in the second phase switched-capacitor circuit SC2 are turned off, and the sixth transistor Q6B and the third transistor Q3B are turned on. In the third mode D2, the tenth transistor Q10B, the fourth transistor Q4B, the fifth transistor Q5B are also turned off, and the ninth transistor Q9B, the first transistor Q1B, the eighth transistor Q8B are turned on. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14F, the first branch S1B and the second branch S2B are both turned on.

[0196] As shown in FIG. 14G, in the fourth mode D2A, the seventh transistor Q7A in the first phase switched-capacitor circuit SC1 is turned on, and the sixth transistor Q6A, the third transistor Q3A, and the second transistor Q2A are turned off. In the fourth mode D2A, the tenth transistor Q10A, the fourth transistor Q4A, the fifth transistor Q5A are also turned on, and the ninth transistor Q9A, the first transistor Q1A, the eighth transistor Q8A are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14H, the first branch S1A loop is blocked, and the second branch S2A is turned on.

[0197] In the fourth mode D2A, the third transistor Q3B in the second phase switch capacitor circuit SC2 is turned on, and the seventh transistor Q7B, the sixth transistor Q6B and the second transistor Q2B are turned off. In the fourth mode D2B, the tenth transistor Q10B, the fourth transistor Q4B and the fifth transistor Q5B are turned off, and the ninth transistor Q9B, the first transistor Q1B and the eighth transistor Q8B are turned on. The equivalent circuit diagram of the switch capacitor circuit SC is shown in FIG. 14H, and the first branch S1B is blocked and the second branch S2B is turned on.

[0198] At this time, although the second branch S2A is turned on and the second branch S2B is turned on, since the capacitance values on the two branches are equal, there is no impact current between the two branches.

[0199] In the embodiments of the present application, as shown in FIG. 13B, the second mode D1A can be located after the first mode D1, and the fourth mode D2A can be located after the third mode D2. As shown in FIG. 13C, the second mode D1A can be located before the first mode D1, and the fourth mode D2A can be located before the third mode D2.

[0200] Based on this, after the switch capacitor circuit SC is driven by the driving method provided in the embodiments of the present application, the impact current between the first capacitor Cf1A, the second capacitor Cf2A and the third capacitor Cf3A in the first phase switch capacitor circuit SC1 and the impact current between the first capacitor Cf1B, the second capacitor Cf2B and the third capacitor Cf3B in the second phase switch capacitor circuit SC2 can be suppressed without increasing the capacitance value of the first capacitor Cf1, thereby reducing the loss of the switch capacitor circuit SC and improving the efficiency of the switch capacitor circuit SC.

[0201] In some embodiments, as shown in FIG. 13B and FIG. 13C, the duty cycles of the first mode D1 and the third mode D2 are 3 / 8 respectively, and the duty cycles of the second mode D1A and the fourth mode D2A are 1 / 8 respectively.

[0202] In this way, the voltage drops of the branches in each mode can be equal, and the impact current between the first capacitor Cf1A, the second capacitor Cf2A and the third capacitor Cf3A in the first phase switch capacitor circuit SC1 and the impact current between the first capacitor Cf1B, the second capacitor Cf2B and the third capacitor Cf3B in the second phase switch capacitor circuit SC2 can be better suppressed.

[0203] FIG. 15 is a topological schematic diagram of another switch capacitor circuit provided in the embodiments of the present application.

[0204] In some embodiments, in the case that the switched-capacitor circuit SC comprises two-phase switched-capacitor sub-circuits coupled in parallel, the seventh transistor Q7 in one phase switched-capacitor sub-circuit is multiplexed as the third transistor Q3 in the other phase switched-capacitor sub-circuit, or the eighth transistor Q8 in one phase switched-capacitor sub-circuit is multiplexed as the fourth transistor Q4 in the other phase switched-capacitor sub-circuit.

[0205] As shown in FIG. 15, in an example, the switched-capacitor circuit SC comprises a first phase switched-capacitor sub-circuit SC1 and a second phase switched-capacitor sub-circuit SC2. The seventh transistor Q7A in the first phase switched-capacitor sub-circuit SC1 is the same transistor as the third transistor Q3B in the second phase switched-capacitor sub-circuit SC2, and the eighth transistor Q8A in the first phase switched-capacitor sub-circuit SC1 is the same transistor as the fourth transistor Q4B in the second phase switched-capacitor sub-circuit SC2. The third transistor Q3A in the first phase switched-capacitor sub-circuit SC1 is the same transistor as the seventh transistor Q7B in the second phase switched-capacitor sub-circuit SC2, and the fourth transistor Q4A in the first phase switched-capacitor sub-circuit SC1 is the same transistor as the eighth transistor Q8B in the second phase switched-capacitor sub-circuit SC2.

[0206] In this way, the number of transistors in the switched-capacitor circuit SC can be reduced, and the area occupied by the switched-capacitor circuit SC can be reduced.

[0207] FIGS. 16A-16D are driving timing diagrams of a switched-capacitor circuit provided in an embodiment of the present application. FIGS. 17A, 17C, 17E, 17G are another intermediate mode diagrams of a switched-capacitor circuit provided in an embodiment of the present application, and FIGS. 17B, 17D, 17F, 17H are equivalent diagrams of the another intermediate mode of the switched-capacitor circuit provided in an embodiment of the present application.

[0208] In other embodiments, the switched-capacitor circuit SC comprises the switched-capacitor circuit SC shown in FIG. 13A. As shown in FIGS. 16A-16D, the driving method of the switched-capacitor circuit SC comprises:

[0209] As shown in FIG. 14A, in the first mode D1, the driving process of the first phase switched-capacitor sub-circuit SC1 and the second phase switched-capacitor sub-circuit SC2 in the switched-capacitor circuit SC is the same as described above.

[0210] As shown in FIG. 17A, in the second mode D1A, the driving process of the first phase switched-capacitor sub-circuit SC1 is the same as described above in FIG. 14C.

[0211] In the second mode D1A, the sixth transistor Q6B and the third transistor Q3B in the second phase switched-capacitor circuit SC2 are turned off, and the seventh transistor Q7B and the second transistor Q2B are turned on. In the second mode D1A, the ninth transistor Q9B, the first transistor Q1B, and the eighth transistor Q8B are also turned off, and the tenth transistor Q10B, the fourth transistor Q4B, and the fifth transistor Q5B are turned on. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 17B, and both the first branch S1B and the second branch S2B are turned on. The first branch S1A is turned on, and the second branch S2A is turned off. At this time, the capacitance values of the first branch S1A and the first branch S1B are equal, and there is no inrush current between the first branch S1A and the first branch S1B. By adjusting the duty ratio of each mode, the currents on the first branch S1A, the first branch S1B, and the second branch S2B can be adjusted to make the voltage drops on the three branches equal, thereby eliminating the inrush current.

[0212] As shown in FIG. 17C, in the fifth mode D1B, the sixth transistor Q6A and the third transistor Q3A in the first phase switched-capacitor circuit SC1 are turned on, and the seventh transistor Q7A and the second transistor Q2A are turned off. In the fifth mode D1B, the ninth transistor Q9A, the first transistor Q1A, and the eighth transistor Q8A are also turned on, and the tenth transistor Q10A, the fourth transistor Q4A, and the fifth transistor Q5A are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 17D, and both the first branch S1A and the second branch S2A are turned on.

[0213] In the fifth mode D1B, the second transistor Q2B, the third transistor Q3B, and the sixth transistor Q6B in the second phase switched-capacitor circuit SC2 are turned off, and the seventh transistor Q7B is turned on. In the fifth mode D1B, the ninth transistor Q9B, the first transistor Q1B, and the eighth transistor Q8B are also turned off, and the tenth transistor Q10B, the fourth transistor Q4B, and the fifth transistor Q5B are turned on. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 17D, and the first branch S1B is turned on, and the second branch S2B loop is blocked. Both the first branch S1A and the second branch S2A are turned on. At this time, the capacitance values of the first branch S1A and the first branch S1B are equal, and there is no inrush current between the first branch S1A and the first branch S1B. By adjusting the duty ratio of each mode, the currents on the first branch S1A, the first branch S1B, and the second branch S2A can be adjusted to make the voltage drops on the three branches equal, thereby eliminating the inrush current.

[0214] As shown in FIG. 14E, in the third mode D2, the driving process of the first phase switched-capacitor circuit SC1 and the second phase switched-capacitor circuit SC2 in the switched-capacitor circuit SC is the same as described above.

[0215] As shown in FIG. 17E, under the fourth mode D2A, the seventh transistor Q7A in the first phase switched-capacitor circuit SC1 is turned on, and the sixth transistor Q6A, the third transistor Q3A, and the second transistor Q2A are turned off. Under the fourth mode D2A, it also includes that the tenth transistor Q10A, the fourth transistor Q4A, and the fifth transistor Q5A are turned on, and the ninth transistor Q9A, the first transistor Q1A, and the eighth transistor Q8A are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 17F, and the first branch S1A loop is blocked, and the second branch S2A is turned on.

[0216] Under the fourth mode D2A, the seventh transistor Q7B and the second transistor Q2B in the second phase switched-capacitor circuit SC2 are turned off, and the sixth transistor Q6B and the third transistor Q3B are turned on. Under the fourth mode D2A, it also includes that the tenth transistor Q10B, the fourth transistor Q4B, and the fifth transistor Q5B are turned off, and the ninth transistor Q9B, the first transistor Q1B, and the eighth transistor Q8B are turned on. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 17F, and the first branch S1B and the second branch S2B are both turned on.

[0217] As shown in FIG. 17G, under the sixth mode D2B, the seventh transistor Q7A and the second transistor Q2A in the first phase switched-capacitor circuit SC1 are turned on, and the sixth transistor Q6A and the third transistor Q3A are turned off. Under the sixth mode D2B, it also includes that the tenth transistor Q10A, the fourth transistor Q4A, and the fifth transistor Q5A are turned on, and the ninth transistor Q9A, the first transistor Q1A, and the eighth transistor Q8A are turned off. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 14F, and the first branch S1A and the second branch S2A are both turned on.

[0218] Under the sixth mode D2B, the third transistor Q3B in the second phase switched-capacitor circuit SC2 is turned on, and the seventh transistor Q7B, the sixth transistor Q6B, and the second transistor Q2B are turned off. Under the sixth mode D2B, it also includes that the tenth transistor Q10B, the fourth transistor Q4B, and the fifth transistor Q5B are turned off, and the ninth transistor Q9B, the first transistor Q1B, and the eighth transistor Q8B are turned on. The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 17H, and the first branch S1B loop is blocked, and the second branch S2B is turned on.

[0219] In the embodiments of the present application, the first mode D1 is located before the third mode D2, as shown in FIG. 16A. The fifth mode D1B can be located before the first mode D1, and the second mode D1A can be located after the first mode D1. As shown in FIG. 16B, the second mode D1A can be located before the first mode D1, and the fifth mode D1B can be located after the first mode D1. As shown in FIG. 16C, the sixth mode D2B can be located before the third mode D2, and the fourth mode D2A can be located after the third mode D2. As shown in FIG. 16B, the fourth mode D2A can be located before the third mode D2, and the sixth mode D2B can be located after the third mode D2.

[0220] Based on this, after the switch capacitor circuit SC is driven by the driving method provided in the embodiments of the present application, the impact current between the first capacitor Cf1A, the second capacitor Cf2A and the third capacitor Cf3A in the first-phase switch capacitor circuit SC1 and the impact current between the first capacitor Cf1B, the second capacitor Cf2B and the third capacitor Cf3B in the second-phase switch capacitor circuit SC2 can be suppressed without increasing the capacitance value of the first capacitor Cf1, thereby reducing the loss of the switch capacitor circuit SC and improving the efficiency of the switch capacitor circuit SC. In addition, in the second mode D1A, the fifth mode D1B, the fourth mode D2A and the sixth mode D2B, only one transistor is turned off in advance or turned on with delay each time, so that the ripple of the input and output current can be reduced, thereby reducing the voltage ripple and improving the stability of the charging voltage.

[0221] In some embodiments, as shown in FIG. 16D, the duty cycles of the first mode D1 and the third mode D2 are 3 / 14 respectively, and the duty cycles of the second mode D1A, the fourth mode D2A, the fifth mode D1B and the sixth mode D2B are 1 / 7 respectively.

[0222] In this way, the voltage drops of the branches in each mode can be equalized, and the impact current between the first capacitor Cf1A, the second capacitor Cf2A and the third capacitor Cf3A in the first-phase switch capacitor circuit SC1 and the impact current between the first capacitor Cf1B, the second capacitor Cf2B and the third capacitor Cf3B in the second-phase switch capacitor circuit SC2 can be better suppressed.

[0223] FIG. 18A is a schematic diagram of another architecture of a switch capacitor circuit provided in the embodiments of the present application; FIG. 18B and FIG. 18C are schematic diagrams of the topology of the switch capacitor circuit provided in the embodiments of the present application.

[0224] In some embodiments, as shown in FIG. 18A, the switched-capacitor circuit SC includes a plurality (e.g., n) of switched-capacitor groups, each of which includes the first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 coupled in staggered parallel. The first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 in each group operate in a phase difference of 180°, the first-phase switched-capacitor sub-circuit SCI in adjacent groups operate in a phase difference of 180° / n, and the second-phase switched-capacitor sub-circuit SC2 in adjacent groups operate in a phase difference of 180° / n.

[0225] For example, as shown in FIG. 18B, the switched-capacitor circuit SC includes four switched-capacitor sub-circuits, which are divided into two groups with a phase difference of 180° / 2 between adjacent groups. The first-phase switched-capacitor sub-circuit SCI in the left group operates in a phase of 0°, and the first-phase switched-capacitor sub-circuit SCI in the right group operates in a phase of 90°. The second-phase switched-capacitor sub-circuit SC2 in the left group operates in a phase of 180°, and the second-phase switched-capacitor sub-circuit SC2 in the right group operates in a phase of 270°.

[0226] Alternatively, for example, as shown in FIG. 18C, the switched-capacitor circuit SC includes four switched-capacitor sub-circuits, which are divided into two groups with a phase difference of 180° / 2 between adjacent groups. The first-phase switched-capacitor sub-circuit SCI in the left group operates in a phase of 180°, and the first-phase switched-capacitor sub-circuit SCI in the right group operates in a phase of 270°. The second-phase switched-capacitor sub-circuit SC2 in the left group operates in a phase of 0°, and the second-phase switched-capacitor sub-circuit SC2 in the right group operates in a phase of 90°.

[0227] In the driving process of the switched-capacitor circuit SC, the driving process of the first-phase switched-capacitor sub-circuit SCI in each group can refer to the related description above, and the driving process of the second-phase switched-capacitor sub-circuit SC2 in each group can refer to the related description above, except that the phase difference between groups is 180° / n.

[0228] For example, a driving period of one switch capacitor group is T, and the driving timing of different switch capacitor groups does not affect each other. The phase of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is 180° / n out of phase with the phase of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group, and then the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is delayed by ((180° / n) / 360°)*T compared with the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group. The phase of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is 90° out of phase with the phase of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group, and then the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the right switch capacitor group is delayed by 1 / 4T compared with the driving timing of each transistor of the first phase switch capacitor sub-circuit SC1 in the left switch capacitor group.

[0229] By arranging multiple groups of first phase switch capacitor sub-circuits SC1 and second phase switch capacitor sub-circuits SC2 that are connected and out of phase in the switch capacitor circuit SC, the ripple of the charging voltage can be reduced, and the stability of the charging voltage can be improved.

[0230] FIG. 19 is a topological schematic diagram of another switch capacitor circuit provided by an embodiment of the present application.

[0231] In some embodiments, as shown in FIG. 19, the first phase switch capacitor sub-circuit SC1 includes a first switch capacitor network 1 and multiple levels of second switch capacitor networks 2 that are coupled in series, and the last level of second switch capacitor networks 2 is coupled with the first end of the inductive network L.

[0232] For example, the first switch capacitor network 1 includes a first capacitor Cf1 and a first switch network 11, and the first capacitor Cf1 is coupled with the first switch network 11.

[0233] Each level of second switch capacitor networks 2 includes a second capacitor Cf2, a second switch network 21, a third capacitor Cf3, and a third switch network 22. The second switch network 21 is coupled with the second capacitor Cf2 and the first switch network 11 respectively, and is used to adjust the series-parallel connection between the second capacitor Cf2 and the first capacitor Cf1. The third switch network 22 is coupled with the third capacitor Cf3 and the first switch network 11 respectively, and is used to adjust the series-parallel connection between the third capacitor Cf3 and the first capacitor Cf1.

[0234] For example, the first level of switch networks includes a ninth transistor Q9 and a tenth transistor Q10, the second switch network 21 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4, and the third switch network 22 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8.

[0235] Taking the first transistor Q1 as an example, the first transistor Q11 represents the first transistor Q1 in the first-stage third switched-capacitor network 3, the first transistor Q1 N represents the first transistor Q1 in the Nth-stage third switched-capacitor network 3, and other marks are in this manner.

[0236] The first electrode of the ninth transistor Q9 is coupled with the input terminal VI, and the second electrode of the ninth transistor Q9 is coupled with the positive electrode of the first capacitor Cf1 and the first electrode of the fifth transistor Q51 respectively.

[0237] The first electrode of the tenth transistor Q10 is coupled with the negative electrode of the first capacitor Cf1 and the first electrode of the first transistor Q11 respectively, and the second electrode of the tenth transistor Q10 is coupled with the reference ground voltage terminal GND.

[0238] In each stage of the switched-capacitor network 2, the first electrode of the fourth transistor Q4 is coupled with the second electrode of the third transistor Q3, and the second electrode of the fourth transistor Q4 is coupled with the reference ground voltage terminal GND; the first electrode of the eighth transistor Q8 is coupled with the second electrode of the seventh transistor Q7, and the second electrode of the eighth transistor Q8 is coupled with the reference ground voltage terminal GND.

[0239] In the first-stage switched-capacitor network 2, the first electrode of the first transistor Q11 is coupled with the negative electrode of the first capacitor, and the second electrode of the first transistor Q11 is coupled with the first electrode of the second transistor Q21 and the positive electrode of the second capacitor Cf21 respectively. The first electrode of the fifth transistor Q51 is coupled with the positive electrode of the first capacitor Cf11, and the second electrode of the fifth transistor Q51 is coupled with the first electrode of the sixth transistor Q61 and the positive electrode of the third capacitor Cf31 respectively. In the switched-capacitor network 2 except the first stage, the first electrode of the first transistor Q1 is coupled with the second electrode of the second transistor Q2 in the previous-stage switched-capacitor network 2, and the second electrode of the first transistor Q1 is coupled with the first electrode of the second transistor Q2 and the positive electrode of the second capacitor Cf2 respectively; the first electrode of the fifth transistor Q5 is coupled with the second electrode of the sixth transistor Q6 in the previous-stage switched-capacitor network 2, and the second electrode of the fifth transistor Q5 is coupled with the first electrode of the sixth transistor Q6 and the positive electrode of the third capacitor Cf3 respectively.

[0240] In the last-stage switched-capacitor network 2, the second electrode of the second transistor Q2 N , the first electrode of the third transistor Q3 N , the second electrode of the sixth transistor Q6 N , and the first electrode of the seventh transistor Q7 N are all coupled with the output terminal VO. In the switched-capacitor network 2 except the last stage, the second electrode of the second transistor Q2 N is coupled with the first electrode of the seventh transistor Q7 N , and the second electrode of the sixth transistor Q6N The second and third transistors Q3 N The first pole is coupled. This is a simple topology.

[0241] The switched capacitor circuit SC includes a multi-stage (N-stage) series-coupled second switched capacitor network 2, which can achieve an input voltage to output voltage ratio Vvi:Vvo of 2 at the input terminal VI. N+1 The ratio is increased to 1 to achieve a high transformation ratio and meet different application requirements. For example, when N=2, the voltage transformation ratio of the switched capacitor circuit SC changes from 4:1 in Figure 7 to 8:1.

[0242] In the first implementation, in the first-phase switched capacitor circuit SC1, the capacitance of the first capacitor Cf1 is greater than the capacitance of the second capacitor Cf2 in each stage of the second switched capacitor network 2, and the capacitance of the second capacitor Cf2 is equal to the capacitance of the third capacitor Cf3. For example, Cf1 >> Cf2 = Cf3.

[0243] For example, the capacitance of the first capacitor Cf1 is more than twice the capacitance of the second capacitor Cf2. For instance, the first capacitor Cf1 has a withstand voltage of twice the output voltage Vvo, and the second capacitor Cf2 has a withstand voltage of once the output voltage Vvo.

[0244] This can suppress the inrush current between the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 in the first phase switched capacitor circuit SC1, thereby reducing the loss of the switched capacitor circuit SC and improving the efficiency of the switched capacitor circuit SC.

[0245] In the second implementation, the capacitance values ​​of the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 in the first-phase switched capacitor circuit SC1 are equal, i.e., Cf1 = Cf2 = Cf3. By changing the driving timing of the switched capacitor circuit SC, the inrush current is reduced. This allows for a reduction in the capacitance value of the first capacitor Cf1, thus reducing the area occupied by it.

[0246] The following is a schematic illustration of the driving method of the switched capacitor circuit SC, taking N=2 and the voltage change ratio of the switched capacitor circuit SC as an example of 8:1.

[0247] Figure 20 is a driving timing diagram of a switched capacitor circuit provided in an embodiment of this application. Figures 21A, 21C, 21E, 21G, 21I, 21K, 21M, and 21O are another intermediate mode diagram of the switched capacitor circuit provided in an embodiment of this application. Figures 21B, 21D, 21F, 21H, 21J, 21L, 21N, and 21P are equivalent diagrams of another intermediate mode of the switched capacitor circuit provided in an embodiment of this application.

[0248] In some embodiments, the switched-capacitor circuit SC comprises the switched-capacitor circuit SC shown in FIG. 19. As shown in FIG. 20, the driving method of the switched-capacitor circuit SC comprises:

[0249] As shown in FIG. 21A, in the first mode D1, the third transistor Q31 and the sixth transistor Q61 in the first-stage second switched-capacitor network 2 are turned on, and the seventh transistor Q71 and the second transistor Q21 are turned off. The seventh transistor Q72 and the second transistor Q22 in the last-stage second switched-capacitor network 2 are turned on, and the sixth transistor Q62 and the third transistor Q32 are turned off. In the first mode D1, the ninth transistor Q91, the first transistor Q11, and the eighth transistor Q81 in the first-stage second switched-capacitor network 2 are also turned on, and the tenth transistor Q101, the fourth transistor Q41, and the fifth transistor Q51 are turned off. The fourth transistor Q42 and the fifth transistor Q52 in the last-stage second switched-capacitor network 2 are turned on, and the first transistor Q12 and the eighth transistor Q82 are turned off.

[0250] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 21B, in which the first branch first branch S11, the first branch second branch S12, and the second branch S2 are all turned on.

[0251] As shown in FIG. 21C, in the second mode D1A, the third transistor Q31 in the first-stage second switched-capacitor network 2 is turned on, and the sixth transistor Q61, the seventh transistor Q71, and the second transistor Q21 are turned off. The seventh transistor Q72 and the second transistor Q22 in the last-stage second switched-capacitor network 2 are turned on, and the sixth transistor Q62 and the third transistor Q32 are turned off. In the second mode D1A, the ninth transistor Q91, the first transistor Q11, and the eighth transistor Q81 in the first-stage second switched-capacitor network 2 are also turned on, and the tenth transistor Q101, the fourth transistor Q41, and the fifth transistor Q51 are turned off. The fourth transistor Q42 and the fifth transistor Q52 in the last-stage second switched-capacitor network 2 are turned on, and the first transistor Q12 and the eighth transistor Q82 are turned off.

[0252] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 21D, in which the first branch first branch S11 is turned on, the first branch second branch S12 is blocked, and the second branch S2 is turned on. The capacitance on the first branch first branch S11 is 1 / 3 of the capacitance of the second branch S2. By adjusting the duty cycle of each mode, the current on the first branch first branch S11 can be made to be 1 / 3 of the current of the second branch S2, so as to ensure that the voltage drops of the two branches are equal, and there is no inrush current between the two branches.

[0253] As shown in FIG. 21E, in the third mode D2, the second transistor Q21 and the seventh transistor Q71 in the first-stage second switched-capacitor network 2 are turned on, and the sixth transistor Q61 and the third transistor Q31 are turned off. The third transistor Q32 and the sixth transistor Q62 in the last-stage second switched-capacitor network 2 are turned on, and the second transistor Q22 and the seventh transistor Q72 are turned off. In the third mode D2, the ninth transistor Q91, the first transistor Q11, and the eighth transistor Q81 in the first-stage second switched-capacitor network 2 are turned off, and the tenth transistor Q101, the fourth transistor Q41, and the fifth transistor Q51 are turned on. The fourth transistor Q42 and the fifth transistor Q52 in the last-stage second switched-capacitor network 2 are turned off, and the first transistor Q12 and the eighth transistor Q82 are turned on.

[0254] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 21F, in which the first branch first branch S11, the first branch second branch S12, and the second branch S2 are all turned on.

[0255] As shown in FIG. 21G, in the fourth mode D2A, the seventh transistor Q71 in the first-stage second switched-capacitor network 2 is turned on, and the sixth transistor Q61, the second transistor Q21, and the third transistor Q31 are turned off. The sixth transistor Q62 and the third transistor Q32 in the last-stage second switched-capacitor network 2 are turned on, and the second transistor Q22 and the seventh transistor Q72 are turned off. In the fourth mode D2A, the ninth transistor Q91, the first transistor Q11, and the eighth transistor Q81 in the first-stage second switched-capacitor network 2 are turned off, and the tenth transistor Q101, the fourth transistor Q41, and the fifth transistor Q51 are turned on. The fourth transistor Q42 and the fifth transistor Q52 in the last-stage second switched-capacitor network 2 are turned off, and the first transistor Q12 and the eighth transistor Q82 are turned on.

[0256] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 21H, in which the first branch first branch S11 is turned on, the first branch second branch S12 is blocked, and the second branch S2 is turned on. The capacitance on the first branch first branch S11 is 1 / 3 of the capacitance of the second branch S2. By adjusting the duty cycle of each mode, the current on the first branch first branch S11 can be made to be 1 / 3 of the current of the second branch S2, so as to ensure that the voltage drops of the two branches are equal, and there is no inrush current between the two branches.

[0257] As shown in FIG. 21I, in the fifth mode D1B, the third transistor Q31 and the sixth transistor Q61 in the first stage of the second switched-capacitor network 2 are turned on, and the seventh transistor Q71 and the second transistor Q21 are turned off. The seventh transistor Q72 in the last stage of the second switched-capacitor network 2 is turned on, and the sixth transistor Q62, the second transistor Q22 and the third transistor Q32 are turned off. In the fifth mode D1B, the ninth transistor Q91, the first transistor Q11 and the eighth transistor Q81 in the first stage of the second switched-capacitor network 2 are turned on, and the tenth transistor Q101, the fourth transistor Q41, the fifth transistor Q51 are turned off. The fourth transistor Q42, the fifth transistor Q52 in the last stage of the second switched-capacitor network 2 are turned on, and the first transistor Q12, the eighth transistor Q82 are turned off.

[0258] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 21J, the first branch first branch S11 and the first branch second branch S12 are both turned on, and the second branch S2 is turned on.

[0259] As shown in FIG. 21K, in the sixth mode D2B, the second transistor Q21 and the seventh transistor Q71 in the first stage of the second switched-capacitor network 2 are turned on, and the sixth transistor Q61, the third transistor Q31 are turned off. The third transistor Q32 in the last stage of the second switched-capacitor network 2 is turned on, and the sixth transistor Q62, the second transistor Q22 and the seventh transistor Q72 are turned off. In the sixth mode D2B, the ninth transistor Q91, the first transistor Q11 and the eighth transistor Q81 in the first stage of the second switched-capacitor network 2 are turned off, and the tenth transistor Q101, the fourth transistor Q41, the fifth transistor Q51 are turned on. The fourth transistor Q42, the fifth transistor Q52 in the last stage of the second switched-capacitor network 2 are turned off, and the first transistor Q12, the eighth transistor Q82 are turned on.

[0260] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in FIG. 21L, the first branch first branch S11, the first branch second branch S12, the second branch S2 are all turned on.

[0261] As shown in Fig. 21M, in the seventh mode D1C, the third transistor Q31 in the first-stage second switched-capacitor network 2 is turned on, and the sixth transistor Q61, the seventh transistor Q71 and the second transistor Q21 are turned off. The seventh transistor Q72 in the last-stage second switched-capacitor network 2 is turned on, and the sixth transistor Q62, the second transistor Q22 and the third transistor Q32 are turned off. In the seventh mode D1C, the ninth transistor Q91, the first transistor Q11 and the eighth transistor Q81 in the first-stage second switched-capacitor network 2 are turned on, and the tenth transistor Q101, the fourth transistor Q41 and the fifth transistor Q51 are turned off. The fourth transistor Q42 and the fifth transistor Q52 in the last-stage second switched-capacitor network 2 are turned on, and the first transistor Q12 and the eighth transistor Q82 are turned off.

[0262] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in Fig. 21N, the first branch first sub-branch S11 is turned on, and the first branch second sub-branch S12 and the second branch S2 are blocked.

[0263] As shown in Fig. 21O, in the eighth mode D2C, the seventh transistor Q71 in the first-stage second switched-capacitor network 2 is turned on, and the sixth transistor Q61, the second transistor Q21 and the third transistor Q31 are turned off. The third transistor Q32 in the last-stage second switched-capacitor network 2 is turned on, and the sixth transistor Q62, the second transistor Q22 and the seventh transistor Q72 are turned off. In the eighth mode D2C, the ninth transistor Q91, the first transistor Q11 and the eighth transistor Q81 in the first-stage second switched-capacitor network 2 are turned off, and the tenth transistor Q101, the fourth transistor Q41 and the fifth transistor Q51 are turned on. The fourth transistor Q42 and the fifth transistor Q52 in the last-stage second switched-capacitor network 2 are turned off, and the first transistor Q12 and the eighth transistor Q82 are turned on.

[0264] The equivalent circuit diagram of the switched-capacitor circuit SC is shown in Fig. 21P, the first branch first sub-branch S1 is turned on, and the first branch second sub-branch S12 and the second branch S2 are blocked.

[0265] The order of the modes is not limited in the embodiments of the present application. In the driving process of the switched-capacitor circuit SC, the driving is not limited to the order of the above modes.

[0266] The above description is illustrative with the switched-capacitor circuit SC including two-stage second switched-capacitor networks 2. In the case of the switched-capacitor circuit SC including multi-stage second switched-capacitor networks 2, the adjacent two-stage second switched-capacitor networks 2 operate in the way of 180° phase difference. The switching relationship of the transistors in the operation of 180° phase difference can refer to the switching relationship of the transistors between the first-stage second switched-capacitor network 2 and the last-stage second switched-capacitor network 2.

[0267] In some embodiments, as shown in FIG. 20, the duty cycles of the first mode D1 and the third mode D2 are 1 / 4 respectively, the duty cycles of the second mode D1A and the fourth mode D2A are 1 / 8 respectively, the duty cycles of the fifth mode D1B and the sixth mode D2B are 3 / 32 respectively, and the duty cycles of the seventh mode D1C and the eighth mode D2C are 1 / 32 respectively.

[0268] In this way, the voltage drops of the branches in each mode can be equalized, and the impact current between the first capacitor Cf1, the second capacitor Cf2 and the third capacitor Cf3 in the first phase switched capacitor circuit SC1 can be better suppressed.

[0269] FIG. 22A is a schematic diagram of another topology of a switched capacitor circuit provided by embodiments of the present application.

[0270] In some embodiments, as shown in FIG. 22A, the switched capacitor circuit SC includes a first phase switched capacitor sub-circuit SC1 and a second phase switched capacitor sub-circuit SC2, which are coupled in parallel and in opposite phase between the input terminal VI and the first end of the inductive network L.

[0271] The first phase switched capacitor sub-circuit SC1 can refer to the related description of the first phase switched capacitor circuit SC1 in FIG. 19 above, and the second phase switched capacitor sub-circuit SC2 can also refer to the related description of the first phase switched capacitor circuit SC1 in FIG. 19 above. In FIG. 22A, “A” and “B” are used to distinguish the structures in the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2. During the driving process of the switched capacitor circuit SC, the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 operate in opposite phase by 180°. That is, the switching states of the transistors in the first phase switched capacitor sub-circuit SC1 and the transistors in the second phase switched capacitor sub-circuit SC2 are exactly opposite. Taking the ninth transistor Q9A in the first phase switched capacitor sub-circuit SC1 and the ninth transistor Q9B in the second phase switched capacitor sub-circuit SC2 as an example, when operating in opposite phase by 180°, the ninth transistor Q9A is turned on, and the ninth transistor Q9B is turned off. The ninth transistor Q9A is turned off, and the ninth transistor Q9B is turned on.

[0272] In some embodiments, as shown in FIG. 22B, the seventh transistor Q7A in the last stage third switch network 22A in the first phase switched capacitor sub-circuit SC1 N and the third transistor Q3B in the last stage second switch network 21B in the second phase switched capacitor sub-circuit SC2 N are the same transistor.

[0273] Alternatively, the eighth transistor Q8A in the last stage third switch network 22A in the first phase switched capacitor sub-circuit SC1N and the fourth transistor Q4B of the last-stage second switch network 21B in the second-phase switched-capacitor sub-circuit SC2 N are the same transistor.

[0274] or the seventh transistor Q7B of the last-stage third switch network 22B in the second-phase switched-capacitor sub-circuit SC2 N and the third transistor Q3A of the last-stage second switch network 21A in the first-phase switched-capacitor sub-circuit SC1 N are the same transistor.

[0275] or the eighth transistor Q8B of the last-stage third switch network 22B in the second-phase switched-capacitor sub-circuit SC2 N and the fourth transistor Q4A of the last-stage second switch network 21A in the first-phase switched-capacitor sub-circuit SC1 N are the same transistor.

[0276] In this topology, the number of transistors in the switched-capacitor circuit SC can be reduced, and the area occupied by the switched-capacitor circuit SC can be reduced.

[0277] The switched-capacitor circuit SC includes multi-phase switched-capacitor sub-circuits, and can meet a larger charging power on the basis of realizing a high conversion ratio.

[0278] FIG. 23 is a schematic diagram of another architecture of a switched-capacitor circuit provided in an embodiment of the present application.

[0279] In some embodiments, as shown in FIG. 23, the switched-capacitor circuit SC includes n groups of the first-phase switched-capacitor sub-circuit SC1 and the second-phase switched-capacitor sub-circuit SC2 coupled in parallel, the first-phase switched-capacitor sub-circuits SC1 in adjacent groups operate in a phase difference of 180° / n, and the second-phase switched-capacitor sub-circuits SC2 in adjacent groups operate in a phase difference of 180° / n.

[0280] In the driving process of the switched-capacitor circuit SC, the driving process of the first-phase switched-capacitor sub-circuit SC1 in each group can refer to the related description above, and the driving process of the second-phase switched-capacitor sub-circuit SC2 in each group can refer to the related description above, except that the phase difference between groups is 180° / n.

[0281] By setting multiple groups of the first-phase switched-capacitor sub-circuit SC1 and the second-phase switched-capacitor sub-circuit SC2 coupled in parallel and in a phase difference in the switched-capacitor circuit SC, the ripple of the charging voltage can be reduced, and the stability of the charging voltage can be improved.

[0282] FIG. 24 is a schematic diagram of another topology of a switched-capacitor circuit provided in an embodiment of the present application.

[0283] The embodiment of the present application further provides a switched capacitor circuit SC, as shown in Fig. 24, the switched capacitor circuit SC comprises a first phase switched capacitor sub-circuit SC1. The first phase switched capacitor sub-circuit SC1 comprises the first capacitor Cf1, the first switch network 11, the second capacitor Cf2, the third capacitor Cf3, the second switch network 21 and the third switch network 22, and the related description is referred to the above description, and will not be repeated here.

[0284] The first phase switched capacitor sub-circuit SC1 further comprises one or more of the first inductor network L1, the second inductor network L2, the third inductor network L3, the fourth inductor network L4, the fifth inductor network L5 or the sixth inductor network L6.

[0285] The first inductor network L1 is coupled in series with the first capacitor Cf1, the second inductor network L2 is coupled in series with the second capacitor Cf2, the third inductor network L3 is coupled between the second switch network 21 and the first node A1, the fourth inductor network L4 is coupled between the third switch network 22 and the first node A1, the fifth inductor network L5 is coupled between the first node A1 and the output terminal, and the sixth inductor network L6 is coupled in series with the third capacitor Cf3.

[0286] The first inductor network L1 is in series with the first capacitor Cf1, the first inductor network L1 can be coupled with the positive pole of the first capacitor Cf1, or the first inductor network L1 can be coupled with the negative pole of the first capacitor Cf1. The second inductor network L2 is in series with the second capacitor Cf2, the second inductor network L2 can be coupled with the positive pole of the second capacitor Cf2, or the second inductor network L2 can be coupled with the negative pole of the second capacitor Cf2. The sixth inductor network L6 is in series with the third capacitor Cf3, the sixth inductor network L6 can be coupled with the positive pole of the third capacitor Cf3, or the sixth inductor network L6 can be coupled with the negative pole of the third capacitor Cf3. Fig. 24 is only one kind of schematic, and is not limited in any way.

[0287] Figs. 25A and 25B are another intermediate mode diagram of the switched capacitor circuit provided by the embodiment of the present application.

[0288] As shown in Fig. 25A, after the switched capacitor circuit SC enters the first mode, each inductor network is in series with a capacitor or the output terminal VO. As shown in Fig. 25B, after the switched capacitor circuit SC enters the second mode, each inductor network is in series with a capacitor or the output terminal VO.

[0289] The switched capacitor circuit SC provided by the embodiment of the present application sets the inductor network at one position or multiple positions, so that the capacitor is in series with the inductor network, or the output terminal VO is in series with the inductor network. The branch provided with the inductor network can inhibit the current mutation on the branch due to the existence of the inductor network, and improve the efficiency of the switched capacitor circuit SC.

[0290] In some embodiments, the first-phase switched-capacitor sub-circuit SC1 does not simultaneously include the second inductive network L2 and the third inductive network L3. As can be seen from FIGS. 25A and 25B, both the second inductive network L2 and the third inductive network L3 serve to stabilize the current of the second capacitor Cf2, and the alternative selection can reduce redundancy.

[0291] In some embodiments, the first-phase switched-capacitor sub-circuit SC1 does not simultaneously include the fourth inductive network L4 and the sixth inductive network L6. As can be seen from FIGS. 25A and 25B, both the fourth inductive network L4 and the sixth inductive network L6 serve to stabilize the current of the second capacitor Cf2, and the alternative selection can reduce redundancy.

[0292] In some embodiments, the first-phase switched-capacitor sub-circuit SC1 includes two inductive networks.

[0293] FIG. 26A is a schematic diagram of another topology of a switched-capacitor circuit according to embodiments of the present application; FIGS. 26B and 26C are equivalent diagrams of another intermediate mode of the switched-capacitor circuit according to embodiments of the present application. FIG. 26D is a schematic diagram of simulation results of a capacitor current under different inductance values according to embodiments of the present application.

[0294] For example, as shown in FIG. 26A, the first-phase switched-capacitor sub-circuit SC1 includes the third inductive network L3 and the fourth inductive network L4.

[0295] In the first mode, as shown in FIG. 26B, the third inductive network L3 is connected in series to the first branch S1, and the fourth inductive network L4 is connected in series to the second branch S2. The third inductive network L3 and the fourth inductive network L4 can suppress the current mutation of the first branch S1 and the second branch S2. Although the third branch S3 does not have an inductive network connected in series, the third branch S3 will not generate current mutation in the case that the first branch S1 and the second branch S2 have no current mutation. Thus, the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3, and the output terminal VO is suppressed, and the efficiency of the switched-capacitor circuit SC is improved.

[0296] In the second mode, as shown in FIG. 26C, the third inductive network L3 is connected in series to the first branch S1, and the fourth inductive network L4 is connected in series to the second branch S2. The third inductive network L3 and the fourth inductive network L4 can suppress the current mutation of the first branch S1 and the second branch S2. Although the third branch S3 does not have an inductive network connected in series, the third branch S3 will not generate current mutation in the case that the first branch S1 and the second branch S2 have no current mutation. Thus, the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3, and the output terminal VO is suppressed, and the efficiency of the switched-capacitor circuit SC is improved.

[0297] As shown in FIG. 26D, in the case that the inductive network is not included in the first phase switched capacitor sub-circuit SC1, the impulse current exists in the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3 and the output terminal VO. However, after the third inductive network L3 and the fourth inductive network L4 are added in the switched capacitor circuit SC, the impulse current in the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3 and the output terminal VO is reduced, and it can be considered as no impulse current (circled in FIG. 26D). The greater the inductance of the inductive network, the slower the current rises, and the lower the loss of the switched capacitor circuit SC.

[0298] FIG. 27A is a topological schematic diagram of another switched capacitor circuit provided by the embodiments of the present application; FIG. 27B and FIG. 27C are equivalent diagrams of another intermediate mode of the switched capacitor circuit provided by the embodiments of the present application.

[0299] Alternatively, as shown in FIG. 27A, the first phase switched capacitor sub-circuit SC1 includes the third inductive network L3 and the fifth inductive network L5.

[0300] In the first mode, as shown in FIG. 27B, the third inductive network L3 is connected in series in the first branch S1, and the fifth inductive network L5 is connected in series in the third branch S3. The third inductive network L3 and the fifth inductive network L5 can suppress the current mutation in the first branch S1 and the third branch S3. Although the second branch S2 does not have an inductive network connected in series, the second branch S2 will not generate current mutation in the case that the first branch S1 and the third branch S3 have no current mutation. Thus, the impulse current in the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3 and the output terminal VO is suppressed, and the efficiency of the switched capacitor circuit SC is improved.

[0301] In the second mode, as shown in FIG. 27C, the third inductive network L3 is connected in series in the first branch S1, and the fifth inductive network L5 is connected in series in the third branch S3. The third inductive network L3 and the fifth inductive network L5 can suppress the current mutation in the first branch S1 and the third branch S3. Although the second branch S2 does not have an inductive network connected in series, the second branch S2 will not generate current mutation in the case that the first branch S1 and the third branch S3 have no current mutation. Thus, the impulse current in the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3 and the output terminal VO is suppressed, and the efficiency of the switched capacitor circuit SC is improved.

[0302] FIG. 28A is a topological schematic diagram of another switched capacitor circuit provided by the embodiments of the present application; FIG. 28B and FIG. 28C are equivalent diagrams of another intermediate mode of the switched capacitor circuit provided by the embodiments of the present application.

[0303] Alternatively, as shown in FIG. 28A, the first-phase switched-capacitor sub-circuit SC1 includes a fourth inductive network L4 and a fifth inductive network L5.

[0304] In the first mode, as shown in FIG. 28B, the fourth inductive network L4 is connected in series to the second branch S2, and the fifth inductive network L5 is connected in series to the third branch S3. The fourth inductive network L4 and the fifth inductive network L5 can suppress current surges on the second branch S2 and the third branch S3. Although the first branch S1 does not have an inductive network connected in series, the first branch S1 will not have a current surge in the case that the second branch S2 and the third branch S3 do not have a current surge. Thus, the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3, and the output terminal VO is suppressed, and the efficiency of the switched-capacitor circuit SC is improved.

[0305] In the second mode, as shown in FIG. 28C, the fourth inductive network L4 is connected in series to the second branch S2, and the fifth inductive network L5 is connected in series to the third branch S3. The fourth inductive network L4 and the fifth inductive network L5 can suppress current surges on the second branch S2 and the third branch S3. Although the first branch S1 does not have an inductive network connected in series, the first branch S1 will not have a current surge in the case that the second branch S2 and the third branch S3 do not have a current surge. Thus, the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3, and the output terminal VO is suppressed, and the efficiency of the switched-capacitor circuit SC is improved.

[0306] FIGS. 29-34 are schematic diagrams of another switched-capacitor circuit topology according to embodiments of the present application.

[0307] Alternatively, as shown in FIG. 29, the first-phase switched-capacitor sub-circuit SC1 includes a second inductive network L2 and a sixth inductive network L6.

[0308] Alternatively, as shown in FIG. 30, the first-phase switched-capacitor sub-circuit SC1 includes a second inductive network L2 and a fourth inductive network L4.

[0309] Alternatively, as shown in FIG. 31, the first-phase switched-capacitor sub-circuit SC1 includes a second inductive network L2 and a fifth inductive network L5.

[0310] Alternatively, as shown in FIG. 32, the first-phase switched-capacitor sub-circuit SC1 includes a third inductive network L3 and a sixth inductive network L6.

[0311] Alternatively, as shown in FIG. 33, the first-phase switched-capacitor sub-circuit SC1 includes a fifth inductive network L5 and a sixth inductive network L6.

[0312] Alternatively, as shown in FIG. 34, the first-phase switched-capacitor sub-circuit SC1 includes the fifth inductor network L5 and the first inductor network L1.

[0313] In the above scheme, the first-phase switched-capacitor sub-circuit SC1 includes two inductor networks, which can achieve the effect of suppressing the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3 and the output terminal VO. The principle is the same as above, which will not be described here.

[0314] In some other embodiments, the first-phase switched-capacitor sub-circuit SC1 includes three inductor networks.

[0315] FIG. 35A is a topological schematic diagram of another switched-capacitor circuit provided by the embodiments of the present application; FIG. 35B and FIG. 35C are equivalent diagrams of another intermediate mode of the switched-capacitor circuit provided by the embodiments of the present application.

[0316] For example, as shown in FIG. 35A, the first-phase switched-capacitor sub-circuit SC1 includes the first inductor network L1, the second inductor network L2 and the sixth inductor network L6.

[0317] In the first mode, as shown in FIG. 35B, the first inductor network L1 and the second inductor network L2 are connected in series in the first branch S1, and the sixth inductor network L6 is connected in series in the second branch S2. The first inductor network L1 and the second inductor network L2 can suppress the current mutation in the first branch S1, and the sixth inductor network L6 can suppress the current mutation in the second branch S2. Although the third branch S3 does not have an inductor network connected in series, the third branch S3 will not produce current mutation in the case that the first branch S1 and the second branch S2 have no current mutation. Thus, the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3 and the output terminal VO is suppressed, and the efficiency of the switched-capacitor circuit SC is improved.

[0318] In the second mode, as shown in FIG. 35C, the third inductor network L3 is connected in series in the first branch S1, and the first inductor network L1 and the sixth inductor network L6 are connected in series in the second branch S2. The third inductor network L3 can suppress the current mutation in the first branch S1, and the first inductor network L1 and the sixth inductor network L6 can suppress the current mutation in the second branch S2. Although the third branch S3 does not have an inductor network connected in series, the third branch S3 will not produce current mutation in the case that the first branch S1 and the second branch S2 have no current mutation. Thus, the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3 and the output terminal VO is suppressed, and the efficiency of the switched-capacitor circuit SC is improved.

[0319] FIG. 36-FIG. 40 are topological schematic diagrams of another switched-capacitor circuit provided by the embodiments of the present application.

[0320] Alternatively, as shown in FIG. 36, the first-phase switched-capacitor sub-circuit SC1 includes the first inductive network L1, the second inductive network L2, and the fourth inductive network L4.

[0321] Alternatively, as shown in FIG. 37, the first-phase switched-capacitor sub-circuit SC1 includes the first inductive network L1, the third inductive network L3, and the sixth inductive network L6.

[0322] Alternatively, as shown in FIG. 38, the first-phase switched-capacitor sub-circuit SC1 includes the first inductive network L1, the third inductive network L3, and the fourth inductive network L4.

[0323] When the first-phase switched-capacitor sub-circuit SC1 includes three inductive networks, and the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 are respectively connected in series with one inductive network, the inductive networks and the capacitors can be complementary paired to facilitate accurate adjustment of the resonance state of the first-phase switched-capacitor sub-circuit SC1.

[0324] Alternatively, as shown in FIG. 39, the first-phase switched-capacitor sub-circuit SC1 includes the first inductive network L1, the third inductive network L3, and the fifth inductive network L5.

[0325] Alternatively, as shown in FIG. 40, the first-phase switched-capacitor sub-circuit SC1 includes the first inductive network L1, the second inductive network L2, and the fifth inductive network L5.

[0326] By providing three inductive networks in the first-phase switched-capacitor sub-circuit SC1, current fluctuations can be further reduced, and the impact current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3, and the output terminal VO can be suppressed, thereby improving the efficiency of the switched-capacitor circuit SC.

[0327] FIG. 41A is a topological schematic diagram of another switched-capacitor circuit provided by an embodiment of the present application; FIG. 41B is another intermediate modal diagram of a switched-capacitor circuit provided by an embodiment of the present application; FIG. 41C is an equivalent diagram of another intermediate modal of a switched-capacitor circuit provided by an embodiment of the present application; FIG. 41D is another intermediate modal diagram of a switched-capacitor circuit provided by an embodiment of the present application; and FIG. 41E is an equivalent diagram of another intermediate modal of a switched-capacitor circuit provided by an embodiment of the present application.

[0328] In some embodiments, as shown in FIG. 41A, the first-phase switched-capacitor sub-circuit SC1 includes N-stage second switched-capacitor networks 2 coupled in series. The last-stage second switched-capacitor network 2 is coupled to the first node A1. The manner in which the N-stage second switched-capacitor networks 2 are coupled in series can refer to the related description of FIG. 19 described above, and will not be described here again.

[0329] The second capacitor Cf2 of the second stage of the second switched-capacitor network 2 is coupled in series with a second inductor network L, or the third capacitor Cf3 of the second stage of the second switched-capacitor network 2 is coupled in series with a sixth inductor network L6.

[0330] In FIG. 41A, the second capacitor Cf2 of each stage of the second switched-capacitor network 2 is coupled in series with a second inductor network L2, the third capacitor Cf3 is coupled in series with a sixth inductor network L6, the first node A1 is coupled with a third inductor network L3, a fourth inductor network L4, and a fifth inductor network L5, and the first capacitor Cf1 is coupled in series with a first inductor network L1.

[0331] In the first mode, as shown in FIG. 41B, half of the transistors in the switched-capacitor circuit SC are turned on, and the other half are turned off. As shown in FIG. 41C, an inductor network is arranged on each branch, thereby suppressing the inrush current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3, and the output terminal VO, and improving the efficiency of the switched-capacitor circuit SC.

[0332] In the second mode, as shown in FIG. 41D, half of the transistors in the switched-capacitor circuit SC are turned on, and the other half are turned off. As shown in FIG. 41E, an inductor network is arranged on each branch, thereby suppressing the inrush current of the first capacitor Cf1, the second capacitor Cf2, the third capacitor Cf3, and the output terminal VO, and improving the efficiency of the switched-capacitor circuit SC.

[0333] In FIG. 41A, the second inductor network in series with the second capacitor Cf2 of the Nth stage of the second switched-capacitor network 2 is represented by L2 N for example, and other symbols are also represented in this way, which will not be explained one by one here. N for example, and other symbols are also represented in this way, which will not be explained one by one here.

[0334] The embodiments of the present application do not limit the switched-capacitor circuit SC to include each of the above inductor networks, and one or more of the above inductor networks can be selected to be arranged in the switched-capacitor circuit SC, which can have the effect of suppressing the inrush current.

[0335] Taking the switched-capacitor circuit SC including two stages of the second switched-capacitor network 2 as an example (N=2):

[0336] For example, the switched-capacitor circuit SC can include the first inductor network L1, the second stage of the second inductor network L22, and the fourth inductor network L4.

[0337] Alternatively, for example, the switched-capacitor circuit SC can include the first inductor network L1, the second stage of the second inductor network L22, and the second stage of the sixth inductor network L62.

[0338] Alternatively, the switch capacitor circuit SC can include the first inductive network L1, the third inductive network L3 and the fourth inductive network L4.

[0339] Alternatively, the switch capacitor circuit SC can include the first inductive network L1, the third inductive network L3 and the fourth inductive network L4.

[0340] Alternatively, the switch capacitor circuit SC can include the first inductive network L1, the third inductive network L3 and the fourth inductive network L4.

[0341] Alternatively, the switch capacitor circuit SC can include the first inductive network L1, the third inductive network L3 and the fourth inductive network L4.

[0342] Alternatively, the switch capacitor circuit SC can include the first inductive network L1, the third inductive network L3 and the fourth inductive network L4.

[0343] Alternatively, the switch capacitor circuit SC can include the first inductive network L1, the third inductive network L3 and the fourth inductive network L4.

[0344] Alternatively, the switch capacitor circuit SC can include the first inductive network L1, the third inductive network L3 and the fourth inductive network L4.

[0345] The switch capacitor circuit SC includes a plurality of (N stages) second switch capacitor networks 2 coupled in series, and can realize a ratio Vvi:Vvo of the input voltage and the output voltage of the input terminal VI as 2 N+1 :1, to realize a high conversion ratio and meet different use requirements. For example, when N=2, the voltage conversion ratio of the switch capacitor circuit SC changes from 4:1 in FIG. 7 to 8:1.

[0346] As shown in FIGS. 41C and 41E, in the case of N>2, in the equivalent topology diagram, as long as two branches are provided with inductive networks among the three branches corresponding to any intersection, the current impact on the three branches can be suppressed. When the scheme of selecting at least two branches to provide inductive networks is adopted for all three branches coupled corresponding to the intersections, the current impact on each capacitor in the switch capacitor circuit SC can be suppressed. The present application does not limit the position of the inductive network provided in the switch capacitor circuit SC, as long as the above effect can be achieved.

[0347] FIGS. 42A and 42B are schematic diagrams of another topology of a switch capacitor circuit provided by the present application.

[0348] In some embodiments, as shown in FIG. 42A, the switched-capacitor circuit SC includes a first-phase switched-capacitor sub-circuit SCI and a second-phase switched-capacitor sub-circuit SC2. The first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 are coupled in parallel in an interleaved manner between the input terminal VI and the first node A1.

[0349] The structures of the first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 in FIG. 42A can be referred to the related descriptions of the structure of the first-phase switched-capacitor sub-circuit SCI shown in FIG. 24.

[0350] The switched-capacitor circuit SC includes multiple-phase switched-capacitor sub-circuits, which can make the switched-capacitor circuit SC meet a larger charging power on the basis of realizing a high conversion ratio.

[0351] In some embodiments, as shown in FIG. 42B, the seventh transistor Q7A of the third switch network 22A in the first-phase switched-capacitor sub-circuit SCI N and the third transistor Q3B of the second switch network 21B in the second-phase switched-capacitor sub-circuit SC2 N are the same transistor.

[0352] Alternatively, the eighth transistor Q8A of the third switch network 22A in the first-phase switched-capacitor sub-circuit SCI N and the fourth transistor Q4B of the second switch network 21B in the second-phase switched-capacitor sub-circuit SC2 N are the same transistor.

[0353] Alternatively, the seventh transistor Q7B of the third switch network 22B in the second-phase switched-capacitor sub-circuit SC2 N and the third transistor Q3A of the second switch network 21A in the first-phase switched-capacitor sub-circuit SCI N are the same transistor.

[0354] Alternatively, the eighth transistor Q8B of the third switch network 22B in the second-phase switched-capacitor sub-circuit SC2 N and the fourth transistor Q4A of the second switch network 21A in the first-phase switched-capacitor sub-circuit SCI N are the same transistor.

[0355] In this topology, the number of transistors in the switched-capacitor circuit SC can be reduced, and the area occupied by the switched-capacitor circuit SC can be reduced.

[0356] FIGS. 43A and 43B are schematic diagrams of another topology of a switched-capacitor circuit provided by embodiments of the present application.

[0357] In some embodiments, as shown in FIG. 43A, the switched-capacitor circuit SC includes a first-phase switched-capacitor sub-circuit SCI and a second-phase switched-capacitor sub-circuit SC2. The first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 are coupled in parallel in an interleaved manner between the input terminal VI and the first node Al.

[0358] In FIG. 43A, the devices in the first-phase switched-capacitor sub-circuit SCI and the devices in the second-phase switched-capacitor sub-circuit SC2 are distinguished by A and B. The fifth transistor of the Nth-stage second switched-capacitor network 2A in the first-phase switched-capacitor sub-circuit SCI is denoted as "Q5A N ", and the other transistors are denoted in the same way. The structures of the first-phase switched-capacitor sub-circuit SCI and the second-phase switched-capacitor sub-circuit SC2 can refer to the related descriptions of the structure of the first-phase switched-capacitor sub-circuit SCI illustrated in FIG. 41A.

[0359] The switched-capacitor circuit SC includes multiple-phase switched-capacitor sub-circuits, which can make the switched-capacitor circuit SC meet a greater charging power on the basis of realizing a high conversion ratio.

[0360] In some embodiments, as shown in FIG. 43B, the seventh transistor Q7A N of the last-stage third switched-capacitor network 22A in the first-phase switched-capacitor sub-circuit SCI and the third transistor Q3B N of the last-stage second switched-capacitor network 21B in the second-phase switched-capacitor sub-circuit SC2 are the same transistor.

[0361] Alternatively, the eighth transistor Q8A N of the last-stage third switched-capacitor network 22A in the first-phase switched-capacitor sub-circuit SCI and the fourth transistor Q4B N of the last-stage second switched-capacitor network 21B in the second-phase switched-capacitor sub-circuit SC2 are the same transistor.

[0362] Alternatively, the seventh transistor Q7B N of the last-stage third switched-capacitor network 22B in the second-phase switched-capacitor sub-circuit SC2 and the third transistor Q3A N of the last-stage second switched-capacitor network 21A in the first-phase switched-capacitor sub-circuit SCI are the same transistor.

[0363] Alternatively, the eighth transistor Q8B N of the last-stage third switched-capacitor network 22B in the second-phase switched-capacitor sub-circuit SC2 and the fourth transistor Q4A N of the last-stage second switched-capacitor network 21A in the first-phase switched-capacitor sub-circuit SCI are the same transistor.

[0364] The number of transistors in the switch capacitor circuit SC can be reduced and the area occupied by the switch capacitor circuit SC can be reduced.

[0365] FIG. 44 is a schematic diagram of another topology of a switch capacitor circuit according to an embodiment of the present application.

[0366] In some embodiments, as shown in FIG. 44, the switch capacitor circuit SC includes a plurality of groups of first-phase switch capacitor sub-circuits SC1 and second-phase switch capacitor sub-circuits SC2 coupled in staggered parallel between the input terminal VI and the first node A1.

[0367] In this case, the third inductors L3 included in the first-phase switch capacitor sub-circuits SC1 and the second-phase switch capacitor sub-circuits SC2 in each group can be the same or different. The fourth inductors L4 included in the first-phase switch capacitor sub-circuits SC1 and the second-phase switch capacitor sub-circuits SC2 can be the same or different.

[0368] By arranging a plurality of groups of first-phase switch capacitor sub-circuits SC1 and second-phase switch capacitor sub-circuits SC2 in the switch capacitor circuit SC, the ripple of the charging voltage can be reduced and the stability of the charging voltage can be improved.

[0369] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A switched-capacitor circuit, characterized by, The switch capacitor circuit comprises a switch capacitor sub-circuit, an inductive network, an input end and an output end; The switch capacitor sub-circuit comprises a first capacitor, a first-stage switch network and a switch capacitor network, the switch capacitor network comprises a second capacitor, a third capacitor and a second-stage switch network; the first-stage switch network is coupled with the input end and the first capacitor respectively, and is used for adjusting the on-off between the first capacitor and the input end; the second-stage switch network is coupled with the first capacitor, the second capacitor and the third capacitor respectively, and is used for adjusting the series-parallel relationship among the first capacitor, the second capacitor and the third capacitor; The first end of the inductive network is coupled with the switch capacitor network, and the second end of the inductive network is coupled with the output end.

2. The switched-capacitor circuit of claim 1, wherein, The switch capacitor sub-circuit comprises a plurality of switch capacitor networks coupled in series, and the last-stage switch capacitor network is coupled with the first end of the inductive network.

3. The switched-capacitor circuit of claim 1 or 2, wherein, The switch capacitor circuit comprises at least one switch capacitor group, and the switch capacitor group comprises two-phase switch capacitor sub-circuits coupled in interleaved parallel between the input end and the inductive network.

4. The switched-capacitor circuit of claim 3, wherein, The switch capacitor circuit comprises a plurality of switch capacitor groups coupled in parallel between the input end and the inductive network.

5. The switched-capacitor circuit of any of claims 1-4, wherein, The capacitance of the first capacitor is greater than that of the second capacitor, and the capacitance of the second capacitor is equal to that of the third capacitor.

6. The switched-capacitor circuit of claim 5, wherein, The capacitance of the first capacitor is more than twice that of the second capacitor.

7. The switched-capacitor circuit of any of claims 3-6, wherein, The switch capacitor circuit comprises two-phase switch capacitor sub-circuits; The second-stage switch network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The first pole of the first transistor is coupled with the negative pole of the first capacitor, and the second pole of the first transistor is coupled with the first pole of the second transistor and the positive pole of the second capacitor respectively; The second pole of the second transistor is coupled with the first pole of the third transistor and the first end respectively; The second pole of the third transistor is coupled with the negative pole of the second capacitor and the first pole of the fourth transistor respectively; The second pole of the fourth transistor is coupled with a reference ground voltage end; The first pole of the fifth transistor is coupled with the positive pole of the first capacitor, and the second pole of the fifth transistor is coupled with the first pole of the sixth transistor and the positive pole of the third capacitor respectively; The second pole of the sixth transistor is coupled with the first pole of the seventh transistor and the first end respectively; The second pole of the seventh transistor is coupled with the negative pole of the third capacitor and the first pole of the eighth transistor respectively; The second pole of the eighth transistor is coupled with the reference ground voltage end; The seventh transistor in one-phase switch capacitor sub-circuit and the third transistor in another-phase switch capacitor sub-circuit are the same transistor; or, the eighth transistor in one-phase switch capacitor sub-circuit and the fourth transistor in another-phase switch capacitor sub-circuit are the same transistor.

8. The switched-capacitor circuit of claim 2, wherein, The switch capacitor sub-circuit comprises a plurality of levels of the switch capacitor network coupled in series; The second level switch network in each level of the switch capacitor network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; In each level of the switch capacitor network, a first electrode of the fourth transistor is coupled with a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the eighth transistor is coupled with a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled with the reference ground voltage terminal; In the first level of the switch capacitor network, a first electrode of the first transistor is coupled with a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor; in the switch capacitor network except the first level, a first electrode of the first transistor is coupled with a second electrode of the second transistor in the previous level of the switch capacitor network, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor; a first electrode of the fifth transistor is coupled with a second electrode of the sixth transistor in the previous level of the switch capacitor network, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor; In the last level of the switch capacitor network, a second electrode of the second transistor, a first electrode of the third transistor, a second electrode of the sixth transistor and a first electrode of the seventh transistor are all coupled with the output terminal; in the switch capacitor network except the last level, a second electrode of the second transistor is coupled with a first electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled with a first electrode of the third transistor; The seventh transistor of the last level of the switch capacitor network in one phase of the switch capacitor sub-circuit is the same transistor as the third transistor of the last level of the switch capacitor network in another phase of the switch capacitor sub-circuit; or, the eighth transistor of the last level of the switch capacitor network in one phase of the switch capacitor sub-circuit is the same transistor as the fourth transistor of the last level of the switch capacitor network in another phase of the switch capacitor sub-circuit.

9. A driving method of the switched capacitor circuit according to claim 1, 3 or 4, characterized by, The second level switch network comprises a second transistor, a third transistor, a sixth transistor and a seventh transistor; the second transistor and the third transistor are connected in series and are connected in parallel with the second capacitor, and the sixth transistor and the seventh transistor are connected in series and are connected in parallel with the third capacitor; the first capacitor, the second capacitor and the third capacitor have equal capacitance values; the switch capacitor circuit comprises a first phase of the switch capacitor sub-circuit; The driving method comprises: For the first phase of the switch capacitor sub-circuit, In the first mode, the third transistor and the sixth transistor are turned on, and the second transistor and the seventh transistor are turned off; In the second mode, the sixth transistor is turned off, the third transistor is turned on, and the second transistor and the seventh transistor are turned off; In the third mode, the third transistor and the sixth transistor are turned off, and the second transistor and the seventh transistor are turned on; In the fourth mode, the third transistor and the sixth transistor are turned off, the seventh transistor is turned on, and the second transistor is turned off.

10. The driving method of a switched-capacitor circuit according to claim 9, wherein The switched-capacitor circuit comprises two-phase switched-capacitor sub-circuits; the two-phase switched-capacitor sub-circuits operate in a phase difference of 180°.

11. The driving method of a switched-capacitor circuit according to claim 9 or 10, wherein The duty cycles of the first mode and the third mode are 3 / 8 respectively, and the duty cycles of the second mode and the fourth mode are 1 / 8 respectively.

12. The driving method of a switched-capacitor circuit according to claim 9, wherein The switched-capacitor circuit further comprises a second-phase switched-capacitor sub-circuit; For the second-phase switched-capacitor sub-circuit, In the first mode, the second transistor and the seventh transistor are turned on, and the third transistor and the sixth transistor are turned off; In the second mode, the second transistor and the seventh transistor are turned on, and the third transistor and the sixth transistor are turned off; In the third mode, the second transistor and the seventh transistor are turned off, and the third transistor and the sixth transistor are turned on; In the fourth mode, the second transistor and the seventh transistor are turned off, and the third transistor and the sixth transistor are turned on; The driving method further comprises: In the fifth mode, the third transistor and the sixth transistor of the first-phase switched-capacitor sub-circuit are turned on, and the second transistor and the seventh transistor are turned off; The second transistor of the second-phase switched-capacitor sub-circuit is turned off, the seventh transistor is turned on, and the third transistor and the sixth transistor are turned off; In the sixth mode, the third transistor and the sixth transistor of the first-phase switched-capacitor sub-circuit are turned off, and the second transistor and the seventh transistor are turned on; the sixth transistor of the second-phase switched-capacitor sub-circuit is turned off, the third transistor is turned on, and the second transistor and the seventh transistor are turned off.

13. The driving method of a switched-capacitor circuit according to claim 12, wherein The duty cycles of the first mode and the third mode are 3 / 14 respectively, and the duty cycles of the second mode, the fourth mode, the fifth mode, and the sixth mode are 1 / 7 respectively.

14. The method of driving a switched-capacitor circuit according to any one of claims 10-13, wherein, The switched-capacitor circuit comprises n switched-capacitor groups; the switched-capacitor sub-circuits in adjacent switched-capacitor groups operate in a phase difference of 180° / n.

15. A driving method of the switched capacitor circuit according to claim 2, characterized by, The second-stage switch network comprises a second transistor, a third transistor, a sixth transistor, and a seventh transistor; the second transistor and the third transistor are connected in series and are connected in parallel with the second capacitor, and the sixth transistor and the seventh transistor are connected in series and are connected in parallel with the third capacitor; The capacitances of the first capacitor, the second capacitor, and the third capacitor are equal; The driving method comprises: In the first mode, the third transistor and the sixth transistor in the first stage of the switched-capacitor network are turned on, and the second transistor and the seventh transistor are turned off; the adjacent stages of the switched-capacitor network operate in a 180° out of phase manner; and the second transistor and the seventh transistor in the last stage of the switched-capacitor network are turned on, and the third transistor and the sixth transistor are turned off; In the second mode, the third transistor in the first stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off; the adjacent stages of the switched-capacitor network operate in a 180° out of phase manner; and the second transistor and the seventh transistor in the last stage of the switched-capacitor network are turned on, and the third transistor and the sixth transistor are turned off; In the third mode, the second transistor and the seventh transistor in the first stage of the switched-capacitor network are turned on, and the third transistor and the sixth transistor are turned off; the adjacent stages of the switched-capacitor network operate in a 180° out of phase manner; and the third transistor and the sixth transistor in the last stage of the switched-capacitor network are turned on, and the second transistor and the seventh transistor are turned off; In the fourth mode, the seventh transistor in the first stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; the adjacent stages of the switched-capacitor network operate in a 180° out of phase manner; and the third transistor and the sixth transistor in the last stage of the switched-capacitor network are turned on, and the second transistor and the seventh transistor are turned off; In the fifth mode, the third transistor and the sixth transistor in the first stage of the switched-capacitor network are turned on, and the second transistor and the seventh transistor are turned off; the adjacent stages of the switched-capacitor network operate in a 180° out of phase manner; and the seventh transistor in the last stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; In the sixth mode, the second transistor and the seventh transistor in the first stage of the switched-capacitor network are turned on, and the sixth transistor, the third transistor are turned off; the adjacent stages of the switched-capacitor network operate in a 180° out of phase manner; and the third transistor in the last stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off; In the seventh mode, the third transistor in the first stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off; the adjacent stages of the switched-capacitor network operate in a 180° out of phase manner; and the seventh transistor in the last stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; In the eighth mode, the seventh transistor in the first stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the third transistor are turned off; the adjacent stages of the switched-capacitor network operate in a phase difference of 180°; and the third transistor in the last stage of the switched-capacitor network is turned on, and the sixth transistor, the second transistor and the seventh transistor are turned off.

16. The driving method of a switched-capacitor circuit according to claim 15, wherein The duty cycles of the first mode and the third mode are 1 / 4 respectively, the duty cycles of the second mode and the fourth mode are 1 / 8 respectively, the duty cycles of the fifth mode and the sixth mode are 3 / 32 respectively, and the duty cycles of the seventh mode and the eighth mode are 1 / 32 respectively.

17. The driving method of a switched-capacitor circuit according to claim 15 or 16, wherein The switched-capacitor circuit comprises two-phase switched-capacitor sub-circuits; and the two-phase switched-capacitor sub-circuits operate in a phase difference of 180°.

18. The driving method of a switched-capacitor circuit according to claim 17, wherein The switched-capacitor circuit comprises n switched-capacitor groups coupled in parallel; and the switched-capacitor sub-circuits in adjacent switched-capacitor groups operate in a phase difference of 180° / n.

19. A switched-capacitor circuit, comprising: The switched-capacitor circuit comprises at least one switched-capacitor sub-circuit. The switched-capacitor sub-circuit comprises: a first capacitor, a first switch network and a switched-capacitor network; the switched-capacitor network comprises a second capacitor, a third capacitor, a second switch network and a third switch network; the first switch network is coupled with an input terminal and the first capacitor respectively, and is used for adjusting the on-off relationship between the first capacitor and the input terminal; the second switch network is coupled with the first capacitor, the second capacitor and the third capacitor respectively, and is used for adjusting the series-parallel relationship among the first capacitor, the second capacitor and the third capacitor; a first inductor network coupled with the first capacitor in series; a second inductor network coupled with the second capacitor in series; a third inductor network coupled between the second switch network and a first node; a fourth inductor network coupled between the third switch network and the first node; a fifth inductor network coupled between the first node and an output terminal; a sixth inductor network coupled with the third capacitor in series; The switched-capacitor sub-circuit comprises one or more of the first inductor network, the second inductor network, the third inductor network, the fourth inductor network, the fifth inductor network or the sixth inductor network.

20. The switched-capacitor circuit of claim 19, wherein, The switched-capacitor sub-circuit comprises at least two of the first inductor network, the second inductor network, the third inductor network, the fourth inductor network, the fifth inductor network or the sixth inductor network. The switched-capacitor sub-circuit does not simultaneously comprise the second inductor network and the third inductor network. Or, The switched-capacitor sub-circuit does not simultaneously comprise the fourth inductor network and the sixth inductor network.

21. The switched-capacitor circuit of claim 19 or 20, wherein, The switched-capacitor sub-circuit comprises a plurality of stages of the switched-capacitor network coupled in series, and the last stage of the switched-capacitor network is coupled with the first node. The second capacitor of at least one stage of the switched capacitor network is coupled in series with the second inductor network; or the third capacitor of at least one stage of the switched capacitor network is coupled in series with the sixth inductor network.

22. The switched-capacitor circuit of any of claims 19-21, wherein, The switched capacitor circuit comprises at least one switched capacitor group, and the switched capacitor group comprises two-phase switched capacitor sub-circuits; the two-phase switched capacitor sub-circuits are coupled in parallel between the input terminal and the first node.

23. The switched-capacitor circuit of claim 22, wherein, The switched capacitor circuit comprises a plurality of switched capacitor groups coupled in parallel between the input terminal and the first node.

24. The switched-capacitor circuit of claim 22 or 23, wherein, The switched capacitor circuit comprises two-phase switched capacitor sub-circuits; The second switch network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, the third switch network comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The first electrode of the first transistor is coupled with the negative electrode of the first capacitor, and the second electrode of the first transistor is coupled with the first electrode of the second transistor and the positive electrode of the second capacitor, respectively; The second electrode of the second transistor is coupled with the first electrode of the third transistor and the first node, respectively; The second electrode of the third transistor is coupled with the negative electrode of the second capacitor and the first electrode of the fourth transistor, respectively; The second electrode of the fourth transistor is coupled with a reference ground voltage terminal; The first electrode of the fifth transistor is coupled with the positive electrode of the first capacitor, and the second electrode of the fifth transistor is coupled with the first electrode of the sixth transistor and the positive electrode of the third capacitor, respectively; The second electrode of the sixth transistor is coupled with the first electrode of the seventh transistor and the first node, respectively; The second electrode of the seventh transistor is coupled with the negative electrode of the third capacitor and the first electrode of the eighth transistor, respectively; The second electrode of the eighth transistor is coupled with the reference ground voltage terminal; The seventh transistor in one phase of the switched capacitor sub-circuit is the same transistor as the third transistor in another phase of the switched capacitor sub-circuit, and the eighth transistor in one phase of the switched capacitor sub-circuit is the same transistor as the fourth transistor in another phase of the switched capacitor sub-circuit.

25. The switched-capacitor circuit of claim 21, wherein, The switched capacitor sub-circuit comprises a plurality of stages of the switched capacitor network coupled in series; The second stage switch network in each stage of the switched capacitor network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, respectively; In each stage of the switched capacitor network, the first electrode of the fourth transistor is coupled with the second electrode of the third transistor, and the second electrode of the fourth transistor is coupled with a reference ground voltage terminal; the first electrode of the eighth transistor is coupled with the second electrode of the seventh transistor, and the second electrode of the eighth transistor is coupled with the reference ground voltage terminal. In the first stage of the switched capacitor network, a first electrode of the first transistor is coupled to a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled to a first electrode of the second transistor and a positive electrode of the second capacitor, respectively; a first electrode of the fifth transistor is coupled to a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor and a positive electrode of the third capacitor, respectively; in the switched capacitor network except the first stage, the first electrode of the first transistor is coupled to a second electrode of the second transistor in the switched capacitor network of the previous stage, and the second electrode of the first transistor is coupled to the first electrode of the second transistor and the positive electrode of the second capacitor, respectively; the first electrode of the fifth transistor is coupled to a second electrode of the sixth transistor in the switched capacitor network of the previous stage, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the positive electrode of the third capacitor, respectively; In the last stage of the switched capacitor network, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are all coupled to the output terminal; in the switched capacitor network except the last stage, the second electrode of the second transistor is coupled to the first electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled to the first electrode of the third transistor; The seventh transistor of the last stage of the switched capacitor network in one phase of the switched capacitor sub-circuit is the same transistor as the third transistor of the last stage of the switched capacitor network in another phase of the switched capacitor sub-circuit; or, the eighth transistor of the last stage of the switched capacitor network in one phase of the switched capacitor sub-circuit is the same transistor as the fourth transistor of the last stage of the switched capacitor network in another phase of the switched capacitor sub-circuit.

26. An electronic device, comprising: A switched capacitor circuit as claimed in any one of claims 1-8 or 19-25 and a battery, the switched capacitor circuit being coupled to the battery.

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