Packaging structure for chip with backside power delivery, and preparation method therefor

Abstract

Provided in the present invention are a packaging structure for a chip with backside power delivery, and a preparation method therefor. Firstly, a first shielding layer is arranged in a first wiring layer, a second shielding layer is arranged in a second wiring layer, and a metal shielding fence is arranged around a chip unit with backside power delivery, such that a high-density packaging structure with six-sided electromagnetic shielding is formed around the chip unit with backside power delivery, thereby reducing electromagnetic interference in the packaging structure. Secondly, a support substrate is trenched to form a first thermally conductive member, the first thermally conductive member is connected to a thermally conductive wiring layer to form a thermally conductive composite layer, and the thermally conductive composite layer is connected to the first shielding layer, the metal shielding fence and the second shielding layer to form a thermally conductive rail, such that the problem of slow heat dissipation in the packaging structure for a chip with backside power delivery is solved while electromagnetic interference is shielded. In addition, a trench capacitor layer is arranged between the chip unit with backside power delivery and a third wiring layer, such that the integrity of a power source is realized, thereby finally ensuring the stability of chip structure and performance.

Description

Chip package structure with backside power supply and manufacturing method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor packaging, and relates to a chip package structure with backside power supply and a manufacturing method thereof. BACKGROUND

[0002] At present, in traditional 2.5D or 3D advanced packaging, most of the wiring is on the front side of the wafer, and the signal lines and power lines are vertically stacked and connected to form a semiconductor device with two or more layers of active electronic elements of integrated circuits. The chip is supplied with power through these wires to form a power supply network. However, this area also has a signal network. Treating the power supply network as on the front side of the chip means that the chip power supply network and the signal network must share the same element space, and the power supply network often occupies a large space, making it difficult to further reduce the size of the entire packaging structure. At the same time, the power supply network layer is far away from the chip main body. Compared with a two-dimensional system, for a three-dimensional packaging structure with increased chip density, the system may have a high IR drop (e.g., voltage drop), which will cause increased power consumption and reduced device performance. Therefore, the industry has begun to explore the possibility of moving the power supply network to the back, so that backside PDN has become a hot technical topic.

[0003] In the multi-backside power supply chip packaging technology, heat is difficult to dissipate in the multi-backside packaging structure, which can easily cause irreversible damage to the chip, thereby affecting the stability of the chip structure and performance. In addition, in the existing multi-backside power supply chip packaging structure, the integration and miniaturization of components also develop rapidly with the rapid development of packaging technology. The integration and miniaturization of these components can easily cause electrical properties or electromagnetic interference of the device through electromagnetic radiation, thereby causing problems with the chip structure and performance and causing malfunctions.

[0004] Therefore, how to provide a chip package structure with backside power supply and a manufacturing method thereof to solve the problem of instability of structure and performance of the existing backside power supply chip package structure due to high temperature and electromagnetic interference has become an important technical problem to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and for the convenience of understanding by those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art merely because it is described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the present application aims to provide a backside power supply chip packaging structure and a manufacturing method thereof, which are used to solve the problems of structural instability and performance instability of the backside power supply chip packaging structure caused by high temperature and electromagnetic interference in the prior art.

[0007] To achieve the above-mentioned objects and other related objects, the present application provides a manufacturing method of a backside power supply chip packaging structure, which comprises the following steps:

[0008] A support substrate is provided, which has opposite first and second surfaces. A first heat-conducting hole is formed on the first surface of the support substrate, and a first heat-conducting member is formed to fill the first heat-conducting hole;

[0009] A heat-conducting wiring layer is formed on the first surface of the support substrate, which is in contact with the first heat-conducting member. The heat-conducting wiring layer and the first heat-conducting member constitute a heat-conducting combined layer.

[0010] A first wiring layer is formed on the heat-conducting wiring layer, which comprises a first shielding layer and a first metal wiring. The first shielding layer is in contact with the heat-conducting wiring in the heat-conducting wiring layer, and the first shielding layer is not connected with the first metal wiring.

[0011] A metal shielding fence is formed on the surface of the first wiring layer, which is in a closed shape and is not connected with the first metal wiring.

[0012] A plurality of backside power supply chip units are provided, which comprise power supply connection layers and signal connection layers on opposite surfaces. The plurality of backside power supply chip units are bonded on the first wiring layer along the transverse direction through the signal connection layers and are electrically connected with the first metal wiring. The backside power supply chip units are located inside the metal shielding fence.

[0013] A plastic encapsulation layer is formed on the first wiring layer, which encapsulates the backside power supply chip units and exposes the metal shielding fence and the power supply connection layers.

[0014] A trench combined layer is provided, which comprises a trench capacitor layer and a second wiring layer electrically connected. The trench capacitor layer comprises a plurality of trench capacitor units and a plurality of metal columns. The second wiring layer comprises a second metal wiring and a second shielding layer, and the second shielding layer is not connected with the second metal wiring.

[0015] The trench combined layer is bonded on the plastic encapsulation layer, and the second metal wiring is electrically connected with the power supply connection layers.

[0016] Thin the trench capacitor layer to expose the metal column, and form a third wiring layer on the trench capacitor layer, the third wiring layer being electrically connected with the metal column through a third metal wiring.

[0017] Optionally, a metal bump is further formed on the third wiring layer, and the metal bump is electrically connected with the third metal wiring.

[0018] Optionally, the metal shielding bar is formed by opening a position after patterning photoresist; and the cross-sectional morphology of the metal shielding bar is rectangular.

[0019] Optionally, in the trench capacitor layer, the depth of the metal column is greater than the depth of the trench capacitor unit.

[0020] The application further provides another preparation method of a back-side power supply chip package structure, comprising the following steps:

[0021] An intermediate substrate is provided, the intermediate substrate having opposite first and second surfaces, a trench capacitor and a metal column being formed in the intermediate substrate from the first surface to the second surface of the intermediate substrate as a trench capacitor layer;

[0022] A second wiring layer is formed on the trench capacitor layer, a second metal wiring in the second wiring layer being electrically connected with the metal column, and a second shielding layer being provided in the second wiring layer independently of the second metal wiring;

[0023] A metal shielding bar is formed on the second wiring layer, the metal shielding bar being in a closed shape and not connected with the second metal wiring;

[0024] A plurality of back-side power supply chip units are provided, the back-side power supply chip units comprising power supply connection layers and signal connection layers on opposite surfaces, and the plurality of back-side power supply chip units being bonded on the second wiring layer in a lateral direction through the power supply connection layers and being electrically connected with the second metal wiring, and the back-side power supply chip units being located inside the metal shielding bar;

[0025] A plastic encapsulation layer is formed on the second wiring layer, the plastic encapsulation layer encapsulating the back-side power supply chip units and exposing the metal shielding bar and the signal connection layers;

[0026] A first wiring layer is formed on the plastic encapsulation layer, the first wiring layer comprising a first shielding layer and a first metal wiring, the first metal wiring being electrically connected with the signal connection layers; and the first shielding layer being not connected with the first metal wiring.

[0027] A heat-conductive combination layer is provided, which comprises a support substrate containing a first heat-conductive member and a heat-conductive wiring layer stacked together, and the first heat-conductive member is in contact with the heat-conductive wiring layer;

[0028] The heat-conductive combination layer is bonded to the first wiring layer, and the heat-conductive wiring layer is in contact with the first shielding layer;

[0029] The intermediate substrate is thinned to expose the metal column, a third wiring layer is formed on the second surface of the intermediate substrate, and the third wiring layer is electrically connected to the metal column through a third metal wiring;

[0030] A metal bump is formed on the third wiring layer, and the metal bump is electrically connected to the third metal wiring.

[0031] Optionally, a metal heat-conductive column is arranged inside the metal shielding bar, one end of the metal heat-conductive column is connected to the second shielding layer, and the other end is connected to the first shielding layer.

[0032] Optionally, the second shielding layer, the metal shielding bar, the first shielding layer and the heat-conductive combination layer are connected to form a heat-conductive track.

[0033] In addition, the application also provides a back-side power supply chip packaging structure, which comprises:

[0034] A support substrate has opposite first and second surfaces;

[0035] A first heat-conductive member is located in the support substrate, and the first heat-conductive member extends inward from the first surface of the support substrate;

[0036] A heat-conductive wiring layer is located on the first surface of the support substrate, the heat-conductive wiring of the heat-conductive wiring layer is in contact with the first heat-conductive member, and the heat-conductive wiring layer and the first heat-conductive member form a heat-conductive combination layer;

[0037] A first wiring layer is located above the heat-conductive wiring layer, the first wiring layer comprises a first shielding layer and a first metal wiring, and the first shielding layer is in contact with the heat-conductive wiring layer; the first metal wiring is not connected to the first shielding layer;

[0038] A metal shielding bar is located on the surface of the first wiring layer, and is not connected to the first metal wiring;

[0039] A plurality of back side powered chip units, the back side powered chip units comprising power connection layers and signal connection layers on opposite sides; a plurality of the back side powered chip units are electrically connected with the first wiring layer through the signal connection layers, and the back side powered chip units are located inside the metal shielding fence;

[0040] A plastic sealing layer is located on the first wiring layer, the plastic sealing layer covers the back side powered chip units, and the metal shielding fence and the power connection layers are exposed;

[0041] A groove combination layer, the groove combination layer comprising a groove capacitor layer and a second wiring layer, and the second wiring layer is electrically connected with the power connection layers through second metal wiring; the groove capacitor layer comprises a plurality of groove capacitor units and a plurality of metal columns; the second wiring layer comprises second metal wiring and a second shielding layer, and the second shielding layer is not connected with the second metal wiring;

[0042] A third wiring layer, the third wiring layer is located above the groove capacitor layer, and the third wiring layer is electrically connected with the metal columns;

[0043] Metal bumps, the metal bumps are located above the third wiring layer, and the metal bumps are electrically connected with third metal wiring in the third wiring layer.

[0044] Optionally, the intermediate shielding layer is not connected with the first shielding layer and the second shielding layer, or is connected with one or both of them.

[0045] Optionally, in the groove combination layer, the second wiring layer is electrically connected with the metal columns in the groove capacitor layer through the second metal wiring.

[0046] As described above, the present application provides a back side powered chip packaging structure and a preparation method thereof. First, a first shielding layer is arranged on a first wiring layer, a second shielding layer is arranged in a second wiring layer, and a metal shielding fence is arranged around a back side powered chip, so that a hexahedral electromagnetic shielding high-density packaging structure is formed around the back side powered chip, and electromagnetic interference in the packaging structure is reduced. Second, a first heat conduction member is formed by grooving a support substrate and connecting a heat conduction wiring layer to form a heat conduction combination layer, and the heat conduction combination layer is connected with the first shielding layer, the metal shielding fence and the second shielding layer to form a heat conduction track, which shields electromagnetic interference and solves the problem of slow heat dissipation in the back side powered chip packaging structure. In addition, a groove capacitor layer is arranged between the back side powered chip unit and the third wiring layer, which realizes the integrity of the power supply, thereby finally ensuring the stability of the chip structure and performance. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 shows a flow chart of the process for fabricating the backside power supply chip package structure of the first embodiment of the present application.

[0048] Figure 2 shows a schematic diagram of the structure after forming the first heat conducting member in the support substrate of the first and second embodiments of the present application.

[0049] Figure 3 shows a schematic diagram of the structure after forming the heat conducting wiring layer on the first surface of the support substrate of the first and second embodiments of the present application.

[0050] Figure 4 shows a schematic diagram of the structure after forming the first wiring layer on the heat conducting wiring layer of the first embodiment of the present application.

[0051] Figure 5 shows a schematic diagram of the structure after forming the metal shielding bar on the first wiring layer of the first embodiment of the present application.

[0052] Figure 6 shows a schematic diagram of the cross section of the metal shielding bar of the first embodiment of the present application.

[0053] Figure 7 shows a schematic diagram of the structure after bonding the plurality of backside power supply chip units to the first wiring layer of the first embodiment of the present application.

[0054] Figure 8 shows a schematic diagram of the structure of the backside power supply chip unit of the first embodiment of the present application.

[0055] Figure 9 shows a schematic diagram of the structure after forming the plastic encapsulation layer on the first wiring layer of the first embodiment of the present application.

[0056] Figure 10a shows a schematic diagram of the structure after forming the trench capacitor layer in the intermediate substrate of the first and second embodiments of the present application.

[0057] Figure 10b shows a schematic diagram of the structure after forming the second wiring layer on the trench capacitor layer of the first and second embodiments of the present application.

[0058] Figure 11 shows a schematic diagram of the structure after forming the trench combination layer on the plastic encapsulation layer of the first embodiment of the present application.

[0059] Figure 12 shows a schematic diagram of the structure after forming the third wiring layer on the thinned trench combination layer of the first and second embodiments of the present application.

[0060] Figure 13 shows a schematic diagram of the structure after forming the metal bump on the third wiring layer of the first and second embodiments of the present application.

[0061] Figure 14 shows a schematic diagram of the structure after forming the heat conducting metal pillar in the metal shielding bar of the first embodiment of the present application.

[0062] Figure 15 shows a flow chart of the process for fabricating the backside power supply chip package structure of the second embodiment of the present application.

[0063] Figure 16 shows a schematic diagram of the structure after forming a metal shielding bar on the second wiring layer in the second embodiment of the present application.

[0064] Figure 17 shows a schematic diagram of the structure after bonding a plurality of backside powered chip units to the second wiring layer in the second embodiment of the present application.

[0065] Figure 18 shows a schematic diagram of the structure after forming a plastic encapsulation layer on the second wiring layer in the second embodiment of the present application.

[0066] Figure 19 shows a schematic diagram of the structure after forming a first wiring layer on the plastic encapsulation layer in the second embodiment of the present application.

[0067] Figure 20 shows a schematic diagram of the structure after bonding a heat conducting combination layer to the first wiring layer in the second embodiment of the present application.

[0068] Explanation of Reference Numerals 100 Support Substrate 110 First Heat Conductive Member 200 Heat Conductive Wiring Layer 201 Heat Conductive Wiring 202 Heat Conductive Medium 300 First Wiring Layer 301 First Metal Wiring 302 First Medium 303 First Shielding Layer 400 Encapsulation Layer 410 Backside Powered Chip Unit 412 Power Supply Connection Layer 413 Silicon Substrate Layer 414 Buried Power Layer 415 Dielectric Layer 416 Signal Connection Layer 420 Metal Shielding Bar 421 Heat Conductive Metal Column 500 Second Wiring Layer 501 Second Metal Wiring 502 Second Medium 503 Second Shielding Layer 600 Metal Bump 700 Trench Capacitor Layer 701 Intermediate Substrate 702 Metal Column 703 Trench Capacitor Unit 800 Third Wiring Layer 801 Third Metal Wiring 802 Third Medium DETAILED DESCRIPTION

[0069] Following, the advantages and effects of the present application will be described in detail by specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the present specification. The present application can also be implemented or applied by other different specific embodiments, and various modifications or changes can be made to the details in the present specification based on different views and applications without departing from the spirit of the present application.

[0070] As described in the detailed description of the embodiments of the present application, the cross-sectional views showing the device structure are partially enlarged without the general scale for the convenience of description, and the schematic views are only examples which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual fabrication.

[0071] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature with other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings, which can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features are formed between the first and second features, so that the first and second features can not be in direct contact, and in addition, when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0072] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, not drawn according to the number, shape and size of the components in actual implementation, the type, number and proportion of each component in actual implementation can be arbitrarily changed, and the component layout pattern can also be more complex.

[0073] Embodiment One

[0074] Referring to FIGS. 1-14, the embodiment provides a preparation method of a backside power supply chip packaging structure, wherein FIGS. 2-14 schematically show the structure diagrams presented at each step in the preparation of the backside power supply chip packaging structure. The preparation of the backside power supply chip packaging structure will be introduced in combination with the drawings in the specification.

[0075] First, referring to FIGS. 1 and 2, step S1-1 is performed to provide a support substrate 100 having opposite first and second surfaces, a first heat conduction hole is formed on the first surface of the support substrate 100, and a first heat conduction member 110 filling the first heat conduction hole is formed.

[0076] Specifically, the support substrate 100 can include a glass substrate, a metal substrate, a semiconductor substrate, etc. to provide support for subsequent processes. The size of the support substrate 100 is not limited here, and is preferably wafer level.

[0077] Further, the first heat-conducting member 110 extends inwardly from the first surface of the support substrate 100, and the cross-sectional shape of the first heat-conducting hole is square. In some other embodiments, the cross-sectional shape of the heat-conducting hole can also be conical. The size of the first heat-conducting hole is not limited here.

[0078] Further, the filling material in the first heat-conducting hole is a heat-conducting material and is not limited to one of copper, aluminum, nickel, gold, silver or titanium.

[0079] As an example, the slotting method of the first heat-conducting hole is not limited to one of mechanical slotting, laser etching, plasma etching, and can be selected as needed.

[0080] In some other embodiments, the second surface of the support substrate 100 can also form a second heat-conducting hole, and a second heat-conducting member filling the second heat-conducting hole, and the cross-sectional shape of the second heat-conducting hole can be square or conical.

[0081] Next, referring to FIGS. 1 and 3, step S1-2 is performed to form a heat-conducting wiring layer 200 on the first surface of the support substrate 100, the heat-conducting wiring 201 being in contact with the first heat-conducting member 110, and the heat-conducting wiring layer 200 and the first heat-conducting member 110 constituting a heat-conducting combined layer.

[0082] Specifically, the heat-conducting wiring layer 200 includes heat-conducting wiring 201 and heat-conducting medium 202. The heat-conducting wiring layer 200 is formed based on a damascene process, the heat-conducting wiring 201 of the heat-conducting wiring layer 200 being a heat-conducting material and not being limited to one of copper, aluminum, nickel, gold, silver or titanium. The heat-conducting medium 202 can be formed of a polymer such as polybenzoxazole (PBO) or polyimide, or an inorganic dielectric material such as silicon nitride or silicon oxide; the specific structure and material selection of the heat-conducting wiring layer 200 are not limited here.

[0083] Next, referring to FIGS. 1 and 4, step S1-3 is performed to form a first wiring layer 300 on the heat-conducting wiring layer 200; the first wiring layer 300 includes a first shielding layer 303 and a first metal wiring 301, the first shielding layer 303 being in contact with the heat-conducting wiring 201 in the heat-conducting wiring layer 200, and the first shielding layer 303 and the first metal wiring 301 being not connected.

[0084] Specifically, the first wiring layer 300 is formed based on a damascene process. The first wiring layer 300 includes a first metal wiring 301, a first dielectric 302, and a first shielding layer 303.

[0085] The first dielectric 302 can be one or a combination of silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO, and BCB, and the first metal wiring 301 can include one or a combination of a copper layer, an aluminum layer, a nickel layer, a gold layer, and a silver layer. The first shielding layer 303 can include one or a combination of a copper layer, an aluminum layer, a nickel layer, a gold layer, and a silver layer. The material, the number of wiring layers, and the distribution of the first wiring layer 300 are not limited here and can be selected as needed.

[0086] Next, referring to FIGS. 1 and 5, a step S1-4 is performed to form a metal shielding fence 420 on the surface of the first wiring layer 300. The metal shielding fence 420 is in a closed shape and is not connected to the first metal wiring 301.

[0087] Specifically, the metal shielding fence 420 is formed by opening a position after patterning photoresist. Further, first, a pattern of the metal shielding fence is formed by an exposure process after covering the photoresist, second, a metal shielding fence structure is formed by electroplating a metal layer, and finally, the photoresist is removed to form the metal shielding fence 420. In some other embodiments, the metal shielding fence 420 can also be formed by deposition etching, which is not described here.

[0088] As an example, referring to FIG. 6, the cross-sectional shape of the metal shielding fence 420 is a plurality of rectangles. In some other embodiments, the cross-sectional shape of the metal shielding fence 420 can also be a plurality of circles or other shapes, which are not described here.

[0089] Next, referring to FIGS. 1 and 7, a step S1-5 is performed to provide a plurality of backside power supply chip units 410. Referring to FIG. 8, the backside power supply chip unit 410 includes a power supply connection layer 412 and a signal connection layer 416 on opposite sides. The plurality of backside power supply chip units 410 are transversely bonded to the first metal wiring 301 through the signal connection layer 416 and are electrically connected to the first metal wiring 301. The backside power supply chip unit 410 is located inside the metal shielding fence 420.

[0090] Specifically, referring to FIG. 8, the backside power supply chip unit 410 includes a power supply connection layer 412, a silicon substrate layer 413, a buried power layer 414, a dielectric layer 415, and a signal connection layer 416. The signal connection layers 416 of the plurality of backside power supply chip units 410 are interconnected through the first metal wiring 301.

[0091] Then, referring to FIG. 9, a plastic encapsulation layer 400 is formed on the first wiring layer 300 in step S1-6, the plastic encapsulation layer 400 encapsulates the backside powered chip unit 410, and exposes the metal shielding bar 420 and the power supply connection layer 412.

[0092] Specifically, the plastic encapsulation layer 400 is usually obtained by forming a plastic encapsulation layer first and then thinning. The plastic encapsulation layer 400 can be realized by one of transfer molding or compression molding. Since compression molding does not need to transfer the molding layer material such as epoxy resin to a very far place, but directly places the chip vertically downward on the molding layer material, thus reducing defects such as voids and extension phenomenon, therefore, the plastic encapsulation layer of the embodiment is preferably realized by compression molding. The thinning method of the plastic encapsulation layer 400 can adopt chemical mechanical polishing (CMP), etching method, etc., which will not be described here.

[0093] For example, the plastic encapsulation layer 400 can include one or a combination of a polyimide layer, a silica gel layer, and an epoxy resin layer.

[0094] Then, referring to FIG. 10a and FIG. 10b, a trench combination layer including a point-connected trench capacitor layer 700 and a second wiring layer 500 is provided in step S1-7; the trench capacitor layer 700 includes a plurality of trench capacitor units 703 and a plurality of metal columns 702. The second wiring layer 500 includes a second metal wiring 501 and a second shielding layer 503, and the second shielding layer 503 is not connected with the second metal wiring 501.

[0095] Specifically, the trench capacitor layer 700 further includes an intermediate substrate 701; the metal column 702 and the trench capacitor unit 703 extend into the intermediate substrate 701, and the depth of the metal column 702 is greater than the depth of the trench capacitor unit 703; the second wiring layer 500 further includes a second dielectric 502; the second wiring layer 500 is electrically connected with the trench capacitor layer 700. In some other embodiments, the capacitor unit can also wrap 2 or more layers of trench electrodes and 2 or more layers of capacitor dielectric layers.

[0096] Further, the second dielectric 502 can adopt one or a combination of silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO, and BCB; the second metal wiring 501 can include one or a combination of copper layer, aluminum layer, nickel layer, gold layer, and silver layer. The second shielding layer 503 can include one or a combination of copper layer, aluminum layer, nickel layer, gold layer, and silver layer. The material, wiring layer number and wiring distribution of the second wiring layer 500 are not limited here, and can be selected as needed.

[0097] Then, referring to Fig. 11, the trench combination layer is bonded on the plastic package layer 400, and the second metal wiring 501 is electrically connected with the power supply connection layer 412, in step S1-8.

[0098] For example, the metal shielding bar 420 is connected with the first shielding layer 303 and the second shielding layer 503; in some other embodiments, the metal shielding bar 420 is only connected with the first shielding layer 303; in another embodiment, the metal shielding bar 420 is not connected with the first shielding layer 303 and the second shielding layer 503.

[0099] For example, the second shielding layer 503, the metal shielding bar 420, the first shielding layer 303 and the heat conduction combination layer are connected to form a heat conduction track; in some other embodiments, referring to Fig. 14, a heat conduction metal column 421 can be arranged in the metal shielding bar 420 to connect the first shielding layer 303 and the second shielding layer 503 to form a heat conduction track. The heat conduction metal column 421 is arranged in the metal shielding bar 420 according to actual needs.

[0100] Further, in order to make the heat of the back power supply chip unit 410 dissipate in time, the heat conduction track transmits the heat, first, the heat is transmitted from the second shielding layer 503 to the metal shielding bar 420, and then to the first shielding layer 303, and finally to the heat conduction combination layer composed of the heat conduction wiring layer 200 and the first heat conduction member 110, so that the heat can dissipate in time.

[0101] At this point, the first shielding layer 303 is arranged on the first wiring layer 300, the second shielding layer 503 is arranged on the second wiring layer 500, and the metal shielding bar 420 is arranged around the back power supply chip unit 410, so that a hexahedral electromagnetic shielding high-density packaging structure is formed around the back power supply chip unit 410, and the electromagnetic interference in the packaging structure is reduced.

[0102] Then, referring to Fig. 12, the trench capacitor layer 700 is thinned to expose the metal column 702, and a third wiring layer 800 is formed on the trench capacitor layer 700, and the third wiring layer 800 is electrically connected with the metal column 702 through a third metal wiring 801, in step S1-9.

[0103] Specifically, the thinning method of the trench capacitor layer 700 can adopt chemical mechanical polishing (CMP), etching method, etc., and the thinning process exposes the metal column 702, but does not expose the trench capacitor unit 703.

[0104] Further, the third wiring layer 800 includes a third dielectric 802 and the third metal wiring 801. The third dielectric 802 can be one or a combination of, for example, silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO, and BCB, and the third metal wiring 801 can include one or a combination of, for example, a copper layer, an aluminum layer, a nickel layer, a gold layer, and a silver layer. The material, the number of wiring layers, and the distribution of the wiring of the third wiring layer 800 are not limited here and can be selected as needed.

[0105] Further, a metal bump 600 can be formed on the third wiring layer 800, as shown in FIG. 13, and the metal bump 600 is electrically connected to the third metal wiring 801 in the third wiring layer 800.

[0106] The metal bump 600 can include, for example, a solder bump, a C4 metal bump, a columnar bump, and the like, and the material of the metal bump 600 can be one of copper, aluminum, nickel, gold, silver, and titanium. The specific type of the metal bump 600 is not limited here.

[0107] In the preparation method of the back-side powered chip packaging structure in this embodiment, the first shielding layer 303 is arranged on the first wiring layer 300, the second shielding layer 503 is arranged in the second wiring layer 500, and the metal shielding fence 420 is arranged around the back-side powered chip unit 410, so that a hexahedral electromagnetic shielding high-density packaging structure is formed around the back-side powered chip unit 410, and the electromagnetic interference in the packaging structure is reduced. Secondly, the first heat-conducting member 110 is connected to the heat-conducting wiring layer 200 to form a heat-conducting system, and the heat dissipation effect is increased. The heat-conducting combination layer is connected to the metal shielding fence 420, the first shielding layer 303, and the second shielding layer 503 to form a heat-conducting track. While shielding electromagnetic interference, the problem of slow heat dissipation in the back-side powered chip packaging structure is solved. In addition, the trench combination layer is arranged between the back-side powered chip unit 410 and the third wiring layer 500, and the integrity of the power supply is realized, so as to finally ensure the stability of the chip structure and performance.

[0108] Embodiment Two

[0109] This embodiment provides another preparation method of a back-side powered chip packaging structure. Different from the first embodiment, the first embodiment first forms a heat-conducting combination layer, then arranges wiring on the basis of the heat-conducting combination layer, and then bonds the back-side powered chip unit. This embodiment first forms a trench capacitor layer, then bonds the back-side powered chip unit on the basis of the trench capacitor layer, and then connects the back-side powered chip and the wiring layer through the heat-conducting combination layer. The preparation of the back-side powered chip packaging structure in this embodiment is described below in combination with the accompanying drawings.

[0110] First, referring to FIG. 15 and FIG. 10a, step S2-1 is performed to provide an intermediate substrate 701 having opposite first and second surfaces, and a trench capacitor unit 703 and a metal pillar 702 are formed in the intermediate substrate 701 from the first surface to the second surface of the intermediate substrate 701 as a trench capacitor layer 700.

[0111] Specifically, the depth of the metal pillar 702 is greater than the depth of the trench capacitor unit 703.

[0112] Next, referring to FIG. 15 and FIG. 10b, step S2-2 is performed to form a second wiring layer 500 on the trench capacitor layer 700, and a second metal wiring 501 in the second wiring layer 500 is electrically connected to the metal pillar 702, and the second wiring layer 500 is provided with a second shielding layer 503 independent of the second metal wiring 501.

[0113] Specifically, the second wiring layer 500 is electrically connected to the metal pillar 702 in the trench capacitor layer 700 through the second metal wiring 501.

[0114] Next, referring to FIG. 15 and FIG. 16, step S2-3 is performed to form a metal shielding fence 420 on the second wiring layer 500, and the metal shielding fence 420 is in a closed shape and is not connected to the second metal wiring 501.

[0115] Specifically, the metal shielding fence 420 is formed by forming an opening position after patterning photoresist; further, first, after covering with photoresist, a pattern of the metal shielding fence is formed through an exposure process, and second, after electroplating metal, the photoresist is removed to form the metal shielding fence 420. In some other embodiments, the metal shielding fence 420 can also be formed by deposition etching, which will not be described here.

[0116] Next, referring to FIG. 15 and FIG. 17, step S2-4 is performed to provide a plurality of backside powered chip units 410, the backside powered chip units 410 include power connection layers 412 and signal connection layers 416 on opposite surfaces, and a plurality of the backside powered chip units 410 are bonded on the second wiring layer 500 in the lateral direction through the power connection layers 412 and are electrically connected to the second metal wiring 501, and the backside powered chip units 410 are located inside the metal shielding fence 420.

[0117] Specifically, referring to FIG. 8, the back-powered chip unit 410 includes the power connection layer 412, a silicon substrate layer 413, a buried power layer 414, a dielectric layer 415, and the signal connection layer 416, and the signal connection layer 416 is interconnected by the first metal wiring 301.

[0118] Next, referring to FIG. 15 and FIG. 18, step S2-5 is performed to form a plastic encapsulation layer 400 on the second wiring layer 500, the plastic encapsulation layer 400 encapsulating the back-powered chip unit 410 and exposing the metal shielding bar 420 and the signal connection layer 416.

[0119] Next, referring to FIG. 15 and FIG. 19, step S2-6 is performed to form a first wiring layer 300 on the plastic encapsulation layer 400, the first wiring layer 300 including a first shielding layer 303 and a first metal wiring 301, the first metal wiring being electrically connected to the signal connection layer 416; the first shielding layer 303 is not connected to the first metal wiring 301.

[0120] Specifically, the first wiring layer 300 further includes a first dielectric 302, and the first wiring layer 300 is formed based on a Damascene process.

[0121] For example, the metal shielding bar 420 is connected to the first shielding layer 303 and the second shielding layer 503; in some other embodiments, the metal shielding bar 420 is only connected to the first shielding layer 303; in another embodiment, the metal shielding bar 420 is independent of the first shielding layer 303 and the second shielding layer 503.

[0122] Next, referring to FIG. 15 and FIG. 2 and FIG. 3, step S2-7 is performed to provide a heat-conductive combination layer, the heat-conductive combination layer including a support substrate 100 containing a first heat-conductive member 110 and a heat-conductive wiring layer 200 stacked together, and the first heat-conductive member 110 being in contact with the heat-conductive wiring layer 200.

[0123] Specifically, the support substrate 100 is divided into a first surface and a second surface, a first heat-conductive hole is formed on the first surface of the support substrate 100, and a first heat-conductive member 110 is formed to fill the first heat-conductive hole. A heat-conductive wiring layer 200 is formed on the first surface of the support substrate 100.

[0124] Further, the heat-conductive wiring layer 200 includes a heat-conductive wiring 201 and a heat-conductive dielectric 202. The heat-conductive wiring layer 200 is formed based on a Damascene process.

[0125] Then, referring to FIG. 15 and FIG. 20, the heat-conducting combination layer is bonded to the first wiring layer 300, and the heat-conducting wiring layer 200 is in contact with the first shielding layer 303, in step S2-8.

[0126] Then, referring to FIG. 15 and FIG. 12, the trench capacitor layer 700 is thinned to expose the metal column 702, and a third wiring layer 800 is formed on the trench capacitor groove 700, in step S2-9, and the third wiring layer 800 is electrically connected to the metal column 702 through a third metal wiring 801.

[0127] Specifically, the thinning method of the trench capacitor layer 700 can adopt chemical mechanical grinding (CMP), etching, etc., and the thinning process exposes the metal column 702 but not the trench capacitor unit 703.

[0128] Then, referring to FIG. 15 and FIG. 13, a metal bump 600 is formed on the third wiring layer 800, and the metal bump 600 is electrically connected to the third metal wiring 801, in step S2-10.

[0129] The metal bump 600 can include solder bump, C4 metal bump, columnar bump, etc., and the material of the metal bump 600 can be one of copper, aluminum, nickel, gold, silver or titanium, and the specific type of the metal bump 600 is not limited here.

[0130] The metal wiring and dielectric corresponding to the first wiring layer 300, the second wiring layer 500 and the third wiring layer 800 in this embodiment are mentioned in example one, and will not be repeated here.

[0131] The material of the plastic sealing layer 400 in this embodiment is mentioned in example one, and will not be repeated here.

[0132] The filling material in the first heat-conducting member 110 in this embodiment is mentioned in example one, and will not be repeated here.

[0133] In the present embodiment, the preparation method of the back power supply chip package structure is different from that of embodiment one. First, the trench capacitor layer 700 is formed, then the second wiring layer 500, the metal shielding bar 420 and the back power supply chip unit 410 are formed on the trench capacitor layer 700, then the plastic sealing layer 400 is formed above the second wiring layer 500, then the first wiring layer 300 is formed, then the heat-conducting combined layer is formed above the first wiring layer 300, and then the third wiring layer 800 is formed on the second surface of the trench capacitor layer 700. Thus, the metal shielding bar 420, the first shielding layer 303 and the second shielding layer 503 are arranged around the back power supply chip unit 410, so that a hexahedral electromagnetic shielding high-density package structure is formed around the back power supply chip unit 410, and the electromagnetic interference in the package structure is reduced. Secondly, the heat-conducting combined layer, the metal shielding bar 420, the first shielding layer 303 and the second shielding layer 503 are connected to form a heat-conducting track. While shielding electromagnetic interference, the problem of slow heat dissipation in the back power supply chip package structure is solved. In addition, the trench combined layer is arranged between the back power supply chip unit 410 and the third wiring layer 800, so that the integrity of the power supply is realized, thereby finally ensuring the stability of the chip structure and performance.

[0134] Embodiment three

[0135] The present embodiment also provides a back power supply chip package structure, which is made by the manufacturing method of embodiment one or embodiment two or other suitable similar method. The preparation method, material and structure of the back power supply chip package structure can be referred to embodiment one and embodiment two. Referring to FIG. 13, a cross-sectional structure of the package structure is shown, wherein the back power supply chip package structure comprises:

[0136] A support substrate 100 having opposite first and second surfaces.

[0137] A first heat-conducting member 110 located in the support substrate 100 and extending inwardly from the first surface of the support substrate 100.

[0138] A heat-conducting wiring layer 200 located on the first surface of the support substrate 100, wherein the heat-conducting wiring 201 of the heat-conducting wiring layer 200 is in contact with the first heat-conducting member 110, and the heat-conducting wiring layer 200 and the first heat-conducting member 110 form a heat-conducting combined layer.

[0139] A first wiring layer 300 is located above the heat-conductive wiring layer 200, the first wiring layer 300 includes a first shielding layer 303 and a first metal wiring 301, and the first shielding layer 303 is in contact with the heat-conductive wiring layer 200; the first metal wiring 301 is not connected with the first shielding layer 303.

[0140] A metal shielding bar 420 is located on the surface of the first wiring layer 300 and is not connected with the first metal wiring 301.

[0141] A plurality of back-side powered chip units 410 includes power supply connection layers 412 and signal connection layers 416 located on opposite sides; the plurality of back-side powered chip units 410 are electrically connected with the first wiring layer 300 through the signal connection layers 416, and the back-side powered chip units 410 are located inside the metal shielding bar 420.

[0142] A plastic sealing layer 400 is located on the first wiring layer 300, the plastic sealing layer 400 covers the back-side powered chip units 410, and the metal shielding bar 420 and the power supply connection layers 412 are exposed.

[0143] A groove combination layer includes a groove capacitor layer 700 and a second wiring layer 500, and the second wiring layer 500 is electrically connected with the power supply connection layers 412 through a second metal wiring 501; the groove capacitor layer 700 includes a plurality of groove capacitor units 703 and a plurality of metal columns 702. The second wiring layer 500 includes a second metal wiring 501 and a second shielding layer 503, and the second shielding layer 503 is not connected with the second metal wiring 501.

[0144] A third wiring layer 800 is located above the groove capacitor layer 700, and the third wiring layer 800 is electrically connected with the metal columns 702.

[0145] A metal bump 600 is located above the third wiring layer 800, and the metal bump 600 is electrically connected with a third metal wiring 801 in the third wiring layer 800.

[0146] As an example, the second shielding layer 503, the metal shielding bar 420, the first shielding bar 303, and the heat-conductive combination layer are connected to form a heat-conductive track.

[0147] As an example, the second surface of the support substrate 100 can further include a second heat-conductive member filling the second heat-conductive hole.

[0148] As an example, the cross-sectional profile of the first thermal conductive via in the support substrate 100 is square. In some other embodiments, the cross-sectional profile of the first thermal conductive via can also be conical, which is not limited here.

[0149] As an example, the thermal conductive wiring layer 200 includes a thermal conductive wiring 201 and a thermal conductive medium 202. The thermal conductive wiring layer 200 is formed based on a damascene process, the thermal conductive wiring 201 of the thermal conductive wiring layer 200 is a material that is thermally conductive and is not limited to one of copper, aluminum, nickel, gold, silver or titanium. The thermal conductive medium 202 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the specific structure and material selection of the thermal conductive wiring layer 200 is not limited here.

[0150] As an example, the first wiring layer 300 is formed based on a damascene process. The first wiring layer 300 also includes a first medium 302.

[0151] As an example, the metal shielding bar 420 is rectangular in the projection direction.

[0152] As an example, the backside power supply chip unit 410 includes a power supply connection layer 412, a silicon deposition layer 413, a buried power layer 414, a dielectric layer 415 and a signal connection layer 416; the power supply connection layer 412 and the signal connection layer 416 are distributed on opposite sides of the backside power supply chip unit 410. A plurality of backside power supply chip units 410 are arranged in the lateral direction and are bonded to the first wiring layer 300. The signal connection layers 416 of a plurality of backside power supply chip units 410 are interconnected by the first metal wiring 301.

[0153] As an example, the plastic package layer 400 can include one or a combination of a polyimide layer, a silica gel layer and an epoxy resin layer.

[0154] As an example, the trench capacitor layer 700 includes an intermediate substrate 701, a plurality of trench capacitor units 703 and a plurality of metal pillars 702; the metal pillars 702 and the trench capacitor units 703 extend into the intermediate substrate 701, and the depth of the metal pillars 702 is greater than the depth of the trench capacitor units 703, and the second wiring layer 500 is electrically connected to the metal pillars 702 through the second metal wiring 501.

[0155] In some embodiments, the capacitor unit 703 can also wrap 2 or more layers of trench electrodes and 2 or more layers of capacitor medium layers.

[0156] As an example, the second wiring layer 500 further comprises a second dielectric 502; the second wiring layer 500 is electrically connected with the metal column 702 in the trench capacitor layer 700 through the second metal wiring 501.

[0157] As an example, the metal shielding bar 420 is connected with the first shielding layer 303 and the second shielding layer 503; in some other embodiments, the metal shielding bar 420 is only connected with the first shielding layer 303; in another embodiment, the metal shielding bar 420 is independent structure and not connected with the first shielding layer 303 and the second shielding layer 503.

[0158] As an example, the material of the metal bump 600 can be one of copper, aluminum, nickel, gold, silver or titanium.

[0159] By arranging the first shielding layer 303 on the first wiring layer 300, arranging the second shielding layer 503 on the second wiring layer 500 and arranging the metal shielding bar 420 around the back power chip unit 410, a hexahedral electromagnetic shielding high-density packaging structure is formed around the back power chip unit 410, and the electromagnetic interference in the packaging structure is reduced.

[0160] The back power chip packaging structure of the embodiment comprises the hexahedral electromagnetic shielding high-density packaging structure composed of the first shielding layer 303, the second shielding layer 503 and the metal shielding bar 420. The high-density packaging structure surrounds the back power chip unit 410, and the electromagnetic interference in the packaging structure is reduced; in addition, the heat-conducting combined layer is connected with the first shielding layer 303, the metal shielding bar 420 and the second shielding layer 503 to form a heat-conducting track, so that the heat generated by the back power chip 410 can be dissipated in time. In addition, the structure further comprises the trench capacitor unit 703, and the integrity of the power supply is realized, so that the stability of the chip structure and performance is finally ensured.

[0161] In summary, the application provides a backside power supply chip packaging structure and a preparation method thereof. First, a first shielding layer is arranged on a first wiring layer, a second shielding layer is arranged on a second wiring layer, and a metal shielding fence is arranged around a backside power supply chip unit, so that a hexahedral electromagnetic shielding high-density packaging structure is formed around the backside power supply chip unit, and electromagnetic interference in the packaging structure is reduced. Second, the heat-conducting combined layer is connected with the first shielding layer, the metal shielding fence and the second shielding layer to form a heat-conducting track, which shields electromagnetic interference and solves the problem of slow heat dissipation in the backside power supply chip packaging structure. In addition, a groove capacitor layer is arranged between the backside power supply chip unit and the third wiring layer, the integrity of the power supply is realized, and finally the stability of the chip structure and performance is ensured. Therefore, the application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0162] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. A method for fabricating a back-side powered chip package structure, characterized in that, The method comprises the following steps: providing a support substrate having opposite first and second surfaces, forming a first heat-conducting hole on the first surface of the support substrate and forming a first heat-conducting member filling the first heat-conducting hole; forming a heat-conducting wiring layer on the first surface of the support substrate, the heat-conducting wiring layer being in contact with the first heat-conducting member, the heat-conducting wiring layer and the first heat-conducting member forming a heat-conducting combined layer; forming a first wiring layer on the heat-conducting wiring layer, the first wiring layer comprising a first shielding layer and a first metal wiring, the first shielding layer being in contact with a heat-conducting wiring in the heat-conducting wiring layer, the first shielding layer not being connected with the first metal wiring; forming a metal shielding fence on the surface of the first wiring layer, the metal shielding fence being in a closed shape and not being connected with the first metal wiring; providing a plurality of back-side power supply chip units, the back-side power supply chip units comprising power supply connecting layers and signal connecting layers on opposite surfaces, and the back-side power supply chip units being bonded on the first wiring layer along a transverse direction through the signal connecting layers and being electrically connected with the first metal wiring, and the back-side power supply chip units being located inside the metal shielding fence; forming a plastic encapsulation layer on the first wiring layer, the plastic encapsulation layer covering the back-side power supply chip units and exposing the metal shielding fence and the power supply connecting layers; providing a trench combined layer, the trench combined layer comprising a trench capacitor layer and a second wiring layer electrically connected with each other, the trench capacitor layer comprising a plurality of trench capacitor units and a plurality of metal pillars, the second wiring layer comprising a second metal wiring and a second shielding layer, and the second shielding layer not being connected with the second metal wiring; bonding the trench combined layer on the plastic encapsulation layer, the second metal wiring being electrically connected with the power supply connecting layers; thinning the trench capacitor layer to expose the metal pillars, and forming a third wiring layer on the trench capacitor layer, the third wiring layer being electrically connected with the metal pillars through a third metal wiring.

2. The method of claim 1, wherein: The third wiring layer further comprises a metal bump, and the metal bump is electrically connected with the third metal wiring.

3. The method of claim 1, wherein: The metal shielding fence is formed by opening a hole after patterning a photoresist, and the cross-sectional profile of the metal shielding fence is in a rectangular shape.

4. The method of claim 1, wherein: In the trench capacitor layer, the depth of the metal pillars is greater than the depth of the trench capacitor units.

5. A method for fabricating a back-side powered chip package structure, characterized in that, The method comprises the following steps: providing an intermediate substrate having opposite first and second surfaces, extending from the first surface to the second surface of the intermediate substrate to form a trench capacitor layer and metal pillars in the intermediate substrate; forming a second wiring layer on the trench capacitor layer, a second metal wiring in the second wiring layer being electrically connected with the metal pillars, and a second shielding layer in the second wiring layer being independent of the second metal wiring; forming a metal shielding fence on the second wiring layer, the metal shielding fence being in a closed shape and not being connected with the second metal wiring; The back power supply chip units are bonded on the second wiring layer through the power supply connecting layers in the lateral direction and are electrically connected with the second metal wiring, and the back power supply chip units are located inside the metal shielding fence; A plastic encapsulation layer is formed on the second wiring layer, the plastic encapsulation layer covers the back power supply chip units, and the metal shielding fence and the signal connecting layer are exposed; A first wiring layer is formed on the plastic encapsulation layer, the first wiring layer comprises a first shielding layer and a first metal wiring, the first metal wiring is electrically connected with the signal connecting layer, and the first shielding layer is not connected with the first metal wiring; A heat conduction combined layer is provided, the heat conduction combined layer comprises a support substrate containing a first heat conduction member and a heat conduction wiring layer which are stacked, and the first heat conduction member is in contact with the heat conduction wiring layer; The heat conduction combined layer is bonded on the first wiring layer, and the heat conduction wiring layer is in contact with the first shielding layer; The trench capacitor layer is thinned to expose the metal column, a third wiring layer is formed on the second surface of the intermediate substrate, and the third wiring layer is electrically connected with the metal column through a third metal wiring; A metal bump is formed on the third wiring layer, and the metal bump is electrically connected with the third metal wiring.

6. The method of claim 5, wherein: The metal shielding fence is internally provided with a metal heat conduction column, one end of the metal heat conduction column is connected with the second shielding layer, and the other end is connected with the first shielding layer.

7. The method of claim 1-6, wherein the method further comprises: The second shielding layer, the metal shielding fence, the first shielding layer and the heat conduction combined layer are connected to form a heat conduction track.

8. A back side powered chip package structure, comprising: The back power supply chip package structure comprises: a support substrate having opposite first and second surfaces; a first heat conduction member located in the support substrate and extending inward from the first surface of the support substrate; a heat conduction wiring layer located on the first surface of the support substrate, the heat conduction wiring of the heat conduction wiring layer being in contact with the first heat conduction member, and the heat conduction wiring layer and the first heat conduction member forming a heat conduction combined layer; a first wiring layer located above the heat conduction wiring layer, the first wiring layer comprising a first shielding layer and a first metal wiring, and the first shielding layer being in contact with the heat conduction wiring layer; the first metal wiring is not connected with the first shielding layer; a metal shielding fence located on the surface of the first wiring layer and not connected with the first metal wiring; a plurality of back power supply chip units comprising power supply connecting layers and signal connecting layers located on opposite sides; a plurality of the back power supply chip units are electrically connected with the first wiring layer through the signal connecting layers, and the back power supply plastic encapsulation layer is located on the first wiring layer, the plastic encapsulation layer covers the back power supply chip units, and the exposed chip units are located inside the metal shielding fence; the metal shielding fence and the power supply connecting layer; The trench combination layer includes a trench capacitor layer and a second wiring layer, and the second wiring layer is electrically connected with the power supply connection layer through a second metal wiring; the trench capacitor layer includes a plurality of trench capacitor units and a plurality of metal columns; the second wiring layer includes a second metal wiring and a second shielding layer, and the second shielding layer is not connected with the second metal wiring; A third wiring layer is located above the trench capacitor layer, and the third wiring layer is electrically connected with the metal columns; A metal bump is located above the third wiring layer, and the metal bump is electrically connected with a third metal wiring in the third wiring layer.

9. The back-side powered chip package structure of claim 8, wherein: The metal shielding fence is not connected with the first shielding layer and the second shielding layer, or is connected with one or both of them.

10. The back-side powered chip package structure of claim 8, wherein: In the trench combination layer, the second wiring layer is electrically connected with the metal columns in the trench capacitor layer through the second metal wiring.

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