Packaging structure for chip with backside power delivery, and preparation method therefor

Abstract

Provided in the present invention are a packaging structure for a chip with backside power delivery, and a preparation method therefor. By means of forming, on one side of a signal connection layer of a chip with backside power delivery, a PN-type semiconductor heat dissipation component comprising an N-type semiconductor and a P-type semiconductor, a semiconductor heat dissipation principle can be used to form, by means of the PN-type semiconductor heat dissipation component, a cold end and a hot end between which there is a temperature difference, so as to effectively dissipate heat from the chip with backside power delivery, thereby improving the performance of a semiconductor device while reducing the volume of the packaging structure.

Description

Backside power supply chip packaging structure and preparation method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and relates to a backside power supply chip packaging structure and a preparation method thereof. BACKGROUND

[0002] At present, in the semiconductor 2.5D or 3D advanced packaging, the power supply network is mostly formed by supplying power to the chip through the front surface wiring of the chip, but there is a signal network in this area at the same time. The power supply network arranged on the front surface of the chip will share the space with the signal network, and the power supply network often occupies a large space, thereby making it more and more challenging to reduce the volume of the entire packaging structure, and the industry has begun to explore the feasibility of transferring the power supply network to the back surface of the chip, so that the back surface power supply (Backside PDN) has become a hot technical issue.

[0003] In the existing stacked integrated circuit, the signal lines and the power supply lines are vertically stacked and connected to form a semiconductor device with active electronic elements in two or more layers of the integrated circuit. Compared with two-dimensional systems, three-dimensional systems with increased chip density can have high IR voltage drops (for example, voltage drops), and the increased IR voltage drops can lead to increased power consumption and generate a large amount of heat energy. If the excessive heat cannot be dissipated in time, the high temperature generated by the continuous heat can damage the chip, thereby affecting the structure and performance of the chip.

[0004] Therefore, it is necessary to provide a backside power supply chip packaging structure and a preparation method thereof. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a backside power supply chip packaging structure and a preparation method thereof, which are used to solve the problem that the backside power supply chip packaging structure is difficult to dissipate heat in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a backside power supply chip packaging structure, comprising the following steps:

[0007] providing a substrate;

[0008] forming an N-type semiconductor and a P-type semiconductor arranged at intervals in the substrate, and the first ends of the N-type semiconductor and the P-type semiconductor are exposed on the first surface of the substrate;

[0009] forming a first re-wiring layer on the first surface of the substrate, the first re-wiring layer is electrically connected with the N-type semiconductor and the P-type semiconductor;

[0010] thinning the substrate from a second side of the substrate to expose second ends of the N-type semiconductor and the P-type semiconductor;

[0011] forming a second re-wiring layer on the second side of the substrate, and the second re-wiring layer is electrically connected with the N-type semiconductor and the P-type semiconductor;

[0012] providing a back-side power supply chip, the back-side power supply chip comprising power supply connection layers and signal connection layers on opposite sides;

[0013] bonding the back-side power supply chip on the first re-wiring layer, and the signal connection layers are electrically connected with the first re-wiring layer;

[0014] forming a plastic encapsulation layer on the first re-wiring layer, the plastic encapsulation layer covering the back-side power supply chip;

[0015] forming a metal column in the plastic encapsulation layer, a first end of the metal column being electrically connected with the first re-wiring layer, wherein the N-type semiconductor, the P-type semiconductor, the first re-wiring layer, the second re-wiring layer and the metal column in electrical connection constitute a PN-type semiconductor heat dissipation assembly;

[0016] thinning the plastic encapsulation layer to expose a second end of the metal column and the power supply connection layers;

[0017] forming a third re-wiring layer on the plastic encapsulation layer, the third re-wiring layer being electrically connected with the second end of the metal column and the power supply connection layers;

[0018] forming a metal bump on the third re-wiring layer, and the metal bump being electrically connected with the third re-wiring layer.

[0019] Optionally, the method further comprises the step of forming an isolation layer in the substrate on sidewalls of the N-type semiconductor and the P-type semiconductor.

[0020] Optionally, the isolation layer comprises a silicon oxide layer and / or a silicon nitride layer.

[0021] Optionally, the PN-type semiconductor heat dissipation assembly is formed in a stack from bottom to top and in electrical connection with each other.

[0022] Optionally, the number of layers of the PN-type semiconductor heat dissipation assembly in the stack from bottom to top and in electrical connection with each other comprises N layers, wherein 2≤N≤10.

[0023] The application further provides a back-side power supply chip packaging structure, the back-side power supply chip packaging structure comprising:

[0024] a substrate;

[0025] An N-type semiconductor and a P-type semiconductor, both penetrating through the substrate and being spaced apart;

[0026] A first re-wiring layer, located on a first surface of the substrate, and electrically connected with both the N-type semiconductor and the P-type semiconductor;

[0027] A second re-wiring layer, located on a second surface of the substrate, and electrically connected with both the N-type semiconductor and the P-type semiconductor;

[0028] A back-side power supply chip, including power supply connection layers and signal connection layers on opposite surfaces, bonded on the first re-wiring layer, and the signal connection layers electrically connected with the first re-wiring layer;

[0029] A plastic encapsulation layer, located on the first re-wiring layer, covering the back-side power supply chip, and exposing the signal connection layers;

[0030] A metal pillar, penetrating through the plastic encapsulation layer, and a first end of the metal pillar electrically connected with the first re-wiring layer, wherein the electrically connected N-type semiconductor, P-type semiconductor, first re-wiring layer, second re-wiring layer and metal pillar combine to form a PN-type semiconductor heat dissipation assembly;

[0031] A third re-wiring layer, located on the plastic encapsulation layer, and electrically connected with both a second end of the metal pillar and the power supply connection layers;

[0032] A metal bump, located on the third re-wiring layer, and electrically connected with the third re-wiring layer.

[0033] Optionally, the PN-type semiconductor heat dissipation assembly is stacked from bottom to top and electrically connected with each other.

[0034] Optionally, the number of layers of the PN-type semiconductor heat dissipation assembly stacked from bottom to top and electrically connected with each other includes N layers, wherein 2≤N≤10.

[0035] Optionally, further comprising an isolation layer located on the sidewalls of the N-type semiconductor and the P-type semiconductor.

[0036] Optionally, the isolation layer includes a silicon oxide layer and / or a silicon nitride layer.

[0037] As described above, the back power supply chip packaging structure and the preparation method thereof can utilize the semiconductor heat dissipation principle, form the cold end and the hot end with temperature difference through the PN semiconductor heat dissipation component, effectively dissipate the heat of the back power supply chip, and improve the performance of the semiconductor device while reducing the volume of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0038] Fig. 1 shows the heat dissipation principle of the back power supply chip packaging structure prepared according to the present application.

[0039] Fig. 2 shows the process flow of preparing the back power supply chip packaging structure according to the first embodiment of the present application.

[0040] Figs. 3-13 show the structure of preparing the back power supply chip packaging structure according to the first embodiment of the present application.

[0041] Figs. 14-16 show the structure of preparing the back power supply chip packaging structure according to the second embodiment of the present application.

[0042] Fig. 1 shows the heat dissipation principle of the back power supply chip packaging structure prepared according to the present application. DETAILED DESCRIPTION

[0043] Following, the advantages and effects of the present application will be easily understood by those skilled in the art from the description of the specific examples. The present application can also be implemented or applied by other different specific embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0044] As described in the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged without the general proportion for the convenience of description, and the schematic view is only an example which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0045] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature with other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings, which can include the embodiment that the first and second features are formed in direct contact, and can also include the embodiment that the additional features are formed between the first and second features, so that the first and second features can not be in direct contact, and in addition, when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or one or more layers can be present therebetween.

[0046] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change, and the component layout pattern can be more complex.

[0047] The back power supply chip packaging structure provided in the present application forms the PN type semiconductor heat dissipation assembly including the N type semiconductor and the P type semiconductor on one side of the signal connection layer of the back power supply chip. The semiconductor heat dissipation principle is used to form the cold end and the hot end with temperature difference through the PN type semiconductor heat dissipation assembly to effectively dissipate heat for the back power supply chip. Thus, the volume of the packaging structure is reduced, and the performance of the semiconductor device is improved.

[0048] Wherein, refer to Fig. 1 shows the working principle of the PN semiconductor heat dissipation assembly, wherein, the power supply provides the energy required for the flow of electrons, after the power supply, the electrons start from the negative (-) and pass through the P-type semiconductor element and absorb heat, to the N-type semiconductor element and release heat, so that every NP module, the heat is sent to the other side to form a cold and hot end to cause temperature difference, so that when the cold end and the heat source contact, the heat source can be cooled.

[0049] Embodiment one

[0050] The following combined with the description of Fig. 2 to Fig. 13, further introduce the back power supply chip packaging structure and its preparation method in the embodiment.

[0051] First, refer to Fig. 2 and Fig. 3, step S1 is performed, and the substrate 100 is provided.

[0052] Specifically, the material of the substrate 100 can include, such as glass material, semiconductor material, etc., the size of the substrate 100 is not limited here, preferably wafer level, so as to improve the production efficiency through subsequent processes such as cutting.

[0053] Next, refer to Fig. 2, Fig. 3 to Fig. 5, step S2 is performed, and the N-type semiconductor 101 and the P-type semiconductor 102 are formed in the substrate 100, and the first end of the N-type semiconductor 101 and the P-type semiconductor 102 is exposed on the first surface of the substrate 100.

[0054] Specifically, the method of forming the N-type semiconductor 101 and the P-type semiconductor 102 can be prepared by forming a patterned mask, using ion implantation method, wherein the order of forming the N-type semiconductor 101 and the P-type semiconductor 102 is not limited here, such as Fig. 3, in this embodiment, the N-type semiconductor 101 is formed by ion implantation method, and then refer to Fig. 4, the P-type semiconductor 102 is formed by ion implantation method. Wherein, the dopant used in the N-type semiconductor 101 can include As, P or other N-type dopant, or a combination thereof; the dopant used in the P-type semiconductor 102 can include B, Ga, In or other P-type dopant, or a combination thereof. The depth of ion implantation and the amount of doping of the N-type semiconductor 101 and the P-type semiconductor 102 are not limited here.

[0055] In this embodiment, referring to FIGS. 6 and 7, an isolation layer 103 is preferably formed in the substrate 100 on the sidewalls of the N-type semiconductor 101 and the P-type semiconductor 102 to achieve electrical isolation by the isolation layer 103. The step of forming the isolation layer 103 can include etching, deposition, and polishing steps to form the isolation layer 103 on the sidewalls of the N-type semiconductor 101 and the P-type semiconductor 102. The etching method can include dry etching, wet etching, or a combination thereof, which is not limited herein. The deposition method can include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof. The polishing method can include chemical mechanical polishing (CMP).

[0056] Next, referring to FIGS. 2 and 8, step S3 is performed to form a first re-wiring layer 210 on the first surface of the substrate 100, which is electrically connected to the N-type semiconductor 101 and the P-type semiconductor 102.

[0057] Specifically, the first re-wiring layer 210 includes metal wires and a dielectric layer, which can be formed of polymers such as polybenzoxazole (PBO) or polyimide, or inorganic dielectric materials such as silicon nitride or silicon oxide. The metal wires can include aluminum, copper, tungsten, or alloys thereof. The preparation, specific structure, and material selection of the first re-wiring layer 210 are not limited herein.

[0058] Next, referring to FIGS. 2 and 9, step S4 is performed to thin the substrate 100 from the second surface of the substrate 100 to expose the second ends of the N-type semiconductor 101 and the P-type semiconductor 102. The method of thinning the substrate 100 can include chemical mechanical polishing (CMP), which is not limited herein.

[0059] Next, referring to FIGS. 2 and 10, step S5 is performed to form a second re-wiring layer 220 on the second surface of the substrate 100, which is electrically connected to the N-type semiconductor 101 and the P-type semiconductor 102.

[0060] Specifically, the second re-wiring layer 220 includes metal wires and a dielectric layer, which can be formed of polymers such as polybenzoxazole (PBO) or polyimide, or inorganic dielectric materials such as silicon nitride or silicon oxide. The metal wires can include aluminum, copper, tungsten, or alloys thereof. The preparation, specific structure, and material selection of the second re-wiring layer 220 are not limited herein. The second re-wiring layer 220 can electrically connect the spaced N-type semiconductor 101 and the P-type semiconductor 102 to facilitate the formation of a closed circuit.

[0061] Next, referring to FIG. 2 and FIG. 11, step S6 is performed to provide a back power supply chip 300 including a power connection layer 302 and a signal connection layer 301 on opposite sides. The specific mechanism and type of the back power supply chip 300 are not limited here.

[0062] Next, referring to FIG. 2 and FIG. 11, step S7 is performed to bond the back power supply chip 300 on the first re-wiring layer 210, and the signal connection layer 301 is electrically connected to the first re-wiring layer 210.

[0063] Specifically, in the horizontal direction, the signal connection layers 301 of multiple back power supply chips 300 can be electrically connected through the first re-wiring layer 210, and through the first re-wiring layer 210, the heat generated by the back power supply chip 300 can be transferred to the N-type semiconductor 101 and the P-type semiconductor 102 to achieve good heat dissipation.

[0064] Next, referring to FIG. 2 and FIG. 12, step S8 is performed to form a plastic encapsulation layer 400 on the first re-wiring layer 210, and the plastic encapsulation layer 400 covers the back power supply chip 300.

[0065] Specifically, the method of forming the plastic encapsulation layer 400 can include but is not limited to compression molding, transfer molding, and spin coating, and the material of the plastic encapsulation layer 400 can include but is not limited to epoxy resin and polyamide. The material and preparation method of the plastic encapsulation layer 400 are not limited here.

[0066] Next, referring to FIG. 2 and FIG. 12, step S9 is performed to form a metal column 500 in the plastic encapsulation layer 400, and the first end of the metal column 500 is electrically connected to the first re-wiring layer 210; wherein the electrically connected N-type semiconductor 101, P-type semiconductor 102, first re-wiring layer 210, second re-wiring layer 220, and metal column 500 combine to form a PN-type semiconductor 101 heat dissipation assembly. As shown in FIG. 13, the arrowed line schematically shows the circuit path of the PN-type semiconductor heat dissipation assembly.

[0067] Specifically, the metal column 500 can be formed by etching and electroplating, and the metal column 500 can provide a current path for the N-type semiconductor 101, the P-type semiconductor 102, and the like.

[0068] Next, referring to FIG. 2 and FIG. 12, step S10 is performed to thin the plastic encapsulation layer 400 to expose the second end of the metal column 500 and the power connection layer 302.

[0069] Specifically, the thinning method can adopt the CMP method, but is not limited thereto. During grinding, the second end of the metal pillar 500 and the power supply connection layer 302 can be exposed, facilitating subsequent electrical connection.

[0070] Next, referring to FIGS. 2 and 13, step S11 is performed to form a third re-wiring layer 230 on the plastic package layer 400, the third re-wiring layer 230 being electrically connected to the second end of the metal pillar 500 and the power supply connection layer 302.

[0071] Specifically, the third re-wiring layer 230 includes metal wires and a dielectric layer, the dielectric layer being formed of a polymer such as polybenzoxazole (PBO) or polyimide, or an inorganic dielectric material such as silicon nitride or silicon oxide; and the metal wires can include aluminum, copper, tungsten or an alloy thereof. The preparation, specific structure and material selection of the third re-wiring layer 230 are not limited herein.

[0072] Next, referring to FIGS. 2 and 13, step S12 is performed to form a metal bump 600 on the third re-wiring layer 230, the metal bump 600 being electrically connected to the third re-wiring layer 230.

[0073] Specifically, the metal bump 600 can include a solder ball bump, a C4 metal bump 600, a copper pillar bump, etc. The specific type and material of the metal bump 600 are not limited herein.

[0074] Referring to FIGS. 3-13, the embodiment further provides a backside power supply chip packaging structure, which can be prepared by the above preparation method, but is not limited thereto. In the embodiment, the backside power supply chip packaging structure is directly prepared by the above preparation process, so that the material, preparation method and structure of the backside power supply chip packaging structure can be referred to the above preparation method.

[0075] The backside power supply chip packaging structure includes:

[0076] a substrate 100;

[0077] an N-type semiconductor 101 and a P-type semiconductor 102, the N-type semiconductor 101 and the P-type semiconductor 102 being arranged in a spaced-apart manner through the substrate 100;

[0078] a first re-wiring layer 210 on a first surface of the substrate 100, the first re-wiring layer 210 being electrically connected to the N-type semiconductor 101 and the P-type semiconductor 102;

[0079] a second re-wiring layer 220, which is located on the second surface of the substrate 100, and which is electrically connected to the N-type semiconductor 101 and the P-type semiconductor 102;

[0080] a back-side power supply chip 300, which comprises a power supply connecting layer 302 and a signal connecting layer 301 on opposite surfaces, and which is bonded on the first re-wiring layer 210, and the signal connecting layer 301 is electrically connected to the first re-wiring layer 210;

[0081] a plastic encapsulation layer 400, which is located on the first re-wiring layer 210, and which encapsulates the back-side power supply chip 300, and exposes the signal connecting layer 301;

[0082] a metal pillar 500, which penetrates the plastic encapsulation layer 400, and a first end of the metal pillar 500 is electrically connected to the first re-wiring layer 210, wherein the N-type semiconductor 101, the P-type semiconductor 102, the first re-wiring layer 210, the second re-wiring layer 220 and the metal pillar 500 in electrical connection combine to form a PN-type semiconductor 101 heat dissipation assembly;

[0083] a third re-wiring layer 230, which is located on the plastic encapsulation layer 400, and which is electrically connected to the second end of the metal pillar 500 and the power supply connecting layer 302;

[0084] a metal bump 600, which is located on the third re-wiring layer 230, and which is electrically connected to the third re-wiring layer 230.

[0085] wherein, an isolation layer 103 is further included on the sidewalls of the N-type semiconductor 101 and the P-type semiconductor 102, and the isolation layer 103 can comprise a silicon oxide layer and / or a silicon nitride layer.

[0086] Embodiment Two

[0087] Referring to FIGS. 3-16, the embodiment further provides a back-side power supply chip packaging structure with a stacked structure and a preparation method thereof. The embodiment differs from the first embodiment mainly in that the back-side power supply chip packaging structure comprises the PN-type semiconductor heat dissipation assembly stacked from bottom to top and electrically connected to each other, so as to further improve the heat dissipation performance. Only the differences will be introduced below, and other aspects about the back-side power supply chip packaging structure, materials and preparation steps can be referred to the first embodiment, and will not be repeated here.

[0088] In the embodiment, as shown in Fig. 14, the metal column 500 is prepared on the basis of the structure A prepared in Fig. 10 of the first embodiment, and is electrically connected with the first rewiring layer 210 and penetrates the substrate 100 and the second rewiring layer 220, so as to form a structure B shown in Fig. 15, thereby providing a current communication path for the stacked PN-type semiconductor heat-dissipation component through the metal column 500.

[0089] In the embodiment, as shown in Fig. 15, the A structure and the B structure are stacked by bonding, thereby forming the 4-layer PN-type semiconductor heat-dissipation component stacked from bottom to top and electrically connected with each other, but the number of layers of the stacked PN-type semiconductor heat-dissipation component is not limited here, and can include N-layer PN-type semiconductor heat-dissipation component stacked from bottom to top, where N can be 2≤N≤10, and the value of N is not limited here.

[0090] In summary, the back power supply chip packaging structure and the preparation method thereof can form the PN-type semiconductor heat-dissipation component including the N-type semiconductor and the P-type semiconductor on the side of the signal connection layer of the back power supply chip, can utilize the semiconductor heat-dissipation principle, and can form the cold end and the hot end with temperature difference through the PN-type semiconductor heat-dissipation component, so as to effectively dissipate heat for the back power supply chip, thereby reducing the volume of the packaging structure, and improving the performance of the semiconductor device.

[0091] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a back-side power supply chip packaging structure, characterized in that, The method comprises the following steps: providing a substrate; forming an N-type semiconductor and a P-type semiconductor in the substrate, and the first ends of the N-type semiconductor and the P-type semiconductor are exposed on the first surface of the substrate; forming a first re-wiring layer on the first surface of the substrate, and the first re-wiring layer is electrically connected with the N-type semiconductor and the P-type semiconductor; thinning the substrate from the second surface of the substrate to expose the second ends of the N-type semiconductor and the P-type semiconductor; forming a second re-wiring layer on the second surface of the substrate, and the second re-wiring layer is electrically connected with the N-type semiconductor and the P-type semiconductor; providing a backplane power chip, the backplane power chip comprises power connection layers and signal connection layers on opposite surfaces; bonding the backplane power chip on the first re-wiring layer, and the signal connection layers are electrically connected with the first re-wiring layer; forming a plastic encapsulation layer on the first re-wiring layer, and the plastic encapsulation layer covers the backplane power chip; forming metal pillars in the plastic encapsulation layer, and the first ends of the metal pillars are electrically connected with the first re-wiring layer, wherein the N-type semiconductor, the P-type semiconductor, the first re-wiring layer, the second re-wiring layer and the metal pillars are combined to form a PN-type semiconductor heat dissipation assembly; thinning the plastic encapsulation layer to expose the second ends of the metal pillars and the power connection layers; forming a third re-wiring layer on the plastic encapsulation layer, and the third re-wiring layer is electrically connected with the second ends of the metal pillars and the power connection layers; forming metal bumps on the third re-wiring layer, and the metal bumps are electrically connected with the third re-wiring layer.

2. The method of claim 1, wherein: The method further comprises the step of forming an isolation layer on the sidewalls of the N-type semiconductor and the P-type semiconductor in the substrate.

3. The method of claim 1, wherein: The isolation layer comprises a silicon oxide layer and / or a silicon nitride layer.

4. The method of claim 1, wherein: The PN-type semiconductor heat dissipation assembly is formed in a stack from bottom to top and is electrically connected with each other.

5. The method of claim 4, wherein: The number of layers of the PN-type semiconductor heat dissipation assembly formed in a stack from bottom to top and electrically connected with each other comprises N layers, wherein 2≤N≤10.

6. A back side power supply chip package structure, characterized by, The backplane power chip packaging structure comprises: a substrate; an N-type semiconductor and a P-type semiconductor, the N-type semiconductor and the P-type semiconductor are both through the substrate and are spaced apart; a first re-wiring layer on the first surface of the substrate, and the first re-wiring layer is electrically connected with the N-type semiconductor and the P-type semiconductor; a second re-wiring layer on the second surface of the substrate, and the second re-wiring layer is electrically connected with the N-type semiconductor and the P-type semiconductor; a backplane power chip comprising power connection layers and signal connection layers on opposite surfaces, the backplane power chip is bonded on the first re-wiring layer, and the signal connection layers are electrically connected with the first re-wiring layer; a plastic encapsulation layer on the first re-wiring layer, covering the backplane power chip, and exposing the signal connection layers; a metal column, the metal column penetrating the plastic sealing layer, and a first end of the metal column being electrically connected with the first re-wiring layer, wherein the N-type semiconductor, the P-type semiconductor, the first re-wiring layer, the second re-wiring layer and the metal column in electrical connection combine to form a PN-type semiconductor heat dissipation assembly; a third re-wiring layer, the third re-wiring layer being located on the plastic sealing layer, and the third re-wiring layer being electrically connected with both a second end of the metal column and the power supply connection layer; a metal bump, the metal bump being located on the third re-wiring layer, and the metal bump being electrically connected with the third re-wiring layer.

7. The back side powered chip package structure of claim 6, wherein: The PN-type semiconductor heat dissipation assembly is stacked from bottom to top and is electrically connected with each other.

8. The back side powered chip package structure of claim 7, wherein: The number of layers of the PN-type semiconductor heat dissipation assembly stacked from bottom to top and electrically connected with each other includes N layers, wherein 2≤N≤10.

9. The back side powered chip package structure of claim 6, wherein: Further comprising an isolation layer located on the side wall of the N-type semiconductor and the P-type semiconductor.

10. The back side powered chip package structure of claim 6, wherein: The isolation layer includes a silicon oxide layer and / or a silicon nitride layer.

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