Arbitrary size and precision number-theoretic transforms via optical fourier transforms

Abstract

A method for performing a number-theoretic transform using and optical Fourier transform device, comprising: receiving an input vector; generating, based on the input vector, a modified input vector; calculating, using a first optical Fourier transform device, a first Fourier transform of the modified input vector; applying a mathematical operation to the first Fourier transform and to a kernel to obtain a modified Fourier transform; calculating, using the first or a second Fourier transform device, a second Fourier transform of the modified Fourier transform; applying a mathematical operation to the modified second Fourier transform and to a set of complex numbers to obtain a pre-output; and outputting the pre-output or a subset thereof.

Description

[0001] P232296GB

[0002] Arbitrary Size and Precision Number-Theoretic Transforms via Optical Fourier Transforms

[0003] Field

[0004] The present disclosure relates to methods for obtaining Fourier transforms and number-theoretic transforms using Fourier transform hardware devices. More particularly, the present disclosure relates to obtaining high precision Fourier transforms from low precision Fourier transform operations carried out using a hardware device. The present disclosure also relates to obtaining number theoretic transforms from a complex output from a Fourier transform hardware device.

[0005] Background

[0006] The Fourier transform is a mathematical operation that decomposes a function into its constituent frequencies and their amplitudes. The Fourier transform has applications in a large number of areas: in signal processing, image analysis and optics, for example. As this operation is, in its full generality, notoriously difficult to calculate, Fourier transforms are essentially always obtained via technical means, be it using a general-purpose processor programmed to carry out one of the Fourier-transform methods or using a special purpose device.

[0007] Applications often use a discrete Fourier transform; that is, a type of Fourier transform applied to a discrete collection of samples of a function. Several algorithms exist for calculating discrete Fourier transforms.

[0008] Known algorithms for calculating discrete Fourier transforms often operate on the assumption that the device on which the algorithm runs can perform individual operations (such as addition, subtraction and multiplication) on complex numbers with enough accuracy (typically using, for example, 16, 32 or 64 bits) to retain enough precision on the end result. This is either not possible on optical hardware or would require the slowing down of modulators and detectors to such an extent that the use of optical hardware would provide little or no acceleration over conventional hardware. It should be appreciated that optical computing is a different computing paradigm compared to traditional computing using an array of logical gates. Therefore, it is not a priori clear how to efficiently interface with and / or embed optical computing elements when using conventional computing elements, such as electronic circuitry.

[0009] Number Theoretic Transform (NTT) is a specific kind of Discrete Fourier Transform (DFT) over finite fields (a field is a particular mathematical algebraic structure). Unlike the traditional DFTs where inputs and outputs can be complex numbers, the inputs and outputs to NTTs are unsigned integers (UINT). This allows modern digital computers to calculate NTTs exactly with a finite word size. However, digital NTT computations can still present a bottleneck for data processing, for instance because NTTs require additional processing at slower digital clock speeds.

[0010] Optical Fourier Transforms (OFT) use the properties of light to perform Fourier transforms (e.g. discrete Fourier transforms ‘DFT’). Using a photonic or optical technology to perform DFTs offers significant P232296GB advantages over electrical physical links. Photonic or optical links can carry larger data / symbol rates for the same optical bandwidth. DFTs can therefore be calculated faster using OFT than using digital electronics. However, performing OFTs on individual high-precision complex numbers is relatively slow compared with performing OFTs on low-precision complex numbers.

[0011] Modern cryptographic applications such as Fully Homomorphic Encryption (FHE) uses both NTTs and DFTs and can involve high precision complex numbers. Whereas OFTs can calculate DFTs at speeds much faster than digital electronics, there is still room for improved speed. Furthermore, NTTs are traditionally processed at much slower clock speeds using digital electronics.

[0012] Therefore, there exists a need to provide methods to efficiently operate various devices to fully exploit the potential speed-ups inherent to them. In particular, there exists a need to provide methods to fully exploit the potential of optical computing elements.

[0013] Summary

[0014] An invention is defined in the appended claims.

[0015] Brief description of the drawings

[0016] The following description of the disclosure will be better understood when read in conjunction with the appended drawings. It should be understood, however, that the disclosure is not limited to the precise algorithmic steps and / or parameters shown. In the drawings:

[0017] Figure 1 shows steps of a first accuracy build-up method for obtaining a Fourier transform.

[0018] Figure 2a shows steps of a second accuracy build-up algorithm for obtaining a Fourier transform.

[0019] Figure 2b shows a method of splitting an input vector into frames, which may be performed by the methods depicted in Figures 1 and 2a.

[0020] Figure 2c shows a method of combining Fourier transforms of frames in order to obtain a Fourier transform of an input from which the frames are derived, which may be performed by the algorithms depicted in Figures 1 and 2a.

[0021] Figure 3 shows a Fourier transform stage using a radix-4 decomposition.

[0022] Figure 4a shows a first method for obtaining a Fourier transform of an input vector whose size is an odd power of two, which may be performed by the methods depicted in Figures 1 and 2a. Figure 4b shows a second method for obtaining a Fourier transform of an input vector whose size is an odd power of two, which may be performed by the algorithms depicted in Figures 1 and 2a.

[0023] Figure 5a shows a method for obtaining a number-theoretic transform by way of obtaining Fourier transforms using a Fourier transform device.

[0024] Figure 5b shows a first stage of the method depicted in Figure 5a.

[0025] Figure 5c shows a second stage of the method depicted in Figure 5a. P232296GB

[0026] Figure 6a shows a first method for obtaining a number-theoretic transform of size N from a Fourier transform of size N.

[0027] Figure 6b shows a second method for obtaining a number-theoretic transform of size N from a Fourier transform of size N.

[0028] Figure 6c shows a first variant of a modular reduction method.

[0029] Figure 6d shows a second variant of a modular reduction method.

[0030] Figure 6e shows a third variant of a modular reduction method.

[0031] Figure 7 shows a number-theoretic transform stage using a radix-4 decomposition.

[0032] Figure 8a shows a schematic of an optical Fourier transform apparatus.

[0033] Figure 8b shows a schematic of an optical Fourier transform apparatus showing an example of an arrangement of input and output ports.

[0034] Figure 9 shows an optical circuit diagram of a photonic integrated circuit including an optical Fourier transform apparatus.

[0035] Overview

[0036] The present disclosure seeks to address at least the above problems and related problems with existing methods for calculating, obtaining, or otherwise determining Fourier transforms and number-theoretic transforms. In particular, the disclosure seeks to address method for manipulating signals or computer memory that comprise information corresponding to or encoding numerical data, wherein said numerical data is to be processed via Fourier transformation. In a particular aspect, this disclosure describes an improved method for operating a Fourier transform device. This overview is not intended to be limiting and various modifications and variants of the described methods and apparatuses are encompassed in addition to those described.

[0037] Modern cryptographic applications, such as FHE, require Fourier transform (for example, Fourier transforms of high-precision individual complex numbers) as well as NTT operations (for example, NTT operations on unsigned integers). While Optical Fourier Transform devices have been recognised as providing significant data processing speed improvements over digital systems, they are typically better suited to performing DFT (rather than NTT). Furthermore, OFT devices are typically better suited to performing low-precision operations than high-precision operations.

[0038] The inventors have recognised that OFT devices can be utilised to perform both DFTs involving high- precision operations and NTTs at faster rates. In particular, the inventors have recognised that performing operations on (or applying algorithms to) the data input to, and / or output from, a physical OFT device in order to carry out DFT or NTT operations can provide significant data processing speed improvements for data processing applications, for example, cryptographic applications such as FHE, and that the output from an optical Fourier transform of low-precision inputs can be used to determine the results of a high-precision operation. For example, a low-precision Fourier transform device can be operated to obtain a high-precision output from a high precision input. P232296GB

[0039] The present disclosure offers at least two distinct types of method: an “FFT” method involving the use of low precision OFTs (that is, outputs of an OFT device configured to operate with said low precision) to perform high-precision DFT operations, and an “NTT” method involving performing NTTs using an OFT device. The labels “FFT” and “NTT” are only used to label the methods disclosed herein and are not meant to limit the method to a particular algorithm for computing Fourier transforms or number- theoretic transforms.

[0040] The “FFT” method includes the decomposition of a signal representing at least one high-precision complex number (e.g., P bits of computer memory are used to encode a complex numbers) into lower precision complex numbers (e.g., Q bits of computer memory are used to encode a complex number), performing multiple OFTs of the lower precision complex numbers and then building up low-precision complex number outputs of the OFTs into a higher precision Fourier transform of the original input before decomposition. This method makes use of the fact that optical hardware can be better suited to performing many operations involving low-precision complex numbers rather than fewer operations involving higher-precision complex numbers. Accuracy in the optical Fourier transform of low-precision complex numbers can be assured at higher data frame rates than for higher-precision complex numbers. In other words, the method describes an improved way of using an optical computing element configured to operate with low precision inputs and outputs in order to obtain a high precision output from a high precision input. In particular, the method or at least a part thereof may be implemented in electronics, fixed-function circuitry, may be computer-implemented, or otherwise embodied in one or more devices.

[0041] The “NTT” method includes the transformation of one or more signals representing integer numbers (e.g. those originally intended as inputs to an NTT operation) as an input to an OFT device, optionally after decomposition using the “FFT” method, followed by optical Fourier transform of those inputs, followed by conversion of the OFT outputs to an NTT result.

[0042] Both of these methods make use of the rapid nature of the Fourier transforms performed by optical hardware (OFT devices and photonic integrated circuits including such OFT devices). In some embodiments, the Fourier transform can be alternatively performed digitally, or obtained via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit. However, the use of OFT devices in any of the Fourier transform steps of the methods described in the present disclosure can provide a faster means of obtaining the Fourier transform than digital (electronic) processors, especially for low precision numbers, functions or data strings. For example, an optical Fourier transform can be carried out in a single clock cycle (e.g., a clock cycle of the electronics interfacing with the optical device), whereas several clock cycles are usually necessary for Fourier transform operations using digital (electronic) processors. Therefore, the methods of the present disclosure are designed to make improved use of optical Fourier transform devices to increase frame rates of FT and / or NTT operations while maintaining high output accuracy. It may be understood that the OFT device itself may be passive and the system comprising said OFT device (e.g., one or P232296GB more transmitters and receivers) are synchronised with a clock. The data may be sent synchronised to the OFT device and the optical circuit may be designed to preserve the synchronicity.

[0043] Description of the drawings

[0044] The following drawings illustrate the content of the present disclosure. As such, they are not meant to be restrictive. Instead, they describe particular exemplary realisations of the technical teaching disclosed herein. As many of these examples relate to particular ways to manipulate signals and / or computer memory, it is understood that a skilled person would implement these examples using technical means (e.g., processor, digital signal processors, electronic or optical circuitry, fixed-function circuits or other suitable technical means). While these examples may show information encoded or represented using a particular representation or scheme, it is understood that a skilled person would readily adapt these examples to a different representation, encoding, or scheme.

[0045] First accuracy build-up algorithm

[0046] Figure 1 depicts the steps of a first “accuracy build-up” algorithm (or alternatively, method) 100 for performing, by operating a Fourier transform device, a Fourier transform. The algorithm / method 100 receives as input a first signal comprising an information corresponding to an input vector 101 comprising N memory or compute elements with P bits per memory or compute element, where N and P are both positive integers. For example, the first signal may correspond to an electrical signal. Said encoding may be based, for example, on voltage levels. Various methods to encode information in various signals are well-known, and a skilled person would readily provide a first signal according to a chosen standard or method.

[0047] While this disclosure may refer to direct manipulation of information, it should be understood that this manipulation may comprise various operations carried out on a signal that carries, encodes, or represents said information.

[0048] Each bit of each memory or compute element of the input vector 101 takes on one of two binary values, which are represented, for example, as ‘0’ or ‘1 ’. The received input vector 101 is a high-precision input vector, for example an input vector each memory or compute element of which comprises a large number of bits (or an equivalent thereof, e.g., a non-binary memory or compute element that can comprise an information encoded or represented using a large number of bits). In general, the phrase “high-precision” may be understood as “encoded or represented using a high number of bits”, wherein said high number should be understood relative to other, “low-precision” input vectors. At step 102, the algorithm / method 100 splits the input vector 101 into K frames 103, where K is an integer greater than or equal to 2. The splitting operation of step 102 may represent, for example:

[0049] • a radix-2 decomposition, wherein the input vector 101 is recursively split into two vectors each half the size of the input vector 101 , in which case K is equal to 2;

[0050] • a radix-4 decomposition, wherein the input vector 101 is recursively split into four vectors each a quarter of the size of the input vector 101 , in which case K is equal to 4; or P232296GB

[0051] • a split-radix decomposition, wherein the input vector 101 is recursively split into three vectors: two being half the size of the input vector 101 , and the remaining vector of these three vectors being a quarter of the size of the input vector 101 , in which case K is equal to 3.

[0052] The operation of splitting may comprise manipulating a signal, a computer memory, a compute element or another information carrier.

[0053] In more general terms, the algorithm / method 100 depicted in Figure 1 performs steps of receiving a first signal comprising an information corresponding to an input vector comprising N memory or compute elements each comprising P bits, and then generating, based on the information corresponding to the input vector, a first and a second frame, wherein each of the first and second frames comprises M memory or compute elements each comprising Q bits, optionally wherein generating the first and second frames comprises performing a radix-2 or radix-4 decomposition of the input vector. For example, said frames may correspond to computer memory comprising an array of bits, or a signal encoding said array of bits, as illustrated in Fig. 2b of the present disclosure. If a device implementing the method 100 (e.g., fixed-function or field-reconfigurable circuitry) comprises computer memory, said frames may correspond to chunks of computer memory. A skilled person would readily see other ways to encode, represent, store or otherwise reason about and manipulate said frames.

[0054] Each frame 103 resulting from the splitting step 102 comprises N memory or compute elements with Q bits per memory or compute element for some positive integer Q. Thus, each of the K frames 103 comprises the same number of memory or compute elements as the input vector 101 . The number of bits in each memory or compute element of each frame 103 may however differ from the number of bits in each memory or compute element of the input vector 101 . For example, the number of bits Q in each memory or compute element of each frame 103 may be smaller than the number of bits P in each memory or compute element of the input vector 101 (i.e. Q < P), in which case a higher-precision input vector is split into a plurality of lower-precision frames. This is described in more detail in relation to Figure 2b.

[0055] The algorithm / method 100 depicted in Figure 1 may optionally include a padding step 104, in which each memory or compute element of each frame 103 is multiplied by pre-computed twiddle factors and then padded, yielding K frames 105 each comprising M memory or compute elements with Q bits per memory or compute element. The pre-computed twiddle factors may correspond for instance to complex-valued trigonometric constant coefficients (e.g. of the general form = e~N~). More generally, the pre-computed twiddle factors may represent any data-independent multiplicative constant(s). Each frame 103 is padded, for example by adding a new memory or compute element or memory or compute elements comprising all ‘0’ bits, or by any other suitable means, so that each resulting frame 105 comprises M memory or compute elements, where M > 2N - 2. In other words, the step of padding may comprise an operation on a signal, computer memory, compute element or another signal carrier that results in a transformation of the information encoded by said signal, computer P232296GB memory, compute element or another signal carrier while also extending the number of bits that is used to encode, represent or store said information.

[0056] In more general terms, the padding operation may comprise adding to each of the first and second frames one or more memory or compute elements comprising all ‘0’ bits. Additionally or alternatively, the padding operation is configured such that, when provided an input whose size is a power of two that is not a power of four, an output of the padding operation has size a power of four. In some examples, bits of an output of the padding operation correspond, alternately, to a corresponding bit of the input to the padding operation and to a new ‘0’ bit. In other examples, a first set of consecutive bits of an output of the padding operation correspond to the input to the padding operation, and wherein the remaining bits of the output correspond to new ‘0’ bits.

[0057] At step 106, the algorithm / method 100 operates a Fourier transform (FT) device 107 and submits each frame 105 yielded by step 104 to said FT device. Thus, for each frame 105, there is a corresponding Fourier transform output 107 comprising M memory or compute elements with Q' bits per memory or compute element, where Q’ is a pre-defined positive integer. The Fourier transforms obtained at step 106 are obtained using a physical hardware component, for example optically using an optical Fourier transform device, or through a digital processor such as a field-programmable gate array or an application-specific integrated circuit. Optical Fourier transform can provide a faster means of obtaining the Fourier transform than digital processors and the (e.g. error free) achievable speed of accurate optical Fourier transforms is increased for lower number of bits (e.g. Q bits) in the frame 103 compared with higher number of bits (e.g. P bits) in the input vector. In other words, the method 100 depicted in Figure 1 performs a step of obtaining, using a (hardware) Fourier transform device, a first Fourier transform of the first frame and a second Fourier transform of the second frame.

[0058] An example of an optical Fourier transform device suitable for use in step 106 is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices suitable for the described method step 106 are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit. However, optical Fourier transform devices can provide a faster means of obtaining the Fourier transform than digital (electronic) processors. For example, an optical Fourier transform can be carried out in a single clock cycle, whereas several clock cycles are usually necessary for Fourier transform operations using digital (electronic) processors. All other steps in Figure 1 described herein can be carried out digitally, for example using field- programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. In a particular example, the method can be implemented using a fixed-function circuitry interfacing with the FT device, or a field-reconfigurable circuitry specifically configured to carry out the method. P232296GB

[0059] It should be understood that the method may be used to operate any FT device and will lead to high precision outputs even if the FT device itself is “low precision” (relative to the inputs / outputs of the method). If the FT device in question is capable of providing Fourier-transformed outputs faster than conventional FT devices (which is true, for example, for optical FT devices), the method will lead to technical effects analogous to those described in connection with OFT devices.

[0060] Step 102 may be carried out in such a way as to ensure that the number of bits Q in each of the M elements of each of the K frames is no larger than the effective number of bits (ENoB) of the corresponding transmitters of the optical Fourier transform device. The number of elements M in each of the K frames is equal to the number of input ports of the OFT device. The number of K frames is greater than or equal to two so that the number of bits Q per element of the K frames is less that the number of bits P per element of the input vector. This allows a lower bit precision per element to be formed in each frame. The method comprises inputting each of the K frames into an optical Fourier transform device by encoding each of the M elements onto a corresponding one of the M input channels. Each of the M input channels of the OFT device includes an encoder (or transmitter) that is configured to encode signals of Q bit precision (in some cases Q bit precision and no greater). That is, the effective number of bits (ENoB) of each encoder of the OFT device may be Q bits. This exploits the lower precision format of the OFT device so that each of the K frames can undergo optical Fourier transform at a significantly higher frame rate than would be possible by feeding the input vector with P bits per element through an optical Fourier transform device capable of processing higher precision numbers (i.e. those with encoders having a higher ENoB and detectors having a yet even higher ENoB). Alternatively, the ENoB of the encoder can be higher than Q bits and match the receiver ENoB. In this case, the encoder deliberately uses only subsets of possible transmitted levels to transmit only Q bits (for example, uses only levels 0 and 1 , or 2 and 3, of a possible 5 levels 0,1 ,2,3,4).

[0061] The bit width of the output channel signals is dependent on the bit width of the input channel signals. In general, a bit width of some output channel signals is equal to the bit width of the input channel signals + Iog2(radix decomposition of the input vector). That is, the maximum bit width of the optical output signals received is equal to the bit width of input port + Iog2(number of input ports M). For example, (bit width of output port) = (bit width of input port) + 2 if running the OFT on an optical device with 4 input ports.

[0062] The required minimum resolution (e.g. ENoB) of the receivers (i.e. detectors or decoders) in the output channels of the optical Fourier transform stage may scale with the required minimum ENoB of the encoders on the input channels. For example, for a four-input port, four output port OFT device (e.g. any of those described with reference to Figs. 8a, 8b or 9) the output bit precision is N+2 (where N is the input bit precision). Due to the nature of the Fourier transform and the interference pattern at the output thereof, some output channels (e.g. output channels 1 & 3 of output channels 1-4 numbered from the top to the bottom of Figs. 8a, 8b, or 9) receive (and therefore need to be configured to resolve) output signals of a higher number of bits (e.g. N+2 bits), and other (interleaving) channels (e.g. output P232296GB channels 2 & 4 in Figs. 8a, 8b or 9) receive (and therefore need to be configured to resolve) output signals of a relatively lower number of bits (e.g. N+1 bits). Nevertheless, the output of each channel that is processed according to the method described with reference to Fig. 2c may have the same number of bits for each output channel. Padding with zeros at the most significant bits may be used for some output channels receiving signals with a lower number of bits than other output channels.

[0063] Therefore, optical Fourier transform devices of the present disclosure may employ transmitters (encoders) and receivers (decoders), which have a maximum ENoB of Q+2. The higher the bit precision of the transmitters and receivers, the more complex the digital electronics required to process the input and output of the optical Fourier transform device. The more complex the digital electronics, the slower the overall optical Fourier transform process. Therefore, limiting the ENoB of the transmitters and receivers in this way provides a simpler architecture and / or improved hardware performance over higher ENoB hardware. The ENoB of the transmitters and / or some of the output receivers can be reduced even further depending on the input and output signals to be handled so that the ENoB of each transmitter and receiver is tailored to be a minimum to resolve (encode or decode) the respective intended input or output signals.

[0064] The benefit of splitting the input vector into K frames as described herein is therefore at least twofold. First, the K frames can be (optionally) processed in parallel with each other. Second, the time taken for each of the K frames to undergo optical Fourier transform is less than the time that would be required for the input vector to undergo optical Fourier transform (both with and without taking into account the time taken for the data to be prepared for transmission through the optical Fourier transform device and the time taken for the data output form the optical Fourier transform device to be decoded and unpacked). Even if the K frames undergo OFT in a serial manner (one frame at a time, one frame after another), it is still faster to optically Fourier transform the K frames than to optically Fourier transform the input vector without first splitting it up.

[0065] We now describe steps 108-1 16 of Figure 1 , which are optionally performed by the algorithm / method 100 depicted in Figure 1. Thus, the algorithm / method 100 can proceed from step 106 directly to step 118, or optional steps 108-116 are performed between step 106 and step 118.

[0066] At step 108, each Fourier transform output 107 is multiplied (e.g., the signal, computer memory or similar may be operated on, by technical means, to transform an information relate to Fourier transform output 107 stored, encoded, represented or otherwise carried therein, wherein said operation corresponds to multiplication in an abstract sense) by a pre-computed kernel, yielding a corresponding frame 109 comprising M memory or compute elements with Q” bits per memory or compute element. The precomputed kernel may represent an array or matrix of complex numbers. Multiplication of each Fourier transform output 107 by the pre-computed kernel at step 108 represents, for example, a convolution operation (which can be seen as a multiplication in Fourier space). In other words, each signal 107 obtained from the FT device may be manipulated further to obtain a new frame 109. P232296GB

[0067] At step 110, an inverse Fourier transform, iFT, is obtained for each frame 109, yielding a corresponding inverse Fourier transform output 11 1 comprising M memory or compute elements with Q’” bits per memory or compute element. An example of an optical Fourier transform device suitable for use in step 204 is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other (optical or non-optical) Fourier transform devices suitable for the described method step 204 are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit. All other steps in Figure 1 (referring to steps other than the FT step 106 and the iFT step 110) described herein may be carried out digitally, for example using field-programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods, or fixed-function circuitry. In at least some examples, the steps of the method may be implemented using multiple devices, for example, a first device may implement the steps prior to inputting signal into a Fourier transform device and a second device may implement the steps after obtaining signals from the Fourier transform device. Where multiplication or addition is concerned, these steps may be alternatively carried out using optical circuits such as optical combiners and / or hybrid sub-systems such as electronically controlled optical phase or amplitude modulators.

[0068] At step 1 12, each inverse Fourier transform output 1 11 is multiplied by pre-computed twiddle factors, yielding K frames 113 each comprising M memory or compute elements with Q’” bits per memory or compute element. As described in relation to step 104, the pre-computed twiddle factors may correspond for instance to complex-valued trigonometric constant coefficients (e.g. of the general form -2nni

[0069] = e~N~), and more generally may represent any data-independent multiplicative constant(s). This multiplication, and other mathematical operations described herein, may involve using a processor or a signal processing element to carry out a transformation of a signal or computer memory that effects the desired transformation of an information encoded in said signal or computer memory.

[0070] At step 114, the K frames 113 resulting from step 1 12 are quantized, yielding K corresponding frames 115 each comprising M memory or compute elements with Q’” bits per memory or compute element. Quantization of the K frames 113 may be performed by applying a bit shift operation to each memory or compute element of each of the K frames 113. For example, each memory or compute element of each of the K frames 113 is bit shifted to the right in order to remove one or more of the least significant bits. Accordingly, the bit depth of each memory or compute element of each of the K frames 113 can be reduced.

[0071] At step 116, the K quantized frames 115 are rescaled, yielding K frames 117 each comprising M memory or compute elements with Q’” bits per memory or compute element. Rescaling of the K quantized frames 1 15 may be performed by applying a bit shift operation to each memory or compute element of each of the K frames 115. For example, each memory or compute element of each of the K frames 115 is bit shifted to the left in order to introduce ‘0’ bits in place of any of the least significant bits that have P232296GB been removed in the quantization step 114. More generally, the bit shift operation applied for rescaling may be in a direction different to the direction of the bit shift operation applied for quantization.

[0072] Finally, at step 118, the K frames obtained as a result of step 106 (or of steps 108-116 if these steps are performed) are combined to produce a single output frame 119 comprising N memory or compute elements with P bits per memory or compute element. The K frames 117 may be combined to produce output frame 119 by way of a sum operation, for example a bitwise sum. More specifically, the K frames 117 may be combined in the following way: for each integer i between 0 and N - 1 inclusive, set the ithelement of the output frame 119 to be equal to the bitwise sum of the ithelements of each of the K frames 117. In this particular example, elements with an index greater than N - 1 are not involved in the bitwise sum operation, and therefore may be discarded. More generally, the algorithm / method 100 depicted in Figure 1 performs a step of combining, to obtain a Fourier transform of the input vector, a first part and a second part, wherein the first part is based on the first Fourier transform and the second part is based on the second Fourier transform. In one example, the first part is equal or corresponds to the first Fourier transform and the second part is equal or corresponds to the second Fourier transform. Alternatively, the first part is equal or corresponds to a modified first Fourier transform (e.g. a frame obtained from optional steps 108-1 16) and the second part is equal or corresponds to a modified second Fourier transform (e.g. another frame obtained from optional steps 108-116). In more general terms, step 118 can be said to comprise combining the first and second parts by bit-shifting the bits of at least one of the first and second parts, and then performing a bitwise sum of the bit-shifted part and the other of the first and second parts to obtain the Fourier transform of the input vector. The combining operation of step 118 is discussed in more detail later in relation to Figure 2c. Analogously to the other steps of the algorithm / method 100, these steps may be also carried out by technical means, for example using fixed-function circuitry, a digital signal processing device, or any other suitable device or processor.

[0073] Second accuracy build-up algorithm

[0074] Figure 2a depicts a second “accuracy build-up” algorithm / method 200 for obtaining a Fourier transform. The algorithm 200 receives as input an input signal comprising information corresponding to (e.g., storing, encoding or representing) an input vector 201 . At step 202, the algorithm 200 splits the input vector 201 into k frames 203, each comprising k memory or compute elements. In this way, the algorithm 200 performs a radix-fc decomposition of the input vector 201. At step 204, the algorithm / method 200 involves a Fourier transform 205 of each of the k frames 203 carried out on a Fourier transform device. The Fourier transform outputs 205 for each of the k frames 203 are then combined, and the result is bit-shifted at step 206 to produce the output 207 of the algorithm / method 200. This output 207 represents a Fourier transform of the input vector 201. The steps of the algorithm / method 200 depicted in Figure 2a are now described in more detail with reference to Figures 2b and 2c. P232296GB

[0075] Splitting the input vector

[0076] Figure 2b depicts a method of splitting an input vector into frames, as performed by the methods depicted in Figures 1 and 2a, for example. The input vector 211 comprises k elements 212 for some positive integer k. Each of the k memory or compute elements of the input vector 211 comprises a real component 213 (e.g., a chunk of memory that encodes a real part of a complex number) and an imaginary component 214 (e.g., a chunk of memory that encodes a real part of a complex number). Each of the real components 213 comprises a sign bit together with k sets of n bits for some positive integer n. Similarly, each of the imaginary components 214 comprises a sign bit together with K sets of Q bits. Thus, each element 212 of the input vector 211 comprises 2(KQ+1 ) bits, and therefore the input vector 21 1 comprises 2K(KQ+1 ) bits. In Figures 2a-c, Kis equal to four, and therefore the input vector 211 in this case comprises 2*4(4Q+1 ) bits. While Figure 2b uses a particular representation of information using binary digits and a real / imaginary split to encode complex numbers, with both the real and imaginary parts encoded via a sign-and-value approach, a skilled person would realise that any other suitable encoding of information may be employed.

[0077] At step 202, the algorithm / method 200 splits the input vector 211 into K frames 215, each comprising M memory or compute elements 216. In this way, the algorithm 200 performs a radix-K decomposition of the input vector 211. Each element 216 of each frame 215 comprises a real component 217 and an imaginary component 218. Each of the real components 217 comprises a sign bit together with Q additional bits, and similarly each of the imaginary components 218 comprises a sign bit together with Q additional bits. Each element 216 of each frame 215 therefore comprises 2(Q + 1) bits, and hence each frame 215 comprises 2M(Q + 1) bits. The elements 216 of the frames 215 may be populated as follows:

[0078] • for all integers i between 1 and M inclusive, and for all integers j between 1 and K inclusive: o set the Q bits of the ithelement of the ythframe to be equal to the ythset of Q bits of the ithelement of the input vector 211 ; o set the sign bit of the real component of the ithelement of the ythframe to be equal to the sign bit of the real component of the ithelement of the input vector 211 ; and o set the sign bit of the imaginary component of the ithelement of the ythframe to be equal to the sign bit of the imaginary component of the ithelement of the input vector 211 .

[0079] In other words, in embodiments each element of the first frame may comprise a subset of the bits of a corresponding element of the input vector, and each element of the second frame may comprise a subset of the P bits of a corresponding element of the input vector. Optionally, the P bits of each element of the input vector are partitioned into K subsets of consecutive bits for some positive integer K; each subset of each element of the first frame corresponds to a first subset of the K subsets that partition the corresponding element of the input vector; and each subset of each element of the second frame corresponds to a second subset of the K subsets that partition the corresponding element of the input vector. Possibly, K = 2 or K = 4. Optionally, the first subset additionally comprises one or more of the most significant bits of the corresponding element in the input vector and / or the second subset P232296GB comprises one or more of the most significant bits of the corresponding element of the input vector that do not belong to the first subset and so on.

[0080] Although not shown in Figure 2b, the algorithm alternatively splits the input vector 211 into 2K frames, K of which correspond to elements of the input vector 21 1 whose sign bit indicates a positive sign and K of which correspond to elements of the input vector 21 1 whose sign bit indicates a negative sign. Each of the 2K frames comprises K memory or compute elements, each memory or compute element comprising a real component and an imaginary component. Each real component and each imaginary component comprises n bits, and therefore each memory or compute element of each frame comprises 2Q bits. Thus, each of the 2K frames comprises 2KQ bits.

[0081] The input vector 211 may be split into real and imaginary components so that the splitting algorithm may be implemented on hardware that supports only real numbers (or where real-valued operations are faster).

[0082] Calculating Fourier transforms

[0083] Continuing with the description of Figure 2a, at step 204, the algorithm / method 200 calculates (e.g., proceed to obtain using a Fourier transform device) a Fourier transform 205 of each of the K frames 203. More specifically, at step 204, a Fourier transform is applied to each of the 2KQ-bit or 2K(Q+1 ) bit frames, yielding a corresponding output comprising 2K(Q+2) bits or 2K(Q+3) bits, depending on the radix of the decomposition performed in the splitting step 202, each such output comprising M memory or compute elements with 2(QK+3) or 2(QK+2)bits per memory or compute element. The larger number of bits in the outputs obtained during step 204 accounts for the larger dynamic range of Fourier transform output.

[0084] The Fourier transforms calculated at step 204 may be performed in batches. For instance, if the algorithm 200 is performed on hardware that can perform L Fourier transforms in parallel for some integer L, then the Fourier transforms calculated at step 204 may be performed in fK / L batches ([■] denotes the upper integer part).

[0085] The Fourier transforms calculated at step 204 are performed using a physical hardware component, for example optically, using an optical Fourier transform stage, or through a digital processor such as a field-programmable gate array or an application-specific integrated circuit or fixed-function circuitry.

[0086] An example of an optical Fourier transform device suitable for use in step 204 is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices suitable for the described method step 204 are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit. In either optical or digital FT, parallelisation of the P232296GB

[0087] Fourier transforms performed at step 204 can be carried out faster and more accurately than Fourier transforms of the higher precision inputs. All other steps in Figure 2a described herein can be carried out digitally, for example using field-programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. Where multiplication or addition is concerned (for example multiplication by twiddle factors or kernels), these steps may be alternatively carried out using optical circuits such as optical combiners and / or hybrid sub-systems such as electronically controlled optical phase or amplitude modulators.

[0088] In at least some examples, the steps of the method 200 may be implemented using multiple devices, for example, a first device may implement the steps prior to inputting signal into a Fourier transform device and a second device may implement the steps after obtaining signals from the Fourier transform device.

[0089] Combining Fourier transform outputs

[0090] In the algorithm depicted in Figure 2a, the Fourier transform outputs 205 for each of the K frames 203 are combined to form the output 207 of the algorithm / method 200. Similarly, in the algorithm depicted in Figure 1 , the Fourier transform outputs 107 obtained as a result of step 106 (optionally, the Fourier transform outputs 117 obtained after additionally performing steps 108-116) are combined to form the output 119 of the algorithm 100. This output 119, 207 represents a Fourier transform of the input vector 101 , 201 . The Fourier transform outputs 107, 117, 205 may be combined to form the output 1 19, 207 in the following way, as depicted in Figure 2c:

[0091] • Assign an ordering to the Fourier transform outputs 107, 117, 205.

[0092] • Bit shift to the left the bits of each Fourier transform output 107, 117, 205 by an amount that is dependent on the position of the Fourier transform output 107, 117, 205 in the ordering. In Figure 2c, the first Fourier transform output 221 is bit shifted to the left by six bits, the second 222 by four bits, the third 223 by two bits, and the fourth 224 by zero bits.

[0093] • Perform a bitwise sum operation on the bit-shifted Fourier transform outputs to form the output 225.

[0094] Figure 3 depicts a Fourier transform stage using a radix-4 decomposition. The results of smaller Fourier transforms are combined to produce a larger Fourier transform. An example of an optical Fourier transform device suitable for use performing these smaller Fourier transforms is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices for performing this optical Fourier transform are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit.

[0095] The four Fourier transforms 301 in Figure 3, each of size 4'vfor some positive integer N, are calculated, permuted, and then multiplied by pre-computed twiddle factors 302, the result of which is passed to a P232296GB next Fourier transform stage which performs a Fourier transform of size 4W+1. The multiplication by precomputed twiddle factors may be carried out using optical circuits such as optical combiners and / or phase / amplitude modulators or by digital processing of the FT results. The Fourier transform of size 4w+1can be carried out optically or digitally as described with reference to the smaller Fourier transforms of size 4'v. The permutation of the four Fourier transforms 301 may represent, for example, a butterfly transposition. Figure 7 is identical to Figure 3 except for that it relates to number-theoretic transforms instead of Fourier transforms. The NTTs of size 4'vin Figure 7 can be derived optically and / or digitally as described with reference to the smaller Fourier transforms of size 4'vwith reference to Figure 3.

[0096] Similarly to the other parts of the disclosure, the operations (such as permuting) described above may be implemented using (e.g., electronic and / or optical) circuitry, one or more processors, one or more signal processors, FPGAs, fixed-function circuitry or other suitable technical means.

[0097] Padding Fourier transform inputs

[0098] The algorithm / method 100 depicted in Figure 1 calculates (e.g., obtains using a Fourier transform device) Fourier transforms at step 106, and the algorithm 200 depicted in Figure 2 calculates Fourier transforms at step 204. If a Fourier transform is to be calculated for an input whose size is an odd power of two, i.e. an input of size 22iV+1for some non-negative integer N, then the input may first be padded so that its size is an even power of two, i.e. of the form 22Mfor some positive integer M.

[0099] Figure 4a depicts a first method for calculating a Fourier transform of an input 401 whose size is an odd power of two. The input 401 is of size 22iV+1for some non-negative integer N. The input 401 is padded (e.g., as described in connection with Figure 1 ) with ‘0’ bits 401 in an alternating fashion. That is:

[0100] • the first element of the padded input is equal to the first bit of the input 401 ;

[0101] • the second element of the padded input is a new ‘0’ element;

[0102] • the third element of the padded input is equal to the second element of the input 401 ;

[0103] • the fourth element of the padded input is a new ‘0’ element;

[0104] • and so on.

[0105] In other words, the odd-indexed elements of the padded input correspond to the elements of the input 401 , and the even-indexed elements of the padded input correspond to new ‘0’ elements 402. That is, the bits of the output of the padding operation correspond, alternately, to a corresponding element of the input to the padding operation and to a new ‘0’ element. Then, a Fourier transform of the padded input is calculated, yielding a Fourier transform output 403 of size 22iV+2.

[0106] The Fourier transform output 403 represents a Fourier transform (e.g., a signal or memory comprising information encoding, representing or otherwise carrying the result of said Fourier transform) of the padded input. The latter 22iV+1elements 404 of the Fourier transform output 403 are discarded, and the first 22iV+1elements of the Fourier transform output 403 are retained, forming the output 405 of the algorithm / method. The retained elements 405 represent a Fourier transform of the input 401 . Although P232296GB

[0107] Figure 4a is described in relation to Fourier transforms, the depicted method may equally be used in the context of number-theoretic transforms.

[0108] An example of an optical Fourier transform device suitable for use performing the Fourier transform of the padded input is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices for performing this optical Fourier transform are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit. All other steps in Figure 4a including the padding operation can be carried out digitally, for example using field- programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. The padding operation may alternatively be hardwired (e.g. optically hardwired) into the system by an appropriate arrangement and connection of the input channels of the Fourier transform device arranged to perform the FT step. Likewise, the retaining and discarding of bits of the Fourier transform output can be hardwired (e.g. optically hardwired) into the Fourier transform device by an appropriate arrangement and connection of the output channels of the Fourier transform device.

[0109] In at least some examples, the steps of the method may be implemented using multiple devices, for example, a first device may implement the steps prior to inputting signal into a Fourier transform device and a second device may implement the steps after obtaining signals from the Fourier transform device. In general, any method in the present disclosure may be implemented in a way where the steps of the method are split among one or more devices.

[0110] Figure 4b depicts a second method for calculating a Fourier transform of an input 411 whose size is an odd power of two. The input 411 is of size 22iV+1for some non-negative integer N. The input 411 is padded with ‘0’ elements 412, to obtain a padded input of size 22iV+2, in the following way:

[0111] • the first 22iV+1elements of the padded input correspond to the elements of the input 41 1 ; and

[0112] • the next 22iV+1elements of the padded input are new ‘0’ elements 412.

[0113] That is, a first set of consecutive elements of an output of the padding operation (e.g., as described in connection with Figure 1 ) correspond to the input to the padding operation, and the remaining elements of the output of the padding operation correspond to new ‘0’ elements. Thus, in more general terms, the padding operation of the above-described methods may comprise adding to frames of an input one or more memory or compute elements comprising all ‘0’ bits. The padding operation may be configured such that, when provided an input whose size is a power of two that is not a power of four, an output of the padding operation has size a power of four. For example, the padding operation may be used when the information in the input vector 211 does not saturate the full bit-width of the input vector (e.g., if the device implementing the method expects a vector with M memory or compute elements, but only j, j<M, memory or compute elements are provided) to “fill up” the input vector to the size expected by the device. P232296GB

[0114] A Fourier transform of the padded input is calculated (e.g., using an FT device, as described in connection with Figure 1 ), yielding a Fourier transform output 413 of size 22iV+2.

[0115] The Fourier transform output 413 represents a Fourier transform of the padded input. The odd-indexed bits of the Fourier transform output 413 are retained and the remaining bits 414 of the Fourier transform output 413 are discarded, forming the output 415 of the algorithm. The retained bits represent a Fourier transform of the input 41 1 . Although Figure 4b is described in relation to Fourier transforms, the depicted method may equally be used in the context of the number-theoretic transforms described herein.

[0116] An example of an optical Fourier transform device suitable for use performing the Fourier transform of the padded input described with reference to Figures 4a and 4b is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices for performing these optical Fourier transforms are also envisaged. In some embodiments, the Fourier transforms can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array, fixed-function circuitry, or an application-specific integrated circuit. All other steps in Figure 4a and 4b, including the padding operation and discarding / retaining operation, can be carried out digitally, for example using field-programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. The padding operation may alternatively be hardwired (e.g. optically hardwired) into the system by an appropriate arrangement and connection of the input channels of the Fourier transform device arranged to perform the FT step. Alternatively, the retaining and discarding of bits of the Fourier transform output may be hardwired (e.g. optically hardwired) into the Fourier transform device by an appropriate arrangement and connection of the output channels of the Fourier transform device.

[0117] Number-theoretic transforms from Fourier transforms

[0118] NTT operations involve non-complex inputs comprising unsigned real integers. The outputs are also non-complex unsigned real integers. Performing an NTT operation on an optical Fourier transform device is conventionally considered not possible, because the inevitable output of the optical Fourier transformation is complex, even if the input to the optical Fourier transform device is a real and / or positive and / or unsigned integer in form. Methods of the present disclosure provide a way to use an optical Fourier transform device to perform an NTT operation. NTT operations carried out using optical Fourier transform devices according to the methods of the present disclosure are performed faster and with less energy than any corresponding NTT methods carried out using digital processors. Thus, the methods of the present disclosure provide means for performing NTT calculations faster and more efficiently than on general purpose computers.

[0119] Figure 5a depicts an algorithm / method 500 for calculating a number-theoretic transform by way of calculating Fourier transforms. The algorithm / method 500 receives an input 501 comprising N integers for some positive integer N. P232296GB

[0120] At step 502, the input 501 is multiplied (e.g., using technical means, as described in connection with Figure 1 ) by a first set of pre-computed twiddle factors 503 comprising N complex numbers and then padded (e.g., using technical means, as described in connection with Figure 1 ) with ‘0’ bits, yielding an information corresponding to a first complex array 504 comprising M complex numbers, where M is a positive integer greater than or equal to 2N - 1. That is, based on the input vector, the method generates a modified input vector. The pre-computed twiddle factors 503 may correspond for instance to complex-valued trigonometric constant coefficients (e.g. of the general form = e~N~). Padding is described further in more detail in relation to Figure 5b.

[0121] At step 505, a Fourier transform of the first complex array 504 is calculated using a Fourier transform device, yielding a Fourier transform output 506 comprising information corresponding to M complex numbers.

[0122] The method thus calculates, using a Fourier transform device, a Fourier transform of the modified input vector. At step 507, the Fourier transform output 506 is multiplied by a pre-computed kernel 508 comprising M complex numbers, yielding a second complex array 509 comprising M complex numbers. In more general terms, a signal or memory processing operation corresponding to or representable by a mathematical operation is applied to the Fourier transform and to a kernel to obtain an information corresponding to a modified Fourier transform. At step 510, a Fourier transform of the second complex array 509 is calculated using a Fourier transform device, and optionally half of the bits of the resulting output are discarded, yielding an information corresponding to a third complex array 511 comprising N complex numbers. The discarding of bits from the Fourier transform of the second complex array 509 is discussed in more detail in relation to Figure 5c. At step 512, the third complex array 511 is multiplied by a second set of pre-computed twiddle factors 513 (optically or digitally) and then the imaginary component of each complex number of the third complex array 511 is discarded, yielding an output 514 comprising N integers. In other words, a processing operation corresponding to or representable by a mathematical operation is applied to the Fourier transform and to a set of complex numbers to obtain a pre-output, from which bits are possibly discarded to obtain an output. The output 514 represents a number-theoretic transform of the input 501 .

[0123] Alternatively, the input 501 may comprise complex numbers, in which case at step 510 the imaginary components of the third complex array 509 should be retained, not discarded, so that the real components and imaginary components of the third complex array 509 respectively represent the number-theoretic transforms of the real components and imaginary components of the input 501. In other words, if the input vector comprises integers, then the output step comprises outputting a subset of the pre-output, the subset comprising only the real components of each complex number of the preoutput, whereas if the input vector comprises complex numbers, then the output step comprises outputting all memory or compute elements of the pre-output. P232296GB

[0124] An example of an optical Fourier transform device suitable for use performing the Fourier transform FT at step 505 and the inverse Fourier transform iFT in Figure 5a is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices for performing this optical Fourier transform are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). That is, fixed function circuitry or dedicated hardware devices such as FPGAs or ASICs may alternatively be configured to perform the Fourier transform (also when implementing other methods disclosed herein). Such use of fixed function circuitry may allow a smaller device that uses less power than a general processing unit such as a CPU programmed to perform the same function. This can lead to the reductions in the physical size (e.g. silicon area) of the hardware and in the power consumption of the Fourier transform device. However, by using an optical Fourier transform device, the Fourier transform may be carried out many times faster even than using (other) fixed function (e.g. digital) circuitry and with far less power since the optical Fourier transform is carried out passively (for example as exemplified in the operation of the OFT devices of Figs 8a, 8b and 9).

[0125] All other steps in Figure 5a described herein can be carried out digitally, for example using field- programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. Where multiplication (e.g. by twiddle factors 503, 508 or 513) or addition is concerned, these steps may be alternatively carried out using optical circuits such as optical combiners and / or hybrid sub-systems such as electronically controlled optical phase or amplitude modulators.

[0126] In at least some examples, the steps of the method 500 may be implemented using multiple devices, for example, a first device may implement the steps prior to inputting signal into a Fourier transform device and a second device may implement the steps after obtaining signals from the Fourier transform device. In general, any method in the present disclosure may be implemented in a way where the steps of the method are split among one or more devices.

[0127] Figure 5b depicts the padding and multiplication (e.g., both as described in connection with Figure 1 ) by the first set of pre-computed twiddle factors step 502 of the algorithm depicted in Figure 5a. For each integer i between 1 and N inclusive, the ithcomplex number of the input 501 is multiplied by the ithcomplex number of the first set of pre-computed twiddle factors 503, yielding the first N complex numbers of the first array of complex numbers 504. The remaining complex numbers of the first array of complex numbers 504 are set to be equal to zero. Thus, the method may comprise multiplying the input vector by pre-computed twiddle factors and then adding to the resulting vector one or more new memory or compute elements comprising zero-valued real or complex numbers.

[0128] Figure 5c depicts the stage of the algorithm / method 500 depicted in Figure 5a that calculates (e.g., obtains using a Fourier transform device) a Fourier transform 510 of the second complex array (e.g., a P232296GB complex array represented or encoded by computer memory, a signal, or any appropriate information carrier). At step 510, a Fourier transform of the second complex array is calculated, and half of the bits of the resulting output are discarded, yielding the third complex array 51 1 comprising N complex numbers.

[0129] In particular, in Figure 5c, to form the third complex array 511 the first bit and the last - 1 bits of the Fourier transform of the second complex array 506 are retained and their values are divided by M, and the remaining bits of the Fourier transform are discarded.

[0130] Small number-theoretic transforms from small Fourier transforms

[0131] Figure 6a depicts a first algorithm / method 600a for calculating (e.g., obtaining using a Fourier transform device) a number-theoretic transform of size N from a Fourier transform of size N. The algorithm 600a receives as input 601 an array of real numbers, the input 601 comprising N(P + 1) bits. At step 602, a Fourier transform of size N is calculated for the input 601 , yielding a Fourier transform output 603 comprising a real part 604 comprising N(P + log(N) + 1) bits and an imaginary part 605 comprising ( / V / 2)(P + log N) + 1) bits. An example of an optical Fourier transform device suitable for use performing this Fourier transform is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices for performing this optical Fourier transform are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit. All other steps in Figure 6a described herein can be carried out digitally, for example using field- programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. Where multiplication or addition is concerned, these steps may be alternatively carried out using optical circuits such as optical combiners and / or phase / amplitude modulators.

[0132] In at least some examples, the steps of the method 600 may be implemented using multiple devices, for example, a first device may implement the steps prior to inputting signal into a Fourier transform device and a second device may implement the steps after obtaining signals from the Fourier transform device. In general, any method in the present disclosure may be implemented in a way where the steps of the method are split among one or more devices.

[0133] At step 606, the imaginary part 605 is multiplied by pre-computed real numbers 607 (e.g., analogously to other parts of this application, this may be implemented as using a computing element to transform a signal or computer memory corresponding to, representing, or encoding said imaginary part 605 and real number 607) comprising P + log(N) bits, and the result 608 is added at step 609 to the real part 604, yielding an output 610 of real numbers, the output 610 comprising N(2P + log N) + 1) bits. The output 610 represents a number-theoretic transform of size N of the input 601 . The sizes of the input 601 , the real part 604 and imaginary part 605 of the Fourier transform output 603, the pre-computed real numbers 607 and the output 610 are all chosen in this case so that no overflow (e.g., memory P232296GB overflow on a device implementing said method), or similar problem related to real-world implementation, occurs. In particular, the output 610 comprises more bits than the input 601 .

[0134] Figure 6b depicts a second algorithm / method 600b for calculating (e.g., obtaining using a Fourier transform device) a number-theoretic transform of size N from a Fourier transform of size N. Whereas the algorithm 600a of Figure 6a ensures that no (memory) overflow occurs by carefully choosing the sizes of the input 601 , the output 610, and variables for any intermediate calculations, the algorithm 600b of Figure 6b avoids overflow by performing modular reduction steps. Barrett modular reduction for multiplication (which occurs at steps 616 and 624 of the algorithm 600b) is discussed in more detail in relation to Figures 6c and 6d.

[0135] The algorithm / method 600b depicted in Figure 6b receives as input 611 a signal, computer memory, compute element or similar information carrier corresponding to, encoding, or representing an array of real numbers, the input 611 comprising N(P + 1) bits. At step 612, a Fourier transform of size N is calculated (e.g., obtained using a Fourier transform device) for the input 611 , yielding a Fourier transform output 613 comprising a real part 614 comprising N(P + log(N) + 1) bits and an imaginary part 615 comprising ( / V / 2)(P + logiN) + 1 bits. An example of an optical Fourier transform device suitable for use performing the Fourier transform of size N is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices for performing this optical Fourier transform are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field-programmable gate array or an application-specific integrated circuit. All other steps in Figure 6b described herein can be carried out digitally, for example using field-programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. Where multiplication or addition is concerned, these steps may be alternatively carried out using optical circuits such as optical combiners and / or hybrid sub-systems such as electronically controlled optical phase or amplitude modulators.

[0136] In at least some examples, the steps of the methods 600a and 600b may be implemented using multiple devices, for example, a first device may implement the steps prior to inputting signal into a Fourier transform device and a second device may implement the steps after obtaining signals from the Fourier transform device. In general, any method in the present disclosure may be implemented in a way where the steps of the method are split among one or more devices.

[0137] At step 616, modular reduction is performed for both the real part 614 and the imaginary part 615, yielding a reduced real part 617 comprising N(P + 1) bits and a reduced imaginary part 618 comprising ( / V / 2)(P + 1) bits. As elsewhere in this application, this may be understood as applying, using technical means, corresponding transformations to corresponding information / signal carriers. At step 619, the reduced imaginary part 618 is multiplied by pre-computed real numbers 620 comprising P bits, the multiplication being a Barrett modular reduction for multiplication, the result of which 621 is then added P232296GB at step 622 to the reduced real part 617 to form an intermediate output 623 comprising real numbers, the intermediate output 623 comprising N(P + 2) bits. At step 624, modular reduction is performed for the intermediate output 623, yielding an output 625 comprising real numbers, the output 625 comprising N(P + 1) bits. The output 625 represents a number-theoretic transform of size N of the input 611. Notably the output 625 comprises the same number of bits as the input 611 .

[0138] In another example, a number-theoretic transform may be calculated from an optical Fourier transform as follows. An input to a four-channel (e.g. optical) Fourier transform device is provided, on which a Fourier transform is performed, yielding output at the four channels, e.g. OFT CH1 , OFT CH2, OFT CH3 and OFT CH4. The Fourier transform device can take any of the forms described herein. An example of an optical Fourier transform device suitable for use performing the Fourier transform of the input is described in detail with reference to Figures 8a, 8b and 9. However, the present disclosure is not limited to these types of optical Fourier transform devices and the use of other optical Fourier transform devices for performing this optical Fourier transform are also envisaged. In some embodiments, the Fourier transform can be alternatively performed digitally via a digital (electronic) processor such as a field- programmable gate array or an application-specific integrated circuit. All other steps in the present example can be carried out digitally, for example using field-programmable gate arrays or digital electronics using known computing hardware / processors and data processing methods. Where multiplication or addition is concerned, these steps may be alternatively carried out using optical circuits such as optical combiners and / or hybrid sub-systems such as electronically controlled optical phase or amplitude modulators.

[0139] The output at each output channel represents a complex number, and therefore includes (e.g., represents or corresponds to) both a real part and an imaginary part of said complex number. Certain parts of this output may be selected for further processing. For instance, a first selected memory or compute element, OFT_1_1 , may correspond to the real component of OFT CH3, a second selected memory or compute element, OFT_1_2, may correspond to the real component of OFT CH2, a third selected memory or compute element, OFT_1_3, may correspond to the real component of OFT CH1 , and a fourth selected memory or compute element, OFT_1_4, may correspond to the imaginary component of OFT CH4. Thus, the method comprises calculating a Fourier transform of memory or compute elements of the input, the Fourier transform comprising a real part (e.g. OFT_1_2, or Real 2 of Figure 6a) and an imaginary part (e.g. OFT_1_4, or Imag 2 of Figure 6a).

[0140] The memory or compute elements selected from the (e.g. optical) Fourier transform output may then be converted into a number-theoretic transform comprising four memory or compute elements, NTT_1_1 , NTT_1_2, NTT_1_3 and NTT_1_4, as follows:

[0141] • NTT_1_1 = (OFT_1_1) % MODULUS;

[0142] • NTT_1_2 = (OFT_1_2 + (W_1 x OFT_1_4) % MODULUS) % MODULUS;

[0143] • NTT_1_3 = (OFT_1_3) % MODULUS; and

[0144] • NTT_1_4 = (OFT_1_2 - (W_1 x OFT_1_4) % MODULUS) % MODULUS; P232296GB where:

[0145] • ‘%’ denotes the modulo operation;

[0146] • ‘x’ denotes scalar multiplication;

[0147] • ‘W_1’ is a fixed constant possibly derived from twiddle factors; and

[0148] • ‘MODULUS’ is the ring modulus over which the number-theoretic transform is performed.

[0149] In other words, this method comprises the following steps. The method receives an input (e.g. Real 1 of Figure 6a). A Fourier transform of the input is then calculated using a Fourier transform device, wherein the Fourier transform comprises a real part (e.g. OFT_1_2, or Real 2 of Figure 6a) and an imaginary part (e.g. OFT_1_4, or Imag 2 of Figure 6a). The imaginary part is multiplied by a fixed constant (e.g. W_1 , or w of Figure 6a). Then, the real part is added to the imaginary part (e.g. OFT_1_2 is added to W_1 x OFT_1_4, or, referring to Figure 6a, Real 2 is added to Imag 4), the result of which forms the output of the method.

[0150] Optionally, a modulus operation is applied to the term W_1 x OFT_1_4 (or, referring to Figure 6b, a Barrett modular multiplication may be performed on Imag 3 and w) before it is added to OFT_1_2 (or Real 3 of Figure 6b) to form the sum. In other words, the method may further comprise applying a primary modulus operation to the imaginary part to provide a primary modulo result; wherein the output comprises a sum of the real part and the primary modulo result. Additionally, a modulus operation may be applied to the sum of the real part and the primary modulo result before it is output. In other words, the method may further comprise a step of applying a secondary modulus operation to the sum of: a term based at least in part on the real part and the primary modulo result to provide a first secondary modulo result. The term may be equal to the real part (e.g. OFT_1_2, or Real 2 of Figure 6b), or it may be equal to the result of applying a tertiary modulus operation to the product of the real part and a fixed constant (e.g. to the product OFT_N_2 x W_N, as appears below in the calculation of NTT_N_2, or to Real 3 of Figure 6b).

[0151] The output of the (e.g. optical) Fourier transform device may also be converted into a number-theoretic transform in the following way (for example from subsequent OFT systems or subsequent data in a multiplexed system):

[0152] • NTT_N_1 = (OFT_N_1 x W_N) % MODULUS;

[0153] • NTT_N_2 = ((OFT_N_2) x W_N) % MODULUS + (W_N x OFT_N_4) % MODULUS) % MODULUS;

[0154] • NTT_N_3 = (OFT_N_3 x W_N) % MODULUS; and

[0155] • NTT_N_4 = ((OFT_N_2) x W_N) % MODULUS - (W_N x OFT_N_4) % MODULUS) % MODULUS; where ‘W_N’ is a fixed constant possibly derived from twiddle factors.

[0156] The Fourier transform calculated (e.g., obtained using a Fourier transform device) in the two examples described immediately above may further comprise a second real part (e.g. OFT_1_1 ) and a third real P232296GB part (e.g. OFT_1_3). Thus, the method may further comprise applying a second modulus operation to a second term based at least in part on the second real part to provide a second modulo result and applying a third modulus operation to a second term based at least in part on the third real part to provide a third modulo result; wherein the output of the method comprises the second modulo result (e.g. OFT_1_1 % MODULUS), the third modulo result (e.g. OFT_1_3 % MODULUS) and the result of subtracting the primary modulo result from the real part. In some cases, the second term may be equal to the second real part (e.g. OFT_1_1 ) and the third term may be equal to the third real part (e.g. OFT_1_3). In other cases, the second term may be equal to the second real part multiplied by a fixed constant (e.g. OFT_N_1 x W_N) and the third real part may be equal to the third real part multiplied by the fixed constant (e.g. OFT_N_3 x W_N). In more general terms, the output may comprise a number- theoretic transform comprising a first memory or compute element (e.g. the second modulo result), a second memory or compute element (e.g. the first secondary modulo result) and a third memory or compute element (e.g. the third modulo result).

[0157] The output may further comprise a fourth memory or compute element, e.g. NTT_N_4. Thus, in obtaining the fourth output memory or compute element, the method may further comprise applying a secondary modulus operation to the result of subtracting the primary modulo result from the real part to provide a second secondary modulo result; wherein the output comprises the second secondary modulo result. In this case, the fourth memory or compute element may comprise the second secondary modulo result.

[0158] NTTs calculated using the above-described methods may be processed to construct higher-element NTTs. For example, to perform an 8-channel NTT, two 4-channel NTTs are multiplied by NTT twiddle factors, the result of which undergoes butterfly rearrangement, and then the rearranged data undergoes a radix-2 NTT, after which the output possibly undergoes an additional butterfly rearrangement.

[0159] Similarly, two 8-channel NTTs may be combined to form a 16-channel NTT, as follows:

[0160] • The input data undergoes a radix-2 butterfly rearrangement.

[0161] • The rearranged data undergoes a radix-2 NTT.

[0162] • The outputs of the radix-2 NTT are logically partitioned into 8-channel vectors, each of which is multiplied by NTT twiddle factors.

[0163] • The two 8-channel vectors are processed using the method described above.

[0164] • The resulting outputs may undergo an additional butterfly rearrangement.

[0165] A system implementing any of the above-described methods may operate in the physical (PHY) layer and in the media access and control (MAC) layer to perform NTT calculations from FT data obtained using any of the Fourier transform devices described herein. Such a system may comprise multiple hosts, for example HOST 1 and HOST 2, where an integer N number of channels send data from HOST 1 to HOST 2. The MAC layer may perform computations on the sent data prior to transmission of the data and subsequent to receiving the data. The MAC layer may be modified to use a faster clock in P232296GB order to perform efficient NTT computations. In particular, the MAC layer may perform, for example, butterfly rearrangement, modular addition, subtraction and multiplication, and modular reduction, and any combination thereof.

[0166] Barrett modular reduction

[0167] Figure 6c depicts a first algorithm 600c that implements Barrett reduction for multiplication. The algorithm / method 600c receives as input a first number 631 and a second number 632, each comprising N bits. At step 633, the first number 631 and the second number 632 are multiplied, yielding a first product 634 comprising 2N bits. At step 635, the first product 634 is multiplied by a pre-computed number 636 comprising N bits, the result of which is bit shifted at step 637, yielding a second product 638 comprising N bits. At step 639, the second product 638 is multiplied by a modulus 640 comprising N bits, after which at step 641 the first product 634 is subtracted from the result of multiplying the second product 638 by the modulus 640, yielding a pre-output comprising N bits. At step 642, if the pre-output is determined to be less than the modulus 640, then the pre-output forms the output 643 of the algorithm 600c; and otherwise, i.e. if the pre-output is determined to be greater than or equal to the modulus 640, then at step 644 the modulus 640 is subtracted from the pre-output, the result of which forms the output 643 of the algorithm 600c. The output 600c represents the product of the first number 631 and the second number 632.

[0168] Figure 6d depicts a second algorithm 600d that implements Barrett reduction for multiplication. The algorithm 600d receives as input a first number 651 and a second number 652, each comprising N bits. At step 653, the first number 651 and the second number 652 are multiplied, yielding a first product 654 comprising 2N bits. At step 655, the first product is bit shifted and then at step 656 it is multiplied by a pre-computed number 657 comprising N bits, the result of which is bit shifted at step 658, yielding a second product 659 comprising N bits. At step 660, the second product 659 is multiplied by a modulus 661 comprising N bits, after which at step 662 the first product 654 is subtracted from the result of multiplying the second product 659 by the modulus 661 , yielding a pre-output comprising N bits. At step 663, if the pre-output is determined to be less than the modulus 661 , then the pre-output forms the output 664 of the algorithm 600d. Otherwise, i.e. if the pre-output is determined (e.g., using a processor or circuitry) to be greater than or equal to the modulus 661 , then at step 665 the modulus 661 is subtracted from the pre-output, the result of which forms the output 664 if it is less than the modulus 661 . Otherwise the output 664 is formed by subtracting, at step 666, for a second time the modulus 661 from the pre-output. The output 664 represents the product of the first number 651 and the second number 652. Notably, no intermediate result of the algorithm / method 600d of Figure 6d comprises more than 2N bits. Given this bound on any intermediate result, a device implementing the method 600d may use registers (or analogous devices acting as intermediate memory) of size 2N, which may simplify the manufacturing and the internal structure of said device.

[0169] Figure 6e depicts a third algorithm 600e that implements Barrett reduction for multiplication (although the multiplication step is not shown explicitly). The algorithm receives as input a number t comprising P232296GB

[0170] 2N bits and two numbers m and q, each comprising N bits. The input t may correspond, for example, to the result of multiplying two / V-bit numbers. Input numbers t and m are multiplied at step 670, producing an intermediate result comprising 3N bits. The intermediate result is then bit-shifted at step 671 , yielding a number s comprising N bits. At step 672, the number s is multiplied by q, and the result is subtracted from t at step 673, yielding a pre-result. If the pre-result is smaller than q, then the preresult forms the output 674 of the algorithm 600e. Otherwise, i.e. if the pre-result is greater than or equal to q, then at step 675 the number q is subtracted from the pre-result to form the output 674 of the algorithm 600e.

[0171] Any of the methods described in relation to Figures 6c, 6d and 6e may be used to perform any one of or any combination of the modulus operations described above, including the primary modulus operation, secondary modulus operation, tertiary modulus operation, second modulus operation and third modulus operation. Each of these modulus operations may have the same divisor. In some cases, the divisor corresponds to a ring modulus of the number-theoretic transform operation. These modulus operations may perform Barrett reduction or Montgomery reduction.

[0172] The Fourier transform calculations in any of the above-described methods may be performed by a Fourier transform device that is, for example, any one or a combination of: optical means; a digital processor; a field-programmable gate array; fixed-function circuitry, or an application-specific integrated circuit.

[0173] In an example of an optical Fourier transform device (or OFT apparatus or OFT stage) suitable for use in the Fourier transform operations of any of the methods described herein, a one-dimensional (1 D) OFT device (such as an integrated photonics OFT device) can be realised in a two-dimensional structure, where the light is confined in one dimension and diffracts freely in the other two. In an example of such an OFT device, the input and output of the OFT device are arrays of input and output ports serving as the exit or entrance of waveguides or light channels. The light from each input port is diffracted into a wavefront wide enough to cover all output ports. At each output port, the contribution from each input port has the same intensity when the optical power at all the input ports is the same. The angle of the wavefront at the output array is determined by the angle of the input port, and sets the phase delay at each output port.

[0174] One way to achieve this is to have the input and output arrays arranged on the arc of a different circle, on which lies the centre of the other circle. The Fourier transform of the input array forms on the line of the second circle. For a given radius of circle and number of input ports the angular spacing of the input and output arrays can be calculated so that the output ports sample a single order of the Fourier transform of the input data.

[0175] The device will have some tolerance to how close the input and output ports need to be to the arc, with small changes in radial distance or lateral distance (but not angle) able to be compensated. If the radius P232296GB is large enough, the arc can be approximated to a straight line. ‘Large enough’ means the distance between the arc and its tangent at the edge of the zero order FT is much less than a wavelength.

[0176] Figure 8a shows a known 1 D OFT device (or Fourier transform waveguide) 800 of this type. In brief summary, Figure 8a shows a Fourier Transform slab waveguide 800 where the light is constrained in one (cartesian) dimension (z) and diffracts freely in the other two dimensions (x and y). The OFT device includes a first array 810 of input ports 81 1 , a second array 820 of output ports 821 . The second array 820 of output ports is arranged along the Fourier plane of the Fourier transform waveguide. As will be understood by the skilled person, the Fourier plane may be a plane or a curved surface at which the Fourier transformation of the light at the input ports is formed. An interference region 830 is defined in the space or volume between the first array and second array, and may include an input coupling region connecting the first input array and the diffraction region and an output coupling region connecting the diffraction region and the second output array. The interference region 830 is surrounded in the x and y plane by a boundary 841 . The boundary 841 may be directly adjacent the interference region 830 or there may be a spatial margin between at least some edges (perimeters) of the interference region 830 and the boundary 841 .

[0177] The interference region and any surrounding volume in which the light from the input ports propagates can be formed by etching or machining a block, slab or wafer of material to form the interference region and any surrounding volume within the boundary 841 (e.g. as a relief therein or as a standalone block or an embossed structure). The boundary 841 surrounding or adjacent the interference region 830 therefore includes sides (as in the minor faces of a three-dimensional slab). The interference region is constrained in the z-direction (as in the thickness direction of the slab) by faces (as in the major faces of the slab). The faces of the boundary surrounding or adjacent to the interference region 830 are exposed to the light emitted from the input ports.

[0178] The slab waveguide is any photonic waveguide and may be realised using any of the following technology or combination of:

[0179] • A slab waveguide in silicon-on-insulator (SOI)

[0180] • A photonic crystal (PhC) with or without periodic defects or sub-wavelength holes

[0181] • A slab waveguide in silicon nitride (SiN)

[0182] • A waveguide on a compound photonic technology (lll-V or ll-VI)

[0183] • Any plasmonic waveguide

[0184] • A metasurface

[0185] • Or another photonic technology

[0186] In the interference region, there may be a void or, alternatively, a (for example, homogenous) medium, and / or a medium with uniform refractive index (at least along the optical path) or engineered to have a uniform refractive index (at least along the optical path). P232296GB

[0187] The first array 810 is arranged on (or along) a first arc 810a of a first circle 810c and the second array 820 is arranged on (or along) a second arc 820a of a second circle 820c offset from the first circle. Preferably, the first circle 810c has a centre which lies on the second arc 820a and the second circle 820c has a centre which lies on the first arc 810a. Preferably, the centre of the first circle 810c lies at or near the centre of the second array 820 and the centre of the second circle 820c lies at or near the centre of the first array 810.

[0188] The first arc 810a and second arc 820a respectively define a first portion 831a and second portion 831 b of the perimeter 831 of the interference region 830. A third portion 831 c and fourth portion 831 d of the perimeter 831 join respective ends (or edges) of the first portion 831a and second portion 831 b. That is, the third portion 831 c is a virtual face which extends in a plane between a first end of the first portion 831 a and first end of the second portion 831 b, and the fourth portion 831 d is a virtual face which extends in a straight line (or a plane) between a second end of the first portion 831a and second end of the second portion 831 b. The first to fourth portions 831 a-d constitute the whole of the perimeter 831 in the x-y plane (the plane in which the input and output ports are arranged).

[0189] The input ports 81 1 are the exits (e.g. exit pupils or exit apertures) of input channels 801 , which can also be described as waveguides or coupling structures. That is, the input ports can be connected to any of the following, or combination of:

[0190] • Waveguides manufactured using the same technology, methods and / or materials as the free space Fourier Transform slab waveguide region.

[0191] • Coupling structures such as grating couplers or edge couplers, that couple in light from an external source.

[0192] • Coupling structures such as tapered couplers, that couple in light between vertically displaced waveguides (i.e. waveguides in a silicon layer coupling light into a SiN Fourier Transform slab waveguide region).

[0193] • Impedance matching structures that reduce the reflection between the free space Fourier Transform slab waveguide and any of the above.

[0194] Embodiments (e.g., of the device 800) can be used with existing photonic technology. For example, both the phase and amplitude of light in input channels 801 connected to the input ports 811 can be controlled or modulated using a transmitter in the input channel. The term transmitter when used throughout this disclosure can be any photonic modulator. It can encompass a light source or emitter (provided that it is coherent and each transmitter has some detectable or controllable phase relationship to other transmitters in the OFT apparatus); a transmitter arranged to control the transmission of (coherent) light from a light source; a modulator arranged to modulate (coherent) light from a light source; or an encoder arranged to encode a signal onto a (coherent) optical signal. That is, the transmitter can be an optical light transmitter, optical encoder, photoemitter or photomodulator, including, by way of non-limiting example, the following or a combination of:

[0195] • Mach Zehnder Modulators P232296GB

[0196] • PN modulators

[0197] • Ring modulators

[0198] • Thermal modulators

[0199] • Another photonic integrated circuit arranged to modulate an optical input signal.

[0200] The term transmitter also encompasses any of the optical encoders described with reference to Figures 2, 3a, 3b, 4a-g, 5a-f, 6a-e, 7a and 7b of WO2023170405(A1 ), the disclosure of which is hereby incorporated by reference. Protection is sought for an OFT apparatus as described herein and including such optical encoders, though the present disclosure is not limited to these types of transmitters.

[0201] The output ports 821 can be placed to sample one or more orders of the Fourier transform of the input data either as a fast Fourier transform or otherwise. Generally, the output ports are positioned to capture or sample the zero-order Fourier transform; however, in some embodiments, output ports may alternatively or in addition be positioned to capture or sample higher order Fourier transform modes, such as the first or second order.

[0202] Embodiments (e.g., of the device 800) are directed to sampling a Fast Fourier Transform. If sampling a Fast Fourier T ransform, the number of output ports used to extract data must be at least the same as the number of input ports. The maximum number of data points is the same as the number of input ports i.e. additional ports can be used to extract other orders of the Fourier transform but the extra ports will contain copies of the zero-order data and no additional information. The number of input ports 811 can be two or more up to sixteen. As will be described with reference to Figure 8b, the number of input ports in a particularly advantageous arrangement is four. However, a Fourier transform device may be configured with a number of ports different than four. In general, a particular realisation of the Fourier transform device 800 may have any number of ports and a skilled person would be able to adapt the disclosure of the present application to an FT device with any number of ports. For example, a skilled person may decide to use less than the full number of ports available on a particular Fourier transform device. In some examples, a skilled person may employ multiple Fourier transform devices to increase the number of inputs that can be processed at once.

[0203] In operation, the Fourier Transform slab waveguide is illuminated with modulated or unmodulated light at one or more of the input ports 811 .

[0204] In more detail, a light source, e.g. a solid-state semiconductor laser source (not shown), provides coherent light. The light source can be housed off-chip, in which case the light is coupled into the OFT device using a fibre and coupling said fibre via grating couplers, or edge couplers using ferrules, or V- shaped grooves. Alternatively, the light source can be packaged in the same carrier substrate with the OFT device and light coupled into the OFT device through edge couplers and photonic wire bonds. Alternatively, the light source can be integrated with the OFT device and light coupled into the OFT device through edge couplers and tapers with or without photonic wire bonds. P232296GB

[0205] Coherent light from the light source is amplified using an optical amplifier (not shown) before being split into the plurality of input channels 801 . This is achieved by either splitting coherent light from the light source off-chip and coupling in light to fibre bundles which feed the input channels or act as the input channels themselves, or using a fibre splitter, or by coupling in the light to a single channel initially, and splitting the light into input streams using cascaded MMIs or Y-branches. If using cascaded MMIs or Y- branches the input streams stem from the output of the last stacked or cascaded 1x2 splitters. The input channels 801 carry the input streams of light split from the light source to the input ports 81 1 .

[0206] The inserted modulated or unmodulated light undergoes diffraction within the interference region 830. The output ports 821 are placed on the Fourier plane, i.e. where the diffracted light forms the optical Fourier transform of the light pattern from the input ports 811 .

[0207] The input ports 81 1 bring light into the interference region 830. The light at an input port 811 has information encoded into the phase and / or amplitude of the field. The size and shape of the optical field contained within each input port 811 to the free space Fourier transform slab waveguide will define the envelope function of the Fourier transform according to the convolution theorem.

[0208] The output ports 821 are placed in the Fourier plane (which lies along the second arc 820a). Light arrives at the output ports 821 as a set of waves at a range of angles which match the relative positions of the input ports 811 . The waves from all input ports 811 sum (e.g., coherently) to form an analogue Fourier transform. The Fourier transform in the Fourier (or output) plane (which lies along the second arc 820a) contains the full Fourier transform of the light pattern at the input plane (which lies along the first arc 810a), including the input mode shape and input envelope function.

[0209] The input ports 811 and the output ports 812 may be configured to interface with one or more devices implementing the FT-device operating methods disclosed herein, for example so as to allow input and output operations with the FT device 800. For example, the input ports 811 may accept light input that is based on a signal delivered to electronics configured to provide an input interface between at least one from said one or more devices and the FT device 800. Similarly, the signal detected at output ports may be further communicated to at least one from said one or more devices, for example using an output interface.

[0210] The FT is sampled for detection by the output ports 821 , and then the detection method will determine if the solution to the Fourier Transform is analogue or digital. Light collected by the output ports 821 and channelled through the output channels connected to the output ports is detected typically using at least one receiver.

[0211] The term ‘receiver’ when used throughout the present disclosure includes any component arranged to detect the parameters of an optical signal, in particular relative or absolute amplitude (intensity), relative P232296GB or absolute phase, or both. That is, the term receiver means an optical receiver. The receiver can be analogue (connected to an analogue-to-digital converter, ADC) or digital. A receiver can include one or more (e.g. a pair of) photodiodes and said light is either detected on a single photodiode per channel or the signal is mixed with a reference beam for homodyne detection. The receiver can be a coherent detector with 90° optical hybrid for detecting the phase of the optical signal. PINs or Avalanche Photo Diodes may be used with trans impedance amplifiers. The receivers that are used to extract data for detection may preserve the amplitude of the Fourier transform, and the phase if the phase is being detected. The term receiver also encompasses any of the balanced detectors or combinations thereof described with reference to Figure 8a or 8b of W02023170405(A1 ), the disclosure of which is hereby incorporated by reference. Protection is sought for an OFT apparatus as described herein and including such balanced detector arrangements, and the associated methods of operating such an OFT apparatus, though the present disclosure is not limited to these types of receivers.

[0212] In addition to the first arc 810a and the second arc 820a, the waveguide shown in Figure 8a comprises boundaries adjacent to, and outside of, the third portion 831 c and fourth portion 831 d of the perimeter 831 interference region 830. In particular, the waveguide of Figure 8a comprises a first waveguide boundary 841 a and a second waveguide boundary 841 b. The first waveguide boundary 841a is a planar surface extending between a first end of the first arc 810a and a first end of the second arc 420a. The second waveguide boundary 841 b is a planar surface extending between a second end of the first arc 810a and a second end of the second arc 820a. The first and second waveguide boundaries 841a, 841 b may take other forms other than planar boundaries. For example, the first and second waveguide boundaries can be shaped, angled or otherwise configured to absorb or redirect stray light passing through the virtual planes 831 c, 831 d so that it does not reflect back into the interference region 830.

[0213] The interference region 830 is positioned between the input ports 811 (i.e. at the input plane of the OFT device) and the output ports 821 (i.e. at the output or Fourier plane of the OFT device). In the interference region 830, the light from the individual input ports interferes to produce a diffraction pattern. The output ports 821 are positioned to capture the diffraction pattern at the Fourier plane (though a diffraction pattern will be present throughout the interference region).

[0214] Each output port 821 is connected via an output channel 802 to an optical amplifier (not shown) and then on to a detector (which may also be described as a receiver or decoder). Each optical amplifier is arranged to amplify the respective output stream. The optical amplifiers may be semiconductor optical amplifiers (SOAs). However, embodiments are not limited thereto and other types of optical amplifier may be used. Alternatively, no optical amplifiers are used.

[0215] The value of a first complex element encoded onto each of the input streams emerging from the input ports 811 can differ between input streams so that the value of the input function varies with the positions of the input ports in the first array due to the spatial variations in the input function. P232296GB

[0216] Two variables can be used to define or approximate each of the input and output functions: (i) the relative position of the ports within the array; and (ii) the value of the complex number encoded onto the streams of light passing through (e.g. entering or exiting) the ports. It may therefore be understood that the input and output functions are each sampled versions of a continuous function, wherein the sampling resolution is determined by the aperture size of the ports and / or the port spacing or pitch.

[0217] Temporal variation in the input streams can also be applied by varying the value of the first complex element encoded onto each input stream over time. The input streams may be continuous (always on, or on for multiple cycles of a clock signal). Alternatively, the input streams may also be pulsed (intermittently on and off, optionally in sync with a clock signal). The value of the first complex elements encoded onto the input streams may change with each clock cycle so that multiple optical Fourier transforms can be carried out consecutively, frame-by-frame.

[0218] The inputs channels of one device may be arranged to receive one frame of input at a time, with the value of the bits in each frame determining the value of the input (e.g. phase and / or amplitude) at different channels. The output channels are arranged to output one frame at a time with the value of the individual output channels (e.g. phase and / or amplitude) determining the value of the bits in each output frame. Depending on the method within which the Fourier transform device is employed, the input frame may include and of the input frames to a Fourier transform step or operation in any of the methods described herein and the output frame may include any of the corresponding output frames.

[0219] For example, the input frame can include: one or more of the K frames 105 frames 109 comprising M memory or compute elements with Q” bits per memory or compute element described with reference to Figure 1 , or one or more of the k frames 203, 215 described with reference to Figure 2a or 2b, or the first or second complex array 504, 509 described with reference to Figure 5a, or the input 601 (or input 611 ) described with reference to Figures 6a (or 6b).

[0220] The output frame can include, for example: the Fourier transform output 107 or 111 described with reference to Figure 1 , or one or more of the Fourier transform outputs 205 described with reference to Figure 2a, or Fourier transform output 506 or third complex array 511 described with reference to Figure 5a, or the Fourier transform output 603 (or Fourier transform output 613) described with reference to Figures 6a (or Figure 6b).

[0221] In the example of the input frame being one of the k frames 215 of Figure 2b, each input channel is encoded with a memory or compute element 216 of the frame 215. As described with reference to Figure 2b, each memory or compute element comprises a real component 217 and an imaginary component 218. Each of the real components 217 comprises a sign bit together with n additional bits, P232296GB and similarly each of the imaginary components 218 comprises a sign bit together with n additional bits. The real and imaginary components of each memory or compute element can be encoded together onto a signal carried by one of the input channels using, for example, an encoder described with reference to Figure 3b of W02023170405(A1 ), the disclosure of which is hereby incorporated by reference.

[0222] The detector (or receiver or decoder) is arranged to detect (or decode) a second complex element encoded onto each output stream collected by the output ports 821. In, for example, the method described with reference to Figured 2a and 2b, the output comprises 2k(n + 2) bits or 2k(n + 3) bits, depending on the radix of the decomposition performed in the splitting step 202, each such output comprising k memory or compute elements with 2(nk + 3) or 2(nk + 2) bits per memory or compute element. The real and imaginary components for each of the k memory or compute elements are decoded from an output channel of the Fourier transform device using for example, the decoder described with reference to Figure 8a or 8b of W02023170405(A1 ), the disclosure of which is hereby incorporated by reference.

[0223] The terms ‘input stream’ and ‘input signal’ are used interchangeably in the present disclosure. Likewise, the terms ‘output stream’ and ‘output signal’ are used interchangeably in the present disclosure. Input streams may be carried by input channels and output streams by output channels described in the present disclosure.

[0224] The decoder is arranged to decode a second complex element from each of the output streams based on at least one characteristic of the respective output stream. A value of the at least one characteristic is detected by the decoder and translated into a form which is representative of the second complex element. In embodiments, the at least one characteristic is a phase and / or amplitude of the output stream and the value of said phase and / or amplitude is equal to or correlates with the value of the second complex element. The phase may be a phase relative to the phase of the input streams at the input ports 811 .

[0225] The OFT apparatus (or OFT device) can be any optical apparatus capable of performing an optical Fourier transform of an input optical field delivered via two or more input channels and received at a corresponding number of output channels. This can take the form of a waveguide array including N input channels, the output of which is split into N mixing channels, nth mixing channels from each input channel are then joined to form K output channels. However, a more efficient arrangement is a free- space OFT apparatus (such as described with reference to Figures 8a and 8b) in which N input channels deliver light into a free space region which allows the light from the input channels to diffract and create an interference pattern at K output channels. N is an integer of at least 2, optionally an integer multiple of 2 or 4, optionally 4. K is at least equal to N. Examples of an OFT apparatus are described with reference to Figures 1a, 1 b and 2, though the present disclosure is not limited to these examples. P232296GB

[0226] For an input vector comprising the frame of input states simultaneously present at the input channels, the full discrete optical Fourier transform of the frame of input states is derivable from the output states detected at all output channels. In this sense, the OFT apparatus is arranged to perform an operation corresponding to or representable by a discrete Fourier transform. The discrete Fourier transform satisfies equation 1 :

[0227] Xk= ^Nn=-olxn.e-1^ (Equation 1 ) where k is the index of output channel, Xkis the channel k output, n is the index of input channel, xnis the channel n input, N is the number of input channels.

[0228] Figure 8b shows a special form of the 1 D OFT device described with reference to Figure 8a.

[0229] In Figure 8b, each of the input ports are arranged on a first circular arc and each of the output ports are arranged on a second circular arc. The distance between the first and second circular arcs is equal to the radius of the first circular arc and also equal to the radius of the second circular arc. The input ports are arranged at angles On from a zeroth position on the second arc and the output ports are arranged at angles 0nfrom a zeroth position on the first arc. The zeroth position on the first arc is directly opposite the zeroth position on the second arc with respect to a virtual line bisecting the common radius of the first arc and second arc. That is, the zeroth position on the first arc and the zeroth position on the second arc lie at opposite ends of the common radius of the first arc and second arc. The angles 0nare defined (e.g., determined, possibly within an uncertainty tolerable in a particular implementation) by equation 2:

[0230] (Equation 2) wherein n is the port number, N is the total number of input ports or output ports, R is the radius and neff is the effective index of the waveguide mode. In Figure 8b, the port number n starts at -(N / 2)+1 if N is even and -((N-1 )}2 if N is odd at the lowest port, and increases in integers up to the top. The effective index of the waveguide mode neffdescribes the characteristics of guiding mode propagation in the OFT device and can be determined using methods known to those skilled in the art from the optical properties of the materials used to construct the waveguide and the dimensions of the waveguide.

[0231] The OFT device of embodiments can also take other forms other than that described with reference to Figure 8b. Embodiments include any OFT device capable of preforming a discrete Fourier transform optically. Such OFT devices satisfy the discrete Fourier transform equation (equation 1 ).

[0232] In an illustrative example, a signal processing device (e.g., an electronic circuit, a processor, a fixed- function circuit, or similar) may be configured to carry out a method with multiple input signals, of which at least one input signal will be submitted to a FT device. The signal that will be submitted to the FT device may correspond to a high precision information (e.g., information encoded using P bits). P232296GB

[0233] However, the FT device (e.g., an optical FT device) may be configured to process signals encoding low- precision information (e.g., information encoded using Q bits, Q<P). Therefore, a splitting method, for example the method described in connection with Figs. 2a and 2b, may be employed to split the input (e.g., input vector 211 ) into K smaller frames 215, each frame 215 comprising M memory or compute elements 216. Said frames can be viewed as a representation of the information that will be submitted, possibly after a signal conversion, to the input ports 811 of a Fourier transform device, such as the device 800. For example, if the FT device has 4 inputs and 4 corresponding outputs, a frame may comprise 4 memory or compute elements whose sizes (i.e. , the number of bits used to represent the information in said memory or compute element) correspond to the size for which the FT device is configured. Once the inputs are inputted to their particular input ports, this selection of input ports 811 may be used to establish the ordering of Fourier transform outputs 107, 117, 205 as described in connection with Fig. 2c. Once the FT device (e.g., the device 800) provides the output signals, the combination method as described in connection with Fig. 2c may be used to recover a signal encoding high-precision information corresponding to a Fourier transform of the high precision input information. Such a high precision information can be processed further by the signal processing device.

[0234] The memory or compute elements 216 comprised in the frame 215 may be processed by an FT device “all at once”, that is, the memory or compute elements may be input in essentially in parallel, processed essentially in parallel, and the outputs may be read out essentially in parallel. For example, if the FT device or the circuitry interfacing therewith has a clock source, the memory or compute elements 216 in the frame 215 may be all submitted at clock time Tstart and the outputs all read out at clock time Ttinish.

[0235] Figure 9 shows an optical circuit diagram for an OFT apparatus such as those described with reference to Figures 8a or 8b. The OFT apparatus includes an OFT stage 910 having input channels 901 and output channels 902, a grating coupler 903, a source channel 911 , splitters 920, combiners 930, transmitters (including modulators or encoders) 540, input channel phase controls 942, monitor channel receivers 960, monitor channel phase controls 965, output channel receivers 970, reference channel phase controls 980, reference channels 981 , a reference source channel 982, and a reference channel amplifier 990. Said optical components may be configured to interface with one or more devices (e.g., electronic circuitry), for example those configured to implement the FT-device operating methods disclosed herein.

[0236] The grating coupler 903 provides an inlet for a light source (e.g. laser) such as that described with reference to Figure 4a. The input channels 901 are branched off from a single source channel 91 1 using a series of cascaded splitters 920 and extend to the OFT apparatus. A transmitter (or encoder) 940 is provided in-line in each input channel.

[0237] A splitter 920 is provided to separate a portion of the optical input signal from the transmitter 940 via a monitor channel 961 before the transmitter signal reaches the OFT device 910. A combiner 930 combines the optical input signal from the monitor channel 961 with an optical perturbation signal P232296GB provided via a perturbation channel 962 and feeds the combined signal to the monitor channel receiver 960. The perturbation channel 962 includes one of the monitor phase controls 965.

[0238] Each output channel 902 is connected between the OFT stage 910 and a combiner 930 which combines the optical output signal from a corresponding output channel 902 with an optical reference signal from a corresponding reference channel 981 and feeds the combined optical signal into a corresponding output channel receiver 970. Each reference channel 981 includes a reference channel phase control 980. The reference channels 981 are connected via series of cascaded splitters 920 to the reference source channel 982.

[0239] Each transmitter or encoder 940 includes a modulator 941 and an input channel phase control 942. In the example of Figure 9 the modulator 941 is a modulator pair and the phase control 942 is a phase control pair on separate parallel branches of the input channel 901 . In other examples, the input channel phase control 942 is a single-phase control provided in the input channel downstream of the transmitter.

[0240] In operation, the modulator 941 in each input channel 901 modulates light from the light source to provide the optical input signal having an input state to the OFT stage 910. The phase control 942 adjusts the input state.

[0241] The phase of the light in the perturbation channel 962 is controlled by the monitor phase control 965 to produce the optical perturbation signal. The monitor channel receiver 960 detects the state of the combined optical input signal and optical perturbation signal, or just the input state if there is no perturbation light provided in the perturbation channel.

[0242] The output channels each carry the optical output signal in a corresponding output state from the OFT stage 910. The OFT stage can take the form of the OFT device described with reference to Figures 4a and 4b.

[0243] The phase of the light in the reference channels 981 is controlled by the reference channel phase controls 980 to produce the optical reference signal. The reference channel amplifier 990 controls the amplitude and / or phase of the optical reference signal. The output channel receiver 970 detects the state of the combined optical output signal and optical reference signal, or just the output state if the optical reference signal is switched off by the reference channel amplifier 990.

[0244] The term ‘state’ (e.g. input state or output state) as used in the present disclosure refers to a parameter or parameters of an optical signal, or the representation of the parameter(s) in digital or numerical form. The state may be understood to be or represent a value or a level. The parameter may include amplitude or intensity of the signal or may be phase or relative phase of the signal. The digital or numerical form may be a complex number, or a signed or unsigned real or imaginary number, or a (bit) representation thereof. P232296GB

[0245] In one implementation of an apparatus according to the present disclosure, the apparatus comprises a first optical component (for example the OFT device of Figure 4a, or the OFT stage 910 of Figure 9) arranged to perform a first signal processing operation corresponding to or representable by a mathematical operation (for example a Fourier transform or convolution) on a first set of optical input signals

[0246] The above-described methods may be performed by a system, comprising for example an optical Fourier transform apparatus and one or more processors or controllers, wherein the an (e.g. optical) Fourier transform apparatus is configured to carry out the individual Fourier transform operations described herein and the one or more processors or controllers are configured to perform any of other steps of the above-described methods (including the building up of individual Fourier transform results to produce a larger Fourier transform result), and the system comprises one or more transitory or non- transitory computer-readable medium storing instructions that when executed by the one or more processors cause the (e.g. optical) Fourier transform apparatus and the one or more processors to perform operations including any one or a combination of the above-described methods. For example, the method may be carried out using fixed-function circuitry, such as an application-specific integrated circuit (ASIC), purpose-build circuit and / or gate array, field-reconfigurable device specifically adapted to carry out the method (e.g., an FPGA wherein the internal gate array has been configured to carry out the method).

[0247] In an aspect, the present disclosure provides a computer-readable medium storing data which corresponds to a digital representation of a gate array or a signal-processing circuit configured to carry out any of the methods disclosed herein and operating instructions adapted to configure a configurable signal processing apparatus to obtain a device configured to carry out any of the methods disclosed herein when said data is relayed to the configurable signal processing apparatus or to a device configured for configuration thereof. The configurable signal processing apparatus may comprise a field- programmable gate array (FPGA), a complex programmable logic device (CPLD), or a programmable array logic (PAL) device. That is, as an alternative to the use of general-purpose processors, such as CPUs, fixed function circuitry or dedicated hardware devices may be configured to any other parts of the methods described in the present disclosure. Processing logic implemented in the fixed function circuitry may be arranged to carry out either the method steps (other than the Fourier transform steps or in addition to the Fourier transform steps) of any of the methods described in the present disclosure. That is, fixed function circuitry or dedicated hardware devices such as FPGAs or ASICs may alternatively be configured to perform steps of the methods described herein other than the Fourier transform. Such use of fixed function circuitry may allow a smaller device that uses less power than a general processing unit such as a CPU programmed to perform the same function. This can lead to the reductions in the physical size (e.g. silicon area) of the hardware and in the overall power consumption compared with use of a general-purpose processor. Fixed function circuitry may comprise an arrangement of gates, P232296GB transistors and / or registers that achieve a specific function, namely the steps of the methods of the present disclosure.

[0248] The methods of the present disclosure may comprise performing the methods on input vectors forming at least part of encrypted data. In some applications, such as fully homomorphic encryption, the methods of the present disclosure are fixed and are used repeatedly independently of the data to be processed. Fixed function circuitry lends itself well to these methods since the operations often do not need to be reprogrammed and can run indefinitely without software intervention. Thus, the use of fixed function circuitry and dedicated hardware and processing logic implemented therein can reduce the size of devices arranged to perform operations on encrypted data. Furthermore, the power requirements of such operations can be reduced due to the reduction in complexity and power consumption of such dedicated or fixed-function hardware.

[0249] In an aspect, the present disclosure provides a method to manufacture an application-specific circuit or a fixed-function circuit, said circuit configured to interface with a Fourier transform device, wherein the circuit is configured to carry out at least a part of any of the methods disclosed in the present disclosure.

[0250] The methods as disclosed herein may be computer-implemented and / or circuitry-implemented. For example, a general-purpose computer or a processor may be adapted to interface with an FT device (for example, an optical FT device), thus creating a non-conventional computing system, and to carry out the methods disclosed herein by using the FT device. The methods disclosed herein may be implemented in circuitry adapted to interface with the FT device. Said circuitry may comprise one or more fixed-function parts configured to carry out any of the methods disclosed herein, one or more field- programmable gate arrays, one or more complex programmable logic devices, one or more programmable array logic devices, or any other suitable part that can be manufactured, configured, and / or caused to assume a configuration to carry out the method disclosed herein. In a concrete illustrative example, the method may be implemented using a fixed-function electronic circuit. The methods may be implemented using a device employing any signal carrier known to a skilled person. In an example, the methods may be implemented using electronics, optics, spintronics, or any other physical phenomena known to a skilled person useful to carry, encode and / or process signals.

[0251] A skilled person, aware of the usefulness of mathematics in describing signal-processing operations, would understand the steps of the present disclosure to teach a signal-processing method that is essentially equivalent to any mathematical or mental operation described herein. For example, a skilled person would understand that the phrase “compute a (discrete) Fourier transform of a sequence” comprises using a device adapted to receive a signal encoding said sequence and to transform said signal to a second signal encoding a Fourier transform of said sequence to obtain said second signal or a signal based thereon. Similarly, a skilled person would understand that any steps describing storing, manipulating, and / or transferring information may comprise an implementation of these operations in computer memory. For example, an input vector 211 may correspond to a chunk of computer memory, P232296GB while the memory or compute elements 212 may correspond to one or more sub-chunks of said chunk. Likewise, the padding as described, for example, in connection with Fig. 1 may comprise manipulating an information stored in computer memory by adding additional bits to the in-memory representation of said information (in other words, expanding and padding the bit-array encoding said information).

[0252] Although methods described herein are best suited to being implemented in dedicated hardware, the steps of the methods for operating a Fourier transform device (other than the Fourier transform step itself, for example, the step (internal to the Fourier transform device) of optical Fourier transform using diffraction phenomena, as described in connection with Figure 8a and 8b) could be implemented in software running on general purpose hardware. Therefore, there may be provided computer program code for performing any of the methods described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform any of the methods described herein.

[0253] The word “algorithm”, as used in the present disclosure, may be understood as a synonym of the word “method”.

[0254] The phrase “compute element” shall be understood as any technical element that may be used in the art of computation using technical means. A “compute element” may comprise any device or phenomenon, tangible or non-tangible, which may store and / or retain, transiently or non-transiently, any information used in computation, using any encoding or representation known to a skilled person.

[0255] It will be appreciated by those skilled in the art that various modifications and alterations could be made to disclosure above without departing from the concepts defined in the appended claims. Some implementations have been discussed above and others will be apparent to those skilled in the art. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications and variants within the scope of the appended claims.

[0256] Also described herein are the following numbered clauses:

[0257] Clause 1 . A method for performing a Fourier transform, comprising: receiving an input vector comprising N elements each comprising P bits; generating, based on the input vector, a first and a second frame, wherein each of the first and second frames comprises elements each comprising Q bits, wherein Q < P; calculating, using a Fourier transform device, a first Fourier transform of the first frame and a second Fourier transform of the second frame; and combining, to obtain a Fourier transform of the input vector, a first part and a second part, wherein the first part is based on the first Fourier transform and the second part is based on the second Fourier transform. P232296GB

[0258] Clause 2. The method of clause 1 , wherein generating the first and second frames comprises performing a radix-2 or radix-4 decomposition of the input vector.

[0259] Clause 3. The method of clause 1 or 2, wherein each element of the first frame comprises a subset of the bits of a corresponding element of the input vector, and wherein each element of the second frame comprises a subset of the P bits of a corresponding element of the input vector.

[0260] Clause 4. The method of clause 3, wherein: the P bits of each element of the input vector are partitioned into k subsets of consecutive bits for some positive integer k; each subset of each element of the first frame corresponds to a first subset of the k subsets that partition the corresponding element of the input vector; and each subset of each element of the second frame corresponds to a second subset of the k subsets that partition the corresponding element of the input vector.

[0261] Clause 5. The method of clause 4, wherein the first subset comprises one or more of the most significant bits of the corresponding element and the second subset comprises one or more of the most significant bits that do not belong to the first subset.

[0262] Clause 6. The method of clause 4 or 5, wherein k = 2 or k = 4.

[0263] Clause 7. The method of any preceding clause, wherein, subsequent to calculating the first and second Fourier transforms, each of the first and second frames is multiplied by a set of pre-computed twiddle factors and then padded.

[0264] Clause 8. The method of clause 7, wherein the padding operation comprises adding to each of the first and second frames one or more elements comprising all ‘0’ bits.

[0265] Clause 9. The method of clause 7 or 8, wherein the padding operation is configured such that, when provided an input whose size is a power of two that is not a power of four, an output of the padding operation has size a power of four.

[0266] Clause 10. The method of any of clauses 7-9, wherein bits of an output of the padding operation correspond, alternately, to a corresponding bit of the input to the padding operation and to a new ‘0’ bit.

[0267] Clause 11 . The method of any of clauses 7-9, wherein a first set of consecutive bits of an output of the padding operation correspond to the input to the padding operation, and wherein the remaining bits of the output correspond to new ‘0’ bits. P232296GB

[0268] Clause 12. The method of any preceding clause, wherein subsequent to calculating and prior to combining the first and second parts, each of the first and second Fourier transforms is modified by performing, in the recited order, the following steps: multiplication by a kernel; calculation, using a Fourier transform device, of an inverse Fourier transform; multiplication by twiddle factors; quantization; and rescaling.

[0269] Clause 13. The method of clause 12, wherein quantization comprises applying a bit shift operation to each element of each of the modified first and second Fourier transforms.

[0270] Clause 14. The method of clause 12 or 13, wherein rescaling comprises applying a bit shift operation to each element of each of the modified first and second Fourier transforms.

[0271] Clause 15. The method of clause 14 when dependent on clause 13, wherein the bit shift operation applied for rescaling is in a direction different to the direction of the bit shift operation applied for quantization.

[0272] Clause 16. The method of any of clauses 1-11 , wherein the first part is equal to the first Fourier transform and the second part is equal to the second Fourier transform.

[0273] Clause 17. The method of any of clauses 12-15, wherein the first part is equal to the modified first Fourier transform and the second part is equal to the modified second Fourier transform.

[0274] Clause 18. The method of any preceding clause, wherein combining the first and second parts comprises: bit-shifting the bits of at least one of the first and second parts, and then performing a bitwise sum of the bit-shifted part and the other of the first and second parts to obtain the Fourier transform of the input vector.

[0275] Clause 19. A method for performing a number-theoretic transform, comprising: receiving an input vector; generating, based on the input vector, a modified input vector; calculating, using a Fourier transform device, a first Fourier transform of the modified input vector; applying a mathematical operation to the first Fourier transform and to a kernel to obtain a modified Fourier transform; calculating, using a Fourier transform device, a second Fourier transform of the modified Fourier transform; P232296GB applying a mathematical operation to the modified second Fourier transform and to a set of complex numbers to obtain a pre-output; and outputting the pre-output or a subset thereof.

[0276] Clause 20. The method of clause 19, wherein generating the modified input vector comprises: multiplying the input vector by pre-computed twiddle factors and then adding to the resulting vector one or more new elements comprising zero-valued real or complex numbers.

[0277] Clause 21 . The method of clause 19 or 20, wherein: the input vector comprises either N integers or N complex numbers; the pre-computed kernel comprises N complex numbers; and the modified input vector comprises M complex numbers for some integer M > N each of the first N complex numbers of the modified input vector corresponds to a product of an element of the input vector and an element of the pre-computed kernel divided by M; and the remaining complex numbers of the modified input vector are zero vectors.

[0278] Clause 22. The method of any of clauses 19-21 , wherein: if the input vector comprises integers, then the output step comprises outputting a subset of the pre-output, the subset comprising only the real components of each complex number of the pre-output; and if the input vector comprises complex numbers, then the output step comprises outputting all elements of the pre-output.

[0279] Clause 23. The method of any of clauses 19-22, wherein subsequent to calculating the second Fourier transform and before applying the mathematical operation, the method further comprises discarding one or more elements of the second Fourier transform to obtain a modified second Fourier transform.

[0280] Clause 24. The method of clause 23, wherein discarding the one or more elements of the second Fourier transform comprises discarding: the first element of the second Fourier transform; and the last M — N — 1 elements of the second Fourier transform.

[0281] Clause 25. The method of any of clauses 19-24, wherein the steps of calculating the Fourier transforms are performed according to a method of any of clauses 1-18.

[0282] Clause 26. A method for performing a number-theoretic transform, the method comprising: receiving an input; calculating a Fourier transform of N elements of the input, the Fourier transform comprising a real part and an imaginary part; multiplying the imaginary part by a fixed constant, yielding a modified imaginary part; and P232296GB providing an output comprising a sum of the real part and the modified imaginary part.

[0283] Clause 27. The method of clause 26, wherein the method further comprises, prior to the outputting step, applying a primary modulus operation to the modified imaginary part to provide a primary modulo result; wherein the output comprises a sum of the real part and the primary modulo result.

[0284] Clause 28. The method of clause 26 or 27, further comprising applying a secondary modulus operation to the sum of: a term based at least in part on the real part and the primary modulo result to provide a first secondary modulo result.

[0285] Clause 29. The method of clause 28, wherein the term is equal to the real part.

[0286] Clause 30. The method of clause 28, wherein the term is equal to the result of applying a tertiary modulus operation to the product of the real part and a fixed constant.

[0287] Clause 31. The method of any of clauses 26-30, wherein the Fourier transform further comprises a second real part and a third real part, the method further comprising: applying a second modulus operation to a second term based at least in part on the second real part to provide a second modulo result and applying a third modulus operation to a third term based at least in part on the third real part to provide a third modulo result; and wherein the output comprises the second modulo result, the third modulo result and the result of subtracting the primary modulo result from the real part.

[0288] Clause 32. The method of clause 31 , wherein: the second term is equal to the second real part, and the third term is equal to the third real part.

[0289] Clause 33. The method of clause 31 , wherein: the second term is equal to the second real part multiplied by a fixed constant, and the third term is equal to the third real part multiplied by the fixed constant.

[0290] Clause 34. The method of clause 33, wherein the fixed constant is derived from twiddle factors.

[0291] Clause 35. The method of any of clauses 31-34, further comprising applying a secondary modulus operation to the result of subtracting the primary modulo result from the real part to provide a second secondary modulo result; wherein the output comprises the second secondary modulo result. P232296GB

[0292] Clause 36. The method of clause 35, wherein the output comprises a number-theoretic transform comprising: a first element comprising the second modulo result; a second element comprising the first secondary modulo result; a third element comprising the third modulo result; and a fourth element comprising the second secondary modulo result.

[0293] Clause 37. The method of clause 35 or 36, wherein each of the primary modulus operation, secondary modulus operation, tertiary modulus operation, second modulus operation and third modulus operation have the same divisor.

[0294] Clause 38. The method of clause 37, wherein the divisor corresponds to a ring modulus of the number- theoretic transform operation.

[0295] Clause 39. The method of clause 37 or 38, wherein each of the primary modulus operation, secondary modulus operation, tertiary modulus operation, second modulus operation and third modulus operation performs Barrett reduction or Montgomery reduction.

[0296] Clause 40. The method of clause 26, wherein N is a positive integer or a power of 2, or wherein N is equal to 4.

[0297] Clause 41 . The method of clause 26 or 40, wherein, if N = 4: the input comprises 4(P + 1) bits; the real part comprises 4(P + 3) bits; the imaginary part comprises 2(P + 3) bits; the fixed constant comprises P + 2 bits; and the sum of the real part and the modified imaginary part comprises 4(2P + 3) bits.

[0298] Clause 42. The method of any of clauses 26, 40 and 41 , wherein, subsequent to calculating the Fourier transform, the method comprises applying a modular reduction operation to each of the real and imaginary parts of the Fourier transform.

[0299] Clause 43. A method for calculating a number-theoretic transform of size a multiple of two, the method comprising: calculating, using a method according to any of clauses 1-18, first and second Fourier transforms of size four; multiplying, by pre-computed twiddle factors, each of the first and second Fourier transforms, yielding modified first and second Fourier transforms; permuting the modified first and second Fourier transforms; and P232296GB providing, as input to a Fourier transform stage, the modified first and second Fourier transforms.

[0300] Clause 44. The method of clause 43, wherein the multiple of two is a power of four and / or wherein the size of the input to the Fourier transform stage is a power of four.

[0301] Clause 45. The method of any preceding clause, wherein the Fourier transform device is any one or a combination of: an optical Fourier transform device; a digital processor; a field-programmable gate array; an application-specific integrated circuit.

[0302] Clause 46. A system, comprising: an optical Fourier transform device; and one or more processors or controllers; wherein: the one or more processors or controllers and the optical Fourier transform device are together configured to perform the method of any of clauses 1-45, or the system comprises one or more transitory or non-transitory computer-readable media storing instructions that when executed by the one or more processors cause the one or more processors to perform operations including the method of any of clauses 1 -45.

[0303] Clause 47. One or more tangible or non-tangible, transitory or non-transitory computer-readable media storing computer-readable instructions that when executed by one or more processors or controllers, cause the one or more processors or controllers to perform operations including the method of any of clauses 1-45.

[0304] Also described herein are the following numbered embodiments:

[0305] Embodiment 1 . A method for performing a number-theoretic transform, comprising: receiving an input vector; generating, based on the input vector, a modified input vector; calculating, using a Fourier transform device, a first Fourier transform of the modified input vector; applying a mathematical operation to the first Fourier transform and to a kernel to obtain a modified Fourier transform; calculating, using the or another Fourier transform device, a second Fourier transform of the modified Fourier transform; applying a mathematical operation to the modified second Fourier transform and to a set of complex numbers to obtain a pre-output; and outputting the pre-output or a subset thereof. P232296GB

[0306] Embodiment 2. The method of embodiment 1 , wherein generating the modified input vector comprises: multiplying the input vector by pre-computed twiddle factors and then adding to the resulting vector one or more new elements comprising zero-valued real or complex numbers.

[0307] Embodiment 3. The method of embodiment 1 or 2, wherein: the input vector comprises either N integers or N complex numbers; the pre-computed kernel comprises N complex numbers; and the modified input vector comprises M complex numbers for some integer M > N each of the first N complex numbers of the modified input vector corresponds to a product of an element of the input vector and an element of the pre-computed kernel divided by M; and the remaining complex numbers of the modified input vector are zero vectors.

[0308] Embodiment 4. The method of any of embodiments 1-3, wherein: if the input vector comprises integers, then the output step comprises outputting a subset of the pre-output, the subset comprising only the real components of each complex number of the pre-output; and if the input vector comprises complex numbers, then the output step comprises outputting all elements of the pre-output.

[0309] Embodiment 5. The method of any of embodiments 1-4, wherein subsequent to calculating the second Fourier transform and before applying the mathematical operation, the method further comprises discarding one or more elements of the second Fourier transform to obtain a modified second Fourier transform.

[0310] Embodiment 6. The method of embodiment 5, wherein discarding the one or more elements of the second Fourier transform comprises discarding: the first element of the second Fourier transform; and the last M — N — 1 elements of the second Fourier transform.

[0311] Embodiment 7. A method for performing a number-theoretic transform using a Fourier transform device, the method comprising: receiving an input; calculating, using the Fourier transform device, a Fourier transform of N elements of the input, the Fourier transform comprising a real part and an imaginary part; multiplying the imaginary part by a fixed constant, yielding a modified imaginary part; and providing an output comprising a sum of the real part and the modified imaginary part.

[0312] Embodiment 8. The method of embodiment 7, wherein the method further comprises, prior to the outputting step, applying a primary modulus operation to the modified imaginary part to provide a primary modulo result; wherein the output comprises a sum of the real part and the primary modulo result. P232296GB

[0313] Embodiment 9. The method of embodiment 7 or 8, further comprising applying a secondary modulus operation to the sum of: a term based at least in part on the real part and the primary modulo result to provide a first secondary modulo result.

[0314] Embodiment 10. The method of embodiment 9, wherein the term is equal to the real part.

[0315] Embodiment 11. The method of embodiment 9, wherein the term is equal to the result of applying a tertiary modulus operation to the product of the real part and a fixed constant.

[0316] Embodiment 12. The method of any of embodiments 7-11 , wherein the Fourier transform further comprises a second real part and a third real part, the method further comprising: applying a second modulus operation to a second term based at least in part on the second real part to provide a second modulo result and applying a third modulus operation to a third term based at least in part on the third real part to provide a third modulo result; and wherein the output comprises the second modulo result, the third modulo result and the result of subtracting the primary modulo result from the real part.

[0317] Embodiment 13. The method of embodiment 12, wherein: the second term is equal to the second real part, and the third term is equal to the third real part

[0318] Embodiment 14. The method of embodiment 12, wherein: the second term is equal to the second real part multiplied by a fixed constant, and the third term is equal to the third real part multiplied by the fixed constant.

[0319] Embodiment 15. The method of embodiment 14, wherein the fixed constant is derived from twiddle factors.

[0320] Embodiment 16. The method of any of embodiments 12-15, further comprising applying a secondary modulus operation to the result of subtracting the primary modulo result from the real part to provide a second secondary modulo result; wherein the output comprises the second secondary modulo result.

[0321] Embodiment 17. The method of embodiment 16, wherein the output comprises a number-theoretic transform comprising: a first element comprising the second modulo result; a second element comprising the first secondary modulo result; a third element comprising the third modulo result; and P232296GB a fourth element comprising the second secondary modulo result.

[0322] Embodiment 18. The method of embodiment 16 or 17, wherein each of the primary modulus operation, secondary modulus operation, tertiary modulus operation, second modulus operation and third modulus operation have the same divisor.

[0323] Embodiment 19. The method of embodiment 18, wherein the divisor corresponds to a ring modulus of the number-theoretic transform operation.

[0324] Embodiment 20. The method of embodiment 18 or 19, wherein each of the primary modulus operation, secondary modulus operation, tertiary modulus operation, second modulus operation and third modulus operation performs Barrett reduction or Montgomery reduction.

[0325] Embodiment 21. The method of embodiment 7, wherein N is a positive integer or a power of 2, or wherein N is equal to 4.

[0326] Embodiment 22. The method of embodiment 7 or 21 , wherein, if N = 4: the input comprises 4(P + 1) bits; the real part comprises 4(P + 3) bits; the imaginary part comprises 2(P + 3) bits; the fixed constant comprises P + 2 bits; and the sum of the real part and the modified imaginary part comprises 4(2P + 3) bits.

[0327] Embodiment 23. The method of any of embodiments 7, 21 or 22, wherein, subsequent to calculating the Fourier transform, the method comprises applying a modular reduction operation to each of the real and imaginary parts of the Fourier transform.

[0328] Embodiment 24. The method of any preceding embodiment, wherein the Fourier transform device is any one or a combination of: an optical Fourier transform device; a fixed function circuitry; a field- programmable gate array; an application-specific integrated circuit.

[0329] Embodiment 25. A system, comprising: an optical Fourier transform device; and one or more processors or controllers; wherein: the one or more processors or controllers and the optical Fourier transform device are together configured to perform the method of any of embodiments 1-24, or P232296GB the system comprises one or more transitory or non-transitory computer-readable media storing instructions that when executed by the one or more processors cause the one or more processors to perform operations including the method of any of embodiments 1-24.

[0330] Embodiment 26. One or more tangible or non-tangible, transitory or non-transitory computer-readable media storing computer-readable instructions that when executed by one or more processors or controllers, cause the one or more processors or controllers to perform operations including the method of any of embodiments 1-24.

Claims

CLAIMS1. A method for performing a number-theoretic transform using one or more optical Fourier transform devices, comprising: receiving an input vector; generating, based on the input vector, a modified input vector; calculating, using a first optical Fourier transform device, a first Fourier transform of the modified input vector; applying a mathematical operation to the first Fourier transform and to a kernel to obtain a modified Fourier transform; calculating, using the first or a second optical Fourier transform device, a second Fourier transform of the modified Fourier transform; applying a mathematical operation to the modified second Fourier transform and to a set of complex numbers to obtain a pre-output; and outputting the pre-output or a subset thereof.

2. The method of claim 1 , wherein generating the modified input vector comprises: multiplying the input vector by pre-computed twiddle factors and then adding to the resulting vector one or more new elements comprising zero-valued real or complex numbers.

3. The method of claim 1 or 2, wherein: the input vector comprises either N integers or N complex numbers; the pre-computed kernel comprises N complex numbers; and the modified input vector comprises M complex numbers for some integer M > N each of the first N complex numbers of the modified input vector corresponds to a product of an element of the input vector and an element of the pre-computed kernel divided by M; and the remaining complex numbers of the modified input vector are zero vectors.

4. The method of any of claims 1-3, wherein: if the input vector comprises integers, then the output step comprises outputting a subset of the pre-output, the subset comprising only the real components of each complex number of the pre-output; and if the input vector comprises complex numbers, then the output step comprises outputting all elements of the pre-output.

5. The method of any of claims 1-4, wherein subsequent to calculating the second Fourier transform and before applying the mathematical operation, the method further comprises discarding one or more elements of the second Fourier transform to obtain a modified second Fourier transform.

6. The method of claim 5, wherein discarding the one or more elements of the second Fourier transform comprises discarding: the first element of the second Fourier transform; and the last M — N — 1 elements of the second Fourier transform.

7. A method for performing a number-theoretic transform using an optical Fourier transform device, the method comprising: receiving an input; calculating, using the optical Fourier transform device, a Fourier transform of N elements of the input, the Fourier transform comprising a real part and an imaginary part; multiplying the imaginary part by a fixed constant, yielding a modified imaginary part; and providing an output comprising a sum of the real part and the modified imaginary part.

8. The method of claim 7, wherein the method further comprises, prior to the outputting step, applying a primary modulus operation to the modified imaginary part to provide a primary modulo result; wherein the output comprises a sum of the real part and the primary modulo result.

9. The method of claim 7 or 8, further comprising applying a secondary modulus operation to the sum of: a term based at least in part on the real part and the primary modulo result to provide a first secondary modulo result.

10. The method of claim 9, wherein the term is equal to the real part.11 . The method of claim 9, wherein the term is equal to the result of applying a tertiary modulus operation to the product of the real part and a fixed constant.

12. The method of any of claims 7-11 , wherein the Fourier transform further comprises a second real part and a third real part, the method further comprising: applying a second modulus operation to a second term based at least in part on the second real part to provide a second modulo result and applying a third modulus operation to a third term based at least in part on the third real part to provide a third modulo result; and wherein the output comprises the second modulo result, the third modulo result and the result of subtracting the primary modulo result from the real part.

13. The method of claim 12, wherein: the second term is equal to the second real part, and the third term is equal to the third real part14. The method of claim 12, wherein: the second term is equal to the second real part multiplied by a fixed constant, and the third term is equal to the third real part multiplied by the fixed constant.

15. The method of claim 14, wherein the fixed constant is derived from twiddle factors.

16. The method of any of claims 12-15, further comprising applying a secondary modulus operation to the result of subtracting the primary modulo result from the real part to provide a second secondary modulo result; wherein the output comprises the second secondary modulo result.

17. The method of claim 16, wherein the output comprises a number-theoretic transform comprising: a first element comprising the second modulo result; a second element comprising the first secondary modulo result; a third element comprising the third modulo result; and a fourth element comprising the second secondary modulo result.

18. The method of claim 16 or 17, wherein each of the primary modulus operation, secondary modulus operation, tertiary modulus operation, second modulus operation and third modulus operation have the same divisor.

19. The method of claim 18, wherein the divisor corresponds to a ring modulus of the number-theoretic transform operation.

20. The method of claim 18 or 19, wherein each of the primary modulus operation, secondary modulus operation, tertiary modulus operation, second modulus operation and third modulus operation performs Barrett reduction or Montgomery reduction.21 . The method of claim 7, wherein N is a positive integer or a power of 2, or wherein N is equal to 4.

22. The method of claim 7 or 21 , wherein, if N = 4: the input comprises 4(P + 1) bits; the real part comprises 4(P + 3) bits; the imaginary part comprises 2(P + 3) bits; the fixed constant comprises P + 2 bits; and the sum of the real part and the modified imaginary part comprises 4(2P + 3) bits.

23. The method of any of claims 7, 21 or 22, wherein, subsequent to calculating the Fourier transform, the method comprises applying a modular reduction operation to each of the real and imaginary parts of the Fourier transform.

24. The method of any preceding claim, wherein the Fourier transform device is any one or a combination of: an optical Fourier transform device; a digital processor; a field-programmable gate array; an application-specific integrated circuit.

25. A system, comprising: an optical Fourier transform device; and one or more processors or controllers; wherein: the one or more processors or controllers and the optical Fourier transform device are together configured to perform the method of any of claims 1-24, or the system comprises one or more transitory or non-transitory computer-readable media storing instructions that when executed by the one or more processors cause the one or more processors to perform operations including the method of any of claims 1-24.

26. One or more tangible or non-tangible, transitory or non-transitory computer-readable media storing computer-readable instructions that when executed by one or more processors or controllers, cause the one or more processors or controllers to perform operations including the method of any of claims 1 -24.

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