Semiconductor module

Abstract

This semiconductor module comprises a first functional element, a second functional element, a lead frame, and a board unit. The function of a first electrode of the first functional element is different from the function of a third electrode of the second functional element. A board electrode includes: a first element connecting portion connected to a second electrode of the first functional element; a second element connecting portion connected to the fourth electrode of the second functional element; and an electrode lead-out portion which is led out from at least one of the first element connecting portion and the second element connecting portion and through which a current flowing toward the first element connecting portion or a current emitted from the second element connecting portion flows. The lead frame includes: a first element connecting region connected to the first electrode of the first functional element; a second element connecting region connected to the third electrode of the second functional element; a first current path region disposed between the first element connecting region and the second element connecting region; and a second current path region disposed in a position facing the electrode lead-out portion along a normal direction.

Description

Semiconductor module

[0001] This disclosure relates to a semiconductor module.

[0002] In recent years, attention has been focused on so-called power functional elements that handle large currents. As a method for reducing the loss of a semiconductor module including a power functional element, a method of increasing the switching speed of the semiconductor module is known. The higher the switching speed of the semiconductor module, the larger the surge voltage. Therefore, in order not to exceed the breakdown voltage of the power functional element inside the semiconductor module, a measure is generally taken to reduce the switching speed to a certain extent to reduce the surge voltage. In order to reduce the surge voltage while increasing the switching speed, it is effective to reduce the parasitic inductance inside the semiconductor module.

[0003] Patent Documents 1 to 3 disclose techniques for reducing the parasitic inductance inside a semiconductor module. The semiconductor device described in Patent Document 1 includes two lead frames through which currents flowing in opposite directions flow. These lead frames are respectively connected to two semiconductor elements and are arranged side by side so as to be close to each other along the lateral direction. The semiconductor device described in Patent Document 2 includes a first internal conductor pattern and a second internal conductor pattern that are connected to electrical components and through which currents flowing in opposite directions flow. These conductor patterns face each other while being vertically close to each other inside the substrate body. The semiconductor device disclosed in Patent Document 3 includes a high-voltage bus bar connected by wire bonding to one surface of a semiconductor chip, a first metal wiring board connected by wire bonding to the other surface of the semiconductor chip, a low-voltage bus bar connected by wire bonding to one surface of another semiconductor chip, and a second metal wiring board connected by wire bonding to the other surface of another semiconductor chip.

[0004] Japanese Unexamined Patent Application Publication No. 2022-181823, Japanese Unexamined Patent Application Publication No. 2022-154937, Japanese Unexamined Patent Application Publication No. 2007-329427

[0005] In semiconductor modules as described above, further reduction of parasitic inductance is required to reduce losses. Furthermore, since semiconductor modules perform desired circuit functions by interconnecting multiple power functional elements, the wiring structure for connecting these elements tends to become complex. Therefore, there is a need to simplify semiconductor modules.

[0006] This disclosure describes a semiconductor module that can reduce losses with a simple structure.

[0007] A semiconductor module according to one embodiment of the present invention includes a first functional element including a first electrode and a second electrode positioned opposite the first electrode, a second functional element including a third electrode and a fourth electrode positioned opposite the third electrode, a lead frame to which the first electrode of the first functional element is connected and to which the third electrode of the second functional element is connected, and a substrate unit including a substrate electrode on the main surface of the substrate to which the second electrode of the first functional element is connected and to which the fourth electrode of the second functional element is connected. The function of the first electrode of the first functional element is different from the function of the third electrode of the second functional element. The substrate electrode includes a first element connection portion connected to the second electrode of the first functional element, a second element connection portion connected to the fourth electrode of the second functional element, and an electrode lead portion drawn out from at least one of the first element connection portion and the second element connection portion, through which a current flows toward the first element connection portion or a current is discharged from the second element connection portion. The lead frame includes: a first element connection region connected to the first electrode of a first functional element to which current is input from the first functional element; a second element connection region connected to the third electrode of a second functional element to which the current input to the first element connection region is output; a first current path region positioned between the first element connection region and the second element connection region, through which the first current of the current input to the first element connection region flows toward the second element connection region; and a second current path region positioned opposite the electrode lead portion along the normal direction of the main surface of the substrate, through which the second current of the current input to the first element connection region flows toward the second element connection region via a path different from the first current flowing through the first current path region.

[0008] The semiconductor module disclosed herein can reduce losses with a simple structure.

[0009] Figure 1 is a cross-sectional view of a semiconductor module according to the first embodiment. Figure 2 is a diagram showing the circuit formed by the semiconductor module of Figure 1. Figure 3 is a plan view of the semiconductor module of Figure 1. Figure 4 is a cross-sectional view showing a first modified example of the semiconductor module of Figure 1. Figure 5 is a cross-sectional view showing a second modified example of the semiconductor module of Figure 1. Figure 6 is a cross-sectional view showing a third modified example of the semiconductor module of Figure 1. Figure 7 is a cross-sectional view showing a fourth modified example of the semiconductor module of Figure 1. Figure 8 is a cross-sectional view showing a fifth modified example of the semiconductor module of Figure 1. Figure 9 is a plan view showing a sixth modified example of the semiconductor module of Figure 1. Figure 10 is a cross-sectional view of a semiconductor module according to the second embodiment. Figure 11 is a cross-sectional view showing a modified example of the semiconductor module of Figure 10. Figure 12 is a plan view of a semiconductor module according to the third embodiment. Figure 13 is a diagram showing the circuit formed by the semiconductor module of the fourth embodiment. Figure 14 is a cross-sectional view of a semiconductor module according to the fourth embodiment. Figure 15 is a cross-sectional view showing a modified example of the semiconductor module of Figure 14. Figure 16 is a plan view of a semiconductor module according to the fifth embodiment. Figure 17 is a plan view of the semiconductor module according to the sixth embodiment. Figure 18 is a plan view of the semiconductor module according to the seventh embodiment. Figure 19 is a plan view of the semiconductor module according to the eighth embodiment.

[0010] A semiconductor module according to one embodiment of the present invention includes a first functional element including a first electrode and a second electrode positioned opposite the first electrode, a second functional element including a third electrode and a fourth electrode positioned opposite the third electrode, a lead frame to which the first electrode of the first functional element is connected and to which the third electrode of the second functional element is connected, and a substrate unit including a substrate electrode on the main surface of the substrate to which the second electrode of the first functional element is connected and to which the fourth electrode of the second functional element is connected. The function of the first electrode of the first functional element is different from the function of the third electrode of the second functional element. The substrate electrode includes a first element connection portion connected to the second electrode of the first functional element, a second element connection portion connected to the fourth electrode of the second functional element, and an electrode lead portion drawn out from at least one of the first element connection portion and the second element connection portion, through which a current flows toward the first element connection portion or a current is discharged from the second element connection portion. The lead frame includes: a first element connection region connected to the first electrode of a first functional element to which current is input from the first functional element; a second element connection region connected to the third electrode of a second functional element to which the current input to the first element connection region is output; a first current path region positioned between the first element connection region and the second element connection region, through which the first current of the current input to the first element connection region flows toward the second element connection region; and a second current path region positioned opposite the electrode lead portion along the normal direction of the main surface of the substrate, through which the second current of the current input to the first element connection region flows toward the second element connection region via a path different from the first current flowing through the first current path region.

[0011] During the operation of the semiconductor module described above, for example, current input to the electrode lead portion of the substrate electrode flows from the electrode lead portion toward the first element connection portion, passes through the first functional element, and is input to the first element connection region of the lead frame. Alternatively, current discharged from the second element connection portion flows in the electrode lead portion in a direction away from the second element connection portion. The first current input to the first element connection region passes through the first current path region of the lead frame and is input to the second element connection region, passes through the second functional element, and is discharged from the second element connection portion of the second substrate electrode. The second current input to the first element connection region passes through the second current path region of the lead frame and is input to the second element connection region, passes through the second functional element, and is discharged from the second element connection portion of the second substrate electrode. The second current path region is positioned opposite the electrode lead portion along the normal direction. In the second current path region, the second current flows from the first element connection region toward the second element connection region. In this case, the path of the second current flowing through the second current path region can be made to run parallel to the path of the current flowing through the electrode lead-out section, and the direction of current flow in each path can be made to be opposite to each other. This makes it possible to obtain a magnetic flux cancellation effect due to the currents flowing through each path, thereby reducing parasitic inductance. As a result, the losses of the semiconductor module can be reduced. Furthermore, in the above semiconductor module, the function of the first electrode of the first functional element connected to the lead frame is different from the function of the third electrode of the second functional element connected to the lead frame. With such an arrangement of functional elements, it becomes possible to easily form circuit elements that perform the desired function. In other words, it becomes possible to reduce the number of connecting components such as bonding wires used to form the circuit elements and to create a simple wiring structure. Therefore, with the above semiconductor module, it is possible to reduce losses with a simple structure.

[0012] In some embodiments, the substrate electrode may include an electrode extraction portion comprising a first electrode extraction portion drawn out from a first element connection portion through which a current toward the first element connection portion flows, and a second electrode extraction portion drawn out from a second element connection portion through which a current discharged from the second element connection portion flows. The first electrode extraction portion may include a first extension portion extending along a first direction along the main surface of the substrate. The second electrode extraction portion may include a second extension portion extending along the first direction and adjacent to the first extension portion with a gap between them, along a second direction intersecting the first direction. In this case, the path of the current flowing through the first extension portion toward the first element connection portion can be brought close to the path of the current flowing from the second element connection portion to the second extension portion. As a result, the effect of magnetic flux cancellation by currents flowing in opposite directions can be obtained between the path of the current flowing through the first extension portion and the path of the current flowing through the second extension portion, making it possible to further reduce parasitic inductance.

[0013] In some embodiments, the width of the gap between the first and second extending portions in the second direction may be smaller than the respective widths of the first and second extending portions in the second direction. In this case, the effect of magnetic flux cancellation by currents flowing in opposite directions can be effectively obtained between the current path in the first extending portion and the current path in the second extending portion, thereby further reducing parasitic inductance.

[0014] In some embodiments, the first functional element may be aligned with the second functional element along the first direction. The second current path region may be positioned opposite the first extension portion along the normal direction and may include a first electrode-facing region that extends along the first direction parallel to the first extension portion. In this case, the path of the second current flowing through the first electrode-facing region of the second current path region can run parallel to the path of the current flowing through the first extension portion of the first electrode extraction portion over a longer distance. This makes it possible to obtain a more effective magnetic flux cancellation effect between the first electrode-facing region and the first extension portion, thereby further reducing parasitic inductance.

[0015] In some embodiments, the substrate electrode may include an electrode extraction section comprising a first electrode extraction section drawn out from a first element connection section through which a current toward the first element connection section flows, and a second electrode extraction section drawn out from a second element connection section through which a current discharged from the second element connection section flows. The second current path region may include a first electrode opposing region facing the first electrode extraction section along the normal direction, and a second electrode opposing region facing the second electrode extraction section along the normal direction. In this case, the direction of current flow in the first electrode opposing region can be reversed from the direction of current flow in the first electrode extraction section, and furthermore, the direction of current flow in the second electrode opposing region can also be reversed from the direction of current flow in the second electrode extraction section. This makes it possible to obtain a magnetic flux cancellation effect between the second electrode opposing region and the second electrode extraction section, in addition to the magnetic flux cancellation effect between the first electrode opposing region and the first electrode extraction section. This makes it possible to further reduce parasitic inductance.

[0016] In some embodiments, the area of ​​the first electrode-facing region may differ from the area of ​​the second electrode-facing region when viewed along the normal direction. In this case, the path of the second current flowing through the first electrode-facing region can run parallel to the path of the current flowing through the first electrode-outlet portion for a longer distance, or the path of the second current flowing through the second electrode-facing region can run parallel to the path of the current flowing through the second electrode-outlet portion for a longer distance. This makes it possible to more effectively obtain the magnetic flux cancellation effect between the first electrode-facing region and the first electrode-outlet portion, or between the second electrode-facing region and the second electrode-outlet portion, thereby effectively reducing parasitic inductance.

[0017] In some embodiments, the first electrode lead portion may further include a third extending portion that extends along a first direction and is located on the opposite side of the first extending portion, with the second extending portion in between, along a second extending portion. The third extending portion may be adjacent to the second extending portion with a gap between them along the second direction. In this case, the current path flowing through the third extending portion toward the first element connection portion can be brought close to the current path flowing from the second element connection portion toward the second extending portion. As a result, the effect of magnetic flux cancellation by currents flowing in opposite directions can be obtained between the current path flowing through the third extending portion and the current path flowing through the second extending portion, making it possible to further reduce parasitic inductance.

[0018] In some embodiments, the second current path region may include a first electrode-facing region facing the first extension portion in the direction normal to the extension portion, a second electrode-facing region facing the second extension portion in the direction normal to the extension portion, and a third electrode-facing region facing the third extension portion in the direction normal to the extension portion. In this case, the direction of current flow in the first electrode-facing region can be opposite to the direction of current flow in the first extension portion of the first electrode extraction portion. The direction of current flow in the second electrode-facing region can also be opposite to the direction of current flow in the second extension portion of the second electrode extraction portion. Furthermore, the direction of current flow in the third electrode-facing region can also be opposite to the direction of current flow in the third extension portion of the first electrode extraction portion. This makes it possible to obtain a magnetic flux cancellation effect between the first electrode facing region and the first extension of the first electrode extraction portion, a magnetic flux cancellation effect between the second electrode facing region and the second extension of the second electrode extraction portion, and a magnetic flux cancellation effect between the third electrode facing region and the third extension of the first electrode extraction portion, thereby further reducing parasitic inductance.

[0019] In some embodiments, the substrate electrode may include an electrode lead section comprising a first electrode lead section drawn out from a first element connection section through which a current toward the first element connection section flows, and a second electrode lead section drawn out from a second element connection section through which a current discharged from the second element connection section flows. The first electrode lead section and the second electrode lead section may be drawn out so as to extend toward a first edge of the main surface of the substrate in a first direction along the main surface of the substrate. The lead frame may be drawn out in the opposite direction from which the first electrode lead section and the second electrode lead section are drawn out, to a position where it does not face the substrate electrode along the normal direction. If the lead frame is drawn out along the same direction as the first electrode lead section and the second electrode lead section, the wiring structures connected to the lead frame, the first electrode lead section, and the second electrode lead section, respectively, are concentrated in the same region, which may complicate the wiring structure. In contrast, as in the configuration described above, when the lead frame is led out on the opposite side from the first electrode lead-out section and the second electrode lead-out section, the wiring structure connected to the lead frame and the wiring structures connected to the first electrode lead-out section and the second electrode lead-out section, respectively, can be arranged in separate areas, thereby simplifying the wiring structure in each area.

[0020] In some embodiments, the substrate electrode may include an electrode lead portion, which is drawn out from the first element connection portion along a first direction along the main surface of the substrate, and through which a current toward the first element connection portion flows. The second functional element may be positioned in a location aligned with the first functional element along the first direction, and aligned with the first electrode lead portion along a second direction intersecting the first direction. The substrate unit may have an insulating layer including the main surface of the substrate on which the substrate electrode is provided. The second current path region may include a first electrode opposing region facing the first electrode lead portion along the direction normal to the first electrode lead portion, and a first intermediate region facing the insulating layer between the first electrode lead portion and the second functional element along the direction normal to the insulating layer. In this case, the second current of the current input to the first element connection region is input to the second element connection region through the first electrode opposing region and the first intermediate region of the lead frame, and is discharged from the second element connection portion of the second substrate electrode through the second functional element. Therefore, in this case as well, the path of the second current flowing through the second current path region can be made to run parallel to the path of the current flowing through the electrode extraction section, and the direction of current flow in each path can be made to be opposite to each other, thus making it possible to reduce losses with a simple structure.

[0021] Another embodiment of the present invention is a semiconductor module comprising: a first functional element including a first electrode and a second electrode positioned opposite the first electrode; a second functional element including a third electrode and a fourth electrode positioned opposite the third electrode; a lead frame to which the first electrode of the first functional element is connected and to which the third electrode of the second functional element is connected; and a substrate unit including a substrate electrode on the main surface of the substrate to which the second electrode of the first functional element is connected and to which the fourth electrode of the second functional element is connected. The function of the first electrode of the first functional element is different from the function of the third electrode of the second functional element. The substrate electrode includes a first element connection portion connected to the second electrode of the first functional element; a second element connection portion connected to the fourth electrode of the second functional element; and an electrode lead portion drawn out from at least one of the first element connection portion and the second element connection portion, through which a current flows toward the first element connection portion or a current is discharged from the second element connection portion. The lead frame includes a first element connection region connected to the first electrode of a first functional element, a second element connection region connected to the third electrode of a second functional element, a first current path region positioned between the first and second element connection regions, and a second current path region positioned opposite the electrode lead portion along the normal direction of the main surface of the substrate. As described above, this semiconductor module makes it possible to reduce losses with a simple structure.

[0022] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the attached drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant explanations are omitted.

[0023] [First Embodiment] The semiconductor module 1A shown in Figure 1 is, for example, a component of an inverter that supplies three-phase AC power to a motor. The semiconductor module 1A includes power semiconductor elements 20A and 20B (first functional element and second functional element) as functional elements. The number of functional elements included in the semiconductor module 1A is at least two, and may be three or more. As will be described later, the semiconductor module 1A may include all functional elements of the same type, or it may include functional elements of different types.

[0024] The semiconductor module 1A includes power semiconductor elements 20A and 20B, a substrate unit 3, a cooler 30, and a lead frame 4. The power semiconductor elements 20A and 20B are arranged on the main surface 3a of the substrate unit 3 to form an electrical circuit that performs a desired function.

[0025] An example of an electrical circuit that performs the desired function is the circuit element 10A shown in Figure 2. The semiconductor module 1A forms the circuit element 10A shown in Figure 2. The circuit element 10A functions as a so-called half-bridge circuit. The circuit element 10A corresponds to a so-called one leg of a power conversion circuit. The circuit element 10A includes a first terminal P10a, a second terminal P10b, and an output terminal P10s. The first terminal P10a corresponds to the element pad 91A, which will be described later. The second terminal P10b corresponds to the element pad 91B, which will be described later. The output terminal P10s corresponds to the lead frame 4 or its connection portion.

[0026] As described later, each of the power semiconductor elements 20A and 20B is, for example, a MOSFET and includes a gate, source, and drain. The drain of power semiconductor element 20A is connected to the first terminal P10a. The source of power semiconductor element 20A is connected to power semiconductor element 20B and the output terminal P10s. The source of power semiconductor element 20B is connected to the second terminal P10b. The drain of power semiconductor element 20B is connected to the source and output terminal P10s of power semiconductor element 20A. The operation of circuit element 10A is controlled by voltage signals applied to the gates of power semiconductor elements 20A and 20B.

[0027] Refer to Figure 1 again. The power semiconductor elements 20A and 20B are connected to each other by wiring patterns provided on the substrate unit 3. The power semiconductor elements 20A and 20B are also connected to each other by lead frames 4. The heat generated by the power semiconductor elements 20A and 20B is transferred to the substrate unit 3. The heat transferred to the substrate unit 3 is released to the outside by the cooler 30.

[0028] [Functional Elements] Power semiconductor elements 20A and 20B perform desired electrical functions upon receiving external electrical signals. Examples of power semiconductor elements 20A and 20B are transistors. The power semiconductor elements 20A and 20B shown in Figure 1 are field-effect transistors, or MOSFETs, which combine metal-oxide-semiconductor elements. A MOSFET controls the current flowing between the source and drain by controlling the voltage between the gate and source. In other words, a MOSFET is a switching element. A MOSFET includes a gate, source, and drain as input and output terminals for external electrical signals. The functional elements, which are power semiconductor elements 20A and 20B, may be insulated-gate bipolar transistors (IGBTs) or high-electron-mobility transistors (HEMTs). The functional elements may also be diode elements. Semiconductor materials used for the functional elements include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga ２ O ３ ), or diamond (C).

[0029] The functional elements included in semiconductor module 1A have a so-called vertical structure. Elements with a vertical structure have a structure that allows current to flow between the front and back surfaces of the element. The direction of current flow may be from the front surface to the back surface, or from the back surface to the front surface. Current may also flow in both directions, from the front surface to the back surface and from the back surface to the front surface.

[0030] Each of the power semiconductor elements 20A and 20B includes an element main surface 20a and an element back surface 20b. Power semiconductor element 20A may include a source electrode 21S (first electrode), a gate electrode 21G, and a Kelvin electrode 21K that is electrically conductive with the source electrode 21S, all exposed on the element main surface 20a. The source electrode 21S is an electrode that functions as a source. A gate voltage is supplied to the gate electrode 21G with reference to the source electrode 21S or the Kelvin electrode 21K. A Kelvin terminal may be connected to the Kelvin electrode 21K. Power semiconductor element 20A has a drain electrode 21D (second electrode) exposed on the element back surface 20b. The drain electrode 21D is an electrode that functions as a drain. Power semiconductor element 20B has a drain electrode 21D (third electrode) exposed on the element main surface 20a. The power semiconductor element 20B may include a source electrode 21S (fourth electrode), a gate electrode 21G, and a Kelvin electrode 21K, which are exposed on the back surface 20b of the element.

[0031] As described above, power semiconductor elements 20A and 20B are of the same type, but their embodiments differ. The source electrode 21S of power semiconductor element 20A is connected to the lead frame 4. The drain electrode 21D of power semiconductor element 20A is connected to the substrate unit 3. The source electrode 21S of power semiconductor element 20B is connected to the substrate unit 3. The drain electrode 21D of power semiconductor element 20B is connected to the lead frame 4. In the following description, the mounting configuration of power semiconductor element 20A will be referred to as "normal mounting," and the mounting configuration of power semiconductor element 20B will be referred to as "inverted mounting." The semiconductor module 1A includes a normally mounted power semiconductor element 20A and an inverted mounted power semiconductor element 20B.

[0032] The definitions of "standard mounting" and "inverted mounting" are not limited to those described above. For example, a mounting configuration like that of power semiconductor element 20A could be defined as "inverted mounting," while a mounting configuration like that of power semiconductor element 20B could be defined as "standard mounting."

[0033] If the functional element is an electrical component other than a MOSFET, the definition may be appropriately defined according to the configuration of the component. For example, if a unipolar transistor is used as the functional element, not limited to a MOSFET, the configuration in which the drain electrode is connected to the substrate unit 3 may be defined as "normal mounting," and the configuration in which the source electrode is connected to the substrate unit 3 may be defined as "inverted mounting." If the functional element is a bipolar transistor including an IGBT, the configuration in which the collector electrode is connected to the substrate unit 3 may be defined as "normal mounting," and the configuration in which the emitter electrode is connected to the substrate unit 3 may be defined as "inverted mounting." If the functional element is a diode, the configuration in which the cathode electrode is connected to the substrate unit 3 may be defined as "normal mounting," and the configuration in which the anode electrode is connected to the substrate unit 3 may be defined as "inverted mounting." Not limited to the same type of element as in this embodiment, normal mounting and inverted mounting may be combined for different types of elements. For example, power semiconductor element 20A may be replaced with a normally mounted MOSFET, and power semiconductor element 20B may be replaced with an inverted mounted IGBT or diode.

[0034] By combining "normal mounting" and "inverted mounting" in this way to arrange the functional elements, the number of lead frames 4 can be reduced and the wiring for forming the semiconductor module 1A can be simplified.

[0035] [Substrate Unit] The substrate unit 3 includes a main substrate surface 3a and a back substrate surface 3b facing the opposite side from the main substrate surface 3a. The main substrate surface 3a is provided with multiple wiring patterns, pads, and lands. These are connected by multiple power semiconductor elements 20A, 20B, multiple lead frames 4, and multiple bonding wires to form the circuit element 10A shown in Figure 2.

[0036] The substrate unit 3 includes a metal layer 31, an insulating layer 32, a substrate electrode 91, and a heat spreader 36. The metal layer 31 is the base material of the substrate unit 3. By including the metal layer 31 as the base material of the substrate unit 3, the heat dissipation of the substrate unit 3 can be improved. The metal layer 31 may include, as an example, a copper plate or an aluminum plate.

[0037] The heat spreader 36 is provided on the back surface 31b of the metal layer 31. The main surface 36a of the heat spreader 36 is in contact with the back surface 31b of the metal layer 31. The back surface 36b of the heat spreader 36 is in contact with the cooler 30. The heat spreader 36 helps to transfer heat from the metal layer 31 to the cooler 30. The back surface 36b of the heat spreader 36 is the aforementioned back surface 3b of the substrate.

[0038] The insulating layer 32 is provided on the main surface 31a of the metal layer 31. In other words, the metal layer 31 is provided on the back surface 32b of the insulating layer 32. It can also be said that the insulating layer 32 is laminated along the lamination direction D1 (normal direction) with respect to the main surface 31a of the metal layer 31. The lamination direction D1 coincides with the normal direction of the main surface 3a of the substrate. The back surface 32b of the insulating layer 32 is in contact with the main surface 31a of the metal layer 31. The main surface 32a of the insulating layer 32 is the aforementioned main surface 3a of the substrate. Examples of materials used to form the insulating layer 32 include silicon nitride, aluminum nitride, and resin.

[0039] The substrate electrode 91 is provided on the main surface 3a of the substrate unit 3 (i.e., the main surface 32a of the insulating layer 32). It can also be said that the substrate electrode 91 is stacked on the main surface 3a of the substrate in the stacking direction D1. The substrate electrode 91 includes two element pads 91A and 91B. The power semiconductor element 20A is positioned between the element pad 91A and the lead frame 4 in the stacking direction D1. The power semiconductor element 20B is positioned between the element pad 91B and the lead frame 4 in the stacking direction D1. Each of the element pads 91A and 91B is formed of, for example, copper or aluminum. Element pad 91A is a P electrode and is connected to the drain electrode 21D of a normally mounted power semiconductor element 20A. Element pad 91B is an N electrode and is connected to the source electrode 21S of a reverse-mounted power semiconductor element 20B. Element pad 91B is not connected to the gate electrode 21G and Kelvin electrode 21K of the power semiconductor element 20B.

[0040] As shown in Figure 3, when viewed along the stacking direction D1, the power semiconductor elements 20A are arranged adjacent to the power semiconductor elements 20B with a gap between them. For example, the power semiconductor elements 20A are aligned along the alignment direction D2 (first direction) along the main surface 3a of the substrate with respect to the power semiconductor elements 20B. The power semiconductor elements 20B are aligned along the intersecting direction D3 with respect to the extension portion P2b of the electrode lead-out portion PA2.

[0041] The power semiconductor element 20A is positioned, for example, in the array direction D2, closer to the side edge 3ab than to the side edge 3aa (first edge) of the main surface 3a of the substrate. The power semiconductor element 20A is positioned, for example, in the intersecting direction D3 (second direction) that intersects the array direction D2, closer to the side edge 3ad than to the side edge 3ac of the main surface 3a of the substrate. The side edge 3aa is the first edge of the main surface 3a of the substrate in the array direction D2. The side edge 3ab is the second edge of the main surface 3a of the substrate in the array direction D2. The side edge 3ac is the third edge of the main surface 3a of the substrate in the intersecting direction D3. The side edge 3ad is the fourth edge of the main surface 3a of the substrate in the intersecting direction D3.

[0042] The power semiconductor element 20B is positioned, for example, between the side edge 3aa and the power semiconductor element 20A in the array direction D2, and at the same position as the power semiconductor element 20A in the intersecting direction D3. The power semiconductor element 20B is adjacent to the power semiconductor element 20A with a gap in between along the array direction D2.

[0043] The element pads 91A and 91B are electrodes arranged on the main surface 3a of the substrate, and are positioned with gaps between them on the main surface 3a of the substrate. Element pad 91B extends outward from the position connected to element pad 91A along the array direction D2. Element pad 91B is, for example, rectangular in shape with the array direction D2 as its longitudinal direction. Element pad 91A extends outward from the position connected to element pad 91A, wrapping around element pad 91B which is connected to element pad 91B, along the array direction D2. Element pad 91A is, for example, L-shaped, extending along the array direction D2 and the intersecting direction D3, and is positioned to surround element pad 91B.

[0044] The first end 91Ba of the element pad 91B in the extending direction (i.e., the array direction D2) is disposed at a position close to the side edge 3aa of the substrate main surface 3a in the array direction D2. The second end 91Bb of the element pad 91B in the extending direction of the element pad 91B is disposed at a position close to the side edge 3ab of the substrate main surface 3a in the array direction D2. The first end 91Aa of the element pad 91A in the extending direction of the element pad 91A is disposed at a position close to the side edge 3aa of the substrate main surface 3a in the array direction D2. The first end 91Aa of the element pad 91A is disposed at the same position as the first end 91Ba of the element pad 91B in the array direction D2. The second end 91Ab of the element pad 91A in the extending direction of the element pad 91A is disposed at a position close to the side edge 3ad of the substrate main surface 3a in the crossing direction D3.

[0045] The element pad 91B includes an element connection portion PB1 (second element connection portion) and an electrode lead-out portion PB2 (second electrode lead-out portion). The element connection portion PB1 is a portion connected to the source electrode 21S of the power semiconductor element 20B. The element connection portion PB1 overlaps the power semiconductor element 20B in the stacking direction D1. The electrode lead-out portion PB2 is a portion drawn from the element connection portion PB1 toward the side edge 3aa side along the array direction D2, and is disposed at a position where it does not overlap the power semiconductor element 20B in the stacking direction D1. The electrode lead-out portion PB2 includes an extending portion P1a (second extending portion) extending along the array direction D2 from the element connection portion PB1 to the first end 91Ba. The electrode lead-out portion PB2 may include another extending portion extending along a direction different from the extending portion P1a. The length of the electrode lead-out portion PB2 from the power semiconductor element 20B to the first end 91Ba in the array direction D2 may be, for example, equal to or greater than the length of the power semiconductor element 20B in the array direction D2. The area of the electrode lead-out portion PB2 from the power semiconductor element 20B to the first end 91Ba may be, for example, equal to or greater than the area of the power semiconductor element 20B.

[0046] The element pad 91A includes an element connection portion PA1 (first element connection portion) and an electrode lead-out portion PA2 (first electrode lead-out portion). The element connection portion PA1 is a portion connected to the drain electrode 21D of the power semiconductor element 20A. The element connection portion PA1 overlaps the power semiconductor element 20A in the stacking direction D1. The electrode lead-out portion PA2 is a portion drawn out toward the side edge 3aa while wrapping around the element pad 91B from the element connection portion PA1 along the arrangement direction D2. The electrode lead-out portion PA2 is arranged at a position that does not overlap the power semiconductor element 20A in the stacking direction D1.

[0047] The electrode lead-out portion PA2 includes an extending portion P2a extending along the intersecting direction D3 from the element connection portion PA1, and an extending portion P2b (first extending portion) extending from the extending portion P2a to the first end 91Aa along the arrangement direction D2. The extending portion P2b is adjacent to the element pad 91B with a gap therebetween along the intersecting direction D3. The extending portion P2b extends along the arrangement direction D2 side by side with the extending portion P1a of the element pad 91B. The extending portion P2b is drawn out toward the side edge 3aa side in the arrangement direction D2 together with the extending portion P1a. A gap G is formed between the extending portion P2b and the extending portion P1a in the intersecting direction D3. The width W1 of the gap G in the intersecting direction D3 is smaller than the width W2 of the extending portion P2b in the intersecting direction D3 and the width W3 of the extending portion P1a in the intersecting direction D3, respectively. The length of the electrode lead-out portion PA2 from the power semiconductor element 20A to the first end 91Aa in the arrangement direction D2 may be, for example, equal to or greater than the length of the power semiconductor element 20A in the arrangement direction D2. The area of the electrode lead-out portion PA2 from the power semiconductor element 20A to the first end 91Aa may be, for example, equal to or greater than the area of the power semiconductor element 20A.

[0048] [Cooler] The cooler 30 shown in FIG. 1 dissipates the heat generated by the power semiconductor element 20. An example of the cooler 30 is a heat sink provided with a plurality of fins. The cooler 30 may be another device having a heat dissipation function. The cooler 30 may be a water-cooled device. The back surface 36b of the heat spreader 36 is in contact with the main surface 30a of the cooler 30. In the semiconductor module 1A of the present disclosure, the cooler 30 is provided only on the back surface 3b of the substrate of the substrate unit 3.

[0049] [Lead Frame] The lead frame 4 shown in Figure 1 is connected to the source electrode 21S of the power semiconductor element 20A. The lead frame 4 is also connected to the drain electrode 21D of the power semiconductor element 20B. The lead frame 4 may also be connected to other functional elements, etc. The power semiconductor elements 20A and 20B receive electrical signals from the outside through the lead frame 4. Therefore, the lead frame 4 is a conductive conductor. The lead frame 4 is, for example, a thin plate. The lead frame 4 is formed from, for example, a copper plate or an aluminum plate.

[0050] The cross-sectional shape of the lead frame 4 is, for example, rectangular. The cross-sectional shape of the lead frame 4 has a large width relative to its thickness. Therefore, the cross-sectional area of ​​the lead frame 4 is larger than the cross-sectional area of ​​a thin metal wire, a so-called bonding wire. Consequently, it is possible to supply a large current to the source electrode 21S of the power semiconductor element 20A and the drain electrode 21D of the power semiconductor element 20B.

[0051] As shown in Figure 3, the lead frame 4 is positioned in the stacking direction D1, facing the element pads 91A and 91B, with the power semiconductor elements 20A and 20B in between. The lead frame 4 is in contact only with the electrodes of the element pads 91A and 91B that should be electrically connected. Specifically, the lead frame 4 is in contact with the source electrode 21S of the power semiconductor element 20A and is electrically connected to the source electrode 21S. The lead frame 4 is away from the gate electrode 21G and the Kelvin electrode 21K of the power semiconductor element 20A. The lead frame 4 is not electrically connected to the gate electrode 21G. The lead frame 4 is away from the Kelvin electrode 21K of the power semiconductor element 20A, and outside the power semiconductor element 20A, the lead frame 4 and the Kelvin electrode 21K are not electrically connected. Since the source electrode 21S and the Kelvin electrode 21K are electrically connected inside the power semiconductor element 20A, the lead frame 4 may be in contact with the Kelvin electrode 21K. A connection element (e.g., a bonding wire) separate from the lead frame 4 is connected to the gate electrode 21G and the Kelvin electrode 21K. The gate electrode 21G receives a gate voltage through the connection element with reference to the source electrode 21S or the Kelvin electrode 21K. Since the source electrode 21S and the Kelvin electrode 21K are electrically connected inside the power semiconductor device 20A, the other connection element (such as a bonding wire) may be connected to the lead frame 4 instead of the Kelvin electrode 21K. The lead frame 4 is in contact with the drain electrode 21D of the power semiconductor device 20B and is electrically connected to the drain electrode 21D.

[0052] The lead frame 4 is, for example, rectangular in shape with the array direction D2 as the longitudinal direction and the intersecting direction D3 as the short direction. The lead frame 4 is arranged such that it overlaps at least a portion of each of the element pads 91A and 91B in the stacking direction D1. In this embodiment, the lead frame 4 overlaps the element connection portion PA1 and electrode lead portion PA2 of the element pad 91A and the element connection portion PB1 and electrode lead portion PB2 of the element pad 91B in the stacking direction D1. The lead frame 4 is arranged such that it is offset along the array direction D2 with respect to the element pads 91A and 91B. The lead frame 4 is led out in the opposite direction to the direction in which the element pads 91A and 91B are led out. Specifically, while the element pads 91A and 91B are led out to one side of the array direction D2 (i.e., the side edge 3aa side), the lead frame 4 is led out to the other side of the array direction D2 (i.e., the side edge 3ab side).

[0053] In the array direction D2, the first end 4aa of the lead frame 4 is positioned offset to the other side of the array direction D2 (i.e., the side edge 3ab side) relative to the first end 91Aa of the element pad 91A and the first end 91Ba of the element pad 91B. The first end 4aa of the lead frame 4 does not overlap with the first end 91Aa and the first end 91Ba in the stacking direction D1. The second end 4bb of the lead frame 4 in the array direction D2 is offset along the array direction D2 relative to the element pads 91A and 91B to a position where it does not overlap with the substrate unit 3 including the element pads 91A and 91B in the stacking direction D1. Therefore, the second end 4bb of the lead frame 4 does not overlap with either the element pad 91A or the element pad 91B in the stacking direction D1.

[0054] The lead frame 4 includes an element connection region R4A (first element connection region), an element connection region R4B (second element connection region), a current path region R5 (first current path region), a current path region R5A (second current path region), and a frame lead-out region R6. The frame lead-out region R6 is an end region that includes the second end 4bb of the lead frame 4. The frame lead-out region R6 is positioned in a location that does not overlap with either the element pad 91A or the element pad 91B in the stacking direction D1.

[0055] The element connection region R4A is the region facing the element connection portion PA1 in the stacking direction D1, with the power semiconductor element 20A in between. The element connection region R4A is connected to the source electrode 21S of the power semiconductor element 20A. The element connection region R4B is the region facing the element connection portion PB1 in the stacking direction D1, with the power semiconductor element 20B in between. The drain electrode 21D of the power semiconductor element 20B is connected to the element connection region R4B. The element connection region R4B is adjacent to the element connection region R4A along the array direction D2 with a gap between them.

[0056] In this specification, when a first component faces a second component in the stacking direction D1, it means that the first component overlaps with the second component in the stacking direction D1, or more specifically, that at least a portion of the first component overlaps with at least a portion of the second component when viewed along the stacking direction D1. Each of the first and second components is an arbitrary element that forms the semiconductor module 1A.

[0057] The current path region R5 is positioned between the element connection region R4A and the element connection region R4B in the alignment direction D2, connecting the element connection region R4A and the element connection region R4B along the alignment direction D2. The current path region R5 forms the shortest path from the element connection region R4A to the element connection region R4B. In the stacking direction D1, the current path region R5 faces the main surface 3a of the substrate through the gap between the element connection portion PA1 and the element connection portion PB1. Therefore, the current path region R5 does not overlap with either the element pad 91A or 91B in the stacking direction D1.

[0058] The current path region R5A connects the element connection region R4A and the element connection region R4B via a different path than the current path region R5. For example, the current path region R5A extends from the element connection region R4A to the element connection region R4B, passing through a position facing the electrode lead-out portion PA2 of the element pad 91A and a position facing the electrode lead-out portion PB2 of the element pad 91B. Therefore, the current path region R5A does not form the shortest path from the element connection region R4A to the element connection region R4B, but rather forms a detour path that bypasses the element connection region R4A to reach the element connection region R4B.

[0059] The current path region R5A includes the electrode-facing region R51 (first electrode-facing region), the electrode-facing region R52 (second electrode-facing region), the intermediate region R53, and the intermediate region R54. The electrode-facing region R51 is the region facing the extended portion P2b of the electrode extraction portion PA2 in the stacking direction D1. The electrode-facing region R51 is aligned with the extended portion P2b of the electrode extraction portion PA2 along the stacking direction D1, and extends along the array direction D2 together with the extended portion P2b. The electrode-facing region R52 is the region facing the extended portion P1a of the electrode extraction portion PB2 along the stacking direction D1. The electrode-facing region R52 is aligned with the extended portion P1a of the electrode extraction portion PB2 along the stacking direction D1, and extends along the array direction D2 together with the extended portion P1a.

[0060] When viewed along the stacking direction D1, the area of ​​electrode-facing region R51 is larger than the area of ​​electrode-facing region R52. Since electrode-facing region R51 overlaps with the extension portion P2b of electrode-extraction portion PA2, the area of ​​electrode-facing region R51 can also be replaced with the area of ​​extension portion P2b. Since electrode-facing region R52 overlaps with the extension portion P1a of electrode-extraction portion PB2, the area of ​​electrode-facing region R52 can also be replaced with the area of ​​extension portion P1a.

[0061] The intermediate region R53 is located between the electrode-facing region R51 and the element-connecting region R4A in the intersecting direction D3. The intermediate region R53 connects the electrode-facing region R51 and the element-connecting region R4A along the intersecting direction D3. The intermediate region R53 faces the extended portion P2a of the electrode lead-out portion PA2 in the stacking direction D1. The intermediate region R54 is located between the electrode-facing region R51 and the electrode-facing region R52 in the intersecting direction D3. The intermediate region R54 connects the electrode-facing region R51 and the electrode-facing region R52 along the intersecting direction D3. The intermediate region R54 faces the main substrate surface 3a in the stacking direction D1 through the gap G between the electrode-facing region R51 and the electrode-facing region R52 in the intersecting direction D3.

[0062] Figure 3 shows the currents E1, E2, E2a, E2b, and E3 flowing through the element pads 91A, 91B, or the lead frame 4. The black arrows indicate currents E1 and E3, which flow through element pads 91A and 91B. The white arrows indicate currents E2a and E2b, which flow through the lead frame 4. The hatched arrow indicates current E2b, which branches off from current E2 and flows along a different path than current E2a.

[0063] As shown in Figure 3, current E1 is input to the electrode lead-out portion PA2 of the element pad 91A through the connecting component. The current E1 input to the electrode lead-out portion PA2 flows along the arrangement direction D2 through the extension portion P2b of the electrode lead-out portion PA2, then folds back in the intersecting direction D3, passes through the extension portion P2a, and is input to the drain electrode 21D of the power semiconductor element 20A connected to the element connection portion PA1. The current E1 input to the drain electrode 21D is output as current E2 from the source electrode 21S of the power semiconductor element 20A. The current E2 output from the power semiconductor element 20A is input to the element connection region R4A of the lead frame 4.

[0064] The main portion of the current E2 input to the element connection region R4A, current E2a (first current), flows through the shortest path, current path region R5, to the element connection region R4B. Current E2a is input from the element connection region R4B to the source electrode 21S of the power semiconductor element 20B and output as current E3 from the drain electrode 21D of the power semiconductor element 20B. Current E3 is input to the element connection portion PB1 of the element pad 91B. Current E3 input to the element connection portion PB1 flows through the electrode lead-out portion PB2 along the arrangement direction D2 and is output to the outside through another connection component.

[0065] Current E2b (second current), which is the other part of current E2 input to element connection region R4A, is a current branched off from the main part, current E2a. Current E2b flows from element connection region R4A to element connection region R4B through current path region R5A, which is different from the shortest path, current path region R5. In other words, current E2b flows from element connection region R4A to element connection region R4B through a different path than current E2a flowing through current path region R5. A different path from current E2a flowing through current path region R5 means a path that passes through the region of the lead frame 4 excluding element connection regions R4A, R4B, and current path region R5. Therefore, a different path from current E2a flowing through current path region R5 is a path that passes through the region that does not face element pads 91A, 91B and their gaps in the stacking direction D1. The flow direction of current E2b flowing through current path region R5A includes a directional component different from the arrangement direction D2, which is the flow direction of current E2a flowing through current path region R5.

[0066] The current E2b that flows through the current path region R5A flows from the element connection region R4A along the crossing direction D3, passes through the intermediate region R53, and then flows through the electrode opposing region R51 along the alignment direction D2. Subsequently, the current E2b flows from the electrode opposing region R51 along the crossing direction D3, passes through the intermediate region R54, and then passes through the element connection region R4B before being input to the drain electrode 21D of the power semiconductor element 20B, where it merges with the main current, current E2a. The current E3 output from the source electrode 21S of the power semiconductor element 20B flows through the electrode lead-out section PB2 along the alignment direction D2 and is output to the outside through another connecting component.

[0067] As shown in Figure 3, the direction of current E2b flowing through the current path region R5A of the lead frame 4 is opposite to the direction of current E1 flowing through the electrode lead-out sections PA2 and PB2 that face the current path region R5A in the stacking direction D1. In this case, the direction of the magnetic flux generated by current E2b flowing through the current path region R5A is opposite to the direction of the magnetic flux generated by currents E1 and E3 flowing through the electrode lead-out sections PA2 and PB2, so the parasitic inductance is reduced by the magnetic flux cancellation effect.

[0068] Furthermore, as shown in Figure 3, the electrode lead-out sections PA2 and PB2 are led out in the same direction (i.e., along the side edge 3aa in the arrangement direction D2). The extension section P2b of the electrode lead-out section PA2 is close to the extension section P1a of the electrode lead-out section PB2 along the intersecting direction D3 with a gap G between them. The direction of current E1 flowing through the extension section P2b of the electrode lead-out section PA2 is opposite to the direction of current E3 flowing through the extension section P1a of the electrode lead-out section PB2. In this case, the direction of the magnetic flux generated by the current E1 flowing through the extension section P2b of the electrode lead-out section PA2 is opposite to the direction of the magnetic flux generated by the current E3 flowing through the extension section P1a of the electrode lead-out section PB2, so the parasitic inductance is further reduced by the magnetic flux cancellation effect.

[0069] As shown in Figure 1, when a conductive metal layer 31 is provided on the back surface 32b of the insulating layer 32, an induced current is generated on the back surface 32b of the insulating layer 32 due to the current flowing through the main surface 32a of the insulating layer 32, and this induced current can further reduce the parasitic inductance. As the material of the conductor provided on the back surface 32b of the insulating layer 32, for example, a material with high electrical conductivity (for example, copper) can be selected.

[0070] Thus, in this embodiment, the effect of reducing parasitic inductance can be synergistically obtained by the magnetic flux cancellation effect of the current E2b flowing through the lead frame 4 that overlaps the element pads 91A and 91B in the stacking direction D1, and the magnetic flux cancellation effect of the currents E1 and E3 flowing through adjacent element pads 91A and 91B that are in close proximity to each other.

[0071] <Effects> In the semiconductor module 1A of this embodiment, as described above, the path of the current E2b flowing through the current path region R5A can be made to run parallel to the path of the current E1 flowing through the electrode lead-out section PA2 and the electrode lead-out section PB2, and the flow directions of the currents E1 and E2b flowing through each path can be made to be opposite to each other. As a result, a magnetic flux cancellation effect can be obtained by the currents E1 and E2b flowing through each path, making it possible to reduce parasitic inductance. As a result, the losses of the semiconductor module 1A can be reduced. In the semiconductor module 1A, the function of the source electrode 21S of the power semiconductor element 20A connected to the lead frame 4 is different from the function of the drain electrode 21D of the power semiconductor element 20B connected to the lead frame 4. With this arrangement of power semiconductor elements 20A and 20B, it becomes possible to easily form a circuit element 10A that exhibits the desired function. In other words, it becomes possible to reduce the number of connecting components such as bonding wires for forming the circuit element 10A and make the wiring structure simpler. Accordingly, the semiconductor module 1A makes it possible to reduce losses with a simple structure.

[0072] As in this embodiment, the electrode lead-out portion PA2 may include an extended portion P2b that extends along the array direction D2. The electrode lead-out portion PB2 may also include an extended portion P1a that extends along the array direction D2 and is adjacent to the extended portion P2b with a gap between them along the intersecting direction D3. In this case, the path of the current E1 flowing through the extended portion P2b toward the element connection portion PA1 can be brought close to the path of the current E3 flowing from the element connection portion PB1 to the extended portion P1a. As a result, the effect of magnetic flux cancellation by the currents E1 and E3 flowing in opposite directions can be obtained between the path of the current E1 flowing through the extended portion P2b and the path of the current E3 flowing through the extended portion P1a, making it possible to further reduce parasitic inductance.

[0073] As in this embodiment, the width W1 of the gap G between the extended portion P2b and the extended portion P1a in the intersecting direction D3 may be smaller than the respective widths W2 and W3 of the extended portion P2b and the extended portion P1a in the intersecting direction D3. In this case, the effect of magnetic flux cancellation by the currents E1 and E3 flowing in opposite directions between the path of the current E1 flowing through the extended portion P2b and the path of the current E3 flowing through the extended portion P1a can be effectively obtained, making it possible to further reduce parasitic inductance.

[0074] As in this embodiment, the power semiconductor element 20A may be aligned with the power semiconductor element 20B along the array direction D2. The current path region R5A may be positioned opposite the extension portion P2b in the stacking direction D1 and may include an electrode-facing region R51 that extends along the array direction D2 alongside the extension portion P2b. In this case, the path of the current E2b flowing through the electrode-facing region R51 of the current path region R5A can be made to run parallel to the path of the current E1 flowing through the extension portion P2b of the electrode-out portion PA2 for a longer distance. This makes it possible to more effectively obtain the magnetic flux cancellation effect between the electrode-facing region R51 and the extension portion P2b, thereby further reducing parasitic inductance.

[0075] As in this embodiment, the current path region R5A may include an electrode-facing region R51 facing the electrode extraction portion PA2 in the stacking direction D1, and an electrode-facing region R52 facing the electrode extraction portion PB2 in the stacking direction D1. In this case, the direction of current E2b flowing through the electrode-facing region R51 can be set to be opposite to the direction of current E1 flowing through the electrode extraction portion PA2, and furthermore, the direction of current E2b flowing through the electrode-facing region R52 can also be set to be opposite to the direction of current E3 flowing through the electrode extraction portion PB2. This makes it possible to obtain a magnetic flux cancellation effect between the electrode-facing region R52 and the electrode extraction portion PB2, in addition to the magnetic flux cancellation effect between the electrode-facing region R51 and the electrode extraction portion PA2. This makes it possible to further reduce parasitic inductance.

[0076] As in this embodiment, when viewed along the stacking direction D1, the area of ​​the electrode-facing region R51 may differ from the area of ​​the electrode-facing region R52. In this case, the path of the current E2b flowing through the electrode-facing region R51 can run parallel to the path of the current E1 flowing through the electrode-out section PA2 for a longer distance. This makes it possible to more effectively obtain the magnetic flux cancellation effect between the electrode-facing region R51 and the electrode-out section PA2, thereby effectively reducing parasitic inductance.

[0077] As in this embodiment, the electrode lead-out sections PA2 and PB2 may be drawn out so as to extend toward the side edge 3aa in the arrangement direction D2 on the main surface 3a of the substrate. The lead frame 4 may be drawn out in the opposite direction to the direction in which the electrode lead-out sections PA2 and PB2 are drawn out, to a position in the stacking direction D1 that does not face the element pads 91A and 91B. If the lead frame 4 is drawn out along the same direction as the electrode lead-out sections PA2 and PB2, the wiring structures connected to the lead frame 4 and the electrode lead-out sections PA2 and PB2, respectively, will be concentrated in the same area, which may complicate the wiring structure. In contrast, as in the above configuration, if the lead frame 4 is drawn out on the opposite side from the electrode lead-out sections PA2 and PB2, the wiring structures connected to the lead frame 4 and the wiring structures connected to the electrode lead-out sections PA2 and PB2, respectively, can be arranged in separate areas, thus simplifying the wiring structure in each area.

[0078] The following describes some variations of the first embodiment.

[0079] <Modification 1 of the First Embodiment> Figure 4 is a cross-sectional view of a semiconductor module 1Aa, which is modification 1 of the first embodiment. The substrate unit 3Aa of the semiconductor module 1Aa differs from the substrate unit 3 of the semiconductor module 1A of the first embodiment. The other components of the semiconductor module 1Aa are the same as those of the semiconductor module 1A of the first embodiment. The substrate unit 3Aa has a metal layer 31, an insulating layer 32, and two element pads 91A and 91B. In other words, the substrate unit 3Aa does not include a heat spreader 36. The back surface 31b of the metal layer 31 is the substrate back surface 3b of the substrate unit 3Aa. The back surface 31b of the metal layer 31 is in contact with the main surface 30a of the cooler 30. A semiconductor module 1Aa equipped with such a substrate unit 3Aa can also achieve the same effects as the semiconductor module 1A of the first embodiment.

[0080] <Modification 2 of the First Embodiment> Figure 5 is a cross-sectional view of a semiconductor module 1Ab, which is modification 2 of the first embodiment. The substrate unit 3Ab of the semiconductor module 1Ab also differs from the substrate unit 3 of the semiconductor module 1A of the first embodiment. The other components of the semiconductor module 1Ab are the same as those of the semiconductor module 1A of the first embodiment. The substrate unit 3Ab has an insulating layer 32 and two element pads 91A and 91B. In other words, the substrate unit 3Ab does not include a metal layer 31 and a heat spreader 36. The back surface 32b of the insulating layer 32 is the back surface 3b of the substrate unit 3Ab. The back surface 32b of the insulating layer 32 is in contact with the main surface 30a of the cooler 30. A semiconductor module 1Ab equipped with such a substrate unit 3Ab can also achieve the same effects as the semiconductor module 1A of the first embodiment.

[0081] <Modification 3 of the First Embodiment> Figure 6 is a cross-sectional view of a semiconductor module 1Ac, which is modification 3 of the first embodiment. For the semiconductor module 1Ac, bonding materials such as solder and sintered material, and thermal interface material (TIM) are components used as needed. For this reason, Figure 1 omitted the illustration of bonding materials and TIM. Figure 6 clearly shows examples of locations where bonding materials 22T1, 22B1, 22T2, 22B2, 31B and TIM 36B are used.

[0082] Bonding material 22T1 is provided between the main surface 20a of the power semiconductor element 20A and the back surface 4b of the lead frame 4. In other words, bonding material 22T1 bonds the power semiconductor element 20A to the lead frame 4. Bonding material 22B1 is provided between the back surface 20b of the power semiconductor element 20A and the main surface 91a of the element pad 91A. In other words, bonding material 22B1 bonds the power semiconductor element 20A to the element pad 91A. Bonding material 22T2 is provided between the back surface 20b of the power semiconductor element 20B and the back surface 4b of the lead frame 4. In other words, bonding material 22T2 bonds the power semiconductor element 20B to the lead frame 4. Bonding material 22B2 is provided between the main surface 20a of the power semiconductor element 20B and the main surface 91a of the element pad 91B. In other words, bonding material 22B2 bonds the power semiconductor element 20B to the element pad 91B.

[0083] The bonding material 31B is provided between the back surface 31b of the metal layer 31 and the main surface 36a of the heat spreader 36. In other words, the bonding material 31B bonds the metal layer 31 to the heat spreader 36. The TIM 36B is provided between the back surface 36b of the heat spreader 36 and the main surface 30a of the cooler 30. In other words, the TIM 36B bonds the heat spreader 36 to the cooler 30. A semiconductor module 1Ac having such a configuration can achieve the same effects as the semiconductor module 1A of the first embodiment.

[0084] <Modification 4 of the First Embodiment> Figure 7 is a cross-sectional view of semiconductor module 1Ad, which is modification 4 of the first embodiment. Semiconductor module 1Ad, modification 4, is obtained by adding bonding material and TIM to semiconductor module 1Aa, which is modification 1. Semiconductor module 1Ad, modification 4, has bonding materials 22T1, 22B1, 22T2, 22B2 and TIM 36B. The bonding materials 22T1, 22B1, 22T2, and 22B2 are the same as in modification 3, so their description is omitted. TIM 36B is provided between the back surface 31b of the metal layer 31 and the main surface 30a of the cooler 30. In other words, TIM 36B bonds the metal layer 31 to the cooler 30. Semiconductor module 1Ad having such a configuration can also achieve the same effects as semiconductor module 1A of the first embodiment.

[0085] <Modification 5 of the First Embodiment> Figure 8 is a cross-sectional view of semiconductor module 1Ae, which is modification 5 of the first embodiment. Semiconductor module 1Ae, modification 5, is obtained by adding bonding material and TIM to semiconductor module 1Ab, which is modification 2. Semiconductor module 1Ae, modification 5, has bonding materials 22T1, 22B1, 22T2, 22B2 and TIM 36B. The bonding materials 22T1, 22B1, 22T2, and 22B2 are the same as in modification 3, so their description is omitted. TIM 36B is provided between the back surface 32b of the insulating layer 32 and the main surface 30a of the cooler 30. In other words, TIM 36B bonds the insulating layer 32 to the cooler 30. Semiconductor module 1Ae having such a configuration can also achieve the same effects as semiconductor module 1A of the first embodiment.

[0086] <Modification 6 of the First Embodiment> Figure 9 is a plan view of a semiconductor module 1Af, which is modification 6 of the first embodiment. The lead frame 4A of the semiconductor module 1Af is drawn out in the opposite direction to the lead frame 4 of the semiconductor module 1A in the first embodiment. In other words, the lead frame 4A is drawn out along the same direction as the direction in which the element pads 91A and 91B are drawn out (i.e., the side edge 3aa side).

[0087] The lead frame 4A is positioned to overlap the first end 91Aa of the element pad 91A and the first end 91Ba of the element pad 91B in the stacking direction D1. The first end 4aa of the lead frame 4A is positioned to be offset in the arrangement direction D2, across the side edge 3ab, from the first end 91Aa of the element pad 91A and the first end 91Ba of the element pad 91B. The second end 4bb of the lead frame 4A is positioned to overlap the element pads 91A and 91B in the stacking direction D1. When viewed along the stacking direction D1, the gate electrode 21G and Kelvin electrode 21K of the power semiconductor element 20A are positioned to protrude from the second end 4bb of the lead frame 4A without overlapping the lead frame 4A. A semiconductor module 1Af having such a configuration can also achieve the same effects as the semiconductor module 1A of the first embodiment.

[0088] <Second Embodiment> Figure 10 is a cross-sectional view of a semiconductor module 1B according to the second embodiment. The semiconductor module 1B of the second embodiment differs from the semiconductor module 1A of the first embodiment in that it includes spacers 6SA and 6SB. The other components of the semiconductor module 1B are the same as those of the semiconductor module 1A of the first embodiment. The spacers 6SA and 6SB form paths for current conduction and heat dissipation. Therefore, the spacers 6SA and 6SB are formed from a conductive material. From the viewpoint of forming paths for current conduction and heat dissipation, it is desirable that the material forming the spacers 6SA and 6SB has high electrical conductivity and thermal conductivity.

[0089] The spacer 6SA is positioned between the power semiconductor element 20A and the lead frame 4. If the material of the spacer 6SA is the same as the material of the lead frame 4, the spacer 6SA may be integrated with the lead frame 4. The main surface 6Sa of the spacer 6SA is in contact with the back surface 4b of the lead frame 4. The back surface 6Sb of the spacer 6SA is in contact with the main surface 20a of the power semiconductor element 20A. This arrangement allows for a longer distance from the lead frame 4 to the power semiconductor element 20A. In other words, a long insulation distance can be maintained.

[0090] The spacer 6SB is positioned between the power semiconductor element 20B and the element pad 91B. If the material of the spacer 6SB is the same as the material of the element pad 91B, the spacer 6SB may be integrated with the element pad 91B. The main surface 6Sa of the spacer 6SB is in contact with the main surface 20a of the power semiconductor element 20B. The back surface 6Sb of the spacer 6SB is in contact with the main surface 91a of the element pad 91B. This arrangement allows for a longer distance from the element pad 91B to the power semiconductor element 20B. In other words, a longer insulation distance can be maintained.

[0091] A semiconductor module 1B having such a configuration can achieve the same effects as the semiconductor module 1A of the first embodiment.

[0092] <Modification of the Second Embodiment> The semiconductor module 1B of the second embodiment may also use bonding materials and TIM. Figure 11 is a cross-sectional view of a semiconductor module 1Ba, which is a modification of the second embodiment. The semiconductor module 1Ba, which is a modification of the second embodiment, includes bonding materials 22T1, 22M1, 22B1, 22T2, 22M2, 22B2, 31B and TIM 36B in addition to the configuration of the semiconductor module 1B of the second embodiment. The semiconductor module 1B of the second embodiment includes spacers 6SA and 6SB. The semiconductor module 1Ba, which is a modification of the second embodiment, includes bonding material 22M1 disposed between spacer 6SA and power semiconductor element 20A. Furthermore, the semiconductor module 1Ba includes bonding material 22M2 disposed between spacer 6SB and power semiconductor element 20B. The bonding materials 22T1, 22B1, 22T2, 22B2, 31B and TIM 36B are the same as those of the above-described modification 3, so their description is omitted. A semiconductor module 1Ba having such a configuration can also achieve the same effects as the semiconductor module 1A of the first embodiment.

[0093] <Third Embodiment> Figure 12 is a plan view of a semiconductor module 1C according to the third embodiment. The element pad 91A1 of the semiconductor module 1C has an electrode lead-out portion PA3 in addition to the electrode lead-out portion PA2. The electrode lead-out portion PA3 is formed symmetrically with respect to the electrode lead-out portion PA2, for example, with respect to the center position of the element connection portion PA1 in the intersecting direction D3. The electrode lead-out portion PA3 includes an extension portion P3a that extends along the intersecting direction D3 from the element connection portion PA1 toward the opposite side of the extension portion P2a, and an extension portion P3b (third extension portion) that extends from the extension portion P3a toward the side edge 3aa in the arrangement direction D2.

[0094] The extended portion P3b is positioned on the opposite side of the extended portion P2b in the intersecting direction D3, with the element pad 91B in between. The extended portion P3b is adjacent to the element pad 91B along the intersecting direction D3 with a gap between them. Therefore, a gap G is formed between the extended portion P3b and the electrode lead-out portion PB2 in the intersecting direction D3. The extended portion P3b extends along the array direction D2, alongside the extended portion P1a of the electrode lead-out portion PB2. The extended portion P3b, together with the extended portions P1a and P2b, is drawn out to one side of the array direction D2 (i.e., the side edge 3aa side).

[0095] The lead frame 4B of the semiconductor module 1C is positioned offset along the array direction D2 from the element pads 91A1 and 91B so as not to overlap with the gate electrode 21G and Kelvin electrode 21K of the power semiconductor element 20B in the stacking direction D1. As a result, the lead frame 4B overlaps with the element connection portion PB1 of the element pad 91B in the stacking direction D1, but does not overlap with the electrode lead-out portion PB2 of the element pad 91B in the stacking direction D1.

[0096] The current path regions R5A1 and R5A2 of the lead frame 4B are regions that connect element connection regions R4A and R4B by a different path than the current path region R5, which connects element connection region R4A and element connection region R4B by the shortest path, bypassing them. The current path region R5A1 extends from element connection region R4A to element connection region R4B, passing through a position opposite the electrode lead-out portion PA2. The current path region R5A1 includes an electrode opposing region R511 (first electrode opposing region) corresponding to the electrode opposing region R51, an intermediate region R531 corresponding to the intermediate region R53, and an intermediate region R541 corresponding to the intermediate region R54.

[0097] The current path region R5A2 is located on the opposite side of the current path region R5A1, with the element connection regions R4A and R4B in between, along the intersecting direction D3. The current path region R5A2 is formed symmetrically, for example, with reference to the center positions of the element connection regions R4A and R4B in the intersecting direction D3. The current path region R5A2 extends from the element connection region R4A to the element connection region R4B, passing through a position opposite the electrode lead-out portion PA3. The current path region R5A2 includes the electrode opposing region R512 (third electrode opposing region), the intermediate region R532, and the intermediate region R542.

[0098] The electrode-facing region R512 is the region facing the extended portion P3b of the electrode extraction portion PA3 in the stacking direction D1. The electrode-facing region R512 is aligned with the extended portion P3b of the electrode extraction portion PA3 along the stacking direction D1, and both the extended portion P3b and R512 extend along the alignment direction D2. The intermediate region R532 is the region located between the electrode-facing region R512 and the element connection region R4A in the crossing direction D3. The intermediate region R532 connects the electrode-facing region R512 and the element connection region R4A along the crossing direction D3. The intermediate region R542 is the region located between the electrode-facing region R512 and the element connection region R4B in the crossing direction D3. The intermediate region R54 connects the electrode-facing region R511 and the element connection region R4B along the crossing direction D3.

[0099] As shown in Figure 12, a current E1 is input to the electrode lead-out portion PA2 of the element pad 91A1 through the connecting component. The current E1 input to the electrode lead-out portion PA2 flows along the arrangement direction D2 through the extension portion P2b of the electrode lead-out portion PA2, then folds back in the intersecting direction D3, passes through the extension portion P2a, and is input to the drain electrode 21D of the power semiconductor element 20A connected to the element connection portion PA1. The current E1 input to the drain electrode 21D is output as current E2 from the source electrode 21S of the power semiconductor element 20A. The current E2 output from the power semiconductor element 20A is input to the element connection region R4A of the lead frame 4B.

[0100] Current E1 is input to the electrode lead-out portion PA3 of the element pad 91A1 through the connecting component. The current E1 input to the electrode lead-out portion PA3 flows along the alignment direction D2 through the extension portion P3b of the electrode lead-out portion PA3, then folds back in the intersecting direction D3, passes through the extension portion P3a, and is input to the drain electrode 21D of the power semiconductor element 20A connected to the element connection portion PA1. The current E1 input to the drain electrode 21D is output as current E2 from the source electrode 21S of the power semiconductor element 20A. The current E2 output from the power semiconductor element 20A is input to the element connection region R4A of the lead frame 4B.

[0101] The main portion of the current E2 input to the element connection region R4A, current E2a (first current), flows through the shortest path, current path region R5, to the element connection region R4B. Current E2a is input from the element connection region R4B to the source electrode 21S of the power semiconductor element 20B and output as current E3 from the drain electrode 21D of the power semiconductor element 20B. Current E3 is input to the element connection portion PB1 of the element pad 91B. Current E3 input to the element connection portion PB1 flows through the electrode lead-out portion PB2 along the arrangement direction D2 and is output to the outside through another connection component.

[0102] Current E2b (second current), which is the other part of current E2 input to element connection region R4A, is a current branched off from the main current, current E2a. Current E2b flows from element connection region R4A to element connection region R4B through current path region R5A1, which is different from the shortest path, current path region R5. Specifically, current E2b flows from element connection region R4A along the crossing direction D3, passes through intermediate region R531, and then flows through electrode opposing region R511 along the alignment direction D2. After that, current E2b flows from electrode opposing region R511 to element connection region R4B, is input to the drain electrode 21D of power semiconductor element 20B, and merges with the main current, current E2a.

[0103] Current E2c (second current), which is the other part of current E2 input to element connection region R4A, is a current branched off from the main current, current E2a. Current E2c flows from element connection region R4A to element connection region R4B through current path region R5A2, which is different from the shortest path, current path region R5. Specifically, current E2c flows from element connection region R4A along the crossing direction D3, passes through intermediate region R532, and then flows through electrode opposing region R512 along the alignment direction D2. After that, current E2c flows from electrode opposing region R512 to element connection region R4B, is input to the drain electrode 21D of power semiconductor element 20B, and merges with the main current, current E2a. Then, current E3 output from source electrode 21S of power semiconductor element 20B flows through electrode lead-out section PB2 along the alignment direction D2 and is output to the outside through another connection component.

[0104] As shown in Figure 12, the direction of current E2b flowing through the current path region R5A1 of the lead frame 4B is opposite to the direction of current E1 flowing through the electrode lead-out section PA2 facing the current path region R5A1 in the stacking direction D1. The direction of current E2c flowing through the current path region R5A2 of the lead frame 4B is opposite to the direction of current E1 flowing through the electrode lead-out section PA3 facing the current path region R5A2 in the stacking direction D1. In this case, the direction of the magnetic fields generated by currents E2b and E2c flowing through the current path regions R5A1 and R5A2, respectively, is opposite to the direction of the magnetic field generated by current E1 flowing through the electrode lead-out section PA2, thus reducing parasitic inductance.

[0105] As shown in Figure 12, the electrode leads PA2 and PB2 are drawn out in the same direction (i.e., towards the side edge 3aa in the arrangement direction D2). The extension P2b of electrode leads PA2 is close to the extension P1a of electrode leads PB2 along the intersecting direction D3 with a gap G between them. The direction of current E1 flowing through the extension P2b of electrode leads PA2 is opposite to the direction of current E3 flowing through the extension P1a of electrode leads PB2. Electrode leads PA3 and PB2 are also drawn out in the same direction. The extension P3b of electrode leads PA3 is close to the extension P1a of electrode leads PB2 along the intersecting direction D3 with a gap between them. The direction of current E1 flowing through the extended portion P3b of electrode extraction portion PA3 is opposite to the direction of current E3 flowing through the extended portion P1a of electrode extraction portion PB2. In this case, the direction of the magnetic field generated by the current E1 flowing through the extended portion P2b of electrode extraction portion PA2 and the extended portion P3b of electrode extraction portion PA3 is opposite to the direction of the magnetic field generated by the current E3 flowing through the extended portion P1a of electrode extraction portion PB2, thus further reducing parasitic inductance.

[0106] Thus, in semiconductor module 1C, the effect of reducing parasitic inductance can be significantly obtained through the magnetic flux cancellation effect of currents E2b and E2c flowing through the lead frame 4B that overlaps the element pads 91A1 and 91B in the stacking direction D1, and the magnetic flux cancellation effect of currents E1 and E3 flowing through adjacent element pads 91A1 and 91B that are in close proximity to each other. In this way, semiconductor module 1C can obtain the effects of semiconductor module 1A of the first embodiment to a more significant degree.

[0107] <Fourth Embodiment> In the first to third embodiments, the semiconductor module had two functional elements. As shown in Figure 14, the fourth embodiment illustrates a semiconductor module 1D having four functional elements.

[0108] The semiconductor module 1D has two power semiconductor elements 20A and 20B and two diodes 80A and 80B as functional elements. The semiconductor module 1D forms a circuit element 10D that functions as a half-bridge circuit as shown in Figure 13. Circuit element 10D is the same as the circuit element 10A of the first embodiment shown in Figure 2, with the addition of two diodes 80A and 80B. Therefore, the connection configuration of the two power semiconductor elements 20A and 20B is the same as that of circuit element 10A of the first embodiment, so a detailed explanation is omitted. The cathode of diode 80A is connected to the drain of power semiconductor element 20A. The anode of diode 80A is connected to the source of power semiconductor element 20A. The cathode of diode 80B is connected to the drain of power semiconductor element 20B. The anode of diode 80B is connected to the source of power semiconductor element 20B.

[0109] The main surface 80a of diode 80A is in contact with the main surface 91a of element pad 91A. As a result, the cathode electrode 81K of diode 80A is connected to the drain electrode 21D of power semiconductor element 20A through element pad 91A. The back surface 80b of diode 80A is in contact with the back surface 4b of lead frame 4. As a result, the anode electrode 81A of diode 80A is connected to the source electrode 21S of power semiconductor element 20A through lead frame 4. The main surface 80a of diode 80B is in contact with the back surface 4b of lead frame 4. As a result, the cathode electrode 81K of diode 80B is connected to the drain electrode 21D of power semiconductor element 20B through lead frame 4. The back surface 80b of diode 80A is in contact with the main surface 91a of element pad 91B. As a result, the anode electrode 81A of diode 80A is connected to the source electrode 21S of power semiconductor element 20B through element pad 91B.

[0110] As described above, the semiconductor module 1D of the fourth embodiment can realize a circuit element 10D that has the function of a half-bridge circuit, including two power semiconductor elements 20A, 20B and two diodes 80A, 80B, by means of a lead frame 4 and two element pads 91A, 91B.

[0111] <Modification of the Fourth Embodiment> The semiconductor module 1D of the fourth embodiment may also use bonding material and TIM. Figure 15 is a cross-sectional view of a semiconductor module 1Da which is a modification of the fourth embodiment. The semiconductor module 1Da which is a modification of the fourth embodiment includes bonding materials 22T1, 22B1, 22T2, 22B2, 31B and TIM 36B. The bonding materials 22T1, 22B1, 22T2, 22B2, 31B and TIM 36B are the same as before, so their description is omitted. Furthermore, the semiconductor module 1Da includes bonding materials 82T1, 82B1, 82T2, and 82B2. Bonding material 82T1 is placed between the diode 80A and the lead frame 4. In other words, bonding material 82T1 bonds the diode 80A to the lead frame 4. Bonding material 82B1 is placed between the diode 80A and the element pad 91A. In other words, bonding material 82B1 bonds diode 80A to element pad 91A. Bonding material 82T2 is placed between diode 80B and lead frame 4. In other words, bonding material 82T2 bonds diode 80B to lead frame 4. Bonding material 82B2 is placed between diode 80B and element pad 91B. In other words, bonding material 82B2 bonds diode 80B to element pad 91B.

[0112] <Fifth Embodiment> The semiconductor module 1E of the fifth embodiment shown in Figure 16 comprises eight power semiconductor elements 20A1, 20A2, 20A3, 20A4, 20B1, 20B2, 20B3, and 20B4.

[0113] The normally mounted power semiconductor elements 20A1, 20A2, 20A3, and 20A4 are arranged on the element pad 91A. The element pad 91A connects the drain electrodes 21D of each of the power semiconductor elements 20A1, 20A2, 20A3, and 20A4 in parallel. Therefore, the element pad 91A functions as a P electrode. The power semiconductor elements 20A1, 20A2, 20A3, and 20A4 are, for example, arranged in a line along the crossing direction D3 on the element pad 91A.

[0114] The inverted power semiconductor elements 20B1, 20B2, 20B3, and 20B4 are arranged on the element pad 91B. The element pad 91B connects the source electrodes 21S of each power semiconductor element 20B1, 20B2, 20B3, and 20B4 in parallel. Therefore, the element pad 91B functions as the N electrode. The power semiconductor elements 20B1, 20B2, 20B3, and 20B4 are, for example, arranged in a line along the crossing direction D3 on the element pad 91B, and are arranged adjacent to each other along the arrangement direction D2 with respect to the power semiconductor elements 20A1, 20A2, 20A3, and 20A4.

[0115] The lead frame 4C is positioned to overlap with the eight power semiconductor elements 20A1, 20A2, 20A3, 20A4, 20B1, 20B2, 20B3, and 20B4. In other words, the lead frame 4C connects in parallel the source electrodes 21S of each power semiconductor element 20A1, 20A2, 20A3, and 20A4, and the drain electrodes 21D of each power semiconductor element 20B1, 20B2, 20B3, and 20B4. Therefore, the lead frame 4C functions as an output electrode.

[0116] The lead frame 4C is positioned offset along the array direction D2 from the element pads 91A and 91B, for example, so as not to overlap with the gate electrodes 21G and Kelvin electrodes 21K of the power semiconductor elements 20B1, 20B2, 20B3, and 20B4, respectively, in the stacking direction D1. As a result, the lead frame 4C overlaps with the element connection portion PB1 of the element pad 91B in the stacking direction D1, but does not overlap with the electrode lead-out portion PB2 of the element pad 91B in the stacking direction D1.

[0117] The element connection region R4A of the lead frame 4C is positioned to face the power semiconductor elements 20A1, 20A2, 20A3, and 20A4 in the stacking direction D1. The element connection region R4B of the lead frame 4C is positioned to face the power semiconductor elements 20B1, 20B2, 20B3, and 20B4 in the stacking direction D1. The current path region R5A of the lead frame 4C connects the element connection regions R4A and R4B via a different path than the current path region R5, which connects the element connection regions R4A and R4B via the shortest path, bypassing them. The current path region R5A includes an electrode-facing region R51 (first electrode-facing region) that faces the extended portion P2b of the electrode lead-out portion PA2 of the element pad 91A in the stacking direction D1, an intermediate region R53 located between the electrode-facing region R51 and the element connection region R4A in the intersecting direction D3, and an intermediate region R54 located between the electrode-facing region R51 and the element connection region R4B in the intersecting direction D3.

[0118] A semiconductor module 1E having such a configuration can achieve the same effects as the semiconductor module 1A of the first embodiment.

[0119] <Sixth Embodiment> The semiconductor module 1F of the sixth embodiment shown in Figure 17 also comprises eight power semiconductor elements 20A1, 20A2, 20A3, 20A4, 20B1, 20B2, 20B3, and 20B4. The eight power semiconductor elements 20A1, 20A2, 20A3, 20A4, 20B1, 20B2, 20B3, and 20B4 are connected by element pads 91A1, 91B and lead frames 4E. The arrangement and connection configuration of the eight power semiconductor elements 20A1, 20A2, 20A3, 20A4, 20B1, 20B2, 20B3, and 20B4 in the sixth embodiment is the same as that of the fifth embodiment. Therefore, a detailed explanation of this point is omitted.

[0120] The semiconductor module 1F of the sixth embodiment has, in addition to the configuration of the semiconductor module 1E of the fifth embodiment, an electrode lead-out portion PA3 of the element pad 91A1 and a current path region R5A2 of the lead frame 4D. The current path region R5A1 of the lead frame 4D corresponds to the current path region R5A of the lead frame 4C of the fifth embodiment. The electrode lead-out portion PA3 of the element pad 91A1 corresponds to the electrode lead-out portion PA3 of the element pad 91A1 provided in the semiconductor module 1C of the third embodiment described above. The configuration of the current path region R5A2 of the lead frame 4D corresponds to the current path region R5A2 of the lead frame 4B provided in the semiconductor module 1C of the third embodiment described above. Therefore, a detailed explanation of the electrode lead-out portion PA3 and the current path region R5A2 provided in the semiconductor module 1F is omitted.

[0121] A semiconductor module 1F having such a configuration can achieve the same effects as the semiconductor module 1A of the first embodiment.

[0122] <Seventh Embodiment> The semiconductor module 1G of the seventh embodiment shown in Figure 18 also comprises eight power semiconductor elements 20A1, 20A2, 20A3, 20A4, 20B1, 20B2, 20B3, and 20B4. In the semiconductor module 1G, power semiconductor elements 20A1 and 20A2 are adjacent to each other along the crossing direction D3. Power semiconductor elements 20A3 and 20A4 are adjacent to each other along the crossing direction D3 at positions separated from power semiconductor elements 20A1 and 20A2 along the crossing direction D3. Power semiconductor elements 20B1 and 20B2 are arranged along the crossing direction D3 so as to be adjacent to power semiconductor elements 20A1 and 20A2 along the array direction D2. Power semiconductor elements 20B3 and 20B4 are arranged along the crossing direction D3 so as to be adjacent to power semiconductor elements 20A3 and 20A4 along the array direction D2.

[0123] The semiconductor module 1G includes an element pad 91A2 connected to four power semiconductor elements 20A1, 20A2, 20A3, and 20A4, an element pad 91B1 connected to two power semiconductor elements 20B1 and 20B2, and an element pad 91B2 connected to two power semiconductor elements 20B3 and 20B4. The element pad 91A2 includes an element connection portion PA11 (first element connection portion) connected to the two power semiconductor elements 20A1 and 20A2, and an element connection portion PA12 connected to the two power semiconductor elements 20A3 and 20A4. The element connection portion PA11 is a region facing the two power semiconductor elements 20A1 and 20A2 in the stacking direction D1. The element connection portion PA12 is a region facing the two power semiconductor elements 20B1 and 20B2 in the stacking direction D1.

[0124] The element pad 91A2 further includes an electrode lead-out portion PA2 drawn out from the element connection portion PA11, an electrode lead-out portion PA3 drawn out from the element connection portions PA11 and PA12, and an electrode lead-out portion PA4 drawn out from the element connection portion PA12. The electrode lead-out portions PA2, PA3, and PA4 are drawn out in the same direction (i.e., along the side edge 3aa side of the array direction D2). The electrode lead-out portions PA2 and PA3 are positioned to sandwich the element connection portion PA11 in the intersecting direction D3. The electrode lead-out portions PA3 and PA4 are positioned to sandwich the element connection portion PA12 in the intersecting direction D3. Therefore, the element connection portion PA11 is positioned between the electrode lead-out portion PA2 and the electrode lead-out portion PA3 in the array direction D2. The element connection portion PA12 is positioned between the electrode lead-out portion PA3 and the electrode lead-out portion PA4 in the array direction D2.

[0125] The electrode extraction section PA2 includes an extension section P2b (first extension section) extending along the array direction D2, and an extension section P2a connecting the extension section P2b and the element connection section PA11 along the intersecting direction D3. The electrode extraction section PA3 includes an extension section P3b (third extension section) extending along the array direction D2, an extension section P3a connecting the extension section P3b and the element connection section PA11 along the intersecting direction D3, and an extension section P3c connecting the extension section P3b and the element connection section PA12 along the intersecting direction D3. The electrode extraction section PA4 includes an extension section P4b extending along the array direction D2, and an extension section P4a connecting the extension section P4b and the element connection section PA12 along the intersecting direction D3. The element pad 91B1 is positioned between the extended portion P2b of the electrode lead-out portion PA2 and the extended portion P3b of the electrode lead-out portion PA3 in the intersecting direction D3. The element pad 91B2 is positioned between the extended portion P3b of the electrode lead-out portion PA3 and the extended portion P4b of the electrode lead-out portion PA4 in the intersecting direction D3.

[0126] The lead frame 4E of the semiconductor module 1G is positioned, for example, to overlap all eight power semiconductor elements 20A1, 20A2, 20A3, 20A4, 20B1, 20B2, 20B3, and 20B4 in the stacking direction D1. The lead frame 4E is positioned offset along the array direction D2 from the element pads 91A2, 91B1, and 91B2 so that it is drawn out in the opposite direction to the direction in which the electrode lead-out portions PA2, PA3, and PA4 are drawn out.

[0127] The lead frame 4E includes element connection regions R4Aa and R4Ab (first element connection regions), element connection regions R4Ba and R4Bb (second element connection regions), current path regions R5a and R5b (first current path regions), and current path regions R5A1, R5A2, and R5A3 (second current path regions). Element connection region R4Aa is the region connected to two power semiconductor elements 20A1 and 20A2. Element connection region R4Aa overlaps with the two power semiconductor elements 20A1 and 20A2 in the stacking direction D1. Element connection region R4Ab is the region connected to two power semiconductor elements 20A3 and 20A4. Element connection region R4Ab overlaps with the two power semiconductor elements 20A3 and 20A4 in the stacking direction D1. Element connection region R4Ba is the region connected to two power semiconductor elements 20B1 and 20B2. The element connection region R4Ba overlaps with two power semiconductor elements 20B1 and 20B2 in the stacking direction D1. The element connection region R4Bb is the region connected to two power semiconductor elements 20B3 and 20B4. The element connection region R4Bb overlaps with two power semiconductor elements 20B3 and 20B4 in the stacking direction D1.

[0128] Current path region R5a is located between element connection region R4Aa and element connection region R4Ba in the array direction D2, and connects element connection region R4Aa and element connection region R4Ba via the shortest path. Current path region R5b is located between element connection region R4Ab and element connection region R4Bb in the array direction D2, and connects element connection region R4Ab and element connection region R4Bb via the shortest path. Current path region R5A1 is a region that connects element connection region R4Aa and element connection region R4Ba via a different path than current path region R5a. Current path region R5A1 extends from element connection region R4Aa to element connection region R4Ba via a position facing the electrode lead-out portion PA2. The current path region R5A1 includes an electrode-facing region R511 (first electrode-facing region) corresponding to the electrode-facing region R51 of the first embodiment, an intermediate region R531 corresponding to the intermediate region R53 of the first embodiment, and an intermediate region R541 corresponding to the intermediate region R54 of the first embodiment.

[0129] The current path region R5A2 is located on the opposite side of the current path region R5A1, with the element connection regions R4Aa and R4Ba in between, along the intersecting direction D3. The current path region R5A2 extends from the element connection region R4Aa to the element connection region R4Ba, passing through a position opposite the electrode lead-out section PA3. It can also be said that the current path region R5A2 extends from the element connection region R4Ab to the element connection region R4Bb, passing through a position opposite the electrode lead-out section PA3. The current path region R5A2 includes the electrode opposing region R512 (third electrode opposing region), a pair of intermediate regions R532, and a pair of intermediate regions R542.

[0130] The electrode-facing region R512 is the region facing the extended portion P3b of the electrode extraction portion PA3 in the stacking direction D1. The electrode-facing region R512 is aligned with the extended portion P3b of the electrode extraction portion PA3 along the stacking direction D1 and extends together with the extended portion P3b along the arrangement direction D2.

[0131] One of the pair of intermediate regions R532 is located between the electrode-facing region R512 and the element connection region R4Aa in the intersecting direction D3, and connects the electrode-facing region R512 and the element connection region R4Aa along the intersecting direction D3. The other of the pair of intermediate regions R532 is located between the electrode-facing region R512 and the element connection region R4Ab in the intersecting direction D3, and connects the electrode-facing region R512 and the element connection region R4Ab along the intersecting direction D3.

[0132] One of the pair of intermediate regions R542 is located between the electrode-facing region R512 and the element connection region R4Ba in the intersecting direction D3, and connects the electrode-facing region R512 and the element connection region R4Ba along the intersecting direction D3. The other of the pair of intermediate regions R542 is located between the electrode-facing region R512 and the element connection region R4Bb in the intersecting direction D3, and connects the electrode-facing region R512 and the element connection region R4Bb along the intersecting direction D3.

[0133] The current path region R5A3 is located along the intersecting direction D3, flanking the element connection regions R4Ab and R4Bb, and is opposite to the current path region R5A2. The current path region R5A3 extends from the element connection region R4Ab to the element connection region R4Bb, passing through a position opposite the electrode lead-out portion PA4. The current path region R5A3 includes the electrode opposing region R513, the intermediate region R533, and the intermediate region R543.

[0134] The electrode-facing region R513 is the region facing the extended portion P4b of the electrode extraction portion PA4 in the stacking direction D1. The electrode-facing region R513 is aligned with the extended portion P4b of the electrode extraction portion PA4 along the stacking direction D1 and extends together with the extended portion P4b along the arrangement direction D2. The intermediate region R533 is the region located between the electrode-facing region R513 and the element connection region R4Ab in the crossing direction D3. The intermediate region R533 connects the electrode-facing region R513 and the element connection region R4Ab along the crossing direction D3. The intermediate region R543 is the region located between the electrode-facing region R513 and the element connection region R4Bb in the crossing direction D3. The intermediate region R543 connects the electrode-facing region R513 and the element connection region R4Bb along the crossing direction D3.

[0135] A semiconductor module 1G having such a configuration can achieve the same effects as the semiconductor module 1A of the first embodiment.

[0136] <Eighth Embodiment> The semiconductor module 1H of the eighth embodiment shown in Figure 19 differs from the semiconductor module 1A of the first embodiment in that it includes a lead frame 4F that includes a current path region R5B (second current path region) instead of the lead frame 4 that includes a current path region R5A. The other components of the semiconductor module 1H are the same as those of the semiconductor module 1A of the first embodiment.

[0137] The current path region R5B of the lead frame 4F includes an electrode-facing region R51 (first electrode-facing region), an intermediate region R53, and an intermediate region R55 (first intermediate region). The intermediate region R55 is located between the electrode-facing region R51 and the element connection region R4B in the intersecting direction D3. The intermediate region R55 connects the electrode-facing region R51 and the element connection region R4B along the intersecting direction D3. The main surface 32a of the insulating layer 32 is exposed from between the electrode-facing region R51 and the element connection region R4B in the intersecting direction D3.

[0138] The main surface 32a of the insulating layer 32 between the electrode-facing region R51 and the element-connecting region R4B is aligned in a direction D3 that intersects with the region along the arrangement direction D2 in which the power semiconductor elements 20A and 20B are arranged, and extends along the arrangement direction D2 in the gap G. The intermediate region R55 faces the main surface 32a of the insulating layer 32 between the electrode-facing region R51 and the element-connecting region R4B in the stacking direction D1.

[0139] A current E1 is input to the electrode lead-out portion PA2 of the element pad 91A through a connecting component. The current E1 input to the electrode lead-out portion PA2 flows along the arrangement direction D2 through the extension portion P2b of the electrode lead-out portion PA2, then folds back in the intersecting direction D3, passes through the extension portion P2a, and is input to the drain electrode 21D of the power semiconductor element 20A connected to the element connection portion PA1. The current E1 input to the drain electrode 21D is output as current E2 from the source electrode 21S of the power semiconductor element 20A. The current E2 output from the power semiconductor element 20A is input to the element connection region R4A of the lead frame 4.

[0140] The main portion of the current E2 input to the element connection region R4A, current E2a (first current), flows through the shortest path, current path region R5, to the element connection region R4B. Current E2a is input from the element connection region R4B to the source electrode 21S of the power semiconductor element 20B and output as current E3 from the drain electrode 21D of the power semiconductor element 20B. Current E3 is input to the element connection portion PB1 of the element pad 91B. Current E3 input to the element connection portion PB1 flows through the electrode lead-out portion PB2 along the arrangement direction D2 and is output to the outside through another connection component.

[0141] Current E2b (second current), which is the other part of current E2 input to element connection region R4A, flows from element connection region R4A to element connection region R4B through current path region R5B, which is different from the shortest path current path region R5. Current E2b that has flowed through current path region R5B flows from element connection region R4A in the crossing direction D3, passes through intermediate region R53, and then flows through electrode opposing region R51 along the alignment direction D2. After that, current E2b flows from electrode opposing region R51 along the crossing direction D3, passing through intermediate region R55, and is input to element connection region R4B. Current E2b is input to the drain electrode 21D of power semiconductor element 20B via element connection region R4B and merges with the main current, current E2a. Current E3 output from source electrode 21S of power semiconductor element 20B flows through electrode lead-out section PB2 along the alignment direction D2 and is output to the outside through another connection component.

[0142] A semiconductor module 1H having such a configuration can achieve the same effects as the semiconductor module 1A of the first embodiment.

[0143] The semiconductor module of the present invention is not limited to the first to eighth embodiments described above and their modifications, and various modifications are possible without departing from the spirit of the present invention.

[0144] For example, the following are examples of combinations of the first and second functional elements and their mounting configurations: • First configuration: A unipolar transistor with a vertical structure is normally mounted as the first functional element, and a unipolar transistor with a vertical structure is inverted as the second functional element. • Second configuration: A unipolar transistor with a vertical structure is normally mounted as the first functional element, and a bipolar transistor is inverted as the second functional element. • Third configuration: A unipolar transistor with a vertical structure is normally mounted as the first functional element, and a diode is inverted as the second functional element. • Fourth configuration: A bipolar transistor is normally mounted as the first functional element, and a unipolar transistor with a vertical structure is inverted as the second functional element. • Fifth configuration: A bipolar transistor is normally mounted as the first functional element, and a bipolar transistor is inverted as the second functional element. • Sixth configuration: A bipolar transistor is normally mounted as the first functional element, and a diode is inverted as the second functional element. - Seventh configuration: A diode is normally mounted as the first functional element, and a unipolar transistor with a vertical structure is inverted as the second functional element. - Eighth configuration: A diode is normally mounted as the first functional element, and a bipolar transistor is inverted as the second functional element. - Ninth configuration: A diode is normally mounted as the first functional element, and a diode is inverted as the second functional element.

[0145] [Note] This disclosure includes the following:

[0146] This disclosure includes: [1] a first functional element including a first electrode and a second electrode positioned opposite the first electrode; a second functional element including a third electrode and a fourth electrode positioned opposite the third electrode; a lead frame to which the first electrode of the first functional element is connected and to which the third electrode of the second functional element is connected; and a substrate unit including a substrate electrode on the main surface of the substrate to which the second electrode of the first functional element is connected and to which the fourth electrode of the second functional element is connected, wherein the function of the first electrode of the first functional element is different from the function of the third electrode of the second functional element; the substrate electrode includes: a first element connection portion connected to the second electrode of the first functional element; a second element connection portion connected to the fourth electrode of the second functional element; and an electrode lead portion drawn out from at least one of the first element connection portion and the second element connection portion, through which a current flows toward the first element connection portion or a current flows toward the second element connection portion. The lead frame is A semiconductor module comprising: a first element connection region connected to the first electrode of the first functional element, to which the current is input from the first functional element; a second element connection region connected to the third electrode of the second functional element, to which the current input to the first element connection region is output; a first current path region disposed between the first element connection region and the second element connection region, through which the first current of the current input to the first element connection region flows toward the second element connection region; and a second current path region disposed along the normal direction of the main surface of the substrate, opposite the electrode lead-out portion, through which the second current of the current input to the first element connection region flows toward the second element connection region via a path different from the first current flowing through the first current path region.

[0147] The present disclosure is [2] "The substrate electrode includes, as the electrode extraction portion, a first electrode extraction portion drawn out from the first element connection portion and through which the current toward the first element connection portion flows, and a second electrode extraction portion drawn out from the second element connection portion and through which the current discharged from the second element connection portion flows, wherein the first electrode extraction portion includes a first extension portion extending along a first direction along the main surface of the substrate, and the second electrode extraction portion includes a second extension portion extending along the first direction and adjacent to the first extension portion with a gap between it and the first extension portion along a second direction intersecting the first direction, as described in [1] above."

[0148] This disclosure is [3] "the semiconductor module according to [2] above, wherein the width of the gap between the first extension and the second extension in the second direction is smaller than the respective widths of the first extension and the second extension in the second direction."

[0149] This disclosure is [4] "the semiconductor module according to [2] or [3] above, wherein the first functional element is aligned with the second functional element along the first direction, the second current path region is positioned opposite to the first extension portion along the normal direction, and includes a first electrode facing region that extends along the first direction alongside the first extension portion."

[0150] This disclosure is [5] "The substrate electrode includes, as the electrode extraction portion, a first electrode extraction portion drawn out from the first element connection portion and through which the current toward the first element connection portion flows, and a second electrode extraction portion drawn out from the second element connection portion and through which the current discharged from the second element connection portion flows, and the second current path region includes a first electrode facing region facing the first electrode extraction portion in the direction normal to the first electrode extraction portion, and a second electrode facing region facing the second electrode extraction portion in the direction normal to the second electrode extraction portion, as described in any of [2] to [4] above."

[0151] This disclosure is [6] "the semiconductor module according to [5] above, wherein when viewed along the normal direction, the area of ​​the first electrode-facing region is different from the area of ​​the second electrode-facing region."

[0152] The present disclosure is [7] "a semiconductor module according to any one of [2] to [6] above, wherein the first electrode lead portion further includes a third extending portion that extends along the first direction and is located in the second direction on the opposite side of the second extending portion, with the second extending portion in between, and the third extending portion is adjacent to the second extending portion with a gap between them, in the second direction."

[0153] The present disclosure is [8] "the semiconductor module according to [7] above, wherein the second current path region includes a first electrode facing region facing the first extension portion in the direction normal to the extension portion, a second electrode facing region facing the second extension portion in the direction normal to the extension portion, and a third electrode facing region facing the third extension portion in the direction normal to the extension portion."

[0154] This disclosure is [9] "The substrate electrode includes, as the electrode lead portion, a first electrode lead portion drawn out from the first element connection portion and through which the current toward the first element connection portion flows, and a second electrode lead portion drawn out from the second element connection portion and through which the current discharged from the second element connection portion flows, wherein the first electrode lead portion and the second electrode lead portion are drawn out so as to extend toward the first end of the main surface of the substrate in a first direction along the main surface of the substrate, and the lead frame is drawn out in a direction opposite to the direction in which the first electrode lead portion and the second electrode lead portion are drawn out, to a position in the normal direction that does not face the substrate electrode."

[0155] This disclosure is

[10] "The substrate electrode includes a first electrode lead portion, which is led out from the first element connection portion along a first direction along the main surface of the substrate and through which a current toward the first element connection portion flows, the second functional element is positioned in a position aligned with the first functional element along the first direction and aligned with the first electrode lead portion along a second direction intersecting the first direction, the substrate unit has an insulating layer including the main surface of the substrate on which the substrate electrode is provided, and the second current path region includes a first electrode facing region facing the first electrode lead portion along the normal direction, and a first intermediate region facing the insulating layer between the first electrode lead portion and the second functional element along the normal direction, the semiconductor module according to any one of [1] to [9] above."

[0156] This disclosure includes

[11] a first functional element including a first electrode and a second electrode positioned opposite to the first electrode; a second functional element including a third electrode and a fourth electrode positioned opposite to the third electrode; a lead frame to which the first electrode of the first functional element is connected and to which the third electrode of the second functional element is connected; and a substrate unit including a substrate electrode on the main surface of the substrate to which the second electrode of the first functional element is connected and to which the fourth electrode of the second functional element is connected, wherein the function of the first electrode of the first functional element is different from the function of the third electrode of the second functional element; the substrate electrode includes a first element connection portion connected to the second electrode of the first functional element; a second element connection portion connected to the fourth electrode of the second functional element; and an electrode lead portion drawn out from at least one of the first element connection portion and the second element connection portion, through which a current flows toward the first element connection portion or a current flows toward the second element connection portion; and the lead frame is A semiconductor module comprising: a first element connection region connected to the first electrode of the first functional element; a second element connection region connected to the third electrode of the second functional element; a first current path region disposed between the first element connection region and the second element connection region; and a second current path region disposed along the normal direction of the main surface of the substrate, facing the electrode lead-out portion.

[0157] 1A, 1Aa, 1Ab, 1Ac, 1Ad, 1Ae, 1Af, 1B, 1Ba, 1C, 1D, 1Da, 1E, 1F, 1G, 1H Semiconductor module 3, 3Aa, 3Ab Substrate unit 3a Main surface of substrate 3aa Side edge (first end) 4, 4A, 4B, 4C, 4D, 4E, 4F Lead frame 4aa, 91Aa, 91Ba First end 21D Drain electrode (second electrode, third electrode) 21S Source electrode (first electrode, fourth electrode) 32 Insulating layer 91 Substrate electrode D1 Stacking direction (normal direction) D2 Alignment direction (first direction) D3 Crossing direction (second direction) E1, E2, E3 Current E2a Current (first current) E2b, E2c Current (second current) G Gap P1a Extension part (second extension part) P2b Extension part (first extension part) P3b Extension part (third extension part) PA1, PA11 Element connection part (first element connection part) PA2, PA3 Electrode extraction part (first electrode extraction part) PB1 Element connection part (second element connection part) PB2 Electrode extraction part (second electrode extraction part) R4A Element connection area (first element connection area) R4B Element connection area (second element connection area) R5 Current path area (first current path area) R5A, R5B Current path area (second current path area) R51, R511 Electrode facing area (first electrode facing area) R52 Electrode facing area (second electrode facing area) R512 Electrode facing area (third electrode facing area) R55 Intermediate area (first intermediate area) W1, W2, W3 width

Claims

1. A first functional element including a first electrode and a second electrode positioned opposite the first electrode; a second functional element including a third electrode and a fourth electrode positioned opposite the third electrode; a lead frame to which the first electrode of the first functional element is connected and to which the third electrode of the second functional element is connected; and a substrate unit including a substrate electrode on the main surface of the substrate to which the second electrode of the first functional element is connected and to which the fourth electrode of the second functional element is connected, wherein the function of the first electrode of the first functional element is different from the function of the third electrode of the second functional element; the substrate electrode includes a first element connection portion connected to the second electrode of the first functional element; a second element connection portion connected to the fourth electrode of the second functional element; and an electrode lead portion drawn out from at least one of the first element connection portion and the second element connection portion, through which a current flows toward the first element connection portion or a current flows toward the second element connection portion; and the lead frame is A semiconductor module comprising: a first element connection region connected to the first electrode of the first functional element and to which the current is input from the first functional element; a second element connection region connected to the third electrode of the second functional element and to which the current input to the first element connection region is output; a first current path region disposed between the first element connection region and the second element connection region, through which the first current of the current input to the first element connection region flows toward the second element connection region; and a second current path region disposed along the normal direction of the main surface of the substrate and opposite the electrode lead portion, through which the second current of the current input to the first element connection region flows toward the second element connection region via a path different from the first current flowing through the first current path region.

2. The semiconductor module according to claim 1, wherein the substrate electrode includes, as the electrode extraction portion, a first electrode extraction portion drawn out from the first element connection portion and through which the current toward the first element connection portion flows, and a second electrode extraction portion drawn out from the second element connection portion and through which the current discharged from the second element connection portion flows, the first electrode extraction portion includes a first extension portion extending along a first direction along the main surface of the substrate, and the second electrode extraction portion includes a second extension portion extending along the first direction and adjacent to the first extension portion with a gap between it and the first extension portion along a second direction intersecting the first direction.

3. The semiconductor module according to claim 2, wherein the width of the gap between the first extended portion and the second extended portion in the second direction is smaller than the respective widths of the first extended portion and the second extended portion in the second direction.

4. The semiconductor module according to claim 2 or 3, wherein the first functional element is aligned with the second functional element along the first direction, and the second current path region is positioned opposite the first extending portion along the normal direction and includes a first electrode facing region that extends along the first direction alongside the first extending portion.

5. The semiconductor module according to any one of claims 1 to 3, wherein the substrate electrode includes, as the electrode extraction portion, a first electrode extraction portion drawn out from the first element connection portion and through which the current toward the first element connection portion flows, and a second electrode extraction portion drawn out from the second element connection portion and through which the current discharged from the second element connection portion flows, and the second current path region includes a first electrode facing region facing the first electrode extraction portion in the direction normal to the first electrode extraction portion, and a second electrode facing region facing the second electrode extraction portion in the direction normal to the second electrode extraction portion.

6. The semiconductor module according to claim 5, wherein, when viewed along the normal direction, the area of ​​the region facing the first electrode is different from the area of ​​the region facing the second electrode.

7. The semiconductor module according to claim 2 or 3, wherein the first electrode lead portion further includes a third extending portion that extends along the first direction and is located in the second direction on the opposite side of the second extending portion, with the second extending portion in between, and the third extending portion is adjacent to the second extending portion with a gap between them in the second direction.

8. The semiconductor module according to claim 7, wherein the second current path region includes a first electrode facing region facing the first extending portion in the direction normal to the first extending portion, a second electrode facing region facing the second extending portion in the direction normal to the second extending portion, and a third electrode facing region facing the third extending portion in the direction normal to the third extending portion.

9. The semiconductor module according to any one of claims 1 to 3, wherein the substrate electrode includes, as the electrode lead portion, a first electrode lead portion drawn out from the first element connection portion and through which the current toward the first element connection portion flows, and a second electrode lead portion drawn out from the second element connection portion and through which the current discharged from the second element connection portion flows, the first electrode lead portion and the second electrode lead portion are drawn out so as to extend toward the first end of the main surface of the substrate in a first direction along the main surface of the substrate, and the lead frame is drawn out in a direction opposite to the direction in which the first electrode lead portion and the second electrode lead portion are drawn out, to a position in the normal direction that does not face the substrate electrode.

10. The semiconductor module according to any one of claims 1 to 3, wherein the substrate electrode includes a first electrode lead portion, which is led out from the first element connection portion along a first direction along the main surface of the substrate and through which a current toward the first element connection portion flows; the second functional element is positioned in a position aligned with the first functional element along the first direction and aligned with the first electrode lead portion along a second direction intersecting the first direction; the substrate unit has an insulating layer including the main surface of the substrate on which the substrate electrode is provided; and the second current path region includes a first electrode facing region facing the first electrode lead portion along the normal direction; and a first intermediate region facing the insulating layer between the first electrode lead portion and the second functional element along the normal direction.

11. A first functional element including a first electrode and a second electrode positioned opposite the first electrode; a second functional element including a third electrode and a fourth electrode positioned opposite the third electrode; a lead frame to which the first electrode of the first functional element is connected and to which the third electrode of the second functional element is connected; and a substrate unit including a substrate electrode on the main surface of the substrate to which the second electrode of the first functional element is connected and to which the fourth electrode of the second functional element is connected, wherein the function of the first electrode of the first functional element is different from the function of the third electrode of the second functional element; the substrate electrode includes a first element connection portion connected to the second electrode of the first functional element; a second element connection portion connected to the fourth electrode of the second functional element; and an electrode lead portion drawn out from at least one of the first element connection portion and the second element connection portion, through which a current flows toward the first element connection portion or a current flows toward the second element connection portion; and the lead frame is A semiconductor module comprising: a first element connection region connected to the first electrode of the first functional element; a second element connection region connected to the third electrode of the second functional element; a first current path region disposed between the first element connection region and the second element connection region; and a second current path region disposed in a position facing the electrode lead portion along the normal direction of the main surface of the substrate.

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