Light detection device

Abstract

The present disclosure relates to a light detection device that makes it possible to achieve even greater improvements in performance. SPAD pixels include: a cathode contact which is provided at a center part of a surface of a semiconductor substrate and is directly connected to an electrode for supplying a cathode potential to a multiplication region for multiplying charges generated in a photoelectric conversion part; and an anode contact which is provided at an outer peripheral part of the surface of the semiconductor substrate within a certain range from the surface to a predetermined depth, and is connected to a light shielding metal for supplying an anode potential to the multiplication region via a conductor. The anode contact and the conductor are connected via a connection surface along at least the depth direction of the semiconductor substrate. The present technology can be applied to, for example, a light detection device provided with SPAD pixels.

Description

Optical detection device

[0001] The present disclosure relates to an optical detection device, and particularly to an optical detection device that can achieve further performance improvement.

[0002] In recent years, for example, the development of SPAD (Single Photon Avalanche Diode) pixels having a multiplication mechanism by a high electric field region provided by applying a high voltage of about 20 V between an anode and a cathode and capable of detecting one electron has been advanced. Conventionally, in a SPAD pixel, a P+ diffusion layer serving as an anode contact is electrically connected to a light-shielding metal provided in a pixel isolation portion via polysilicon provided on the surface side of a semiconductor substrate, and the light-shielding metal is used to supply an anode potential from the outside.

[0003] For example, Patent Document 1 discloses a SPAD pixel having a structure that suppresses edge breakdown by securing a distance between an anode and a cathode by making contact with the anode at a step portion in a stepped sidewall structure. Further, Patent Document 2 discloses a SPAD pixel having a structure that suppresses the generation of dark current by reducing damage by forming an anode or a cathode by high-concentration epitaxial growth instead of forming the anode or the cathode by high-concentration impurity implantation.

[0004] Japanese Patent Application Laid-Open No. 2022-55214, Japanese Patent Application Laid-Open No. 2022-114788

[0005] However, as mentioned above, in a connection structure where the P+ diffusion layer that serves as the anode contact is connected to polysilicon only on the surface side of the semiconductor substrate, as pixel size is miniaturized, for example, it becomes impossible to secure a sufficient connection area, resulting in increased contact resistance. Furthermore, when the contact resistance to the P+ diffusion layer that serves as the anode contact is high, high-intensity light irradiation of the SPAD pixel causes frequent multiplication due to reverse breakdown, which slows down the power supply and consequently slows down the voltage recovery. As a result, the potential supplied to the anode of the SPAD pixel gradually increases, reducing the multiplication probability at high light levels, and consequently worsening the signal-to-noise ratio (SN). Moreover, there is concern that this may result in the SPAD pixel becoming inoperable, and it is necessary to avoid such a degradation in SPAD pixel performance.

[0006] Furthermore, as SPAD pixels are miniaturized, the distance between the anode and cathode narrows, increasing the surface electric field and potentially worsening the Dark Count Rate (DCR), which is equivalent to the dark current. Additionally, as SPAD pixels are miniaturized, the trench width decreases, reducing the contact area between the polysilicon and the light-shielding metal, which is also a concern as it may increase contact resistance.

[0007] This disclosure is made in light of these circumstances and aims to enable further performance improvements.

[0008] The first aspect of the present disclosure of the photodetector includes a semiconductor substrate on which a photoelectric conversion unit is provided that generates an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface; a cathode contact provided in the center of the front surface opposite to the back surface of the semiconductor substrate and directly connected to an electrode that supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit; and an anode contact provided on the semiconductor substrate in a certain range from the outer periphery of the front surface to a predetermined depth from the front surface and connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region, wherein the anode contact and the conductor are connected via a connection surface at least along the depth direction of the semiconductor substrate.

[0009] In a first aspect of this disclosure, the cathode contact is provided in the center of the surface opposite to the back surface of a semiconductor substrate, where a photoelectric conversion unit is provided that generates an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface. The cathode contact is directly connected to an electrode that supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit. The anode contact is provided on the semiconductor substrate in a certain range from the outer periphery of the surface to a predetermined depth from the surface. The anode contact is connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region. The anode contact and the conductor are connected via a connection surface that is at least along the depth direction of the semiconductor substrate.

[0010] A second aspect of the present disclosure of a photodetector includes a semiconductor substrate on which a photoelectric conversion unit is provided that generates an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface; a cathode contact provided in the center of the front surface opposite to the back surface of the semiconductor substrate and directly connected to an electrode that supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit; and an anode contact provided in a stepped portion formed inside a trench provided in the semiconductor substrate so as to surround the outer periphery in order to separate it from other adjacent pixels, and at a position at a predetermined depth from the surface, and connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region, wherein the conductor and the light-shielding metal are connected via a connection surface along the depth direction of the semiconductor substrate.

[0011] In a second aspect of this disclosure, the cathode contact is directly connected to an electrode provided in the center of the front surface opposite to the back surface of the semiconductor substrate, which is provided in the center of the front surface opposite to the back surface of the semiconductor substrate and supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit. The anode contact is provided in a stepped portion formed inside a trench provided in the semiconductor substrate so as to surround the outer periphery in order to isolate it from other adjacent pixels, and is provided in a stepped portion formed at a predetermined depth from the surface, and is connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region. The conductor and the light-shielding metal are connected via a connection surface along the depth direction of the semiconductor substrate.

[0012] This is a cross-sectional view showing an example configuration of a first embodiment of a SPAD pixel provided in a photodetector to which this technology is applied. This is a plan view cross-sectional view of the SPAD pixel in Figure 1. This is a diagram illustrating the first to third steps. This is a diagram illustrating the fourth to sixth steps. This is a diagram illustrating the seventh to ninth steps. This is a diagram illustrating the tenth to twelfth steps. This is a diagram illustrating the thirteenth to fifteenth steps. This is a diagram illustrating the sixteenth to eighteenth steps. This is a diagram illustrating the nineteenth to twenty-first steps. This is a diagram illustrating the twenty-second to twenty-fourth steps. This is a cross-sectional view showing an example configuration of a first variation of the SPAD pixel. This is a plan view cross-sectional view of the SPAD pixel in Figure 11. This is a first cross-sectional view showing an example configuration of a second variation of the SPAD pixel. This is a second cross-sectional view showing an example configuration of a second variation of the SPAD pixel. This is a plan view cross-sectional view of the SPAD pixel in Figures 13 and 14. This is a cross-sectional view showing an example configuration of a third variation of the SPAD pixel. This is a plan view cross-sectional view of the SPAD pixel in Figure 16. This is a cross-sectional view showing an example configuration of a fourth variation of the SPAD pixel. Figure 18 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the fifth variation of the SPAD pixel. Figure 20 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the sixth variation of the SPAD pixel. Figure 22 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the seventh variation of the SPAD pixel. Figure 24 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the eighth variation of the SPAD pixel. Figure 26 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the ninth variation of the SPAD pixel. Figure 28 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the tenth variation of the SPAD pixel. Figure 30 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the eleventh variation of the SPAD pixel. Figure 32 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the twelfth variation of the SPAD pixel. Figure 34 is a planar cross-sectional view of a SPAD pixel. This is a cross-sectional view showing an example configuration of the thirteenth variation of the SPAD pixel. Figure 36 is a planar cross-sectional view of a SPAD pixel.This is a cross-sectional view showing an example configuration of a second embodiment of a SPAD pixel provided in a photodetector to which this technology is applied. This is a planar cross-sectional view of the SPAD pixel in Figure 38. This is a diagram illustrating steps 101 to 103. This is a diagram illustrating steps 104 to 106. This is a diagram illustrating steps 107 to 109. This is a diagram illustrating steps 110 to 112. This is a diagram illustrating steps 113 to 115. This is a diagram illustrating steps 116 to 118. This is a diagram illustrating steps 119 to 121. This is a diagram illustrating steps 122 to 124. This is a diagram illustrating steps 125 to 127. This is a first cross-sectional view showing an example configuration of a first variation of the SPAD pixel. This is a second cross-sectional view showing an example configuration of a first variation of the SPAD pixel. This is a planar cross-sectional view of the SPAD pixel in Figures 49 and 50. This is a first cross-sectional view showing an example configuration of a second variation of the SPAD pixel. This is a second cross-sectional view showing an example configuration of a second variation of the SPAD pixel. This is a planar cross-sectional view of the SPAD pixel in Figures 52 and 53. This is a first cross-sectional view showing an example configuration of a third variation of the SPAD pixel. This is a second cross-sectional view showing an example configuration of a third variation of the SPAD pixel. This is a planar cross-sectional view of the SPAD pixel in Figures 55 and 56. This is a cross-sectional view showing an example configuration of a fourth variation of the SPAD pixel. This is a cross-sectional view showing an example configuration of a fifth variation of the SPAD pixel. This is a cross-sectional view showing an example configuration of a sixth variation of the SPAD pixel. This is a first cross-sectional view showing an example configuration of a seventh variation of the SPAD pixel. This is a second cross-sectional view showing an example configuration of a seventh variation of the SPAD pixel. This is a first cross-sectional view showing an example configuration of an eighth variation of the SPAD pixel. This is a second cross-sectional view showing an example configuration of an eighth variation of the SPAD pixel. This is a cross-sectional view showing an example configuration of stacked pixel transistor layers. This is a cross-sectional view showing an example configuration of a third embodiment of the SPAD pixel provided in a photodetector to which this technology is applied. This is a diagram illustrating steps 201 to 203. This is a diagram illustrating steps 204 to 206. This is a diagram illustrating steps 207 through 209. This is a diagram illustrating steps 210 through 212.This is a diagram illustrating steps 213 to 215. This is a diagram illustrating steps 216 to 218. This is a diagram illustrating steps 219 to 221. This is a diagram illustrating steps 222 and 223. This is a diagram illustrating steps 224 and 225. This is a cross-sectional view showing an example configuration of the first variation of the SPAD pixel. This is a cross-sectional view showing an example configuration of the second variation of the SPAD pixel. This is a planar cross-sectional view of the SPAD pixel in Figure 77. This is a cross-sectional view showing an example configuration of the third variation of the SPAD pixel. This is a cross-sectional view showing an example configuration of the fourth variation of the SPAD pixel. This is a cross-sectional view showing an example configuration of the fifth variation of the SPAD pixel. This is a diagram illustrating steps 231 to 233. This is a cross-sectional view showing an example configuration of the sixth variation of the SPAD pixel. This is a cross-sectional view showing an example configuration of the seventh variation of the SPAD pixel. This is a diagram illustrating the connection structure of the VRLD power supply at the outermost periphery of the sensor substrate. This is a diagram illustrating steps 241 and 242. This is a diagram illustrating steps 243 and 244. This is a diagram illustrating steps 245 and 246. This is a cross-sectional view showing an example configuration of the eighth variation of the SPAD pixel. This is a diagram illustrating steps 251 to 253. This is a diagram illustrating steps 254 and 255. This is a diagram illustrating steps 256 and 257. This is a cross-sectional view showing an example configuration of the fourth embodiment of the SPAD pixel provided in a photodetector to which this technology is applied. This is a diagram illustrating steps 301 to 303. This is a diagram illustrating steps 304 to 306. This is a diagram illustrating steps 307 to 309. This is a diagram illustrating steps 310 and 311. This is a cross-sectional view showing an example configuration of the first variation of the SPAD pixel. This is a block diagram showing an example configuration of an imaging device. This is a diagram showing an example of use using an image sensor.

[0013] The following describes in detail a specific embodiment of this technology, with reference to the drawings.

[0014] <First Configuration Example of SPAD Pixel> Referring to Figures 1 to 37, a configuration example of a first embodiment of a SPAD pixel provided in a photodetector to which this technology is applied will be described.

[0015] Figures 1 and 2 are cross-sectional views showing an example of the configuration of a SPAD pixel in the first embodiment.

[0016] Figure 1 is a side cross-sectional view of the SPAD pixel 11 along the dashed line C-C shown in Figure 2. Figure 2A is a plan cross-sectional view of the SPAD pixel 11 along the dashed line A-A shown in Figure 1, and Figure 2B is a plan cross-sectional view of the SPAD pixel 11 along the dashed line B-B shown in Figure 1.

[0017] As shown in Figures 1 and 2, the SPAD pixel 11 is constructed by providing an N+ diffusion layer 22 as the cathode contact, an N diffusion layer 23 as the cathode, a P+ diffusion layer 24 as the anode contact, and a P diffusion layer 25 as the anode on a semiconductor substrate 21. The SPAD pixel 11 converts light incident from the back surface of the semiconductor substrate 21 (the surface facing upward in Figure 1) into electricity using a photoelectric conversion unit formed by the PN junction of the N diffusion layer 23 and the P diffusion layer 25, and then multiplies the charge generated by this photoelectric conversion using a multiplication region for output. Furthermore, as shown in Figure 2, the SPAD pixel 11 is formed so that its cross-sectional shape in plan view is rectangular.

[0018] The N+ diffusion layer 22 is located in the center of the surface of the semiconductor substrate 21 (the side facing downwards in Figure 1) and is directly connected to the electrode metal 26 that supplies the cathode potential to the multiplication region.

[0019] The N diffusion layer 23 is provided in the central part near the surface of the semiconductor substrate 21 so as to connect to the N+ diffusion layer 22.

[0020] The P+ diffusion layer 24 is provided in a region that is on the outer periphery of the surface of the semiconductor substrate 21 and extends to a predetermined depth from the surface of the semiconductor substrate 21, and is connected to a light-shielding metal 28 that supplies an anode potential to the multiplication region via a high-concentration polysilicon layer 27.

[0021] The P diffusion layer 25 is provided along the outer periphery of the semiconductor substrate 21 so as to connect with the P+ diffusion layer 24, and to cover the side surface of the semiconductor substrate 21 from the P+ diffusion layer 24 to the back surface of the semiconductor substrate 21. Furthermore, the P diffusion layer 25 is provided so as to traverse a predetermined region on the surface side of the center in the depth direction of the semiconductor substrate 21, and is formed to have an H-shaped cross-section as shown in Figure 1.

[0022] Each SPAD pixel 11 is configured such that a light-shielding metal 28 surrounds the area where the SPAD pixels 11 are provided, separating them from other adjacent SPAD pixels 11 and shielding the sides of the SPAD pixels 11 from light. A power supply for supplying anode potential from an external source is connected to the light-shielding metal 28.

[0023] The SPAD pixel 11 is constructed by placing a high-density polysilicon layer 27, which is a conductor for electrically connecting the P+ diffusion layer 24 and the light-shielding metal 28, between the P+ diffusion layer 24 and the light-shielding metal 28. The high-density polysilicon layer 27 is composed of a portion that extends in the depth direction of the semiconductor substrate 21 between the P+ diffusion layer 24 and the light-shielding metal 28, and a portion that extends along the surface of the semiconductor substrate 21, and is formed to have an L-shaped cross-section as shown in Figure 1. The high-density polysilicon layer 27 and the P+ diffusion layer 24 are connected to each other via a connection surface along the depth direction of the semiconductor substrate 21, and via the surface of the semiconductor substrate 21 that is substantially perpendicular to the connection surface.

[0024] The SPAD pixel 11 is configured with a fixed charge film 29 provided to surround the side surface of the P diffusion layer 25 and cover the back surface of the semiconductor substrate 21, in order to suppress the generation of dark current.

[0025] The SPAD pixel 11 is configured with a silicon oxide film 30 and a silicon nitride film 31 provided to insulate each part.

[0026] Each SPAD pixel 11 is constructed by stacking an on-chip lens 32 that focuses light on the light incident surface.

[0027] Thus, the SPAD pixel 11 is configured with a connection structure in which the P+ diffusion layer 24 and the high-density polysilicon layer 27 are connected via a connection surface along the depth direction of the semiconductor substrate 21. As a result, the SPAD pixel 11 can increase the connection area for supplying anode potential to the P+ diffusion layer 24 compared to a connection structure in which, for example, the P+ diffusion layer 24 is connected to the high-density polysilicon layer 27 only on the surface side of the semiconductor substrate 21. Consequently, the SPAD pixel 11 can reduce the contact resistance at the connection surface for supplying anode potential to the P+ diffusion layer 24, which in turn can improve the signal-to-noise ratio (S / N) at high light levels, for example, and further improve performance.

[0028] Furthermore, as the SPAD pixels 11 are miniaturized, the connection area on the surface of the semiconductor substrate 21 decreases. Even with such miniaturized SPAD pixels 11, a sufficient connection area for supplying anode potential to the P+ diffusion layer 24 can be secured by using a connection structure in which the P+ diffusion layer 24 and the high-concentration polysilicon layer 27 are connected via a connection surface along the depth direction of the semiconductor substrate 21.

[0029] In the SPAD pixel 11, a high-density polysilicon layer 27 is used, but the conductor provided between the P+ diffusion layer 24 and the light-shielding metal 28 is not limited to the high-density polysilicon layer 27, and may be a material such as metal. Furthermore, the SPAD pixel 11 has a connection structure in which a conductor (high-density polysilicon layer 27) is provided in a part of the element isolation section to connect the P+ diffusion layer 24 and the light-shielding metal 28, but a conductor may be provided in a part other than the element isolation section as long as the connection structure is such that the P+ diffusion layer 24 is connected via a connection surface along the depth direction of the semiconductor substrate 21.

[0030] A method for manufacturing the SPAD pixel 11 will be described with reference to Figures 3 to 10.

[0031] In the first step, as shown in the upper part of Figure 3, a silicon nitride film 41 is formed on the semiconductor substrate 21, and a silicon oxide film 42 is formed on the silicon nitride film 41.

[0032] In the second step, as shown in the middle of Figure 3, dry etching is performed on the semiconductor substrate 21, the silicon nitride film 41, and the silicon oxide film 42 to create deep trenches (FTI: Full Trench Isolation) in the semiconductor substrate 21 so as to surround the area where the SPAD pixels 11 are provided.

[0033] In the third step, for example, by diffusing P-type impurities using a solid-phase diffusion method, a P-diffusion layer 25 is formed on the side walls and bottom surface of the deep trench prepared in the second step, as shown in the lower part of Figure 3.

[0034] In the fourth step, the silicon oxide film 42 is removed as shown in the upper part of Figure 4. Then, a thin oxide film (not shown) is formed on the surface of the P diffusion layer 25.

[0035] In the fifth step, a polysilicon 43 film is formed to fill the inside of the trench. At this time, after forming the polysilicon 43 film, the polysilicon 43 is etched back to a predetermined depth so that the surface of the polysilicon 43 is lower than the surface of the semiconductor substrate 21, as shown in the middle of Figure 4.

[0036] In the sixth step, for example, using high-density plasma (HDP), a silicon oxide film 30 is deposited so as to be layered inside the trench and on the silicon nitride film 41, as shown in the lower part of Figure 4. As a result, the silicon oxide film 30 is embedded in the areas where the polysilicon 43 was etched back in the fifth step.

[0037] In the seventh step, for example, chemical mechanical polishing (CMP) is used to remove the silicon oxide film 30 laminated on the silicon nitride film 41 until the surface of the silicon nitride film 41 is exposed. This flattens the surface as shown in the upper part of Figure 5.

[0038] In the eighth step, as shown in the middle of Figure 5, the silicon nitride film 41 stacked on the semiconductor substrate 21 is removed.

[0039] In the ninth step, for example, by performing impurity implantation (II: Ion Implantation) or the like, as shown in the lower part of FIG. 5, an N+ diffusion layer 22, an N diffusion layer 23, a P+ diffusion layer 24, and a P diffusion layer 25 are formed on the semiconductor substrate 21.

[0040] In the tenth step, for example, TEOS (Tetra Eth Oxy Silane) is deposited to form a silicon oxide film 30 on the surface of the semiconductor substrate 21, as shown in the upper part of FIG. 6.

[0041] In the eleventh step, as shown in the middle part of FIG. 6, a mask 44 is formed on the silicon oxide film 30. For example, the mask 44 is formed to have an opening according to the region where polysilicon 45 to be described later is formed.

[0042] In the twelfth step, dry etching is performed to remove the silicon oxide film 30 in the locations corresponding to the openings of the mask 44 by shallowly digging. At this time, the depth at which the silicon oxide film 30 is removed within the trench corresponds to the depth where the high-concentration polysilicon layer 27 is provided. Thereafter, as shown in the lower part of FIG. 6, the mask 44 is also removed.

[0043] In the thirteenth step, as shown in the upper part of FIG. 7, polysilicon 45 is deposited to fill the portion where the silicon oxide film 30 was removed in the twelfth step and to be laminated on the surface of the silicon oxide film 30.

[0044] In the fourteenth step, for example, using chemical mechanical polishing, the polysilicon 45 laminated on the silicon oxide film 30 is scraped off until the surface of the silicon oxide film 30 is exposed. Thereby, as shown in the middle part of FIG. 7, the surface is planarized.

[0045] In the fifteenth step, as shown in the lower part of FIG. 7, a silicon nitride film 31 is deposited on the surfaces of the silicon oxide film 30 and the polysilicon 45, and then a silicon oxide film 30 is further deposited.

[0046] In the sixteenth step, as shown in the upper part of FIG. 8, an electrode metal 26 is formed to penetrate the silicon oxide film 30 and the silicon nitride film 31 and connect to the N+ diffusion layer 22.

[0047] In the 17th step, as shown in the middle row of FIG. 8, the semiconductor substrate 21 is inverted.

[0048] In the 18th step, as shown in the bottom row of FIG. 8, the semiconductor substrate 21 is thinned until the polysilicon 43 is exposed.

[0049] In the 19th step, as shown in the upper row of FIG. 9, the polysilicon 43 in the trench is removed.

[0050] In the 20th step, the thin oxide film (not shown) formed in the above-described 4th step is washed out from the surface of the P diffusion layer 25, and an SCF film (not shown) is formed. Then, as shown in the middle row of FIG. 9, a fixed charge film 29 is formed on the side surface in the trench and the back surface of the semiconductor substrate 21.

[0051] In the 21st step, as shown in the bottom row of FIG. 9, a silicon oxide film 30 is formed on the side surface and the bottom surface in the trench and on the fixed charge film 29.

[0052] In the 22nd step, by etching back the bottom surface of the trench until the silicon nitride film 31 is exposed, the silicon oxide film 30 and the polysilicon 45 on the bottom surface of the trench are removed. As a result, the polysilicon 45 is separated from other adjacent SPAD pixels 11, and a high-concentration polysilicon layer 27 is formed as shown in the upper row of FIG. 10.

[0053] In the 23rd step, as shown in the middle row of FIG. 10, a light-shielding metal 28 is formed by embedding a metal inside the trench.

[0054] In the 24th step, the surface is planarized by forming a silicon oxide film 30, and an on-chip lens 32 is formed on the surface, whereby the SPAD pixel 11 is manufactured as shown in the bottom row of FIG. 10.

[0055] By the manufacturing method described above, a SPAD pixel 11 can be manufactured in which a high-density polysilicon layer 27 is provided, which is connected to the P+ diffusion layer 24 via a connection surface along the depth direction of the semiconductor substrate 21, by dry etching the silicon oxide film 30 embedded in the trench provided in the semiconductor substrate 21 to a predetermined depth, and then embedding polysilicon 45 in that area.

[0056] Figures 11 and 12 are cross-sectional views showing an example configuration of a first variation of the SPAD pixel 11. In the SPAD pixel 11A shown in Figures 11 and 12, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0057] Figure 11 is a side cross-sectional view of the SPAD pixel 11A along the dashed line C-C shown in Figure 12. Figure 12A is a plan cross-sectional view of the SPAD pixel 11A along the dashed line A-A shown in Figure 11, and Figure 12B is a plan cross-sectional view of the SPAD pixel 11A along the dashed line B-B shown in Figure 11.

[0058] As shown in Figures 11 and 12, the SPAD pixel 11A is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 11 in Figures 1 and 2, in that it is provided with a semiconductor substrate 21, an N+ diffusion layer 22, an N diffusion layer 23, a P+ diffusion layer 24, a P diffusion layer 25, an electrode metal 26, a fixed charge film 29, a silicon oxide film 30, a silicon nitride film 31, and an on-chip lens 32.

[0059] Furthermore, the SPAD pixel 11A differs from the SPAD pixel 11 in Figures 1 and 2 in that the width of the light-shielding metal 28A on the surface side of the semiconductor substrate 21 is formed to a predetermined depth from the surface of the semiconductor substrate 21 (a depth corresponding to a certain range in which the P+ diffusion layer 24 is provided), and the side surface of this widened portion is configured to be a connection surface that connects to the P+ diffusion layer 24. In addition, the SPAD pixel 11A differs from the SPAD pixel 11 in Figures 1 and 2 in that the high-density polysilicon layer 27A is formed only on the surface side of the semiconductor substrate 21 and is connected to the P+ diffusion layer 24 only on the surface of the semiconductor substrate 21.

[0060] In other words, the SPAD pixel 11A is configured with a connection structure in which the light-shielding metal 28A and the P+ diffusion layer 24 are connected via a connection surface along the depth direction of the semiconductor substrate 21, and the high-concentration polysilicon layer 27A and the P+ diffusion layer 24 are connected via the surface of the semiconductor substrate 21.

[0061] The SPAD pixel 11A configured in this way, like the SPAD pixel 11 in Figures 1 and 2, can increase the connection area for supplying the anode potential to the P+ diffusion layer 24. As a result, the SPAD pixel 11A can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (S / N) at high light levels.

[0062] Figures 13 to 15 are cross-sectional views showing an example configuration of a second variation of the SPAD pixel 11. In the SPAD pixel 11B shown in Figures 13 to 15, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0063] Figure 13 is a lateral cross-sectional view of the SPAD pixel 11B along the dashed line C-C shown in Figure 15, and Figure 14 is a lateral cross-sectional view of the SPAD pixel 11B in an oblique direction along the dashed line D-D shown in Figure 15. Figure 15A is a planar cross-sectional view of the SPAD pixel 11B along the dashed line A-A shown in Figures 13 and 14, and Figure 15B is a planar cross-sectional view of the SPAD pixel 11B along the dashed line B-B shown in Figures 13 and 14.

[0064] As shown in Figures 13 to 15, the SPAD pixel 11B is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 11 in Figures 1 and 2, in that it is provided with a semiconductor substrate 21, an N+ diffusion layer 22, an N diffusion layer 23, a P diffusion layer 25, an electrode metal 26, a light-shielding metal 28, a fixed charge film 29, a silicon oxide film 30, a silicon nitride film 31, and an on-chip lens 32.

[0065] Furthermore, as shown in Figure 15, the SPAD pixel 11B has a different configuration from the SPAD pixel 11 in Figures 1 and 2, in that the P+ diffusion layer 24B and the high-density polysilicon layer 27B are provided only near the four corners of the SPAD pixel 11B.

[0066] In other words, the SPAD pixel 11B is configured with a connection structure in which, when viewed from above, the P+ diffusion layer 24B and the high-density polysilicon layer 27B are connected via a connection surface that is aligned with the depth direction of the semiconductor substrate 21, near the four corners. In the SPAD pixel 11B, the connection surface between the P+ diffusion layer 24B and the high-density polysilicon layer 27B is located on the outside of the P+ diffusion layer 24B (on the opposite side from the side of the P+ diffusion layer 24B that faces the center of the semiconductor substrate 21).

[0067] The SPAD pixel 11B configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24 compared to a configuration in which, for example, the high-density polysilicon layer 27B is connected to the P+ diffusion layer 24 only on the surface side of the semiconductor substrate 21 near the four corners when viewed from a planar perspective. As a result, the SPAD pixel 11B can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0068] Figures 16 and 17 are cross-sectional views showing a configuration example of a third variation of the SPAD pixel 11. In the SPAD pixel 11C shown in Figures 16 and 17, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0069] Figure 16 is a side cross-sectional view of the SPAD pixel 11C in an oblique direction along the dashed line D-D shown in Figure 17. Figure 17A is a plan cross-sectional view of the SPAD pixel 11C along the dashed line A-A shown in Figure 16, and Figure 17B is a plan cross-sectional view of the SPAD pixel 11C along the dashed line B-B shown in Figure 16.

[0070] As shown in Figures 16 and 17, the SPAD pixel 11C has a configuration common to the SPAD pixel 11 in Figures 1 and 2, in that it is provided with an N+ diffusion layer 22, an N diffusion layer 23, an electrode metal 26, and a silicon nitride film 31.

[0071] Furthermore, as shown in Figure 17, the SPAD pixel 11C is formed with an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 21C, P+ diffusion layer 24C, P diffusion layer 25C, high-concentration polysilicon layer 27C, light-shielding metal 28C, fixed charge film 29C, silicon oxide film 30C, and on-chip lens 32C are provided, which is a configuration that differs from the SPAD pixel 11 in Figures 1 and 2.

[0072] For example, the SPAD pixel 11C is configured such that the P+ diffusion layer 24C and the high-density polysilicon layer 27C are provided on a protruding portion where, in a plan view, one side of an octagon protrudes outward by a predetermined width. The SPAD pixel 11C is configured with a connection structure in which the P+ diffusion layer 24C and the high-density polysilicon layer 27C are connected via a connection surface along the depth direction of the semiconductor substrate 21C on three of the outer sides of the P+ diffusion layer 24C (three sides other than the inner side that faces the center of the semiconductor substrate 21C from the protruding portion).

[0073] The SPAD pixel 11C configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24C compared to a configuration in which, for example, the high-concentration polysilicon layer 27C is connected to the P+ diffusion layer 24C only on the surface side of the semiconductor substrate 21C at a protruding portion where one side of the octagon protrudes outward by a predetermined width when viewed from above. Consequently, the SPAD pixel 11C can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0074] Figures 18 and 19 are cross-sectional views showing an example configuration of a fourth variation of the SPAD pixel 11. In the SPAD pixel 11D shown in Figures 18 and 19, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0075] Figure 18 is a side cross-sectional view of the SPAD pixel 11D in an oblique direction along the dashed line D-D shown in Figure 19. Figure 19 is a plan cross-sectional view of the SPAD pixel 11D along the dashed line A-A shown in Figure 18.

[0076] As shown in Figures 18 and 19, the SPAD pixel 11D has a configuration common to the SPAD pixel 11 in Figures 1 and 2, in that it is provided with an N+ diffusion layer 22, an N diffusion layer 23, an electrode metal 26, and a silicon nitride film 31.

[0077] Furthermore, as shown in Figure 19, the SPAD pixel 11D is formed with an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 21D, P+ diffusion layer 24D, P diffusion layer 25D, high-concentration polysilicon layer 27D, light-shielding metal 28D, fixed charge film 29D, silicon oxide film 30D, and on-chip lens 32D are provided, which is a configuration that differs from the SPAD pixel 11 in Figures 1 and 2.

[0078] For example, the SPAD pixel 11D is configured such that the P+ diffusion layer 24D and the high-density polysilicon layer 27D are provided on a protruding portion where, in a plan view, one side of an octagon protrudes outward by a predetermined width. The SPAD pixel 11D is configured with a connection structure in which, at the protruding portion, the P+ diffusion layer 24D and the high-density polysilicon layer 27D are connected via a connection surface along the depth direction of the semiconductor substrate 21D on one side that is on the inside of the P+ diffusion layer 24D (the side that faces the center of the semiconductor substrate 21D from the protruding portion).

[0079] The SPAD pixel 11D configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24D compared to a configuration in which, for example, the high-density polysilicon layer 27D is connected to the P+ diffusion layer 24D only on the surface side of the semiconductor substrate 21D at a protruding portion where one side of the octagon protrudes outward by a predetermined width when viewed from above. Consequently, the SPAD pixel 11D can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0080] Figures 20 and 21 are cross-sectional views showing a configuration example of a fifth variation of the SPAD pixel 11. In the SPAD pixel 11E shown in Figures 20 and 21, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0081] Figure 20 is a side cross-sectional view of the SPAD pixel 11E in an oblique direction along the dashed line D-D shown in Figure 21. Figure 21 is a plan cross-sectional view of the SPAD pixel 11E along the dashed line A-A shown in Figure 20.

[0082] As shown in Figures 20 and 21, the SPAD pixel 11E is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 11 in Figures 1 and 2, in that it is provided with a semiconductor substrate 21, an N+ diffusion layer 22, an N diffusion layer 23, a P diffusion layer 25, an electrode metal 26, a fixed charge film 29, a silicon oxide film 30, a silicon nitride film 31, and an on-chip lens 32.

[0083] Furthermore, as shown in Figure 21, the SPAD pixel 11E has a different configuration from the SPAD pixel 11 in Figures 1 and 2, in that the P+ diffusion layer 24E and the high-density polysilicon layer 27E are provided only near the four corners of the SPAD pixel 11E.

[0084] In other words, in the SPAD pixel 11E, when viewed from above, the P+ diffusion layer 24E and the high-density polysilicon layer 27E are connected via a connection surface that runs along the depth direction of the semiconductor substrate 21, near the four corners. Furthermore, in the SPAD pixel 11E, the connection surface between the P+ diffusion layer 24E and the high-density polysilicon layer 27E is located on the inside of the P+ diffusion layer 24E (the side facing the center of the semiconductor substrate 21 from the P+ diffusion layer 24E).

[0085] The SPAD pixel 11E configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24E compared to a configuration in which, for example, the high-density polysilicon layer 27E is connected to the P+ diffusion layer 24E only on the surface side of the semiconductor substrate 21 near the four corners when viewed from a planar perspective. As a result, the SPAD pixel 11E can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0086] Figures 22 and 23 are cross-sectional views showing an example configuration of a sixth variation of the SPAD pixel 11. In the SPAD pixel 11F shown in Figures 22 and 23, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0087] Figure 22 is a side cross-sectional view of the SPAD pixel 11F in the diagonal direction along the dashed line D-D shown in Figure 23. Figure 23 is a plan cross-sectional view of the SPAD pixel 11F along the dashed line A-A shown in Figure 22.

[0088] As shown in Figures 22 and 23, the SPAD pixel 11F is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 11 in Figures 1 and 2, in that it is provided with a semiconductor substrate 21, an N+ diffusion layer 22, an N diffusion layer 23, a P diffusion layer 25, an electrode metal 26, a fixed charge film 29, a silicon oxide film 30, a silicon nitride film 31, and an on-chip lens 32.

[0089] Furthermore, as shown in Figure 23, the SPAD pixel 11F has a different configuration from the SPAD pixel 11 in Figures 1 and 2, in that the P+ diffusion layer 24F and the high-density polysilicon layer 27F are provided only near the four corners of the SPAD pixel 11F, and a single protrusion is provided where a part of the high-density polysilicon layer 27F protrudes into the interior of the P+ diffusion layer 24F.

[0090] In other words, in the SPAD pixel 11F, when viewed from above, the side surfaces of the protrusions provided on the high-density polysilicon layer 27F and the P+ diffusion layer 24F are connected via a connection surface that is aligned with the depth direction of the semiconductor substrate 21, near the four corners, forming a connection structure.

[0091] Compared to a configuration in which, for example, the high-density polysilicon layer 27F is connected to the P+ diffusion layer 24F only on the surface side of the semiconductor substrate 21 near the four corners when viewed from above, the SPAD pixel 11F configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24E according to the protrusions provided on the high-density polysilicon layer 27F. As a result, the SPAD pixel 11F can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0092] In the examples shown in Figures 22 and 23, the protrusions provided on the high-concentration polysilicon layer 27F are formed in a cylindrical shape. However, the shape of these protrusions is not limited to a cylindrical shape and may be a triangular prism, a rectangular prism, or the like.

[0093] Figures 24 and 25 are cross-sectional views showing an example configuration of a seventh variation of the SPAD pixel 11. In the SPAD pixel 11G shown in Figures 24 and 25, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0094] Figure 24 is a side cross-sectional view of the SPAD pixel 11G in an oblique direction along the dashed line D-D shown in Figure 25. Figure 25 is a plan cross-sectional view of the SPAD pixel 11G along the dashed line A-A shown in Figure 24.

[0095] As shown in Figures 24 and 25, the SPAD pixel 11G has a configuration common to the SPAD pixel 11 in Figures 1 and 2, in that it is provided with an N+ diffusion layer 22, an N diffusion layer 23, an electrode metal 26, and a silicon nitride film 31.

[0096] Furthermore, as shown in Figure 25, the SPAD pixel 11G is formed with an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 21G, P+ diffusion layer 24G, P diffusion layer 25G, high-concentration polysilicon layer 27G, light-shielding metal 28G, fixed charge film 29G, silicon oxide film 30G, and on-chip lens 32G are provided, which is a configuration that differs from the SPAD pixel 11 in Figures 1 and 2.

[0097] For example, the SPAD pixel 11G is configured such that the P+ diffusion layer 24G and the high-density polysilicon layer 27G are provided on a protruding portion where, in a plan view, one side of an octagon protrudes outward by a predetermined width. Furthermore, the SPAD pixel 11G is provided with a single protrusion in its protruding portion, formed so that a part of the high-density polysilicon layer 27G protrudes into the interior of the P+ diffusion layer 24G, and the side surface of the protrusion and the P+ diffusion layer 24G are connected via a connection surface along the depth direction of the semiconductor substrate 21G.

[0098] Compared to a configuration in which, for example, the high-density polysilicon layer 27G is connected to the P+ diffusion layer 24G only on the surface side of the semiconductor substrate 21G at a protruding portion where one side of the octagon protrudes outward by a predetermined width when viewed from above, the SPAD pixel 11G configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24G according to the protrusions provided on the high-density polysilicon layer 27G. As a result, the SPAD pixel 11G can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0099] In the examples shown in Figures 24 and 25, the protrusions provided on the high-concentration polysilicon layer 27G are formed in a cylindrical shape. However, the shape of these protrusions is not limited to a cylindrical shape and may be a triangular prism shape, a rectangular prism shape, or the like.

[0100] Figures 26 and 27 are cross-sectional views showing an example configuration of an eighth variation of the SPAD pixel 11. In the SPAD pixel 11H shown in Figures 26 and 27, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0101] Figure 26 is a lateral cross-sectional view of the SPAD pixel 11H in an oblique direction along the dashed line D-D shown in Figure 27. Figure 27 is a planar cross-sectional view of the SPAD pixel 11H along the dashed line A-A shown in Figure 26.

[0102] As shown in Figures 26 and 27, the SPAD pixel 11H is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 11 in Figures 1 and 2, in that it is provided with a semiconductor substrate 21, an N+ diffusion layer 22, an N diffusion layer 23, a P diffusion layer 25, an electrode metal 26, a fixed charge film 29, a silicon oxide film 30, a silicon nitride film 31, and an on-chip lens 32.

[0103] Furthermore, as shown in Figure 27, the SPAD pixel 11H has a different configuration from the SPAD pixel 11 in Figures 1 and 2, in that the P+ diffusion layer 24H and the high-density polysilicon layer 27H are provided only near the four corners of the SPAD pixel 11H, and multiple protrusions are provided such that a portion of the high-density polysilicon layer 27H protrudes into the interior of the P+ diffusion layer 24H.

[0104] In other words, in the SPAD pixel 11H, when viewed from above, the sides of multiple protrusions provided on the high-density polysilicon layer 27H and the P+ diffusion layer 24H are connected via a connection surface along the depth direction of the semiconductor substrate 21, near the four corners, forming a connection structure.

[0105] Compared to a configuration in which, for example, the high-density polysilicon layer 27H is connected to the P+ diffusion layer 24H only on the surface side of the semiconductor substrate 21 near the four corners when viewed from above, the SPAD pixel 11H configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24H in accordance with the multiple protrusions provided on the high-density polysilicon layer 27H. As a result, the SPAD pixel 11H can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0106] In the examples shown in Figures 26 and 27, the multiple protrusions provided on the high-concentration polysilicon layer 27H are formed in a rectangular prism shape. However, the shape (concave and convex shape) of these multiple protrusions is not limited to a rectangular prism shape, and may be cylindrical, triangular prism, or other shapes.

[0107] Figures 28 and 29 are cross-sectional views showing an example configuration of the ninth variation of the SPAD pixel 11. In the SPAD pixel 11J shown in Figures 28 and 29, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0108] Figure 28 is a side cross-sectional view of the SPAD pixel 11J in an oblique direction along the dashed line D-D shown in Figure 29. Figure 29 is a plan cross-sectional view of the SPAD pixel 11J along the dashed line A-A shown in Figure 28.

[0109] As shown in Figures 28 and 29, the SPAD pixel 11J has a configuration common to the SPAD pixel 11 in Figures 1 and 2, in that it is provided with an N+ diffusion layer 22, an N diffusion layer 23, an electrode metal 26, and a silicon nitride film 31.

[0110] Furthermore, as shown in Figure 29, the SPAD pixel 11J is formed with an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 21J, P+ diffusion layer 24J, P diffusion layer 25J, high-concentration polysilicon layer 27J, light-shielding metal 28J, fixed charge film 29J, silicon oxide film 30J, and on-chip lens 32J are provided, which is a configuration that differs from the SPAD pixel 11 in Figures 1 and 2.

[0111] For example, the SPAD pixel 11J is configured such that the P+ diffusion layer 24J and the high-density polysilicon layer 27J are provided on a protruding portion where, in a plan view, one side of an octagon protrudes outward by a predetermined width. Furthermore, the SPAD pixel 11J is provided with a plurality of protrusions in its protruding portion, each of which is formed so that a portion of the high-density polysilicon layer 27J protrudes into the interior of the P+ diffusion layer 24J, and the side surfaces of these protrusions and the P+ diffusion layer 24J are connected via a connection surface along the depth direction of the semiconductor substrate 21J.

[0112] Compared to a configuration in which, for example, the high-concentration polysilicon layer 27J is connected to the P+ diffusion layer 24J only on the surface side of the semiconductor substrate 21J at a protruding portion where one side of the octagon protrudes outward by a predetermined width when viewed from above, the SPAD pixel 11J configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24J according to the multiple protrusions provided on the high-concentration polysilicon layer 27J. As a result, the SPAD pixel 11J can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0113] In the examples shown in Figures 28 and 29, the multiple protrusions provided on the high-concentration polysilicon layer 27J are formed in a rectangular prism shape. However, the shape (concave and convex shape) of these multiple protrusions is not limited to a rectangular prism shape, and may be cylindrical, triangular prism, or other shapes.

[0114] Figures 30 and 31 are cross-sectional views showing an example configuration of the tenth variation of the SPAD pixel 11. In the SPAD pixel 11K shown in Figures 30 and 31, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0115] Figure 30 is a side cross-sectional view of the SPAD pixel 11K in an oblique direction along the dashed line D-D shown in Figure 31. Figure 31 is a plan cross-sectional view of the SPAD pixel 11K along the dashed line A-A shown in Figure 30.

[0116] As shown in Figures 30 and 31, the SPAD pixel 11K is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 11 in Figures 1 and 2, in that it is provided with a semiconductor substrate 21, an N+ diffusion layer 22, an N diffusion layer 23, a P diffusion layer 25, an electrode metal 26, a fixed charge film 29, a silicon oxide film 30, a silicon nitride film 31, and an on-chip lens 32.

[0117] Furthermore, as shown in Figure 31, the SPAD pixel 11K has a different configuration from the SPAD pixel 11 in Figures 1 and 2, in that the P+ diffusion layer 24K and the high-density polysilicon layer 27K are provided only near the four corners of the SPAD pixel 11K, and multiple protrusions are provided such that a portion of the high-density polysilicon layer 27K protrudes into the interior of the P+ diffusion layer 24K.

[0118] In other words, in the SPAD pixel 11K, when viewed from above, the sides of multiple protrusions provided on the high-density polysilicon layer 27H and the P+ diffusion layer 24K are connected via a continuous surface along the depth direction of the semiconductor substrate 21, near the four corners, forming a connection structure.

[0119] Compared to a configuration in which, for example, the high-density polysilicon layer 27K is connected to the P+ diffusion layer 24K only on the surface side of the semiconductor substrate 21 near the four corners when viewed from above, the SPAD pixel 11K configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24K in accordance with the multiple protrusions provided on the high-density polysilicon layer 27K. As a result, the SPAD pixel 11K can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0120] In the examples shown in Figures 30 and 31, the multiple protrusions provided on the high-concentration polysilicon layer 27K are formed in a conical shape. However, the shape (concave and convex shape) of these multiple protrusions is not limited to a conical shape, and may be a triangular pyramidal shape, a square pyramidal shape, or the like.

[0121] Figures 32 and 33 are cross-sectional views showing an example configuration of the eleventh variation of the SPAD pixel 11. In the SPAD pixel 11L shown in Figures 32 and 33, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0122] Figure 32 is a side cross-sectional view of the SPAD pixel 11L in an oblique direction along the dashed line D-D shown in Figure 33. Figure 33 is a plan cross-sectional view of the SPAD pixel 11L along the dashed line A-A shown in Figure 32.

[0123] As shown in Figures 32 and 33, the SPAD pixel 11L has a configuration common to the SPAD pixel 11 in Figures 1 and 2, in that it is provided with an N+ diffusion layer 22, an N diffusion layer 23, an electrode metal 26, and a silicon nitride film 31.

[0124] Furthermore, as shown in Figure 33, the SPAD pixel 11L is formed in an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 21L, P+ diffusion layer 24L, P diffusion layer 25L, high-concentration polysilicon layer 27L, light-shielding metal 28L, fixed charge film 29L, silicon oxide film 30L, and on-chip lens 32L are provided, which is a configuration that differs from the SPAD pixel 11 in Figures 1 and 2.

[0125] For example, the SPAD pixel 11L is configured such that the P+ diffusion layer 24L and the high-density polysilicon layer 27L are provided on a protruding portion where, in a plan view, one side of an octagon protrudes outward by a predetermined width. Furthermore, the SPAD pixel 11L is provided with a plurality of protrusions in its protruding portion, which are formed so that a portion of the high-density polysilicon layer 27L protrudes into the interior of the P+ diffusion layer 24L, and the side surfaces of these protrusions and the P+ diffusion layer 24L are connected via a connection surface along the depth direction of the semiconductor substrate 21L.

[0126] Compared to a configuration in which, for example, the high-density polysilicon layer 27L is connected to the P+ diffusion layer 24L only on the surface side of the semiconductor substrate 21L at a protruding portion where one side of the octagon protrudes outward by a predetermined width when viewed from above, the SPAD pixel 11L configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24L according to the multiple protrusions provided on the high-density polysilicon layer 27L. As a result, the SPAD pixel 11L can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0127] In the examples shown in Figures 32 and 33, the protrusions on the high-concentration polysilicon layer 27L are formed in a conical shape. However, the shape (concave and convex shape) of these multiple protrusions is not limited to a conical shape, but may also be a triangular pyramidal shape, a square pyramidal shape, or the like.

[0128] Figures 34 and 35 are cross-sectional views showing an example configuration of the twelfth variation of the SPAD pixel 11. In the SPAD pixel 11M shown in Figures 34 and 35, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0129] Figure 34 is a side cross-sectional view of the SPAD pixel 11M in an oblique direction along the dashed line D-D shown in Figure 35. A in Figure 35 is a plan cross-sectional view of the SPAD pixel 11M along the dashed line A-A shown in Figure 34, and B in Figure 35 is a plan cross-sectional view of the SPAD pixel 11M along the dashed line B-B shown in Figure 1.

[0130] As shown in Figures 34 and 35, the SPAD pixel 11M has a configuration common to the SPAD pixel 11 in Figures 1 and 2, in that it is provided with an N+ diffusion layer 22, an N diffusion layer 23, an electrode metal 26, and a silicon nitride film 31.

[0131] Furthermore, as shown in Figure 35, the SPAD pixel 11M is formed with an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 21M, P+ diffusion layer 24M, P diffusion layer 25M, high-concentration polysilicon layer 27M, light-shielding metal 28M, fixed charge film 29M, silicon oxide film 30M, and on-chip lens 32M are provided, which is a configuration different from the SPAD pixel 11 in Figures 1 and 2.

[0132] For example, the SPAD pixel 11M is configured such that the P+ diffusion layer 24M and the high-density polysilicon layer 27M are provided on a protruding portion where, when viewed from above, one side of an octagon protrudes outward by a predetermined width. Furthermore, the SPAD pixel 11M is configured with a connection structure in which the high-density polysilicon layer 27M is connected to the P+ diffusion layer 24M via a connection surface along the depth direction of the semiconductor substrate 21M, such that the high-density polysilicon layer 27M surrounds the side surface of the P+ diffusion layer 24M.

[0133] The SPAD pixel 11M configured in this way can expand the connection area for supplying anode potential to the P+ diffusion layer 24M compared to a configuration in which, for example, the high-concentration polysilicon layer 27M is connected to the P+ diffusion layer 24M only on the surface side of the semiconductor substrate 21M at a protruding portion where one side of the octagon protrudes outward by a predetermined width when viewed from above. As a result, the SPAD pixel 11M can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0134] Figures 36 and 37 are cross-sectional views showing an example configuration of the thirteenth variation of the SPAD pixel 11. In the SPAD pixel 11N shown in Figures 36 and 37, components common to the SPAD pixel 11 shown in Figures 1 and 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0135] Figure 36 is a side cross-sectional view of the SPAD pixel 11N along the dashed line C-C shown in Figure 37. Figure 37A is a plan cross-sectional view of the SPAD pixel 11N along the dashed line A-A shown in Figure 36, and Figure 37B is a plan cross-sectional view of the SPAD pixel 11N along the dashed line B-B shown in Figure 36.

[0136] As shown in Figures 36 and 37, the SPAD pixel 11N is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 11 in Figures 1 and 2, in that it is provided with a semiconductor substrate 21, an N+ diffusion layer 22, an N diffusion layer 23, a P+ diffusion layer 24, a P diffusion layer 25, an electrode metal 26, a light-shielding metal 28, a fixed charge film 29, a silicon oxide film 30, a silicon nitride film 31, and an on-chip lens 32.

[0137] Furthermore, the SPAD pixel 11N differs from the SPAD pixel 11 in Figures 1 and 2 in that the high-density polysilicon layer 27N is provided between the P+ diffusion layer 24 and the light-shielding metal 28 (not on the surface side of the semiconductor substrate 21), and the P+ diffusion layer 24 and the high-density polysilicon layer 27N are connected to each other only via a connection surface along the depth direction of the semiconductor substrate 21.

[0138] In other words, the SPAD pixel 11N is configured with a connection structure in which the P+ diffusion layer 24 and the high-density polysilicon layer 27N are not connected on the surface of the semiconductor substrate 21, but are connected only at connection surfaces along the depth direction of the semiconductor substrate 21.

[0139] The SPAD pixel 11N configured in this way can increase the connection area for supplying anode potential to the P+ diffusion layer 24 along the depth direction of the semiconductor substrate 21. As a result, the SPAD pixel 11N can reduce the contact resistance at its connection surface, thereby improving the signal-to-noise ratio (SNR) at high light levels.

[0140] Furthermore, the shape of the high-concentration polysilicon layer 27N is not limited to the shapes shown in Figures 36 and 37, and various shapes can be adopted. Also, instead of the high-concentration polysilicon layer 27N, a material such as metal may be used as the conductor connecting the P+ diffusion layer 24 and the light-shielding metal 28, and the material is not limited.

[0141] <Second Configuration Example of SPAD Pixel> Referring to Figures 38 to 64, a configuration example of a second embodiment of a SPAD pixel provided in a photodetector to which this technology is applied will be described.

[0142] Figures 38 and 39 are cross-sectional views showing an example of the configuration of a SPAD pixel in the second embodiment.

[0143] Figure 38 is a side cross-sectional view of the SPAD pixel 111 along the dashed line C-C shown in Figure 39. Figure 39A is a plan cross-sectional view of the SPAD pixel 111 along the dashed line A-A shown in Figure 38, and Figure 39B is a plan cross-sectional view of the SPAD pixel 111 along the dashed line B-B shown in Figure 38.

[0144] As shown in Figures 38 and 39, the SPAD pixel 111 is constructed by providing an N+ diffusion layer 122 as the cathode contact, an N diffusion layer 123 as the cathode, a P+ diffusion layer 124 as the anode contact, and a P diffusion layer 125 as the anode on a semiconductor substrate 121. The SPAD pixel 111 converts light incident from the back surface of the semiconductor substrate 121 (the surface facing upward in Figure 38) into electricity using a photoelectric conversion unit formed by the PN junction of the N diffusion layer 123 and the P diffusion layer 125, and then multiplies the charge generated by this photoelectric conversion using a multiplication region for output. Also, as shown in Figure 39, the SPAD pixel 111 is formed so that its cross-sectional shape in plan view is rectangular.

[0145] The N+ diffusion layer 122 is located in the center of the surface of the semiconductor substrate 121 (the side facing downwards in Figure 38) and is directly connected to the electrode metal 126 that supplies the cathode potential to the multiplication region.

[0146] The N diffusion layer 123 is provided in the central part near the surface of the semiconductor substrate 121 so as to be connected to the N+ diffusion layer 122.

[0147] The P+ diffusion layer 124 is provided in a stepped portion formed inside a trench provided in the semiconductor substrate 121 to surround the outer periphery in order to separate the SPAD pixel 111 from other adjacent SPAD pixels 111, and is connected to a light-shielding metal 128 that supplies anode potential to the multiplication region via a high-concentration polysilicon layer 127. The stepped portion of the semiconductor substrate 121 on which the P+ diffusion layer 124 is provided is located at a predetermined depth from the surface of the semiconductor substrate 121, for example, at a position deeper than the multiplication region provided in the SPAD pixel 111. Furthermore, the width of the stepped portion of the semiconductor substrate 121 on which the P+ diffusion layer 124 is provided is set according to the difference in trench width between a shallow trench with a wide trench width formed from the surface side of the semiconductor substrate 121 (see the middle section of Figure 40) and a deep trench with a narrow trench width formed on its bottom surface (see the upper section of Figure 41), as will be described later.

[0148] The P diffusion layer 125 is provided along the outer periphery of the semiconductor substrate 121 so as to connect with the P+ diffusion layer 124, and to cover the side surface of the semiconductor substrate 121 from the P+ diffusion layer 124 to the back surface of the semiconductor substrate 121. Furthermore, the P diffusion layer 125 is provided so as to traverse a predetermined region on the surface side of the center in the depth direction of the semiconductor substrate 121. Note that the P diffusion layer 125 shown covering the back surface of the semiconductor substrate 121 represents the P layer that is automatically formed on the back surface of the semiconductor substrate 121 when the fixed charge film 129 is formed on the back surface of the semiconductor substrate 121 in step 123 (see Figure 47), which will be described later.

[0149] Each SPAD pixel 111 is configured such that a light-shielding metal 128 surrounds the area where the SPAD pixels 111 are provided, separating them from other adjacent SPAD pixels 111 and shielding the sides of the SPAD pixels 111 from light. A power supply for supplying an anode potential from the outside is connected to the light-shielding metal 128.

[0150] The SPAD pixel 111 is constructed by placing a high-density polysilicon layer 127, which is a conductor for electrically connecting the P+ diffusion layer 124 and the light-shielding metal 128, between the P+ diffusion layer 124 and the light-shielding metal 128. As will be described later, the high-density polysilicon layer 127 is embedded in a wide, shallow trench formed from the surface side of the semiconductor substrate 121, and is connected to the P+ diffusion layer 124 at the stepped portion that forms the bottom of the shallow trench. Except for the connection point with the P+ diffusion layer 124, it is insulated from the semiconductor substrate 121 by the silicon oxide film 130. The high-density polysilicon layer 127 is also connected to the light-shielding metal 128 via a connection surface (side surface of the high-density polysilicon layer 127) along the depth direction of the semiconductor substrate 121.

[0151] The SPAD pixel 111 is configured such that a fixed charge film 129 is provided to suppress the generation of dark current, covering the side and back surfaces of the semiconductor substrate 121 via a P diffusion layer 125.

[0152] The SPAD pixel 111 is configured with a silicon oxide film 130 and a silicon nitride film 131 for insulating each part.

[0153] Each SPAD pixel 111 is constructed by stacking an on-chip lens 132 that focuses light on the light incident surface.

[0154] In this way, the SPAD pixel 111 can be configured by providing a P+ diffusion layer 124 in a stepped portion formed inside a trench in the semiconductor substrate 121, and forming a high-density polysilicon layer 127 with a thickness from the surface of the semiconductor substrate 121 to a predetermined depth so as to connect to the semiconductor substrate 121 at that stepped portion. As a result, the SPAD pixel 111 can be configured such that the high-density polysilicon layer 127 and the light-shielding metal 128 are connected at the side surface of the high-density polysilicon layer 127, which has a certain thickness, and the connection area between the high-density polysilicon layer 127 and the light-shielding metal 128 can be increased. Consequently, even if the SPAD pixel 111 is miniaturized, the contact resistance can be reduced, resulting in improvements in performance, such as reduced power consumption and reduced IR drop.

[0155] Furthermore, compared to a configuration in which, for example, a P+ diffusion layer 124 is provided on the surface of the semiconductor substrate 121, the SPAD pixel 111 can have its spacing between the N+ diffusion layer 122 and the P+ diffusion layer 124 increased by providing the P+ diffusion layer 124 in a stepped portion formed inside a trench of the semiconductor substrate 121. As a result, even when the SPAD pixel 111 is miniaturized, the electric field near the surface of the semiconductor substrate 121 can be reduced, thereby suppressing the deterioration of DCR associated with the miniaturization of the SPAD pixel 111.

[0156] The manufacturing method for the SPAD pixel 111 will be described with reference to Figures 40 to 48.

[0157] In step 101, as shown in the upper part of Figure 40, a silicon nitride film 141 is formed on the semiconductor substrate 121, and a silicon oxide film 142 is formed on the silicon nitride film 141.

[0158] In step 102, as shown in the middle of Figure 40, dry etching is performed on the semiconductor substrate 121, the silicon nitride film 141, and the silicon oxide film 142 to process shallow trenches with a wide trench width in the semiconductor substrate 121 so as to surround the area where the SPAD pixels 111 are provided. At this time, the depth of the shallow trenches formed in the semiconductor substrate 121 corresponds to the position in the depth direction of the stepped portion where the P+ diffusion layer 124 is provided.

[0159] In step 103, as shown in the lower part of Figure 40, a silicon nitride film 141 is formed so as to be laminated on the side and bottom surfaces of the shallow trenches of the semiconductor substrate 121 prepared in step 102, and also laminated on the silicon oxide film 142.

[0160] In step 104, the silicon nitride film 141 laminated on the silicon oxide film 142 and the silicon nitride film 141 at the bottom of the shallow trench are removed. Then, as shown in the upper part of Figure 41, dry etching is performed on the semiconductor substrate 121 at the bottom of the shallow trench to process a deep trench (FTI: Full Trench Isolation) with a narrow trench width in the semiconductor substrate 121 so as to surround the area where the SPAD pixels 111 are provided.

[0161] In step 105, for example, by diffusing P-type impurities using a solid-phase diffusion method, a P-diffusion layer 125 is formed on the side walls and bottom surface of the deep trench prepared in step 104, as shown in the middle section of Figure 41.

[0162] In step 106, the silicon oxide film 142 is removed, and the silicon nitride film 141 on the side of the shallow trench provided in the semiconductor substrate 121 is also removed. As a result, as shown in the lower part of Figure 41, a stepped portion is provided at a predetermined depth from the surface of the semiconductor substrate 121, exposing the surface side of the semiconductor substrate 121. Subsequently, a thin oxide film (not shown) is formed on the surface of the P diffusion layer 125.

[0163] In step 107, polysilicon 143 is deposited to fill the inside of the trench. At this time, after depositing the polysilicon 143, the polysilicon 143 is etched back to a predetermined depth so that, as shown in the upper part of Figure 42, the surface of the polysilicon 143 is lower than the surface of the stepped portion provided inside the trench of the semiconductor substrate 121.

[0164] In step 108, for example, by performing impurity implantation (II: Ion Implantation), a P+ diffusion layer 124 is formed on the stepped portion provided inside the trench of the semiconductor substrate 121, as shown in the middle of Figure 42.

[0165] In step 109, for example, using high-density plasma (HDP), a silicon oxide film 130 is deposited so as to be layered inside the trench and on the silicon nitride film 141, as shown in the lower part of Figure 42. As a result, the silicon oxide film 130 is embedded in the areas where the polysilicon 143 was etched back in step 107.

[0166] In step 110, for example, chemical mechanical polishing (CMP) is used to remove the silicon oxide film 130 laminated on the silicon nitride film 141 until the surface of the silicon nitride film 141 is exposed. This flattens the surface as shown in the upper part of Figure 43.

[0167] In step 111, as shown in the middle of Figure 43, the silicon nitride film 141 stacked on the semiconductor substrate 121 is removed.

[0168] In step 112, for example, by impurity implantation, an N+ diffusion layer 122, an N diffusion layer 123, and a P diffusion layer 125 are formed on the semiconductor substrate 121, as shown in the lower part of Figure 43.

[0169] In step 113, for example, TEOS (Tetra Eth Oxy Silane) is deposited to form a silicon oxide film 130 on the surface of the semiconductor substrate 121, as shown in the upper part of Figure 44.

[0170] In step 114, a mask 144 is formed on the silicon oxide film 130, as shown in the middle section of Figure 44. For example, the mask 144 is formed to have openings in the region where the polysilicon 145, which will be described later, is formed.

[0171] In step 115, the silicon oxide film 130 in the area corresponding to the opening of the mask 144 is removed by dry etching in a shallow manner. At this time, the silicon oxide film 130 is etched so that the P+ diffusion layer 124, which will be in contact with the high-concentration polysilicon layer 127, is exposed, and the silicon oxide film 130 remains in the trench so as to cover the polysilicon 143. After that, the mask 144 is also removed as shown in the lower part of Figure 44.

[0172] In step 116, as shown in the upper part of Figure 45, polysilicon 145 is formed to fill the portion where the silicon oxide film 130 was removed in step 115 and to laminate on the surface of the silicon oxide film 130.

[0173] In step 117, for example, chemical mechanical polishing is used to remove the polysilicon 145 laminated on the silicon oxide film 130 until the surface of the silicon oxide film 130 is exposed. This flattens the surface as shown in the middle section of Figure 45.

[0174] In step 118, as shown in the lower part of Figure 45, a silicon nitride film 131 is formed on the surface of the silicon oxide film 130 and the polysilicon 145, and then the silicon oxide film 130 is formed.

[0175] In step 119, as shown in the upper part of Figure 46, an electrode metal 126 is formed so as to penetrate the silicon oxide film 130 and the silicon nitride film 131 and connect to the N+ diffusion layer 122.

[0176] In step 120, the semiconductor substrate 121 is inverted as shown in the middle section of Figure 46.

[0177] In step 121, as shown in the lower part of Figure 46, the semiconductor substrate 121 is thinned until the polysilicon 143 is exposed.

[0178] In step 122, the polysilicon 143 in the trench is removed, as shown in the upper part of Figure 47.

[0179] In step 123, the thin oxide film (not shown) formed in step 106 described above is washed out from the surface of the P diffusion layer 125 to form an SCF film (not shown). Then, as shown in the middle of Figure 47, a stationary charge film 129 is formed on the side surface inside the trench and on the back surface of the semiconductor substrate 121.

[0180] In step 124, as shown in the lower part of Figure 47, a silicon oxide film 130 is formed on the sides and bottom of the trench, as well as on the fixed charge film 129.

[0181] In step 125, the bottom surface of the trench is etched back until the silicon nitride film 131 is exposed, thereby removing the silicon oxide film 130 and polysilicon 145 from the bottom surface of the trench. This separates the polysilicon 145 from the adjacent SPAD pixels 111, and a high-concentration polysilicon layer 127 is formed, as shown in the upper part of Figure 48.

[0182] In step 126, as shown in the middle section of Figure 48, a light-shielding metal 128 is formed by embedding metal inside the trench.

[0183] In step 127, the surface is planarized by forming a silicon oxide film 130, and an on-chip lens 132 is formed on that surface, thereby manufacturing a SPAD pixel 111 as shown in the lower part of Figure 48.

[0184] By using the manufacturing method described above, a trench with a stepped portion can be formed on the semiconductor substrate 121 by creating a deep trench with a narrow trench width in relation to a shallow trench with a wide trench width, and a P+ diffusion layer 124 can be formed in the stepped portion. Then, a high-concentration polysilicon layer 127 can be formed from the surface of the semiconductor substrate 121 to the depth of the shallow trench so as to connect to the semiconductor substrate 121 at the stepped portion, and a SPAD pixel 111 with a connection structure in which the side surface of the high-concentration polysilicon layer 127 is connected to the light-shielding metal 128 can be manufactured.

[0185] Figures 49 to 51 are cross-sectional views showing an example configuration of a first variation of the SPAD pixel 111. In the SPAD pixel 111A shown in Figures 49 to 51, components common to the SPAD pixel 111 shown in Figures 38 and 39 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0186] Figure 49 is a side cross-sectional view of the SPAD pixel 111A along the dashed line C-C shown in Figure 51, and Figure 50 is a diagonal side cross-sectional view of the SPAD pixel 111A along the dashed line D-D shown in Figure 51. Figure 51 is a plan cross-sectional view of the SPAD pixel 111A along the dashed line B-B shown in Figures 49 and 50.

[0187] As shown in Figures 49 to 51, the SPAD pixel 111A is formed such that its cross-sectional shape in plan view is rectangular, and it has the same configuration as the SPAD pixel 111 in Figures 38 and 39, in that it is provided with a semiconductor substrate 121, an N+ diffusion layer 122, an N diffusion layer 123, a P+ diffusion layer 124, a P diffusion layer 125, an electrode metal 126, a light-shielding metal 128, a fixed charge film 129, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132.

[0188] Furthermore, the SPAD pixel 111A differs from the SPAD pixel 111 in Figures 38 and 39 in that the high-density polysilicon layer 127A is provided near the four corners of the square SPAD pixel 111A when viewed from above. Specifically, the SPAD pixel 111A has a connection structure in which the P+ diffusion layer 124 and the high-density polysilicon layer 127A are connected at stepped portions formed inside the trenches of the semiconductor substrate 121 near the four corners when viewed from above.

[0189] The SPAD pixel 111A configured in this way can reduce the electric field near the surface of the semiconductor substrate 121 in the 0-degree and 90-degree directions (horizontal and vertical directions in Figure 51) when the SPAD pixel 111A is viewed from above. As a result, the SPAD pixel 111A can improve the DCR on the surface of the semiconductor substrate 121.

[0190] Figures 52 to 54 are cross-sectional views showing a configuration example of a second variation of the SPAD pixel 111. In the SPAD pixel 111B shown in Figures 52 to 54, components common to the SPAD pixel 111 shown in Figures 38 and 39 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0191] Figure 52 is a lateral cross-sectional view of the SPAD pixel 111B along the dashed line C-C shown in Figure 54, and Figure 53 is a lateral cross-sectional view of the SPAD pixel 111B in an oblique direction along the dashed line D-D shown in Figure 54. Figure 54 is a planar cross-sectional view of the SPAD pixel 111B along the dashed line B-B shown in Figures 52 and 53.

[0192] As shown in Figures 52 to 54, the SPAD pixel 111B has a configuration common to the SPAD pixel 111 in Figures 38 and 39, in that it is provided with an N+ diffusion layer 122, an N diffusion layer 123, an electrode metal 126, a light-shielding metal 128, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132.

[0193] Furthermore, the SPAD pixel 111B differs from the SPAD pixel 111 in Figures 38 and 39 in that the high-density polysilicon layer 127B is provided near the four corners of the square SPAD pixel 111B when viewed from above, forming approximately right triangles, with each right angle coinciding with the corners of the square SPAD pixel 111B. In other words, the SPAD pixel 111B has a connection structure in which the P+ diffusion layer 124B and the high-density polysilicon layer 127B are connected at stepped portions formed inside the trenches of the semiconductor substrate 121B near the four corners when viewed from above.

[0194] Furthermore, by providing the high-concentration polysilicon layer 127B in this manner, the SPAD pixel 111B is formed such that the cross-sectional shape of the semiconductor substrate 121B, surrounded by the high-concentration polysilicon layer 127B and the light-shielding metal 128, is octagonal when viewed from above. In addition, in the SPAD pixel 111B, the P+ diffusion layer 124B, the P diffusion layer 125B, and the fixed charge film 129B are formed to conform to the shape of the semiconductor substrate 121B.

[0195] The SPAD pixel 111B configured in this way can reduce the electric field near the surface of the semiconductor substrate 121B in the direction of 0 degrees and 90 degrees (horizontal and vertical directions in Figure 54) when the SPAD pixel 111B is viewed from above. As a result, the SPAD pixel 111B can improve the DCR on the surface of the semiconductor substrate 121B.

[0196] Furthermore, the SPAD pixel 111B can increase the contact area between the high-density polysilicon layer 127B and the light-shielding metal 128 compared to the SPAD pixel 111A shown in Figures 49 to 51 above, thereby reducing contact resistance.

[0197] Figures 55 to 57 are cross-sectional views showing an example configuration of a third variation of the SPAD pixel 111. In the SPAD pixel 111C shown in Figures 55 to 57, components common to the SPAD pixel 111 shown in Figures 38 and 39 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0198] Figure 55 is a lateral cross-sectional view of the SPAD pixel 111C along the dashed line C-C shown in Figure 57, and Figure 56 is a lateral cross-sectional view of the SPAD pixel 111C in an oblique direction along the dashed line D-D shown in Figure 57. Figure 57 is a planar cross-sectional view of the SPAD pixel 111C along the dashed line B-B shown in Figures 55 and 56.

[0199] As shown in Figures 55 to 57, the SPAD pixel 111C has a configuration common to the SPAD pixel 111 in Figures 38 and 39, in that it is provided with an N+ diffusion layer 122, an N diffusion layer 123, an electrode metal 126, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132.

[0200] Furthermore, as shown in Figure 57, the SPAD pixel 111C is formed with an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 121C, P+ diffusion layer 124C, P diffusion layer 125C, high-concentration polysilicon layer 127C, light-shielding metal 128C, and fixed charge film 129C are provided, which is a configuration that differs from the SPAD pixel 111 in Figures 38 and 39.

[0201] For example, the SPAD pixel 111C is configured such that the P+ diffusion layer 124C and the high-density polysilicon layer 127C are provided on a protruding portion where, in a plan view, one side of an octagon protrudes outward by a predetermined width. The SPAD pixel 111C is configured with a connection structure in which the P+ diffusion layer 124C and the high-density polysilicon layer 127C are connected at the protruding portion. Furthermore, the SPAD pixel 111C is configured with a connection structure in which the three outer sides of the high-density polysilicon layer 127C provided on the protruding portion (three sides other than the inner side that faces the center of the semiconductor substrate 121C from the protruding portion) are connected to the light-shielding metal 128C.

[0202] The SPAD pixel 111C configured in this way can reduce the electric field near the surface of the semiconductor substrate 121C in the 0-degree and 90-degree directions (horizontal and vertical directions in Figure 57) when the SPAD pixel 111C is viewed from above. As a result, the SPAD pixel 111C can improve the DCR on the surface of the semiconductor substrate 121C.

[0203] Furthermore, the SPAD pixel 111C can increase the contact area between the high-density polysilicon layer 127C and the light-shielding metal 128C compared to the SPAD pixel 111C shown in Figures 55 to 57, thereby reducing contact resistance.

[0204] Figure 58 is a cross-sectional view showing an example configuration of a fourth variation of the SPAD pixel 111. In the SPAD pixel 111D shown in Figure 58, components common to the SPAD pixel 111 shown in Figures 38 and 39 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0205] Figure 58, similar to Figure 38 above, is a lateral cross-sectional view of the SPAD pixel 111D along the dashed line C-C shown in Figure 39.

[0206] The SPAD pixel 111D is formed such that its cross-sectional shape in plan view is rectangular, and as shown in Figure 58, it has the same configuration as the SPAD pixel 111 in Figures 38 and 39, in that it is provided with a semiconductor substrate 121, an N+ diffusion layer 122, an N diffusion layer 123, a P+ diffusion layer 124, a P diffusion layer 125, an electrode metal 126, a light-shielding metal 128, a fixed charge film 129, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132.

[0207] Furthermore, the SPAD pixel 111D differs from the SPAD pixel 111 in Figures 38 and 39 in that the side surface of the high-density polysilicon layer 127D facing the center is formed as a tapered surface that moves from the center to the outer edge as it moves from the back surface to the front surface of the semiconductor substrate 121.

[0208] For example, in the 115th step described above (see the lower part of Figure 44), when shallow etching the silicon oxide film 130 at the location corresponding to the opening of the mask 144, dry etching can be performed such that the etching width widens as the etching depth increases, thereby forming a reverse taper on the side surface. Then, by depositing polysilicon 145 on the etched portion (116th step), a high-concentration polysilicon layer 127D formed on a tapered surface as shown in Figure 58 can be provided.

[0209] In the SPAD pixel 111D configured in this way, the high-concentration polysilicon layer 127D, which is the anode potential, can be structured so that it is separated from the N+ diffusion layer 122, which is the cathode potential, on the surface of the semiconductor substrate 121. As a result, the SPAD pixel 111D can mitigate the electric field on the surface of the semiconductor substrate 121, thereby improving the DCR on the surface of the semiconductor substrate 121. Furthermore, the SPAD pixel 111D can reduce capacitance by increasing the distance between the anode and the cathode.

[0210] Figure 59 is a cross-sectional view showing an example of a fifth variation configuration of the SPAD pixel 111. In the SPAD pixel 111E shown in Figure 59, components common to the SPAD pixel 111 shown in Figures 38 and 39 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0211] Figure 59, similar to Figure 38 above, is a lateral cross-sectional view of the SPAD pixel 111E along the dashed line C-C shown in Figure 39.

[0212] The SPAD pixel 111E is formed such that its cross-sectional shape in plan view is rectangular, and as shown in Figure 59, it has the same configuration as the SPAD pixel 111 in Figures 38 and 39, in that it is provided with a semiconductor substrate 121, an N+ diffusion layer 122, an N diffusion layer 123, a P+ diffusion layer 124, a P diffusion layer 125, an electrode metal 126, a fixed charge film 129, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132.

[0213] Furthermore, the SPAD pixel 111E differs from the SPAD pixel 111 in Figures 38 and 39 in that the connection surface between the high-density polysilicon layer 127E and the light-shielding metal 128E is formed as a tapered surface that moves from the center to the outer edge as it moves from the back surface to the front surface of the semiconductor substrate 121.

[0214] For example, in the 125th step described above (see the upper part of Figure 48), when etching back the bottom surface of the trench until the silicon nitride film 131 is exposed, the etching width can be narrowed as the etching depth increases, thereby forming a tapered side surface. Then, by embedding metal in the etched portion (126th step), a high-concentration polysilicon layer 127E and a light-shielding metal 128E formed on a tapered surface as shown in Figure 59 can be provided.

[0215] The SPAD pixel 111E configured in this way can increase the contact area by making the connection surface between the high-density polysilicon layer 127E and the light-shielding metal 128E a tapered surface, thereby reducing contact resistance.

[0216] Figure 60 is a cross-sectional view showing an example configuration of a sixth variation of the SPAD pixel 111. In the SPAD pixel 111F shown in Figure 60, components common to the SPAD pixel 111 shown in Figures 38 and 39 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0217] Figure 60, similar to Figure 38 above, is a lateral cross-sectional view of the SPAD pixel 111F along the dashed line C-C shown in Figure 39.

[0218] The SPAD pixel 111F is formed such that its cross-sectional shape when viewed from above is rectangular, and as shown in Figure 60, it has the same configuration as the SPAD pixel 111 in Figures 38 and 39, in that it is provided with a semiconductor substrate 121, an N+ diffusion layer 122, an N diffusion layer 123, a P+ diffusion layer 124, a P diffusion layer 125, an electrode metal 126, a light-shielding metal 128, a fixed charge film 129, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132.

[0219] Furthermore, the SPAD pixel 111F differs from the SPAD pixel 111 in Figures 38 and 39 in that the film thickness (thickness in the depth direction) of the high-density polysilicon layer 127F is formed to be thin. Specifically, in the SPAD pixel 111F, the film thickness of the high-density polysilicon layer 127F is formed to be thinner than the depth of the shallow trench (see the middle section of Figure 40), and the high-density polysilicon layer 127F is formed so that its surface is located deeper than the surface of the semiconductor substrate 121 (i.e., recessed into the trench).

[0220] The SPAD pixel 111F configured in this way can mitigate the electric field on the surface of the semiconductor substrate 121, thereby improving the DCR on the surface of the semiconductor substrate 121. Furthermore, the SPAD pixel 111F can reduce capacitance by increasing the distance between the anode and the cathode. For example, the film thickness of the high-concentration polysilicon layer 127F can be optimized based on the contact area between the high-concentration polysilicon layer 127F and the light-shielding metal 128, the DCR on the surface of the semiconductor substrate 121, and the capacitance between the anode and the cathode.

[0221] Figures 61 and 62 are cross-sectional views showing an example configuration of a seventh variation of the SPAD pixel 111. In the SPAD pixel 111G shown in Figures 61 and 62, components common to the SPAD pixel 111 shown in Figures 38 and 39, and the SPAD pixel 111B shown in Figures 52 to 54, are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0222] Figure 61 is a lateral cross-sectional view of the SPAD pixel 111G along the dashed line C-C shown in Figure 54, similar to Figure 52 described above, and Figure 62 is a lateral cross-sectional view of the SPAD pixel 111G in an oblique direction along the dashed line D-D shown in Figure 54, similar to Figure 53 described above.

[0223] The SPAD pixel 111G is formed so that its cross-sectional shape in plan view is rectangular, and as shown in Figures 61 and 62, it has the same configuration as the SPAD pixel 111 in Figures 38 and 39, in that it is provided with an N+ diffusion layer 122, an N diffusion layer 123, an electrode metal 126, a light-shielding metal 128, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132. Furthermore, the SPAD pixel 111G has the same configuration as the SPAD pixel 111B shown in Figures 52 to 54, in that the high-density polysilicon layer 127G is provided near the four corners of the rectangular SPAD pixel 111G in plan view, forming approximately right triangles, with each right angle coinciding with the corners of the rectangular SPAD pixel 111G. Furthermore, in the SPAD pixel 111G, the P+ diffusion layer 124G, the P diffusion layer 125G, and the fixed charge film 129G are formed along the shape of the semiconductor substrate 121G, which is octagonal when viewed from above, similar to the SPAD pixel 111B shown in Figures 52 to 54.

[0224] Furthermore, the SPAD pixel 111G has a different configuration from the SPAD pixel 111 shown in Figures 38 and 39, and the SPAD pixel 111B shown in Figures 52 to 54, in that the light-shielding metal 128G is provided to protrude and extend beyond the surface side of the semiconductor substrate 121G.

[0225] The SPAD pixel 111G configured in this way can suppress the occurrence of crosstalk, where self-illumination generated as the charge is multiplied in the multiplication region of the SPAD pixel 111G is incident on adjacent SPAD pixels 111G from the surface side of the semiconductor substrate 121G. That is, the SPAD pixel 111G can, for example, block self-illumination directed in the direction of the white arrows shown in Figures 61 and 62 by the light-shielding metal 128G that extends beyond the surface side of the semiconductor substrate 121G.

[0226] Figures 63 and 64 are cross-sectional views showing an example configuration of an eighth variation of the SPAD pixel 111. In the SPAD pixel 111H shown in Figures 63 and 64, components common to the SPAD pixel 111 shown in Figures 38 and 39, and the SPAD pixel 111B shown in Figures 52 to 54, are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0227] Figure 63, similar to Figure 52 above, is a lateral cross-sectional view of the SPAD pixel 111H along the dashed line C-C shown in Figure 54, and Figure 64, similar to Figure 53 above, is a lateral cross-sectional view of the SPAD pixel 111H in an oblique direction along the dashed line D-D shown in Figure 54.

[0228] The SPAD pixel 111H is formed so that its cross-sectional shape when viewed from above is a rectangle, and as shown in Figures 63 and 64, it has the same configuration as the SPAD pixel 111 in Figures 38 and 39, in that it is provided with an N+ diffusion layer 122, an N diffusion layer 123, an electrode metal 126, a light-shielding metal 128, a silicon oxide film 130, a silicon nitride film 131, and an on-chip lens 132. Furthermore, the SPAD pixel 111H has the same configuration as the SPAD pixel 111B shown in Figures 52 to 54, in that the high-density polysilicon layer 127H is provided near the four corners of the rectangle SPAD pixel 111H when viewed from above, forming approximately right triangles, with each right angle coinciding with the corners of the rectangle SPAD pixel 111H. Furthermore, in the SPAD pixel 111H, the P+ diffusion layer 124H, the P diffusion layer 125H, and the fixed charge film 129H are formed along the shape of the semiconductor substrate 121H, which is octagonal when viewed from above, similar to the SPAD pixel 111B shown in Figures 52 to 54.

[0229] Furthermore, the SPAD pixel 111H differs from the SPAD pixel 111 shown in Figures 38 and 39, and the SPAD pixel 111B shown in Figures 52 to 54, in that the light-shielding metal 128H is provided so as to protrude beyond the surface side of the semiconductor substrate 121H, and the high-concentration polysilicon layer 127H is provided to the same depth as the light-shielding metal 128H.

[0230] The SPAD pixel 111H configured in this way can suppress the occurrence of crosstalk, where self-illumination generated as the charge is multiplied in the multiplication region of the SPAD pixel 111H is incident on adjacent SPAD pixels 111H from the surface side of the semiconductor substrate 121H. That is, the SPAD pixel 111H can block self-illumination directed in the direction of the white arrows shown in Figures 63 and 64 by the light-shielding metal 128H that extends beyond the surface side of the semiconductor substrate 121H. Furthermore, by extending the high-density polysilicon layer 127H beyond the surface side of the semiconductor substrate 121H together with the light-shielding metal 128H, the high-density polysilicon layer 127H is connected to the light-shielding metal 128H and the semiconductor substrate 121H via a connection surface along the depth direction in the extended portion. This increases the connection area between the high-density polysilicon layer 127H and the light-shielding metal 128H, thereby reducing contact resistance.

[0231] <Example of a configuration with stacked pixel transistor layers> The SPAD pixel 11 of the first configuration example, which includes the variations described above, and the SPAD pixel 111 of the second configuration example, which includes the variations described above, can be fitted with a stacked structure in which pixel transistor layers are stacked.

[0232] Figure 65 is a cross-sectional view showing an example of the configuration of a SPAD pixel 111J in which pixel transistor layers 211 are stacked. In the SPAD pixel 111J shown in Figure 65, components common to the SPAD pixel 111 shown in Figures 38 and 39 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0233] The dashed line shown in Figure 65 represents the junction surface of a laminated structure in which a sensor layer 210, on which the photoelectric conversion unit of the SPAD pixel 111J is provided, and a pixel transistor layer 211, on which pixel transistors 221 and 222 for driving the SPAD pixel 111J are provided. For example, in a manufacturing process in which processing is performed from the surface side of the sensor layer 210, no metal is formed, so it is possible to form the pixel transistor layer 211, which is greatly affected by heat.

[0234] The SPAD pixel 111J configured in this way can achieve improvements in DCR and a reduction in contact resistance, similar to the SPAD pixel 111 shown in Figures 38 and 39.

[0235] <Third Configuration Example of SPAD Pixel> Referring to Figures 66 to 92, a configuration example of a third embodiment of a SPAD pixel provided in a photodetector to which this technology is applied will be described.

[0236] Figure 66 is a side cross-sectional view showing an example of the configuration of a SPAD pixel in the third embodiment.

[0237] As shown in Figure 66, the SPAD pixel 311 is constructed by providing an N+ diffusion layer 322 as the cathode contact, an N diffusion layer 323 as the cathode, a P+ diffusion layer 324 as the anode contact, and a P diffusion layer 325 as the anode on a semiconductor substrate 321. The SPAD pixel 311 converts light incident from the back surface of the semiconductor substrate 321 (the surface facing upward in Figure 66), which is the light incident surface, into electricity using a photoelectric conversion unit formed by the PN junction of the N diffusion layer 323 and the P diffusion layer 325. The charge generated by this photoelectric conversion is then multiplied by a multiplication region and output. The SPAD pixel 311 is formed to have a rectangular cross-sectional shape when viewed from above, similar to the SPAD pixel 11 (see Figure 2) described above.

[0238] The N+ diffusion layer 322 is located in the center of the surface of the semiconductor substrate 321 (the side facing downwards in Figure 66) and is directly connected to the electrode metal 326 that supplies the cathode potential to the multiplication region.

[0239] The N diffusion layer 323 is provided in the central part near the surface of the semiconductor substrate 321 so as to be connected to the N+ diffusion layer 322.

[0240] The P+ diffusion layer 324 is located in a region near the surface of the semiconductor substrate 321 (a certain range from the surface of the semiconductor substrate 321 to a predetermined depth), and is provided at at least four corners of the outer periphery of the SPAD pixel 311. It is connected to a light-shielding metal 328 that supplies an anode potential to the multiplication region via a high-concentration polysilicon layer 327.

[0241] The P diffusion layer 325 is provided so as to be connected to the P+ diffusion layer 324 at the four corners of the SPAD pixel 311, and is also provided so as to cover the side surface of the semiconductor substrate 321 along the outer periphery of the semiconductor substrate 321, from the P+ diffusion layer 324 to the back surface of the semiconductor substrate 321. Furthermore, the P diffusion layer 325 is provided so as to traverse a predetermined region on the surface side from the center in the depth direction of the semiconductor substrate 321. Note that the P diffusion layer 325 shown covering the back surface of the semiconductor substrate 321 represents the P layer that is automatically formed on the back surface of the semiconductor substrate 321 when the fixed charge film 329 is deposited on the back surface of the semiconductor substrate 321 in the 221st step (see the lower part of Figure 73) described later.

[0242] The SPAD pixels 311 are configured to be completely separated from other adjacent SPAD pixels 311 by trenches formed to penetrate the semiconductor substrate 521 from the back side (light-receiving surface side) to the front side (wiring layer side). Within these trenches, light-shielding metal 328 is provided to shield the sides of the SPAD pixels 311 from light, surrounding the SPAD pixels 311. A power supply for supplying anode potential from the outside is connected to the light-shielding metal 328.

[0243] The SPAD pixel 311 is constructed by providing a high-concentration polysilicon layer 327, which is a conductor for electrically connecting the P+ diffusion layer 324 and the light-shielding metal 328, on the surface side of the semiconductor substrate 521. As shown in Figure 66, the high-concentration polysilicon layer 327 is formed to have an L-shaped cross-section, with the tip of the portion extending in the depth direction of the semiconductor substrate 521 connected to the P+ diffusion layer 324 on the surface of the semiconductor substrate 521, and the tip of the portion extending along the surface of the semiconductor substrate 21 connected to the side surface of the light-shielding metal 328 (the connection surface along the depth direction of the semiconductor substrate 321).

[0244] The SPAD pixel 311 is constructed by laminating a silicon nitride film 331 on the front side (lower side in Figure 66) of the semiconductor substrate 321. This film is used as a stopper when processing trenches from the back side of the semiconductor substrate 321 to prevent light reflection and to seal hydrogen. For example, the silicon nitride film 331 is directly laminated to the high-concentration polysilicon layer 327 and laminated to the semiconductor substrate 321 via a silicon oxide film 330. A wiring layer is laminated on the front side of the semiconductor substrate 321, and the light-shielding metal 328 is configured to have a protruding portion that penetrates the high-concentration polysilicon layer 327 and the silicon nitride film 331 and protrudes toward the wiring layer. That is, the tip of the protruding portion of the light-shielding metal 328 that protrudes toward the wiring layer side from the surface of the semiconductor substrate 321 is provided at least toward the wiring layer side from the surface of the silicon nitride film 331.

[0245] The SPAD pixel 311 is configured such that a fixed charge film 329 is provided to cover the side and back surfaces of the semiconductor substrate 321 via a P diffusion layer 325, in order to suppress the generation of dark current.

[0246] The SPAD pixel 311 is configured with a silicon oxide film 330 provided to insulate each part.

[0247] Each SPAD pixel 311 is constructed by stacking an on-chip lens 332 that focuses light on the light incident surface.

[0248] The SPAD pixel 311 configured in this way can suppress crosstalk, which occurs when self-illumination generated as the charge is multiplied in the multiplication region of the SPAD pixel 311 wraps around the wiring layer from the surface side of the semiconductor substrate 321 and is incident on other adjacent SPAD pixels 311. That is, the SPAD pixel 311 can block light from the multiplication region, for example, in the direction of the white arrow shown in Figure 66, by the protruding portion of the light-shielding metal 328 that protrudes from the wiring layer side of the semiconductor substrate 321.

[0249] Therefore, the SPAD pixels 311 can suppress the occurrence of adverse effects due to crosstalk, for example, it can suppress malfunctions caused by self-illumination generated in the multiplication region entering other SPAD pixels 311, and thus avoid performance degradation due to such malfunctions.

[0250] The manufacturing method for the SPAD pixel 311 will be described with reference to Figures 67 to 75.

[0251] In step 201, as shown in the upper part of Figure 67, a silicon nitride film 341 is formed on the semiconductor substrate 321, and a silicon oxide film 342 is formed on the silicon nitride film 341.

[0252] In step 202, as shown in the middle of Figure 67, dry etching is performed on the semiconductor substrate 321, silicon nitride film 341, and silicon oxide film 342 to create a deep trench (FTI: Full Trench Isolation) in the semiconductor substrate 321 that surrounds the area where the SPAD pixel 311 is provided.

[0253] In step 203, for example, by diffusing P-type impurities using a solid-phase diffusion method, a P-diffusion layer 325 is formed on the side walls and bottom surface of the deep trench prepared in step 202, as shown in the lower part of Figure 67.

[0254] In step 204, the silicon oxide film 342 is removed as shown in the upper part of Figure 68. Then, a thin oxide film (not shown) is formed on the surface of the P diffusion layer 325.

[0255] In step 205, a polysilicon 343 film is formed to fill the inside of the trench. At this time, after forming the polysilicon 343 film, the polysilicon 343 is etched back to a predetermined depth so that, as shown in the middle of Figure 68, the surface of the polysilicon 343 is lower than the surface of the semiconductor substrate 321 by a predetermined depth.

[0256] In step 206, for example, using high-density plasma (HDP), a silicon oxide film 330 is deposited so as to be layered inside the trench and on the silicon nitride film 341, as shown in the lower part of Figure 68. As a result, the silicon oxide film 330 is embedded in the areas where the polysilicon 343 was etched back in step 205.

[0257] In step 207, for example, chemical mechanical polishing (CMP) is used to remove the silicon oxide film 330 laminated on the silicon nitride film 341 until the surface of the silicon nitride film 341 is exposed. This flattens the surface as shown in the upper part of Figure 69.

[0258] In step 208, as shown in the middle section of Figure 69, the silicon nitride film 341 stacked on the semiconductor substrate 321 is removed.

[0259] In step 209, for example, by performing impurity implantation (II: Ion Implantation), an N+ diffusion layer 322, an N diffusion layer 323, a P+ diffusion layer 324, and a P diffusion layer 325 are formed on the semiconductor substrate 321, as shown in the lower part of Figure 69.

[0260] In step 210, for example, TEOS (Tetra Eth Oxy Silane) is deposited to form a silicon oxide film 330 on the surface of the semiconductor substrate 321, as shown in the upper part of Figure 70.

[0261] In step 211, a mask 344 is formed on the silicon oxide film 330, as shown in the middle section of Figure 70. For example, the mask 344 is formed to have openings in the region where the P+ diffusion layer 324 is provided.

[0262] In step 212, the silicon oxide film 330 corresponding to the opening of the mask 344 is removed by dry etching in a shallow manner, exposing the P+ diffusion layer 324. Then, as shown in the lower part of Figure 70, the mask 344 is also removed.

[0263] In step 213, as shown in the upper part of Figure 71, polysilicon 345 is formed to fill the portion where the silicon oxide film 330 was removed in step 312 and to laminate on the surface of the silicon oxide film 330.

[0264] In step 214, dry etching is performed to remove polysilicon 345 except for the areas where adjacent P+ diffusion layers 324 are connected across the trench, and the polysilicon 345 is processed to have a shape that connects adjacent P+ diffusion layers 324 across the trench, as shown in the middle of Figure 71.

[0265] In step 215, as shown in the lower part of Figure 71, a silicon nitride film 331 is formed on the surfaces of the silicon oxide film 330 and the polysilicon 345.

[0266] In step 216, as shown in the upper part of Figure 72, a silicon oxide film 330 is formed on the silicon nitride film 331, and the surface of the silicon oxide film 330 is planarized, for example, by using chemical mechanical polishing.

[0267] In step 217, as shown in the middle section of Figure 72, an electrode metal 326 is formed so as to penetrate the silicon oxide film 330 and the silicon nitride film 331 and connect to the N+ diffusion layer 322.

[0268] In step 218, the semiconductor substrate 321 is inverted as shown in the lower part of Figure 72.

[0269] In step 219, as shown in the upper part of Figure 73, the semiconductor substrate 321 is thinned until the polysilicon 343 is exposed.

[0270] In step 220, the polysilicon 343 in the trench is removed, as shown in the middle section of Figure 73.

[0271] In step 221, the thin oxide film (not shown) formed in step 204 described above is washed out from the surface of the P diffusion layer 325 to form an SCF film (not shown). Then, as shown in the lower part of Figure 73, a stationary charge film 329 is formed on the side and bottom surfaces of the trench, as well as on the back surface of the semiconductor substrate 321.

[0272] In step 222, as shown in the upper part of Figure 74, a silicon oxide film 330 is formed on the side and bottom surfaces of the trench, as well as on the fixed charge film 329.

[0273] In step 223, the bottom surface of the trench is etched back to penetrate the fixed charge film 329, polysilicon 345, and silicon nitride film 331, extending the trench to the silicon oxide film 330 on the wiring layer side, and forming a trench with a depth corresponding to the protrusion of the light-shielding metal 328. As a result, the polysilicon 345, which is shaped to connect adjacent P+ diffusion layers 324, is divided by the trench, and a high-concentration polysilicon layer 327 with an L-shaped cross-section is formed, as shown in the lower part of Figure 74.

[0274] In step 224, as shown in the upper part of Figure 75, a light-shielding metal 328 is formed by embedding metal inside the trench.

[0275] In step 225, the surface is planarized by forming a silicon oxide film 330, and an on-chip lens 332 is formed on that surface, thereby manufacturing a SPAD pixel 311 as shown in the lower part of Figure 75.

[0276] By the manufacturing method described above, it is possible to manufacture SPAD pixels 311 in which a light-shielding metal 328 is provided inside a trench formed in the semiconductor substrate 321 to separate it from other adjacent SPAD pixels 311, and which is formed to penetrate the high-concentration polysilicon layer 327 and the silicon nitride film 331 and protrude to the wiring layer side.

[0277] Figure 76 is a cross-sectional view showing an example configuration of the first variation of the SPAD pixel 311. In the SPAD pixel 311A ​​shown in Figure 76, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0278] As shown in Figure 76, the SPAD pixel 311A ​​is constructed by stacking a sensor layer 410 on which the photoelectric conversion section of the SPAD pixel 311A ​​is provided, and a pixel transistor layer 411 on which pixel transistors 421 and 422 for driving the SPAD pixel 311A ​​are provided. The dashed line shown in Figure 76 represents the junction surface of the stacked structure in which the sensor layer 410 and the pixel transistor layer 411 are stacked. For example, in a manufacturing process in which processing is performed from the surface side of the sensor layer 410, no metal is formed, so it is possible to form the pixel transistor layer 411, which is greatly affected by heat.

[0279] Thus, the SPAD pixel 311A, which has a stacked structure in which pixel transistor layers 411 are stacked, can suppress the occurrence of adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328, which is provided to protrude from the wiring layer side of the semiconductor substrate 321, similar to the SPAD pixel 311 in Figure 66.

[0280] Figures 77 and 78 are cross-sectional views showing a configuration example of a second variation of the SPAD pixel 311. In the SPAD pixel 311B shown in Figures 77 and 78, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0281] Figure 77 is a side cross-sectional view of the SPAD pixel 311B in an oblique direction along the dashed line D-D shown in Figure 78. Figure 78 is a plan cross-sectional view of the SPAD pixel 311B along the dashed line B-B shown in Figure 77.

[0282] As shown in Figures 77 and 78, the SPAD pixel 311B has the same configuration as the SPAD pixel 311 in Figure 66, in that it is provided with an N+ diffusion layer 322, an N diffusion layer 323, an electrode metal 326, and a silicon nitride film 331.

[0283] As shown in Figure 78, the SPAD pixel 311B is formed with an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width. In accordance with this external shape, the semiconductor substrate 321B, P+ diffusion layer 324B, P diffusion layer 325B, high-concentration polysilicon layer 327B, light-shielding metal 328B, fixed charge film 329B, silicon oxide film 330B, and on-chip lens 332B are provided, which is a different configuration from the SPAD pixel 311 in Figure 66. The light-shielding metal 328B is provided to penetrate the high-concentration polysilicon layer 327B and the silicon nitride film 331 and protrude towards the wiring layer side, similar to the light-shielding metal 328 of the SPAD pixel 311 in Figure 66.

[0284] For example, the SPAD pixel 311B is configured such that the P+ diffusion layer 324B and the high-density polysilicon layer 327B are provided on a protruding portion where, in a plan view, one side of an octagon protrudes outward by a predetermined width. The SPAD pixel 311B is configured with a connection structure in which the P+ diffusion layer 324B and the high-density polysilicon layer 327B are connected on the surface of the semiconductor substrate 321B at the protruding portion.

[0285] The SPAD pixel 311B configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328B which is provided to protrude from the wiring layer side of the semiconductor substrate 321B.

[0286] Figure 79 is a cross-sectional view showing an example configuration of a third variation of the SPAD pixel 311. In the SPAD pixel 311C shown in Figure 79, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0287] As shown in Figure 79, the SPAD pixel 311C has a configuration common to the SPAD pixel 311 in Figure 66, in that it is provided with a semiconductor substrate 321, an N+ diffusion layer 322, an N diffusion layer 323, a P+ diffusion layer 324, a P diffusion layer 325, an electrode metal 326, a light-shielding metal 328, a fixed charge film 329, a silicon oxide film 330, a silicon nitride film 331, and an on-chip lens 332.

[0288] Furthermore, the SPAD pixel 311C differs from the SPAD pixel 311 in Figure 66 in that the high-density polysilicon layer 327C is formed to be thicker (thickness in the depth direction), and the protruding portion of the light-shielding metal 328 is covered by the high-density polysilicon layer 327C. Specifically, the high-density polysilicon layer 327C provided in the SPAD pixel 311C is formed to be thicker than the high-density polysilicon layer 327 provided in the SPAD pixel 311 in Figure 66, and is also provided on the wiring layer side of the protruding portion of the light-shielding metal 328. As a result, the SPAD pixel 311C can have a configuration in which the contact area between the light-shielding metal 328 and the high-density polysilicon layer 327C is increased compared to the SPAD pixel 311 in Figure 66.

[0289] Furthermore, as shown in the figure, the light-shielding metal 328 is formed such that the tip of the protrusion protrudes toward the wiring layer side more than the silicon nitride film 331 (which is laminated to the semiconductor substrate 321 via the silicon oxide film 330) which is provided in locations other than where it is laminated to the high-concentration polysilicon layer 327C.

[0290] The SPAD pixel 311C configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328, which is provided to protrude from the semiconductor substrate 321 towards the wiring layer. Furthermore, by providing a high-concentration polysilicon layer 327C to cover the protruding portion of the light-shielding metal 328, the SPAD pixel 311C can increase the contact area between the light-shielding metal 328 and the high-concentration polysilicon layer 327C compared to the SPAD pixel 311 in Figure 66, thereby reducing contact resistance.

[0291] Figure 80 is a cross-sectional view showing an example configuration of a fourth variation of the SPAD pixel 311. In the SPAD pixel 311D shown in Figure 80, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0292] As shown in Figure 80, the SPAD pixel 311D has a configuration common to the SPAD pixel 311 in Figure 66, in that it is provided with a semiconductor substrate 321, an N+ diffusion layer 322, an N diffusion layer 323, a P+ diffusion layer 324, a P diffusion layer 325, an electrode metal 326, a light-shielding metal 328, a fixed charge film 329, a silicon oxide film 330, a silicon nitride film 331, and an on-chip lens 332.

[0293] Furthermore, the SPAD pixel 311D differs from the SPAD pixel 311 in Figure 66 in that, similar to the SPAD pixel 311C in Figure 79, the high-density polysilicon layer 327D is formed with a thicker film to cover the protruding portion of the light-shielding metal 328, and the line width (length in the planar direction) of the high-density polysilicon layer 327D is wider. In other words, the high-density polysilicon layer 327D provided in the SPAD pixel 311D is formed to have a larger cross-sectional area when viewed from above than the high-density polysilicon layer 327C provided in the SPAD pixel 311C in Figure 79.

[0294] The SPAD pixel 311D configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328, which is provided to protrude from the semiconductor substrate 321 towards the wiring layer. Furthermore, by providing a high-concentration polysilicon layer 327D so as to cover the protruding portion of the light-shielding metal 328 and to have a wide line width, the cross-sectional area of ​​the high-concentration polysilicon layer 327D can be increased, thereby reducing the wiring resistance when supplying the anode potential to the P+ diffusion layer 324.

[0295] Figure 81 is a cross-sectional view showing an example configuration of a fourth variation of the SPAD pixel 311. In the SPAD pixel 311E shown in Figure 81, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0296] As shown in Figure 81, the SPAD pixel 311E has a configuration common to the SPAD pixel 311 in Figure 66, in that it is provided with a semiconductor substrate 321, an N+ diffusion layer 322, an N diffusion layer 323, a P+ diffusion layer 324, a P diffusion layer 325, an electrode metal 326, a fixed charge film 329, a silicon oxide film 330, a silicon nitride film 331, and an on-chip lens 332.

[0297] Furthermore, the SPAD pixel 311E differs from the SPAD pixel 311 in Figure 66 in that the line width of the protruding portion of the light-shielding metal 328E, which protrudes from the surface of the semiconductor substrate 321 towards the wiring layer, is formed to be wider than the line width of the light-shielding metal 328E within the trench of the semiconductor substrate 321. For example, the line width of the protruding portion of the light-shielding metal 328E is formed to cover from one P+ diffusion layer 324 of an adjacent SPAD pixel 311E across the trench to the other P+ diffusion layer 324.

[0298] Furthermore, in the SPAD pixel 311E, a high-concentration polysilicon layer 327E is provided to connect the protruding portion of the light-shielding metal 328E with the P+ diffusion layer 324, and the high-concentration polysilicon layer 327E is also provided to cover the side and tip surfaces of the protruding portion of the light-shielding metal 328E.

[0299] The SPAD pixel 311E configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328E, which is provided to protrude from the semiconductor substrate 321 towards the wiring layer. Furthermore, by forming a wider line width for the protruding portion of the light-shielding metal 328E in the SPAD pixel 311E, the cross-sectional area of ​​the protruding portion of the light-shielding metal 328E can be increased, thereby reducing the wiring resistance when supplying the anode potential to the P+ diffusion layer 324.

[0300] A method for manufacturing the SPAD pixel 311E will be described with reference to Figure 82.

[0301] For example, the same manufacturing method as for the SPAD pixel 311 is used from step 201 to step 213 (see upper part of Figure 67 to upper part of Figure 71), and in step 214 (see middle part of Figure 71), polysilicon 345E is formed according to the thickness of the high-concentration polysilicon layer 327E. Then, the same manufacturing method as for the SPAD pixel 311 is used from step 215 to step 222 (see lower part of Figure 71 to lower part of Figure 74).

[0302] Then, in step 231, as shown in the upper part of Figure 82, the bottom surface of the trench is etched back to a depth corresponding to the tip of the protrusion of the light-shielding metal 328E.

[0303] In step 232, the polysilicon 345E is wet-etched to remove the polysilicon 345E according to the shape of the protrusions of the light-shielding metal 328E, as shown in the middle of Figure 82, thereby forming a high-concentration polysilicon layer 327E.

[0304] In step 233, as shown in the lower part of Figure 82, a light-shielding metal 328E is formed by embedding metal inside the trench. Then, similar to step 225 described above (see the lower part of Figure 75), the surface is planarized by depositing a silicon oxide film 330, and an on-chip lens 332 is formed on that surface to manufacture the SPAD pixel 311E.

[0305] The SPAD pixel 311E configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328E, which is provided to protrude from the semiconductor substrate 321 towards the wiring layer. Furthermore, by forming the protruding portion of the light-shielding metal 328E in a wider shape, the wiring resistance when supplying the anode potential to the P+ diffusion layer 324 can be reduced compared to the SPAD pixel 311 in Figure 66.

[0306] Figure 83 is a cross-sectional view showing an example configuration of a fifth variation of the SPAD pixel 311. In the SPAD pixel 311F shown in Figure 83, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0307] As shown in Figure 83, the SPAD pixel 311F has a configuration common to the SPAD pixel 311 in Figure 66, in that it is provided with a semiconductor substrate 321, an N+ diffusion layer 322, an N diffusion layer 323, a P+ diffusion layer 324, a P diffusion layer 325, an electrode metal 326, a fixed charge film 329, a silicon oxide film 330, a silicon nitride film 331, and an on-chip lens 332.

[0308] Furthermore, the SPAD pixel 311F differs from the SPAD pixel 311 in Figure 66 in that the line width of the protruding portion of the light-shielding metal 328F that protrudes from the surface of the semiconductor substrate 321 towards the wiring layer is wider than the line width of the light-shielding metal 328F within the trench of the semiconductor substrate 321, and the light-shielding metal 328F is formed to be directly connected to the P+ diffusion layer 324. In other words, the SPAD pixel 311F is configured in a connection structure in which the P+ diffusion layer 324 and the light-shielding metal 328F are directly connected, rather than a connection structure in which the P+ diffusion layer 324 and the light-shielding metal 328 are connected via a high-concentration polysilicon layer 327, as in other embodiments.

[0309] The SPAD pixel 311F configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328F, which is provided to protrude from the wiring layer side of the semiconductor substrate 321. Furthermore, the SPAD pixel 311F, with its connection structure in which the P+ diffusion layer 324 and the light-shielding metal 328F are directly connected, can reduce the wiring resistance when supplying anode potential to the P+ diffusion layer 324 compared to, for example, a connection structure via a high-concentration polysilicon layer 327.

[0310] Figure 84 is a cross-sectional view showing an example configuration of a sixth variation of the SPAD pixel 311. In the SPAD pixel 311G shown in Figure 84, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0311] As shown in Figure 84, the SPAD pixel 311G has a configuration common to the SPAD pixel 311 in Figure 66, in that it is provided with a semiconductor substrate 321, an N+ diffusion layer 322, an N diffusion layer 323, a P+ diffusion layer 324, a P diffusion layer 325, a light-shielding metal 328, a fixed charge film 329, a silicon oxide film 330, a silicon nitride film 331, and an on-chip lens 332.

[0312] Furthermore, the SPAD pixel 311G differs from the SPAD pixel 311 in Figure 66 in that the film thickness (thickness in the depth direction) of the high-concentration polysilicon layer 327G is formed to be thicker, and the protruding portion of the light-shielding metal 328 is covered by the high-concentration polysilicon layer 327G. Moreover, the SPAD pixel 311G has a connection structure in which the electrode metal 326G is connected to the N+ diffusion layer 322 via a polysilicon resistor 333, rather than a connection structure in which the electrode metal 326 is directly connected to the N+ diffusion layer 322 as in other embodiments.

[0313] Furthermore, as shown in the figure, the high-concentration polysilicon layer 327G and the polysilicon resistor 333 are formed to have approximately the same film thickness, and a silicon nitride film 334 is laminated on the surfaces of the high-concentration polysilicon layer 327G and the polysilicon resistor 333.

[0314] The SPAD pixel 311G configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328, which is provided to protrude from the semiconductor substrate 321 towards the wiring layer. Furthermore, by providing a high-concentration polysilicon layer 327G to cover the protruding portion of the light-shielding metal 328, the SPAD pixel 311G can increase the contact area between the light-shielding metal 328 and the high-concentration polysilicon layer 327G compared to the SPAD pixel 311 in Figure 66, thereby reducing contact resistance. In addition, by providing a polysilicon resistor 333 on the cathode side of the SPAD pixel 311G, the cathode voltage amplitude can be reduced, thereby reducing power consumption.

[0315] Furthermore, in the case of the SPAD pixels 311G, for example, at the outermost edge of a sensor substrate where multiple SPAD pixels 311G are arranged in an array, the light-shielding metal 328 can be connected to the VRLD power supply without going through the semiconductor substrate 321.

[0316] Referring to Figure 85, the connection structure of the VRLD power supply at the outermost edge of the sensor board will be described.

[0317] As shown in Figure 85A, in the configuration in which a high-concentration polysilicon layer 327G is provided, the light-shielding metal 328 can be connected to the electrode metal 336 connected to the VRLD power supply via the high-concentration polysilicon layer 327G at the outermost periphery of the sensor substrate.

[0318] In contrast, as shown in Figure 85B, in a configuration where the high-concentration polysilicon layer 327G is not provided, the light-shielding metal 328 is connected to the electrode metal 336 connected to the VRLD power supply via the high-concentration polysilicon layer 327, the P+ diffusion layer 337 provided in the semiconductor substrate 321, and the high-concentration polysilicon layer 338 at the outermost periphery of the sensor substrate.

[0319] Thus, in the configuration in which the high-concentration polysilicon layer 327G is provided, the light-shielding metal 328 can be connected to the VRLD power supply without going through the semiconductor substrate 321, as in the configuration in which the high-concentration polysilicon layer 327G is not provided, thus reducing resistance.

[0320] The manufacturing method for the SPAD pixel 311G will be described with reference to Figures 86 to 88.

[0321] For example, the same manufacturing method as for the SPAD pixel 311 is used for steps 201 to 216 described above (see upper part of Figure 67 to upper part of Figure 72).

[0322] Then, in step 241, as shown in the upper part of Figure 86, through holes (Via) that penetrate to the N+ diffusion layer 322 are processed in the silicon oxide film 330, and openings corresponding to the region where the high-concentration polysilicon layer 327G is provided are processed in the silicon oxide film 330.

[0323] In step 242, as shown in the lower part of Figure 86, polysilicon 345 is formed to fill the through holes and openings processed in step 241 and to laminate on the surface of the silicon oxide film 330.

[0324] In step 243, for example, chemical mechanical polishing is used to remove the polysilicon 345 until it reaches the thickness of the high-concentration polysilicon layer 327G and the polysilicon resistor 333, and the surface is flattened as shown in the upper part of Figure 87.

[0325] In step 244, a silicon nitride film 334 is formed on the surface of the polysilicon 345, as shown in the lower part of Figure 87.

[0326] In step 245, the polysilicon 345 and the silicon nitride film 334 are processed to form a high-concentration polysilicon layer 327G and a polysilicon resistor 333, as shown in the upper part of Figure 88.

[0327] In step 246, a silicon oxide film 330 is formed as shown in the lower part of Figure 88. Then, after forming an electrode metal 326G to connect to a polysilicon resistor 333, the SPAD pixel 311G is manufactured using the same manufacturing method as for the SPAD pixel 311, from step 218 to step 225 (see the lower part of Figure 72 to the lower part of Figure 75).

[0328] The SPAD pixel 311G configured in this way can be manufactured, for example, by employing a manufacturing method that increases the thickness of the high-concentration polysilicon layer 327G when forming the polysilicon resistor 333.

[0329] Figure 89 is a cross-sectional view showing an example configuration of the seventh variation of the SPAD pixel 311. In the SPAD pixel 311H shown in Figure 89, components common to the SPAD pixel 311 shown in Figure 66 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0330] As shown in Figure 89, the SPAD pixel 311H has a configuration common to the SPAD pixel 311 in Figure 66, in that it is provided with a semiconductor substrate 321, an N+ diffusion layer 322, an N diffusion layer 323, a P+ diffusion layer 324, a P diffusion layer 325, a light-shielding metal 328, a fixed charge film 329, a silicon oxide film 330, a silicon nitride film 331, and an on-chip lens 332.

[0331] Furthermore, the SPAD pixel 311H differs from the SPAD pixel 311 in Figure 66 in that the film thickness (thickness in the depth direction) of the high-concentration polysilicon layer 327H is formed to be thicker, and the protruding portion of the light-shielding metal 328 is covered by the high-concentration polysilicon layer 327H. In addition, the SPAD pixel 311H has a connection structure in which the electrode metal 326H is connected to the N+ diffusion layer 322 via the polysilicon resistor 333, similar to the SPAD pixel 311G in Figure 84 described above.

[0332] Furthermore, as shown in the figure, the high-concentration polysilicon layer 327H and the polysilicon resistor 333 are formed to have approximately the same thickness, and a silicon nitride film 334 is laminated on the surfaces of the high-concentration polysilicon layer 327H and the polysilicon resistor 333.

[0333] The SPAD pixel 311H configured in this way, like the SPAD pixel 311 in Figure 66, can suppress adverse effects due to crosstalk by the protruding portion of the light-shielding metal 328, which is provided to protrude from the semiconductor substrate 321 towards the wiring layer. Furthermore, by providing a high-concentration polysilicon layer 327H to cover the protruding portion of the light-shielding metal 328, the SPAD pixel 311H can increase the contact area between the light-shielding metal 328 and the high-concentration polysilicon layer 327H compared to the SPAD pixel 311 in Figure 66, thereby reducing contact resistance. In addition, by providing a polysilicon resistor 333 on the cathode side of the SPAD pixel 311H, the cathode voltage amplitude can be reduced, thereby reducing power consumption.

[0334] Furthermore, similar to the SPAD pixel 311G in Figure 84, the SPAD pixel 311H, as described above with reference to Figure 85, allows the light-shielding metal 328 to be connected to the VRLD power supply at the outermost periphery of the sensor substrate without going through the semiconductor substrate 321. This reduces resistance.

[0335] A method for manufacturing the SPAD pixel 311G will be described with reference to Figures 90 to 92.

[0336] For example, the same manufacturing method as for the SPAD pixel 311 is used for steps 201 to 210 described above (see upper part of Figure 67 to upper part of Figure 70).

[0337] Then, in step 251, as shown in the upper part of Figure 90, a silicon nitride film 331 is formed on the surface of the silicon oxide film 330 formed in step 210, and then another silicon oxide film 330 is formed so as to be laminated on the silicon nitride film 331.

[0338] In step 252, as shown in the middle of Figure 90, through holes (vias) that penetrate to the N+ diffusion layer 322 are processed in the silicon oxide film 330 and the silicon nitride film 331, and openings corresponding to the region where the high-concentration polysilicon layer 327G is provided are processed in the silicon oxide film 330 and the silicon nitride film 331.

[0339] In step 253, as shown in the lower part of Figure 90, polysilicon 345 is formed to fill the through holes and openings processed in step 252 and to laminate on the surface of the silicon oxide film 330.

[0340] In step 254, for example, chemical mechanical polishing is used to remove the polysilicon 345 until it reaches the thickness of the high-concentration polysilicon layer 327H and the polysilicon resistor 333, and the surface is flattened as shown in the upper part of Figure 91.

[0341] In step 255, a silicon nitride film 334 is formed on the surface of the polysilicon 345, as shown in the lower part of Figure 91.

[0342] In step 256, the polysilicon 345 and the silicon nitride film 334 are processed to form a high-concentration polysilicon layer 327H and a polysilicon resistor 333, as shown in the upper part of Figure 92.

[0343] In step 257, a silicon oxide film 330 is formed as shown in the lower part of Figure 92. Then, after forming an electrode metal 326H to connect to a polysilicon resistor 333, the SPAD pixel 311H is manufactured using the same manufacturing method as for the SPAD pixel 311, from step 218 to step 225 (see the lower part of Figure 72 to the lower part of Figure 75).

[0344] The SPAD pixel 311H configured in this way can be manufactured by employing a manufacturing method that, for example, forms the polysilicon resistor 333 and the high-concentration polysilicon layer 327G at the same time. In other words, this manufacturing method eliminates the need for a separate step to form only the high-concentration polysilicon layer 327G, thereby reducing costs.

[0345] <Fourth Configuration Example of SPAD Pixels> Referring to Figures 93 to 98, a configuration example of a fourth embodiment of SPAD pixels provided in a photodetector to which this technology is applied will be described.

[0346] Figure 93 is a side cross-sectional view showing an example of the configuration of a SPAD pixel according to the fourth embodiment.

[0347] As shown in Figure 93, the SPAD pixel 511 is constructed by providing an N+ diffusion layer 522 as the cathode contact, an N diffusion layer 523 as the cathode, a P+ diffusion layer 524 as the anode contact, and a P diffusion layer 525 as the anode on a semiconductor substrate 521. The SPAD pixel 511 converts light incident from the back surface of the semiconductor substrate 521 (the surface facing upward in Figure 93) into electricity using a photoelectric conversion unit formed by the PN junction of the N diffusion layer 523 and the P diffusion layer 525, and then multiplies the charge generated by this photoelectric conversion using a multiplication region for output. The SPAD pixel 511 is formed to have a rectangular cross-sectional shape when viewed from above, similar to the SPAD pixel 11 (see Figure 2) described above.

[0348] The N+ diffusion layer 522 is located in the center of the surface of the semiconductor substrate 521 (the side facing downwards in Figure 93) and is directly connected to the electrode metal 526 that supplies the cathode potential to the multiplication region.

[0349] The N diffusion layer 523 is provided in the central part near the surface of the semiconductor substrate 521 so as to connect to the N+ diffusion layer 522.

[0350] The P+ diffusion layer 524 is located in a region near the surface of the semiconductor substrate 521 (a certain range from the surface of the semiconductor substrate 521 to a predetermined depth), and is provided at least at the four corners of the outer periphery of the SPAD pixel 511. The electrode metal 538 that supplies the anode potential to the multiplication region is directly connected to the P+ diffusion layer 524 from the surface side of the semiconductor substrate 521.

[0351] The P diffusion layer 525 is provided so as to be connected to the P+ diffusion layer 524 at the four corners of the SPAD pixel 511, and is also provided so as to cover the side surface of the semiconductor substrate 521 along the outer periphery of the semiconductor substrate 521, from the P+ diffusion layer 324 to the back surface of the semiconductor substrate 521. Furthermore, the P diffusion layer 525 is provided so as to traverse a predetermined region on the surface side from the center in the depth direction of the semiconductor substrate 521. Note that the P diffusion layer 525 shown covering the back surface of the semiconductor substrate 521 represents the P layer that is automatically formed on the back surface of the semiconductor substrate 521 when the fixed charge film 529 is formed on the back surface of the semiconductor substrate 521 in step 307 (see upper part of Figure 96), which will be described later.

[0352] The SPAD pixels 511 are configured to be completely separated from other adjacent SPAD pixels 511 by trenches formed in the semiconductor substrate 521 that penetrate from the back side (light-receiving surface side) to the front side (wiring layer side). Within these trenches, light-shielding metal 528 is provided to shield the sides of the SPAD pixels 511 from light, surrounding the SPAD pixels 511.

[0353] The SPAD pixel 511 is constructed by laminating a silicon nitride film 531 on the front side (lower side in Figure 93) of the semiconductor substrate 521. This film is used as a stopper when processing trenches from the back side of the semiconductor substrate 521 to prevent light reflection and to seal hydrogen. For example, the silicon nitride film 531 is laminated to the semiconductor substrate 521 via a silicon oxide film 530. A wiring layer is laminated on the front side of the semiconductor substrate 521, and the light-shielding metal 528 is configured with a protrusion that penetrates the silicon nitride film 531 and protrudes toward the wiring layer. That is, the light-shielding metal 528 is formed such that the tip of the protrusion that protrudes toward the wiring layer side from the surface of the semiconductor substrate 521 is located at least toward the wiring layer side from the surface of the silicon nitride film 531.

[0354] The SPAD pixel 511 is configured such that a fixed charge film 529 is provided to cover the side and back surfaces of the semiconductor substrate 521 via a P diffusion layer 525, in order to suppress the generation of dark current.

[0355] The SPAD pixel 511 is configured with a silicon oxide film 530 provided to insulate each part.

[0356] Each SPAD pixel 511 is constructed by stacking an on-chip lens 532 that focuses light on the light incident surface.

[0357] The SPAD pixel 511 configured in this way can suppress crosstalk, which occurs when self-illumination generated as the charge is multiplied in the multiplication region of the SPAD pixel 511 wraps around the wiring layer from the surface side of the semiconductor substrate 521 and is incident on other adjacent SPAD pixels 511. Therefore, the SPAD pixel 511 can suppress the occurrence of adverse effects due to crosstalk, for example, it can suppress malfunctions caused by self-illumination generated in the multiplication region entering other SPAD pixels 511, and can avoid performance degradation due to such malfunctions.

[0358] Furthermore, unlike the other embodiments described above, the SPAD pixel 511 is configured such that the anode potential is supplied to the P+ diffusion layer 524 by an electrode metal 538 directly connected to the P+ diffusion layer 524, rather than by utilizing a light-shielding metal 528.

[0359] A method for manufacturing the SPAD pixel 511 will be described with reference to Figures 94 to 97.

[0360] In step 301, for example, by performing impurity implantation (II: Ion Implantation), an N+ diffusion layer 522, an N diffusion layer 523, a P+ diffusion layer 545, and a P diffusion layer 525 are formed on the semiconductor substrate 521, as shown in the upper part of Figure 94. The P+ diffusion layer 545 is formed in a shape that connects adjacent P+ diffusion layers 524 across trenches. Furthermore, for example, TEOS (Tetra Eth Oxy Silane) is deposited to form a silicon oxide film 530 on the surface of the semiconductor substrate 521, as shown in the upper part of Figure 94, and a silicon nitride film 531 is deposited on the surface of the silicon oxide film 530.

[0361] In step 302, as shown in the middle section of Figure 94, a silicon oxide film 530 is formed on the silicon nitride film 531.

[0362] In step 303, as shown in the lower part of Figure 94, an electrode metal 526 is formed so as to penetrate the silicon oxide film 530 and the silicon nitride film 531 and connect to the N+ diffusion layer 522, and an electrode metal 538 is formed so as to connect to the P+ diffusion layer 545.

[0363] In step 304, the semiconductor substrate 521 is inverted as shown in the upper part of Figure 95.

[0364] In step 305, as shown in the middle of Figure 95, the semiconductor substrate 521 is thinned until the P diffusion layer 525 is exposed.

[0365] In step 306, dry etching is performed to form trenches that penetrate the semiconductor substrate 521, as shown in the lower part of Figure 95. As a result, the P+ diffusion layer 545 is divided by the trenches, and the P+ diffusion layer 524 is formed.

[0366] In step 307, as shown in the upper part of Figure 96, a fixed charge film 529 is formed on the side and bottom surfaces of the trench, as well as on the back surface of the semiconductor substrate 521.

[0367] In step 308, as shown in the middle section of Figure 96, a silicon oxide film 530 is formed on the side and bottom surfaces of the trench, as well as on the fixed charge film 329.

[0368] In step 309, the bottom surface of the trench is etched back to penetrate the fixed charge film 329 and the silicon nitride film 331, extending the trench to the silicon oxide film 530 on the wiring layer side, and forming a trench with a depth corresponding to the protrusion of the light-shielding metal 528, as shown in the lower part of Figure 96. When the trench is extended in this way, a step is formed at the location that was the bottom surface of the trench formed in step 308.

[0369] In step 310, as shown in the upper part of Figure 97, a light-shielding metal 528 is formed by embedding metal inside the trench.

[0370] In step 311, the surface is planarized by forming a silicon oxide film 530, and an on-chip lens 532 is formed on that surface, thereby manufacturing a SPAD pixel 511 as shown in the lower part of Figure 97.

[0371] By the manufacturing method described above, it is possible to manufacture a SPAD pixel 511 in which a light-shielding metal 528 is provided inside a trench formed in the semiconductor substrate 521 to separate it from other adjacent SPAD pixels 511, and which is formed to penetrate the silicon nitride film 531 and protrude to the wiring layer side.

[0372] Figure 98 is a cross-sectional view showing an example configuration of the first variation of the SPAD pixel 511. In the SPAD pixel 511A shown in Figure 98, components common to the SPAD pixel 511 shown in Figure 93 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0373] As shown in Figure 98, the SPAD pixel 511A is constructed by stacking a sensor layer 610 on which the photoelectric conversion unit of the SPAD pixel 511A is provided, and a pixel transistor layer 611 on which a pixel transistor 621 for driving the SPAD pixel 511A is provided. In Figure 98, only one pixel transistor 621 is shown on the pixel transistor layer 611, but for example, it can be constructed with multiple pixel transistors, similar to the pixel transistor layer 411 in Figure 76 described above. The dashed line shown in Figure 98 represents the junction surface of the stacked structure in which the sensor layer 610 and the pixel transistor layer 611 are stacked. For example, in a manufacturing process where processing is performed from the surface side of the sensor layer 610, metal is not formed, so it is possible to form the pixel transistor layer 611, which is greatly affected by heat.

[0374] Thus, the SPAD pixel 511A, which has a stacked structure in which pixel transistor layers 611 are stacked, can suppress the occurrence of adverse effects due to crosstalk by the protruding portion of the light-shielding metal 528, which is provided to protrude from the wiring layer side of the semiconductor substrate 521, similar to the SPAD pixel 511 in Figure 93.

[0375] <Example of Electronic Device Configuration> The light detection device equipped with SPAD pixels 11, 111, 311, or 511 as described above can be applied to various electronic devices such as imaging systems like digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0376] Figure 99 is a block diagram showing an example configuration of an imaging device mounted on an electronic device.

[0377] As shown in Figure 99, the imaging device 701 is configured to include an optical system 702, an image sensor 703, a signal processing circuit 704, a monitor 705, and a memory 706, and is capable of capturing still images and moving images.

[0378] The optical system 702 is composed of one or more lenses and guides the image light (incident light) from the subject to the image sensor 703, forming an image on the light-receiving surface (sensor part) of the image sensor 703.

[0379] As the image sensor 703, a light detection device equipped with the aforementioned SPAD pixels 11, 111, 311, or 511 is used. Electrons are accumulated in the image sensor 703 for a certain period of time according to the image formed on the light-receiving surface via the optical system 702. Then, a signal corresponding to the electrons accumulated in the image sensor 703 is supplied to the signal processing circuit 704.

[0380] The signal processing circuit 704 performs various signal processing operations on the pixel signals output from the image sensor 703. The image (image data) obtained by the signal processing circuit 704 is supplied to the monitor 705 for display or supplied to the memory 706 for storage (recording).

[0381] In the imaging device 701 configured in this way, performance can be further improved, for example, by applying a light detection device equipped with SPAD pixels 11 or SPAD pixels 111.

[0382] <Example of Image Sensor Usage> Figure 100 shows an example of using the image sensor (light detection device) described above.

[0383] The image sensor described above can be used in various cases to sense light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0384] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0385] <Examples of configuration combinations> The technology can also take the following configurations: (1) A light detection device comprising: a semiconductor substrate on which a photoelectric conversion unit is provided that generates an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface; a cathode contact provided in the center of the front surface opposite to the back surface of the semiconductor substrate and directly connected to an electrode that supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit; and an anode contact provided on the semiconductor substrate in a certain range from the outer periphery of the front surface to a predetermined depth from the front surface and connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region, wherein the anode contact and the conductor are connected via a connection surface along at least the depth direction of the semiconductor substrate. (2) The light detection device according to (1) above, wherein the anode contact and the conductor are also connected via the front surface of the semiconductor substrate which is substantially perpendicular to the connection surface. (3) The light-shielding metal is formed to be wide to a predetermined depth, the light-shielding metal is connected to the anode contact and the semiconductor substrate via the connection surface in the depth direction, and the anode contact and the conductor are connected via the surface of the semiconductor substrate which is substantially perpendicular to the connection surface, as described in (1) or (2) above. (4) The light-shielding metal is formed to be rectangular in shape when viewed from above, and the anode contact and the conductor are provided near the four corners of the pixel, as described in any of (1) to (3) above. (5) The light-shielding metal is provided on the outer surface or inner surface of the anode contact, as described in (4) above. (6) The light-shielding metal is provided on one or more protrusions on which a part of the conductor protrudes into the interior of the anode contact, as described in (4) or (5) above.(7) The pixel is formed in an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width, and the anode contact and the conductor are provided on the protruding portion, the photodetector according to any one of (1) to (3) above. (8) The connection surface to which the anode contact and the conductor are connected is provided on the outer surface or inner surface of the anode contact, the photodetector according to (7) above. (9) The connection surface to which the anode contact and the conductor are connected is provided on one or more protrusions to which a part of the conductor protrudes into the interior of the anode contact, the photodetector according to (7) or (8) above. (10) A light detection device comprising: a semiconductor substrate on which a photoelectric conversion unit is provided that generates an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface; a cathode contact provided in the center of the front surface opposite to the back surface of the semiconductor substrate and directly connected to an electrode that supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit; and an anode contact provided in a stepped portion formed inside a trench provided in the semiconductor substrate so as to surround the outer periphery in order to separate it from other adjacent pixels, and at a position at a predetermined depth from the surface, and connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region, wherein the conductor and the light-shielding metal are connected via a connection surface along the depth direction of the semiconductor substrate. (11) The photodetector according to (10), wherein the stepped portion is provided by forming a deep trench with a narrow trench width at the bottom surface of a shallow trench with a wide trench width formed from the surface side of the semiconductor substrate, and is provided at a position deeper than the multiplication region from the surface of the semiconductor substrate. (12) The photodetector according to (11), wherein the conductor is made of high-concentration polysilicon embedded in the shallow trench, and is insulated from the semiconductor substrate by an insulating film provided between it and the semiconductor substrate, except at the place where it is connected to the anode contact at the bottom surface of the shallow trench.(13) The photodetector according to any one of (10) to (12), wherein the pixel is formed in a rectangular shape when viewed from above, and the conductor is provided near the four corners of the pixel. (14) The photodetector according to (13), wherein the conductor is formed in a substantially right-angled triangular shape when viewed from above at the four corners of the pixel, and the semiconductor substrate surrounded by the light-shielding metal and the conductor is provided to form an octagon. (15) The photodetector according to any one of (10) to (14), wherein the side surface of the conductor facing the central part is formed as a tapered surface from the central part toward the outer periphery as the semiconductor substrate moves from the back surface toward the front surface. (16) The photodetector according to any one of (10) to (15), wherein the connecting surface where the conductor and the light-shielding metal connect is formed as a tapered surface from the central part toward the outer periphery as the semiconductor substrate moves from the back surface toward the front surface. (17) The photodetector according to (11), wherein the thickness of the conductor is formed to be thinner than the depth of the shallow trench, and the surface of the conductor is located at a position deeper than the surface of the semiconductor substrate. (18) The photodetector according to any one of (10) to (17), wherein the light-shielding metal is provided extended to protrude beyond the surface of the semiconductor substrate. (19) The photodetector according to (18), wherein the conductor is provided extended to protrude beyond the surface of the semiconductor substrate, and the extended portion is connected to the light-shielding metal via a connection surface along the depth direction of the semiconductor substrate. (20) The photodetector according to any one of (1) to (19), wherein the photodetector has a laminated structure in which a sensor layer provided with the photoelectric conversion unit and a pixel transistor layer provided with pixel transistors for driving the pixels are laminated.(21) A light detection device comprising: a semiconductor substrate on which a photoelectric conversion unit is provided for generating an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface; a pixel having a cathode contact provided in the center of the front surface opposite to the back surface of the semiconductor substrate and which serves as a contact of the semiconductor substrate for supplying a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit; an anode contact provided on the outer periphery of the front surface of the semiconductor substrate and which serves as a contact of the semiconductor substrate for supplying an anode potential to the multiplication region; and a light-shielding metal provided in a trench surrounding the pixel and configured to protrude toward the wiring layer laminated toward the front surface of the semiconductor substrate. (22) The light detection device according to (21), wherein the light-shielding metal is connected to a power supply for supplying the anode potential, and further comprises a conductor connecting the light-shielding metal and the anode contact. (23) The light detection device according to (21) or (22), wherein the conductor is connected to the side surface of the light-shielding metal, and the light-shielding metal is formed to penetrate the conductor and protrude toward the wiring layer. (24) The photodetector according to any one of (21) to (23) above, wherein the pixel is formed in a rectangular shape when viewed from above, and the anode contacts are provided at the four corners of the pixel. (25) The photodetector according to any one of (21) to (24) above, wherein the photodetector has a laminated structure in which a sensor layer on which the photoelectric conversion unit is provided and a pixel transistor layer on which a pixel transistor for driving the pixel is provided are laminated. (26) The photodetector according to any one of (21) to (25) above, wherein the pixel is formed in a rectangular shape when viewed from above, with a protruding portion on which one side of the octagon protrudes outward by a predetermined width, and the anode contacts and the conductor are provided at the protruding portion. (27) The photodetector according to (22) above, wherein the conductor is provided with a film thickness such that the light-shielding metal covers the portion that protrudes toward the wiring layer. (28) The light-shielding metal is formed such that the line width of the portion protruding toward the wiring layer is wider than the line width of the portion within the trench.(29) The photodetector according to (21), wherein the light-shielding metal is formed such that the line width of the portion protruding toward the wiring layer is wider than the line width of the portion within the trench, and the portion protruding toward the wiring layer is directly connected to the anode contact. (30) The photodetector according to (27), wherein the cathode contact is connected to an electrode that supplies the cathode potential via a polysilicon resistor, and the conductor and the polysilicon resistor are formed with substantially the same film thickness. (31) The photodetector according to (21), wherein the electrode that supplies the anode potential is directly connected to the anode contact from the surface side of the semiconductor substrate.

[0386] It should be noted that this embodiment is not limited to the embodiment described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0387] 11 SPAD pixel, 21 semiconductor substrate, 22 N+ diffusion layer, 23 N diffusion layer, 24 P+ diffusion layer, 25 P diffusion layer, 26 electrode metal, 27 high-concentration polysilicon layer, 28 light-shielding metal, 29 fixed charge film, 30 silicon oxide film, 31 silicon nitride film, 32 on-chip lens

Claims

1. A light detection device comprising: a semiconductor substrate on which a photoelectric conversion unit is provided that generates an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface; a cathode contact provided in the center of the front surface opposite to the back surface of the semiconductor substrate and directly connected to an electrode that supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit; and an anode contact provided on the semiconductor substrate in a certain range from the outer periphery of the front surface to a predetermined depth from the front surface and connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region, wherein the anode contact and the conductor are connected via a connection surface at least along the depth direction of the semiconductor substrate.

2. The photodetector according to claim 1, wherein the anode contact and the conductor are connected via the surface of the semiconductor substrate which is substantially perpendicular to the connection surface.

3. The photodetector according to claim 1, wherein the surface side of the light-shielding metal is formed to a predetermined depth, the light-shielding metal is connected to the anode contact and the semiconductor substrate via the connection surface along the depth direction, and the anode contact and the conductor are connected via the surface of the semiconductor substrate substantially perpendicular to the connection surface.

4. The photodetector according to claim 1, wherein the pixel is formed in a rectangular shape when viewed from above, and the anode contact and the conductor are provided near the four corners of the pixel.

5. The photodetector according to claim 4, wherein the connection surface connecting the anode contact and the conductor is provided on the outer or inner surface of the anode contact.

6. The photodetector according to claim 4, wherein the connection surface connecting the anode contact and the conductor is provided on one or more protrusions, the portion of which is provided to protrude into the interior of the anode contact.

7. The photodetector according to claim 1, wherein the pixel is formed in an external shape in which, when viewed from above, one side of the octagon protrudes outward by a predetermined width, and the anode contact and the conductor are provided on the protruding portion.

8. The photodetector according to claim 7, wherein the connection surface connecting the anode contact and the conductor is provided on the outer or inner surface of the anode contact.

9. The photodetector according to claim 7, wherein the connection surface connecting the anode contact and the conductor is provided on one or more protrusions provided such that a portion of the conductor protrudes into the interior of the anode contact.

10. A light detection device comprising: a semiconductor substrate provided with a photoelectric conversion unit that generates an electric charge by photoelectric conversion of light incident from the back surface which is the light incident surface; a cathode contact provided in the center of the front surface opposite to the back surface of the semiconductor substrate and directly connected to an electrode that supplies a cathode potential to a multiplication region that multiplies the charge generated by the photoelectric conversion unit; and an anode contact provided in a stepped portion formed inside a trench provided in the semiconductor substrate so as to surround the outer periphery in order to separate it from other adjacent pixels, and at a position at a predetermined depth from the surface, and connected via a conductor to a light-shielding metal that supplies an anode potential to the multiplication region, wherein the conductor and the light-shielding metal are connected via a connection surface along the depth direction of the semiconductor substrate.

11. The photodetector according to claim 10, wherein the stepped portion is provided by forming a deep trench with a narrow trench width relative to the bottom surface of a shallow trench with a wide trench width formed from the surface side of the semiconductor substrate, and is provided at a position deeper than the multiplication region from the surface of the semiconductor substrate.

12. The photodetector according to claim 11, wherein the conductor is made of high-concentration polysilicon embedded in the shallow trench, and is insulated from the semiconductor substrate by an insulating film provided between it and the semiconductor substrate, except at the point where it is connected to the anode contact at the bottom surface of the shallow trench.

13. The light detection device according to claim 10, wherein the pixel is formed in a rectangular shape when viewed from above, and the conductor is provided near the four corners of the pixel.

14. The light detection device according to claim 13, wherein the conductor is formed in the shape of a substantially right triangle when viewed from above at the four corners of the pixel, and the semiconductor substrate surrounded by the light-shielding metal and the conductor is arranged to be octagonal.

15. The photodetector according to claim 10, wherein the side surface of the conductor facing the central portion is formed into a tapered surface that moves from the central portion toward the outer periphery as it moves from the back surface toward the front surface of the semiconductor substrate.

16. The light detection device according to claim 10, wherein the connection surface to which the conductor and the light-shielding metal are connected is formed as a tapered surface from the central part toward the outer periphery as the semiconductor substrate moves from the back surface toward the front surface.

17. The photodetector according to claim 11, wherein the thickness of the conductor is formed to be thinner than the depth of the shallow trench, and the surface of the conductor is located at a deeper position than the surface of the semiconductor substrate.

18. The light-shielding metal is provided extended to protrude beyond the surface of the semiconductor substrate, as described in claim 10.

19. The photodetector according to claim 18, wherein the conductive material is provided extending outward from the surface of the semiconductor substrate, and the extended portion is connected to the light-shielding metal via a connection surface along the depth direction of the semiconductor substrate.

20. The photodetector according to claim 11, wherein the photodetector has a stacked structure comprising a sensor layer on which the photoelectric conversion unit is provided and a pixel transistor layer on which pixel transistors for driving the pixels are provided.

Images