Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device comprising: a drift region provided on a semiconductor substrate having a front surface and a rear surface; a collector region provided on the rear surface of the semiconductor substrate in a transistor portion; a cathode region provided on the rear surface of the semiconductor substrate in a diode portion and having a doping concentration higher than that of the drift region; a first buffer region provided above the cathode region and having a doping concentration higher than that of the drift region; a second buffer region provided above the collector region and having a doping concentration higher than that of the drift region; and a plurality of trench parts arranged in an arrangement direction. A peak closest to the front surface side of the first buffer region in the diode portion is closer to the front surface side than a peak closest to the front surface side of the second buffer region in the transistor portion. The peak closest to the front surface side of the first buffer region in the diode portion is a peak of hydrogen atom concentration.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Patent Document 1 describes "a semiconductor device and a method for manufacturing a semiconductor device that can improve reliability and reduce costs in a semiconductor device having a semiconductor layer inside a drift layer that has the same conductivity type as the drift layer and a higher carrier concentration than the drift layer." [Prior Art Documents] [Patent Documents] [Patent Document 1] International Publication No. 2017 / 047285 [Patent Document 2] Japanese Unexamined Patent Publication No. 2022-882 General disclosure

[0003] In a first embodiment of the present invention, a semiconductor device comprising a transistor portion and a diode portion is provided, the semiconductor device comprising: a drift region of a first conductivity type provided on a semiconductor substrate having a front surface and a back surface; a collector region of a second conductivity type provided on the back surface of the semiconductor substrate in the transistor portion; a cathode region of a first conductivity type provided on the back surface of the semiconductor substrate in the diode portion, having a doping concentration higher than that of the drift region; a first buffer region provided above the cathode region, having a doping concentration higher than that of the drift region; a second buffer region provided above the collector region, having a doping concentration higher than that of the drift region; and a plurality of trench portions arranged in a predetermined arrangement direction on the front surface, wherein the peak of the first buffer region in the diode portion closest to the front surface is closer to the front surface than the peak of the second buffer region in the transistor portion closest to the front surface, and the peak of the first buffer region in the diode portion closest to the front surface is the peak of hydrogen atom concentration.

[0004] In the semiconductor device described above, the integral concentration is defined as the concentration obtained by integrating the doping concentration from the upper end of the drift region toward the back surface, and the critical position is defined as the position where the integral concentration in the transistor portion reaches the critical integral concentration of the semiconductor substrate. In this case, in the direction from the upper end of the drift region toward the back surface, the integral concentration in the diode portion may be higher than the integral concentration in the transistor portion at a first depth and equal to the integral concentration in the transistor portion at a second depth. The second depth may be the critical position or located on the front surface side of the critical position.

[0005] In any of the semiconductor devices described above, the second depth may be located on the front side of the critical position. The integrated concentration in the diode portion may have a region on the front side of the second depth where it is higher than the integrated concentration in the transistor portion, and a region between the second depth and the critical position where it is lower than the integrated concentration in the transistor portion.

[0006] In any of the semiconductor devices described above, the second depth may be located on the front side of the critical position. The integrated concentration in the diode portion may have a region on the front side of the second depth where it is higher than the integrated concentration in the transistor portion, and a region between the second depth and the critical position where it is equal to the integrated concentration in the transistor portion.

[0007] Any of the above semiconductor devices may include a connection region connecting the first buffer region and the second buffer region. The connection region may have a junction that continuously connects at least one peak of the first buffer region and one peak of the second buffer region.

[0008] In any of the above semiconductor devices, the connecting portion does not need to be provided in the transistor portion.

[0009] In any of the above semiconductor devices, the connecting portion may be provided within the thickness of the semiconductor substrate from the end of the diode portion in the arrangement direction.

[0010] In any of the above-described semiconductor devices, at least a portion of the connecting portion may be provided in the transistor portion.

[0011] In any of the above semiconductor devices, the transistor portion may have a boundary region provided adjacent to the diode portion. The end of the connecting portion on the second buffer region side may be provided in the boundary region.

[0012] In any of the semiconductor devices described above, the first buffer region may have a group of peaks having peaks corresponding to the second buffer region. The second buffer region may have a group of peaks having peaks corresponding to the first buffer region. At least one of the peaks included in the group of peaks in the first buffer region may be closer to the front surface side than the corresponding peak included in the group of peaks in the second buffer region.

[0013] In any of the above semiconductor devices, the dopants of the peaks included in the peak group of the first buffer region and the corresponding peaks included in the peak group of the second buffer region may be the same.

[0014] In any of the above-described semiconductor devices, the dopant may be hydrogen.

[0015] In any of the semiconductor devices described above, the number of peaks included in the peak group of the first buffer region may be equal to the number of peaks included in the peak group of the second buffer region.

[0016] In any of the semiconductor devices described above, the peaks included in the peak group of the first buffer region may be continuously connected to the corresponding peaks included in the peak group of the second buffer region.

[0017] In any of the above semiconductor devices, the distance in the depth direction of the semiconductor substrate between at least one peak included in the peak group of the first buffer region and the corresponding peak included in the peak group of the second buffer region may be 1 μm or more and half the thickness of the semiconductor substrate or less.

[0018] In any of the semiconductor devices described above, the distance in the depth direction of the semiconductor substrate between at least one peak included in the peak group of the first buffer region and the corresponding peak included in the peak group of the second buffer region may be 40 μm or less.

[0019] In any of the semiconductor devices described above, the doping concentration of the peak on the front surface side of the first buffer region is 5E+13 cm －３ or more and 7E+14 cm －３ or less.

[0020] In any of the semiconductor devices described above, in the depth direction of the semiconductor substrate, the peak on the back surface side of the first buffer region in the diode portion and the peak on the back surface side of the second buffer region in the transistor portion may be provided at the same depth.

[0021] In any of the semiconductor devices described above, the interval between the peak on the back surface side of the first buffer region and the second peak from the back surface may be larger than the intervals between the other peaks of the first buffer region.

[0022] In any of the semiconductor devices described above, the peak on the back surface side of the first buffer region in the diode portion may be closer to the front surface side than the peak on the back surface side of the second buffer region in the transistor portion.

[0023] In any of the semiconductor devices described above, the number of peaks in the first buffer region in the diode portion may be equal to the number of peaks in the second buffer region in the transistor portion.

[0024] In any of the semiconductor devices described above, the number of peaks in the first buffer region in the diode portion may be larger than the number of peaks in the second buffer region in the transistor portion.

[0025] In any of the semiconductor devices described above, in the depth direction of the semiconductor substrate, the distance from the back surface to the peak on the front surface side of the first buffer region in the diode portion may be 1.1 times or more and 3 times or less the distance from the back surface to the peak on the front surface side of the second buffer region in the transistor portion.

[0026] In any of the semiconductor devices described above, in the depth direction of the semiconductor substrate, the peak on the front surface side of the first buffer region may be located below the center of the semiconductor substrate.

[0027] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a transistor portion and a diode portion, the method including: providing the transistor portion and the diode portion on a semiconductor substrate of a first conductivity type having a front surface and a back surface; and implanting ions from the back surface side to provide a buffer region of the first conductivity type having a doping concentration higher than that of the semiconductor substrate. The step of providing the buffer region includes: providing a resist on the back surface in the transistor portion and implanting ions from the back surface side; and providing a peak of the hydrogen atom concentration in the diode portion as the peak on the front surface side of the buffer region.

[0028] In the method for manufacturing the semiconductor device described above, the angle formed by the side surface of the resist and the back surface may be 45 degrees or more and 90 degrees or less.

[0029] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

[0030] An example of a top view of the semiconductor device 100 is shown. This is an enlarged view of region A in Figure 1A. An example of a cross-section a-a' in Figure 1A is shown. An example of the relationship between the depth of the buffer region in the transistor section 70 and the back surface avalanche withstand capability of the transistor section 70 is shown. An example of the relationship between the depth of the buffer region in the diode section 80 and the oscillation start voltage of the diode section 80 is shown. An example of the trade-off relationship between the back surface avalanche withstand capability of the transistor section 70 and the oscillation start voltage of the diode section 80 is shown. An example of the doping concentration distribution from the upper end of the drift region 18 to the back surface 23 is shown. An example of the doping concentration distribution from the upper end of the drift region 18 to the back surface 23 is shown. An example of the doping concentration distribution from the upper end of the drift region 18 to the back surface 23 is shown. An example of the doping concentration distribution near the junction 242 on the b-b' line in Figure 1C is shown. A cross-section a-a' of a modified example of the semiconductor device 100 is shown. A cross-section a-a' of a modified example of the semiconductor device 100 is shown. A cross-section a-a' of a modified example of the semiconductor device 100 is shown. This flowchart shows an example of a manufacturing method for semiconductor device 100. It illustrates an example of the manufacturing process for semiconductor device 100.

[0031] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0032] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0033] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0034] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0035] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0036] In this specification, when we refer to "identical" or "equal," we may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0037] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0038] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N Ｄ , the acceptor concentration is N Ａ Therefore, the net doping concentration at any given position is N Ｄ -N Ａ In this specification, net doping concentration may sometimes be simply referred to as doping concentration.

[0039] The donor has the function of supplying electrons to the semiconductor. The acceptor has the function of receiving electrons from the semiconductor. The donor and acceptor are not limited to the impurity itself. For example, interstitial Si-H in which interstitial silicon (Si-i) in a silicon semiconductor is bonded to hydrogen, and CiOi-H in which interstitial carbon (Ci) is bonded to interstitial oxygen (Oi) and hydrogen function as donors that supply electrons. In this specification, CiOi-H or interstitial Si-H may be referred to as a hydrogen donor.

[0040] In this specification, in the semiconductor substrate, N-type bulk donors are distributed throughout. The bulk donor is a donor by a dopant that was contained substantially uniformly in the ingot during the production of the ingot that is the source of the semiconductor substrate. The bulk donor in this example is an element other than hydrogen. The dopant of the bulk donor is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited thereto. The bulk donor in this example is phosphorus. The bulk donor is also included in the P-type region. The semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method.The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 １７ ~7×10 １７ / cm ３ . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 １５ ~5×10 １６ / cm ３ . There is a tendency that a higher oxygen concentration makes it easier to generate hydrogen donors. The bulk donor concentration may be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Also, a non-doped substrate that does not contain a dopant such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 １０ / cm ３ or more and 5×10 １２ / cm３ The following applies: The bulk donor concentration (D0) of the non-doped substrate is preferably 1 × 10⁻⁶. １１ / cm ３ That concludes the explanation. The bulk donor concentration (D0) of the non-doped substrate is preferably 5 × 10⁻⁶. １２ / cm ３ The following applies. Note that the concentrations in this invention may be values ​​at room temperature. As an example, the values ​​at room temperature may be those at 300 K (Kelvin) (approximately 26.9°C).

[0041] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are the SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m). Regarding the numerical representation of powers of 10, for example, the representation 1E+16 means 1 × 10⁻¹⁶ １６ This indicates that the 1E-16 designation is 1 × 10 －１６ This indicates.

[0042] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) method. Alternatively, the carrier concentration measured by broadening resistance (SR) method may be used as the net doping concentration. The carrier concentration measured by CV or SR method may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0043] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. ３ , or, / cm ３ This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted. atoms / cm³ is used to express concentration per unit area. ２ , or simply, / cm ２ This unit is used for donor or acceptor concentrations per unit area within a semiconductor substrate, or for chemical concentrations. The dose per unit area is expressed in ions / cm². ２ , or simply, / cm ２ This unit is used. This unit is used as the unit for dose in ion implantation.

[0044] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0045] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV or SR method may be lower than the chemical concentrations of the elements exhibiting donor or acceptor properties. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which is also a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0046] Figure 1A shows an example of a top view of the semiconductor device 100. In Figure 1A, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1A, only some of the components of the semiconductor device 100 are shown, and some components are omitted.

[0047] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 105 when viewed from above. In this specification, when simply referred to as "viewed from above," it means viewed from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 105 that face each other when viewed from above. In Figure 1A, the X and Y axes are parallel to either edge 105. The Z axis is perpendicular to the top surface of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as will be described later.

[0048] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1A. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160.

[0049] The active section 160 is provided with a transistor section 70 including transistor elements such as IGBTs (Insulated Gate Bipolar Transistors), and a diode section 80 including diode elements such as freewheeling diodes (FWDs). In the example shown in Figure 1A, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT).

[0050] In Figure 1A, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1A). The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0051] The diode portion 80 has an N+ type cathode region in the area in contact with the back surface 23 of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. In other words, the diode portion 80 is the region that overlaps with the cathode region when viewed from above. On the back surface 23 of the semiconductor substrate 10, a P+ type collector region may be provided in the area other than the cathode region. In this specification, an extension region 85, which is an extension of the diode portion 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode portion 80. A collector region is provided on the back surface 23 of the extension region 85.

[0052] The transistor section 70 has a P+ type collector region in the area that is in contact with the back surface 23 of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the front surface 21 side of the semiconductor substrate 10, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0053] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is located near the edge 105. The vicinity of the edge 105 refers to the area between the edge 105 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0054] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 112 to the gate trench. In Figure 1A, the gate wiring is hatched with diagonal lines.

[0055] The gate wiring in this example has an outer gate wiring 130 and an active-side gate wiring 131. The outer gate wiring 130 and the active-side gate wiring 131 are examples of the gate metal layer 50. The outer gate wiring 130 is positioned between the active portion 160 and the edge 105 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the front surface 21 of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0056] The outer perimeter gate wiring 130 is connected to the gate pad 112. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like.

[0057] The active-side gate wiring 131 is provided in the active section 160. By providing the active-side gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0058] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed from a semiconductor such as polysilicon doped with impurities.

[0059] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active portion 160, crossing the active portion 160 approximately in the center in the Y-axis direction. When the active portion 160 is divided by the active gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0060] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of the transistor unit 70 provided in the active unit 160.

[0061] In this example, the semiconductor device 100 includes an edge termination structure 140 between the active portion 160 and the edge 105 when viewed from above. In this example, the edge termination structure 140 is positioned between the outer peripheral gate wiring 130 and the edge 105. The edge termination structure 140 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, or a resurf, which is provided in an annular shape surrounding the active portion 160.

[0062] Figure 1B is an enlarged view of region A in Figure 1A. Region A is the region including the transistor section 70 and the diode section 80. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 17, an emitter section 12, a base section 14, and a contact section 15 provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0063] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. The gate metal layer 50 is provided above the gate trench 40 and well region 17.

[0064] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separated from each other.

[0065] The emitter electrode 52 and gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1B. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0066] The contact holes 54 are provided above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are provided above the base region 14 in the boundary region 90. The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extended in the stretching direction.

[0067] The contact hole 55 connects the gate metal layer 50 to the gate conductive part within the transistor section 70. A plug metal layer made of tungsten or the like may be formed inside the contact hole 55.

[0068] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part in the dummy trench 30. A plug metal layer made of tungsten or the like may be formed inside the contact hole 56.

[0069] The connection portion 25 is connected to an electrode on the front side, such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0070] Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the direction of arrangement. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the direction of arrangement. In this example, the diode section 80 does not have gate trench sections 40.

[0071] The ratio of the gate trench portion 40 to the dummy trench portion 30 in the transistor section 70 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, and vice versa. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. Furthermore, the transistor section 70 may have all trenches as gate trench portions 40 and not have dummy trench portions 30.

[0072] The gate trench portion 40 is an example of a plurality of trench portions arranged in a predetermined alignment direction on the front surface 21 of the semiconductor substrate 10. The gate trench portion 40 is arranged at predetermined intervals along a predetermined alignment direction (in this example, the X-axis direction). The gate trench portion 40 may have two extended portions 41 that extend along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the alignment direction, and a connecting portion 43 that connects the two extended portions 41.

[0073] Preferably, at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0074] The dummy trench section 30 is an example of a plurality of trench sections arranged in a predetermined alignment direction on the front surface 21 of the semiconductor substrate 10. The dummy trench section 30 is a trench section electrically connected to the emitter electrode 52. Similar to the gate trench section 40, the dummy trench section 30 is arranged at predetermined intervals along a predetermined alignment direction (in this example, the X-axis direction). The dummy trench section 30 may have a linear shape extending in the extension direction (in this example, the Y-axis direction), and may have two extension portions 31 extending along the extension direction and a connecting portion 33 connecting the two extension portions 31.

[0075] In this example, the transistor section 70 has a boundary region 90 adjacent to the diode section 80. However, the semiconductor device 100 does not necessarily have to have a boundary region 90.

[0076] The boundary region 90 is provided in the transistor section 70 and is adjacent to the diode section 80. The boundary region 90 has a base region 14. In this example, the boundary region 90 does not have an emitter region 12. In one example, the trench portion of the boundary region 90 is a dummy trench portion 30. In this example, the boundary region 90 is arranged such that both ends in the X-axis direction are dummy trench portions 30. In this example, the boundary region 90 does not have a contact region 15, but the boundary region 90 may have a contact region 15.

[0077] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is the part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as one trench portion. That is, the region sandwiched between two extended portions may be considered as the mesa portion.

[0078] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction.

[0079] The mesa portion 91 is provided in the boundary region 90. The mesa portion 91 has a base region 14 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 91 has a well region 17 on the negative side in the Y-axis direction. In this example, the mesa portion 91 does not have a contact region 15, but the mesa portion 91 may have a contact region 15.

[0080] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has a well region 17 on the negative side in the Y-axis direction.

[0081] The emitter region 12 is provided in the mesa portion 71, but it does not need to be provided in the mesa portions 81 and 91. The contact region 15 is provided in the mesa portion 71, but it does not need to be provided in the mesa portions 91 and 81. However, the contact region 15 may be provided in the mesa portion 91.

[0082] In the diode portion 80, an N+ type cathode region 82 is provided in the region adjacent to the back surface 23 of the semiconductor substrate 10. In the region on the back surface 23 of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. In Figure 1B, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0083] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18, which will be described later. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0084] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0085] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, P-type. The base region 14 may be provided at both ends in the Y-axis direction of the mesa portion 71 on the front surface 21 of the semiconductor substrate 10. Note that Figure 1B shows only one end in the Y-axis direction of the base region 14. The base region 14 is also provided below the contact hole 54 in the diode portion 80.

[0086] The contact region 15 is located above the base region 14 and is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the contact region 15 is of type P+. In this example, the contact region 15 is located on the front surface 21 of the mesa portion 71. The contact region 15 may be located in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also located below the contact hole 54.

[0087] The well region 17 is a region of a second conductivity type located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. The well region 17 is, for example, of the P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the extending ends of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0088] The collector region 22 is a region of second conductivity type provided on the back surface 23 of the semiconductor substrate 10 in the transistor section 70. The collector region 22 is, for example, of P+ type.

[0089] The cathode region 82 is provided on the back surface 23 of the semiconductor substrate 10 in the diode portion 80 and is a first conductivity type region with a higher doping concentration than the drift region 18. The cathode region 82 is, for example, of the N+ type. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80. That is, the collector region 22 is provided below the boundary region 90 in this example.

[0090] Figure 1C shows an example of the a-a' cross-section in Figure 1A. The a-a' cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0091] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the front surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0092] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided through the interlayer insulating film 38. The interlayer insulating film 38 may be a BPSG (Boro-phosphosilicate Glass) film, a BSG (borosilicate glass) film, a PSG (Phosphorosilicate glass) film, an HTO film, or a laminate of these materials. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto.

[0093] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well, reaching the drift region 18. The statement that a trench penetrates each region is not limited to manufacturing in the order of forming each region before forming the trenches. It also includes cases where the regions are formed between the trenches after the trenches have been formed, and the trenches penetrate each region.

[0094] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0095] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0096] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 by an interlayer insulating film 38.

[0097] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0098] The base region 14 is a second conductive region located above the drift region 18. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0099] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0100] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is N+ type. However, the storage region 16 does not necessarily have to be provided.

[0101] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region 18. The ion implantation dose in the accumulation region 16 is 1.0E + 12 cm －２The above is 1.0E +13cm －２ The following may be the case. Also, the ion implantation dose for the accumulation region 16 is 3.0E + 12 cm －２ The above is 6.0E +12cm －２ The following is also possible: By providing a storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0102] The collector region 22 is provided on the back surface 23 of the semiconductor substrate 10 in the transistor section 70. The collector region 22 may be provided below the first buffer region 200, the second buffer region 220, and / or the connection region 240. In this example, the collector region 22 is provided below the second buffer region 220.

[0103] The cathode region 82 is provided on the back surface 23 of the semiconductor substrate 10 in the diode portion 80. The cathode region 82 may be provided below the first buffer region 200, the second buffer region 220, and / or the connection region 240. In this example, the cathode region 82 is provided below the first buffer region 200, the second buffer region 220, and the connection region 240.

[0104] The first buffer region 200 is located above the cathode region 82 and is a region with a higher doping concentration than the drift region 18. The first buffer region 200 is, for example, of the N+ type. The first buffer region 200 may have a doping concentration peak 202. The first buffer region 200 may have multiple doping concentration peaks 202. In this example, the first buffer region 200 has four doping concentration peaks 202. The peaks 202 of the first buffer region 200 may be hydrogen atom concentration peaks. However, the dopants of the peaks 202 of the first buffer region 200 are not limited to hydrogen atoms. For example, among the peaks 202 of the first buffer region 200, the dopant of peak 202a on the front side 21 may be a hydrogen atom, and the dopants of the other peaks may be hydrogen atoms or different. For example, the dopant of peak 202d on the back side 23 of the first buffer region 200 may be phosphorus.

[0105] The second buffer region 220 is located above the collector region 22 and has a higher doping concentration than the drift region 18. The second buffer region 220 is, for example, of the N+ type. The second buffer region 220 may function as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the second conductive type collector region 22. The second buffer region 220 may have a doping concentration peak 222. The second buffer region 220 may have multiple doping concentration peaks 222. In this example, the second buffer region 220 has four doping concentration peaks. The peaks 222 of the second buffer region 220 may be hydrogen atom concentration peaks. However, the dopant of the peak 222 of the second buffer region 220 is not limited to hydrogen atoms. For example, the dopant of the peak 222d on the furthest back surface 23 side of the second buffer region 220 may be phosphorus.

[0106] The peak 202a on the outermost surface 21 side of the first buffer region 200 in the diode section 80 is closer to the outermost surface 21 side than the peak 222a on the outermost surface 21 side of the second buffer region 220 in the transistor section 70. The peak 202a on the outermost surface 21 side of the first buffer region 200 in the diode section 80 is the hydrogen atom concentration peak. The doping concentration of the peak 202a on the outermost surface 21 side of the first buffer region 200 is 5E + 13 cm⁻¹ －３ Above, 7E+14cm －３ The following is acceptable:

[0107] In the semiconductor device 100 of this example, the peak 202a on the front surface 21 side of the first buffer region 200 in the diode section 80 is closer to the front surface 21 than the peak 222a on the front surface 21 side of the second buffer region 220 in the transistor section 70. Therefore, the trade-off relationship between the back surface avalanche withstand capability of the transistor section 70 and the oscillation initiation voltage of the diode section 80 can be improved. The back surface avalanche withstand capability of the transistor section 70 increases as the depth from the back surface 23 of the second buffer region 220 decreases. On the other hand, the oscillation initiation voltage of the diode section 80 increases as the depth from the back surface 23 of the first buffer region 200 increases. Therefore, by having peak 202a closer to the front surface 21 than peak 222a, the oscillation initiation voltage of the diode section 80 can be increased while maintaining a high back surface avalanche withstand capability of the transistor section 70. Details on improving the trade-off relationship between the back avalanche withstand capability of the transistor section 70 and the oscillation start voltage of the diode section 80 will be described later.

[0108] In the depth direction of the semiconductor substrate 10, the distance Lda from the back surface 23 to the peak 202a on the outermost surface 21 side of the first buffer region 200 in the diode portion 80 may be 1.1 times or more and 3 times or less of the distance Lta from the back surface 23 to the peak 222a on the outermost surface 21 side of the second buffer region 220 in the transistor portion 70. By setting the distance Lda to 1.1 times or more and 3 times or less of the distance Lta, the oscillation start voltage of the diode portion 80 can be increased while maintaining a high back surface avalanche withstand capability of the transistor portion 70. In the depth direction of the semiconductor substrate 10, the peak 202a on the outermost surface 21 side of the first buffer region 200 may be located below the center of the semiconductor substrate 10.

[0109] The number of peaks 202 in the first buffer region 200 of the diode section 80 may be equal to the number of peaks 222 in the second buffer region 220 of the transistor section 70. However, the number of peaks 202 in the first buffer region 200 of the diode section 80 and the number of peaks 222 in the second buffer region 220 of the transistor section 70 may be different.

[0110] In the depth direction of the semiconductor substrate 10, the peak 202d on the back surface 23 side of the first buffer region 200 in the diode portion 80 and the peak 222d on the back surface 23 side of the second buffer region 220 in the transistor portion 70 may be located at the same depth. The distance between the peak 202d on the back surface 23 side of the first buffer region 200 and the second peak 202c from the back surface 23 may be greater than the distances between other peaks 202 in the first buffer region 200. That is, the distance Ldcd between peak 202d and peak 202c may be greater than the distance Ldab between peak 202a and peak 202b and the distance Ldbc between peak 202b and peak 202c. The distances Ldab and Ldbc may be equal or different.

[0111] The intervals between peaks 222 in the second buffer region 220 may be equal. That is, the interval Ltab between peak 222a and peak 222b, Ltbc between peak 222b and peak 222c, and Ltcd between peak 222c and peak 222d may be equal. However, the intervals between peaks 222 in the second buffer region 220 may be different.

[0112] The connection region 240 is a region that connects the first buffer region 200 and the second buffer region 220. The connection region 240 is, for example, of the N+ type. The connection region 240 may have a connecting portion 242 that continuously connects at least one peak 202 of the first buffer region 200 and one peak 222 of the second buffer region 220. In this example, the connection region 240 includes a connecting section 242a that continuously connects the peak 202a of the first buffer region 200 and the peak 222a of the second buffer region 220, a connecting section 242b that continuously connects the peak 202b of the first buffer region 200 and the peak 222b of the second buffer region 220, a connecting section 242c that continuously connects the peak 202c of the first buffer region 200 and the peak 222c of the second buffer region 220, and a connecting section 242d that continuously connects the peak 202d of the first buffer region 200 and the peak 222d of the second buffer region 220.

[0113] If the peak 202 of the first buffer region 200 and the peak 222 of the second buffer region 220 are not continuously connected, the depletion layer may slip through the gap between peaks 202 and 222. In the semiconductor device 100 of this example, the connection region 240 has a connecting portion 242 that continuously connects at least one peak 202 of the first buffer region 200 and one peak 222 of the second buffer region 220, so that the depletion layer can be prevented from slipping through the gap between peaks 202 and 222. This makes it possible to suppress local depletion layer reach-through and prevent local increases in electric field strength.

[0114] The connecting portion 242 does not have to be provided in the transistor portion 70. That is, the connecting portion 242 may be provided so as to fit within the diode portion 80. If the peak 202a on the outermost surface 21 side of the first buffer region 200 extends to the transistor portion 70, the effect of improving the back surface avalanche withstand capability of the transistor portion 70 by having the peak 222a on the outermost surface 21 side of the second buffer region 220 located on the back surface 23 side of peak 202a may be reduced. That is, the extension of the peak 202a on the outermost surface 21 side of the first buffer region 200 to the transistor portion 70 may reduce the back surface avalanche withstand capability of the transistor portion 70. By providing the connecting portion 242 within the diode portion 80 rather than on the transistor portion 70, the peak 202a on the outermost surface 21 side of the first buffer region 200 can be reliably contained within the diode portion 80, thereby improving the trade-off relationship between the back surface avalanche withstand capability of the transistor portion 70 and the oscillation start voltage of the diode portion 80. However, at least a portion of the connecting portion 242 may be provided on the transistor portion 70.

[0115] In the arrangement direction of the multiple trench sections, the connecting section 242 may be provided within the thickness of the semiconductor substrate 10 from the end of the diode section 80. When the diode section 80 is operating, holes from the front surface 21 side of the transistor section 70 may be injected into the diode section 80. In this case, the expansion of the holes in the arrangement direction is approximately the thickness of the semiconductor substrate 10. The connecting section 242 may be provided within the range of the expansion of the holes injected from the front surface 21 side of the transistor section 70. As a result, at least a portion of the holes injected from the transistor section 70 are injected from the peak 202a side on the front surface 21 side of the first buffer region 200, so that the oscillation start voltage of the diode section 80 can be increased.

[0116] In this example, the connecting portion 242 may be provided within the thickness of the semiconductor substrate 10 from the end of the diode portion 80, that is, from the boundary between the diode portion 80 and the boundary region 90. If the boundary region 90 is electrically floating, the connecting portion 242 may be provided within the thickness of the semiconductor substrate 10 from the opposite end of the boundary region 90. In other words, the connecting portion 242 may be provided within the thickness of the semiconductor substrate 10 from the boundary between the main region of the transistor portion 70 and the boundary region 90.

[0117] The first buffer region 200 may have a peak group 204 having a peak 222 corresponding to the second buffer region 220. In this example, peak 202a has peak 222a corresponding to the second buffer region 220, peak 202b has peak 222b corresponding to the second buffer region 220, peak 202c has peak 222c corresponding to the second buffer region 220, and peak 202d has peak 222d corresponding to the second buffer region 220. Therefore, all peaks 202 of the first buffer region 200 in this example are included in the peak group 204. The first buffer region 200 may also have peaks 202 that do not have peak 222 corresponding to the second buffer region 220.

[0118] Here, the statement that the peak 202 of the first buffer area 200 has a peak 222 corresponding to the second buffer area 220 means that the peak 202 of the first buffer area 200 has a peak 222 in the second buffer area 220 that is continuously applied to the said peak 202. That is, if the peak 202 of the first buffer area 200 is continuously connected to the peak 222 of the second buffer area 220 by a connecting portion 242, then the peak 202 of the first buffer area 200 and the peak 222 of the second buffer area 220 that are continuously connected by the connecting portion 242 may be corresponding peaks.

[0119] The second buffer region 220 may have a peak group 224 having peaks 202 corresponding to the first buffer region 200. In this example, peak 222a has peak 202a corresponding to the first buffer region 200, peak 222b has peak 202b corresponding to the first buffer region 200, peak 222c has peak 202c corresponding to the first buffer region 200, and peak 222d has peak 202d corresponding to the first buffer region 200. Therefore, all peaks 222 of the second buffer region 220 in this example are included in the peak group 224. The second buffer region 220 may have peaks 222 that do not have peaks 202 corresponding to the first buffer region 200. The number of peaks 202 included in the peak group 204 of the first buffer region 200 may be equal to the number of peaks 222 included in the peak group 224 of the second buffer region 220.

[0120] Here, the statement that the peak 222 of the second buffer area 220 has a peak 202 corresponding to the first buffer area 200 means that the peak 222 of the second buffer area 220 has a peak 202 in the first buffer area 200 that is continuously applied to the said peak 222. That is, if the peak 222 of the second buffer area 220 is continuously connected to the peak 202 of the first buffer area 200 by a connecting portion 242, then the peak 222 of the second buffer area 220 and the peak 202 of the first buffer area 200 that are continuously connected by the connecting portion 242 may be corresponding peaks.

[0121] Note that the corresponding peaks in the first buffer region 200 and the second buffer region 220 may be the closest peaks in the depth direction of the semiconductor substrate 10, or they may be other distant peaks. For example, in this example, the peak 222 in the second buffer region 220 that is closest to the peak 202a of the first buffer region 200 in the depth direction of the semiconductor substrate 10 is peak 222a, and the peak corresponding to the peak 202a of the first buffer region 200 is also peak 222a. On the other hand, the peak 222 in the second buffer region 220 that is closest to the peak 202b of the first buffer region 200 in the depth direction of the semiconductor substrate 10 is peak 222a, but the peak corresponding to the peak 202b of the first buffer region 200 is 222b. In other words, the corresponding peaks in the first buffer region 200 and the second buffer region 220 refer to continuously applied peaks, and the order of the corresponding peaks in each region is not particularly limited.

[0122] At least one of the peaks 202 included in the peak group 204 of the first buffer region 200 may be closer to the front surface 21 than the corresponding peak 222 included in the peak group 224 of the second buffer region 220. In this example, peaks 202a, 202b, and 202c included in the peak group 204 of the first buffer region 200 are each closer to the front surface 21 than the corresponding peaks 222a, 222b, and 222c included in the peak group 224 of the second buffer region 220. The depth position from the back surface 23 of peak 202d included in the peak group 204 of the first buffer region 200 and the depth position from the back surface 23 of peak 222d included in the peak group 224 of the second buffer region 220 may be the same.

[0123] The dopant of peak 202 in the peak group 204 of the first buffer region 200 and the corresponding peak 222 in the peak group 224 of the second buffer region 220 may be the same. For example, the dopant is hydrogen, but is not limited to this. The peak 202 in the peak group 204 of the first buffer region 200 and the corresponding peak 222 in the peak group 224 of the second buffer region 220 may be formed by the same ion implantation process. However, the peak 202 in the peak group 204 of the first buffer region 200 and the corresponding peak 222 in the peak group 224 of the second buffer region 220 may be formed by different ion implantation processes.

[0124] Peak 202 included in the peak group 204 of the first buffer area 200 may be continuously connected to the corresponding peak 222 included in the peak group 224 of the second buffer area 220. That is, peak 202 included in the peak group 204 of the first buffer area 200 and the corresponding peak 222 included in the peak group 224 of the second buffer area 220 may be continuously connected by a connecting section 242.

[0125] The distance in the depth direction of the semiconductor substrate 10 between at least one peak 202 included in the peak group 204 of the first buffer region 200 and the corresponding peak 222 included in the peak group 224 of the second buffer region 220 may be 1 μm or more and half the thickness of the semiconductor substrate 10 or less. The distance in the depth direction of the semiconductor substrate 10 between at least one peak 202 included in the peak group 204 of the first buffer region 200 and the corresponding peak 222 included in the peak group 224 of the second buffer region 220 may be 40 μm or less. That is, in the depth direction of the semiconductor substrate 10, the distance La between peak 202a and the corresponding peak 222a, the distance Lb between peak 202b and the corresponding peak 222b, and the distance Lc between peak 202c and the corresponding peak 222c may each be 1 μm or more and half the thickness of the semiconductor substrate 10 or less, and 40 μm or less. Distances La, Lb, and Lc may be equal to each other or may be different from each other.

[0126] Figure 2 shows an example of the relationship between the depth of the buffer region in the transistor section 70 and the back surface avalanche withstand capability of the transistor section 70. In this figure, the horizontal axis represents the normalized depth when a predetermined reference depth is set to 1.0, and the vertical axis represents the normalized back surface avalanche withstand capability when the back surface avalanche withstand capability corresponding to a predetermined reference depth is set to 1.0. The depth of the buffer region in the transistor section 70 may be the distance from the back surface 23 of the semiconductor substrate 10 to the peak on the front surface 21 side of the buffer region.

[0127] The deeper the buffer region in the transistor section 70, the lower the back-side avalanche withstand capability of the transistor section 70 tends to be. Therefore, by making the buffer region in the transistor section 70 shallower, the back-side avalanche withstand capability of the transistor section 70 can be improved. In the semiconductor device 100 of this example, the back-side avalanche withstand capability of the transistor section 70 can be improved by reducing the distance from the back surface 23 of the semiconductor substrate 10 to the peak 222a of the second buffer region 220.

[0128] Figure 3 shows an example of the relationship between the depth of the buffer region in the diode section 80 and the oscillation start voltage of the diode section 80. In this figure, the horizontal axis represents the normalized depth when a predetermined reference depth is set to 1.0, and the vertical axis represents the normalized oscillation start voltage when the oscillation start voltage corresponding to a predetermined reference depth is set to 1.0. The depth of the buffer region in the diode section 80 may be the distance from the back surface 23 of the semiconductor substrate 10 to the peak on the front surface 21 side of the buffer region.

[0129] The deeper the buffer region in the diode section 80, the higher the oscillation start voltage of the diode section 80 becomes, and oscillation tends to become less likely to occur. Therefore, by increasing the depth of the buffer region in the diode section 80, oscillation of the diode section 80 can be suppressed. In the semiconductor device 100 of this example, oscillation of the diode section 80 can be suppressed by increasing the distance from the back surface 23 of the semiconductor substrate 10 to the peak 202a of the first buffer region 200.

[0130] Figure 4 shows an example of the trade-off relationship between the back avalanche withstand capability of the transistor section 70 and the oscillation initiation voltage of the diode section 80. In this figure, the horizontal axis represents the normalized oscillation initiation voltage of the diode section 80 when the oscillation initiation voltage of the diode section 80 corresponding to a predetermined reference depth is set to 1.0, and the vertical axis represents the normalized back avalanche withstand capability of the transistor section 70 when the back avalanche withstand capability of the transistor section 70 corresponding to a predetermined reference depth is set to 1.0.

[0131] This figure shows the trade-off relationships when the ratio of the depth of the buffer region in the diode section 80 to the depth of the buffer region in the transistor section 70 is 1.00, 1.17, 1.33, and 1.50. The black circles show the trade-off relationship when the ratio is 1.00, i.e., when the depth of the buffer region in the transistor section 70 is equal to the depth of the buffer region in the diode section 80. The white circles show the trade-off relationship when the ratio is 1.17, i.e., when the depth of the buffer region in the diode section 80 is 1.17 times the depth of the buffer region in the transistor section 70. The black squares show the trade-off relationship when the ratio is 1.33, i.e., when the depth of the buffer region in the diode section 80 is 1.33 times the depth of the buffer region in the transistor section 70. The white squares show the trade-off relationship when the ratio is 1.50, i.e., when the depth of the buffer region in the diode section 80 is 1.50 times the depth of the buffer region in the transistor section 70.

[0132] When the depth of the buffer region in the transistor section 70 and the depth of the buffer region in the diode section 80 are the same, the trade-off relationship between the back surface avalanche withstand capability of the transistor section 70 and the oscillation start voltage of the diode section 80 is defined by the trade-off relationship shown by the black circle. In other words, when the depth of the buffer region in the transistor section 70 and the depth of the buffer region in the diode section 80 are formed to be the same, it may not be possible to adjust the back surface avalanche withstand capability of the transistor section 70 and the oscillation start voltage of the diode section 80 separately.

[0133] Since the semiconductor device 100 in this example includes a first buffer region 200 and a second buffer region 220, the depth of the buffer region in the transistor section 70 and the depth of the buffer region in the diode section 80 can be made different. This makes it possible to improve the trade-off relationship between the back surface avalanche withstand capability of the transistor section 70 and the oscillation start voltage of the diode section 80.

[0134] For example, if the buffer region depth in the transistor section 70 is dt and the buffer region depth in the diode section 80 is dd1 = dt, the back avalanche withstand capability of the transistor section 70 will be 1.38, and the oscillation start voltage of the diode section 80 will be 0.63. In the semiconductor device 100 of this example, the buffer region depth in the diode section 80 can be set to dd2 = 1.17dt while keeping the buffer region depth in the transistor section 70 at dt. In this case, the oscillation start voltage of the diode section 80 will be 0.82, improving the trade-off relationship by approximately 1.3 times. Furthermore, if the buffer region depth in the diode section 80 is set to dd3 = 1.33dt while keeping the buffer region depth in the transistor section 70 at dt, the oscillation start voltage of the diode section 80 will be 1.0, improving the trade-off relationship by approximately 1.6 times.

[0135] As described above, in the semiconductor device 100 of this example, the peak 202a on the outermost surface 21 side of the first buffer region 200 in the diode section 80 is closer to the outermost surface 21 side than the peak 222a on the outermost surface 21 side of the second buffer region 220 in the transistor section 70. Therefore, the trade-off relationship between the back surface avalanche withstand capability of the transistor section 70 and the oscillation start voltage of the diode section 80 can be improved. In other words, by making the peak 202a closer to the outer surface 21 side than the peak 222a, the oscillation start voltage of the diode section 80 can be increased while maintaining a high back surface avalanche withstand capability of the transistor section 70.

[0136] Figure 5A shows an example of the doping concentration distribution from the upper edge of the drift region 18 to the back surface 23. In this figure, the doping concentration distribution in the transistor section 70 and the doping concentration distribution in the diode section 80 are shown together. The vertical axis representing the doping concentration is on a logarithmic scale. In addition, this figure also shows the integrated concentration from the upper edge of the drift region 18. The vertical axis representing the integrated concentration is on a linear scale. In this figure, the left end of the horizontal axis is the upper edge of the drift region 18.

[0137] In this specification, the integrated concentration is defined as the concentration obtained by integrating the doping concentration from the upper end of the drift region 18 in the direction toward the back surface 23. In this specification, when a forward bias is applied between the collector electrode 24 and the emitter electrode 52, and the maximum value of the electric field strength reaches the critical electric field strength Ec, causing avalanche breakdown, and when the area from the upper end of the drift region 18 to a specific position in the depth direction of the semiconductor substrate 10 becomes depleted, the integrated concentration is said to reach the critical integrated concentration Nc. In the semiconductor device 100, applying a forward bias between the collector electrode 24 and the emitter electrode 52 means that, with the gate off, the potential of the collector electrode 24 is higher than the potential of the emitter electrode 52. When avalanche breakdown occurs in the semiconductor device 100, an avalanche current flows between the collector electrode 24 and the emitter electrode 52, and the increase in voltage between the collector electrode 24 and the emitter electrode 52 stops. In this case, the depletion layer will not extend beyond the critical position Zc where the integrated concentration in the transistor section 70 reaches the critical integrated concentration Nc of the semiconductor substrate 10, on the back side.

[0138] The critical integral concentration Nc is given by the elementary charge q and the permittivity of vacuum ε. ０ , relative permittivity ε of semiconductor substrate 10 ｒ Nc is a concentration determined from the critical electric field strength Ec and is expressed by the following equation: Nc = Ec(ε ｒ ε ０ / q) Since the critical electric field strength Ec depends on the donor concentration in the n-type layer, the critical integral concentration Nc also depends on the donor concentration in the n-type layer. When the donor concentration in the n-type layer is between 1E+13 and 1E+15 cm⁻¹ －３ Within this range, the critical integral concentration Nc is 1.1E+12 to 2.0E+12 cm⁻¹. －２Therefore, considering that the donor concentration in the n-type layer spans several orders of magnitude, the critical integral concentration Nc can be considered to be approximately a constant.

[0139] In the direction from the upper end of the drift region 18 toward the back surface 23, the first depth position where the integrated concentration in the diode portion 80 becomes higher than the integrated concentration in the transistor portion 70 is defined as the first depth Z1. In the direction from the upper end of the drift region 18 toward the back surface 23, the integrated concentration in the diode portion 80 and the integrated concentration in the transistor portion 70 may be equal on the front surface 21 side of the first depth Z1. In the direction from the upper end of the drift region 18 toward the back surface 23, the integrated concentration in the diode portion 80 may be higher than the integrated concentration in the transistor portion 70 at the first depth Z1. In this example, the integrated concentration in the diode portion 80 is higher than the integrated concentration in the transistor portion 70 at the boundary between the drift region 18 and the first buffer region 200. That is, the first depth Z1 in this example is the boundary between the drift region 18 and the first buffer region 200. In the semiconductor device 100 of this example, the peak 202a on the outermost surface 21 side of the first buffer region 200 in the diode section 80 is closer to the outermost surface 21 side than the peak 222a on the outermost surface 21 side of the second buffer region 220 in the transistor section 70. Therefore, the integral concentration in the diode section 80 may start rising before the integral concentration in the transistor section 70.

[0140] In the direction from the upper end of the drift region 18 towards the back surface 23, the depth position at which the integrated concentration in the diode section 80 becomes equal to the integrated concentration in the transistor section 70 is defined as the second depth Z2. If there are multiple depth positions at which the integrated concentration in the diode section 80 becomes equal to the integrated concentration in the transistor section 70, the first depth position at which the integrated concentration in the diode section 80 becomes equal to the integrated concentration in the transistor section 70 in the direction from the upper end of the drift region 18 towards the back surface 23 may be defined as the second depth Z2. That is, in the direction from the upper end of the drift region 18 towards the back surface 23, the integrated concentration in the diode section 80 may be equal to the integrated concentration in the transistor section 70 at the second depth Z2. The second depth Z2 may be the critical position Zc, or it may be located on the front surface 21 side of the critical position Zc. In this example, the integrated concentration in the diode section 80 is equal to the integrated concentration in the transistor section 70 at the critical position Zc. In other words, the second depth Z2 in this example is the critical position Zc, and the position where the integral concentration in the transistor section 70 and the integral concentration in the diode section 80 reach the critical integral concentration Nc is the same.

[0141] In the direction from the upper end of the drift region 18 towards the back surface 23, the integral concentration in the diode portion 80 may be higher, equal to, or lower than the integral concentration in the transistor portion 70 on the back surface 23 side of the second depth Z2. In this example, the integral concentration in the diode portion 80 is slightly higher than the integral concentration in the transistor portion 70 on the back surface 23 side of the second depth Z2. By making the integral concentration in the diode portion 80 higher than the integral concentration in the transistor portion 70, carrier depletion can be prevented.

[0142] The total integral concentration from the upper end of the drift region 18 in the diode section 80 to the lower end of the first buffer region 200 and the total integral concentration from the upper end of the drift region 18 in the transistor section 70 to the lower end of the second buffer region 220 may be approximately the same. For example, the difference between the total integral concentration in the diode section 80 and the total integral concentration in the transistor section 70 is 10% or less of the average of the two.

[0143] If the difference between the total integrated concentration in the diode section 80 and the total integrated concentration in the transistor section 70 becomes large, the difference between the breakdown voltage of the transistor section 70 and the breakdown voltage of the diode section 80 may also become large. In this case, the operation will be limited by the lower breakdown voltage. By making the total integrated concentration in the diode section 80 and the total integrated concentration in the transistor section 70 approximately the same, the breakdown voltage difference between the transistor section 70 and the diode section 80 can be reduced.

[0144] The critical position in the diode section 80 may be located on the front surface 21 side of the critical position Zc of the transistor section 70. In this case, the breakdown voltage calculated using only the diode section 80 may be smaller than the breakdown voltage calculated using only the transistor section 70. The breakdown voltage of the semiconductor device 100 may be the same as the breakdown voltage calculated using only the diode section 80. This allows for, for example, a higher surge current withstand capability.

[0145] Figure 5B shows an example of the doping concentration distribution from the upper end of the drift region 18 to the back surface 23. In this example, the differences from the embodiment in Figure 5A will be explained in detail, but other aspects may be the same as those in the embodiment in Figure 5A.

[0146] The second depth Z2 may be located on the front surface 21 side of the critical position Zc. The integrated concentration in the diode section 80 may have a region on the front surface 21 side of the second depth Z2 where it is higher than the integrated concentration in the transistor section 70. The integrated concentration in the diode section 80 may have a region between the second depth Z2 and the critical position Zc where it is lower than the integrated concentration in the transistor section 70.

[0147] In this example, the integrated concentration in the diode section 80 reaches the critical integrated concentration Nc on the back surface 23 side, which is further than the critical position Zc where the integrated concentration in the transistor section 70 reaches the critical integrated concentration Nc. The position where the integrated concentration in the diode section 80 reaches the critical integrated concentration Nc may be within 5 μm from the critical position Zc on the back surface 23 side. The position where the integrated concentration in the diode section 80 reaches the critical integrated concentration Nc may also be within 5 μm from the critical position Zc on the front surface 21 side.

[0148] In the semiconductor device 100 of this example, the above integral concentration relationship is achieved by the fact that the peak on the outermost surface 21 side of the first buffer region 200 in the diode section 80 is closer to the outermost surface 21 side than the peak on the outermost surface 21 side of the second buffer region 220 in the transistor section 70, and the other peaks of the first buffer region 200 in the diode section 80 are closer to the back surface 23 side than each of the other peaks of the second buffer region 220 in the transistor section 70. However, the positional relationship of the other peaks is not particularly limited as long as the peak on the outermost surface 21 side of the first buffer region 200 in the diode section 80 is closer to the outermost surface 21 side than the peak on the outermost surface 21 side of the second buffer region 220 in the transistor section 70.

[0149] Figure 5C shows an example of the doping concentration distribution in the drift region 18 and the buffer region. In this example, the differences from the embodiment in Figure 5A will be explained in detail, but other aspects may be the same as those in the embodiment in Figure 5A.

[0150] The second depth Z2 may be located on the front surface 21 side of the critical position Zc. The integrated concentration in the diode section 80 may have a region on the front surface 21 side of the second depth Z2 where it is higher than the integrated concentration in the transistor section 70. The integrated concentration in the diode section 80 may have a region between the second depth Z2 and the critical position Zc where it is equal to the integrated concentration in the transistor section 70.

[0151] Figure 6 shows an example of the doping concentration distribution near the junction 242 along the b-b' line in Figure 1C. For comparison, the doping concentration Ddr in the drift region 18 is also shown in this figure.

[0152] The lowest doping concentration Dc in the connecting section 242 may be lower than the doping concentration at peak 222 and lower than the doping concentration at peak 202. The lowest doping concentration Dc in the connecting section 242 may be higher than the doping concentration Ddr in the drift region 18. The connecting section 242 may continuously connect the doping concentration at peak 202 in the first buffer region 200 and the doping concentration at peak 222 in the second buffer region 220. The doping concentration in the connecting section 242 may be higher than the doping concentration Ddr in the drift region 18.

[0153] Figure 7 shows a cross-section of a modified example of the semiconductor device 100 along the line a-a'. This example of the semiconductor device 100 differs from the embodiment in Figure 1C in that the position of the connecting portion 242 is different. In this example, the differences from the embodiment in Figure 1C will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 1C.

[0154] In this example, the collector region 22 is located below the second buffer region 220 and the connection region 240. In this example, the cathode region 82 is located below the first buffer region 200 and the connection region 240.

[0155] At least a portion of the connecting portion 242 may be provided in the transistor portion 70. The end of the connecting portion 242 on the second buffer region 220 side may be provided in the boundary region 90. This maintains the effect of suppressing the back surface avalanche withstand capability of the transistor portion 70. That is, by providing the end of the connecting portion 242 on the second buffer region 220 side in the boundary region 90, only the second buffer region 220 exists in the main region of the transistor portion 70, and the back surface avalanche withstand capability of the transistor portion 70 can be maintained. Therefore, the semiconductor device 100 in this example can improve the trade-off relationship between the back surface avalanche withstand capability of the transistor portion 70 and the oscillation start voltage of the diode portion 80.

[0156] Figure 8 shows a cross-section a-a' of a modified example of the semiconductor device 100. The semiconductor device 100 in this example differs from the embodiment in Figure 1C in that the position of the peak on the back surface 23 side of the first buffer region 200 is different. In this example, the differences from the embodiment in Figure 1C will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 1C.

[0157] The peak on the back surface 23 side of the first buffer region 200 in the diode section 80 may be closer to the front surface 21 side than the peak on the back surface 23 side of the second buffer region 220 in the transistor section 70. The spacing between peaks 202 in the first buffer region 200 may be equal to each other. That is, the spacing Ldab between peak 202a and peak 202b, Ldbc between peak 202b and peak 202c, and Ldcd between peak 202c and peak 202d may be equal to each other. However, the spacing between peaks 202 in the first buffer region 200 may be different to each other.

[0158] In the depth direction of the semiconductor substrate 10, the distance La between peak 202a and the corresponding peak 222a, the distance Lb between peak 202b and the corresponding peak 222b, the distance Lc between peak 202c and the corresponding peak 222c, and the distance Ld between peak 202d and the corresponding peak 222d may be 1 μm or more, 10 μm or more, or 20 μm or more. The distance Lb between peak 202b and the corresponding peak 222b, the distance Lc between peak 202c and the corresponding peak 222c, and the distance Ld between peak 202d and the corresponding peak 222d may be half the thickness of the semiconductor substrate 10 or less, 50 μm or less, 40 μm or less, or 30 μm or less. The distances La, Lb, Lc, and Ld may be equal to each other or different from each other.

[0159] Figure 9 shows a cross-section a-a' of a modified example of the semiconductor device 100. The semiconductor device 100 in this example differs from the embodiment in Figure 1C in that the number of peaks in the first buffer region 200 and the number of peaks in the second buffer region 220 are different. In this example, the differences from the embodiment in Figure 1C will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 1C.

[0160] The number of peaks 202 in the first buffer region 200 of the diode section 80 may be greater than the number of peaks 222 in the second buffer region 220 of the transistor section 70. In this example, the number of peaks 202 in the first buffer region 200 is 5, and the number of peaks 222 in the second buffer region 220 is 4.

[0161] Peak 202e in the first buffer region 200 does not correspond to any of the peaks 222 in the second buffer region 220. Therefore, peak 202e may not be included in the peak group 204. Thus, the first buffer region 200 may have a peak 202 that does not correspond to any of the peaks 222 in the second buffer region 220. The interval Ldae between peak 202e and peak 202a may be the same as or different from the intervals between other peaks.

[0162] In this example, a peak 202e that does not have a peak 222 corresponding to the second buffer region 220 is provided on the outermost surface 21 side of the first buffer region 200. However, the position of the peak 202 that does not have a peak 222 corresponding to the second buffer region 220 is not limited to this. The peak 202e that does not have a peak 222 corresponding to the second buffer region 220 may be located between each of the peaks 202 included in the peak group 204, and may be located on the outermost surface 23 side of the first buffer region 200.

[0163] Figure 10 is a flowchart showing an example of a method for manufacturing a semiconductor device 100. In step S100, a transistor portion 70 and a diode portion 80 are provided on a first-conductivity semiconductor substrate 10 having a front surface 21 and a back surface 23. Step S100 may include the step of providing a dummy trench portion 30 and a gate trench portion 40 as element structures for the transistor portion 70 and the diode portion 80, and may also include the step of providing each doping region by ion implantation into the semiconductor substrate 10.

[0164] In step S110, ions are implanted from the back surface 23 to provide a buffer region of a first conductivity type with a higher doping concentration than the semiconductor substrate 10. Step S110 may be a step of providing a first buffer region 200, a second buffer region 220, and a connection region 240. The order of steps S100 and S110 is not particularly limited. Also, steps S100 and S110 do not necessarily have to be separate steps and may have a common process.

[0165] Step S110 for providing a buffer region may include Step S112 of providing a resist on the back surface 23 of the transistor section 70 and implanting ions from the back surface 23 side, and Step S114 of providing a hydrogen atom concentration peak in the diode section 80 as the peak on the outermost surface 21 side of the buffer region. Steps S112 and S114 may be the same process or different processes. Step S114 may be the step of providing peak 202a in Figures 1C, 7 and 8. In this case, peak 222a in the transistor section 70 may be provided in the same process. However, peak 222a in the transistor section 70 may be provided in different processes. Also, Step S114 may be the step of providing peak 202e in Figure 9. In this case, peak 222a in the transistor section 70 may be provided in different processes.

[0166] In the manufacturing method of the semiconductor device 100 in this example, a resist is provided on the back surface 23 of the transistor section 70, and ions are implanted from the back surface 23 side. As a result, the peak on the front surface 21 side of the first buffer region 200 in the diode section 80 is closer to the front surface 21 side than the peak on the front surface 21 side of the second buffer region 220 in the transistor section 70. Therefore, the trade-off relationship between the back surface avalanche withstand capability of the transistor section 70 and the oscillation start voltage of the diode section 80 can be improved.

[0167] Figure 11 shows an example of the manufacturing process for a semiconductor device 100. In each step of this figure, only the vicinity of the back surface 23 of the semiconductor substrate 10 is shown, and the front surface 21 of the semiconductor substrate 10 is omitted.

[0168] The first stage shows step S100, in which the transistor section 70 and the diode section 80 are provided. However, the subsequent steps shown may be performed in the middle of step S100, in which the transistor section 70 and the diode section 80 are provided.

[0169] The second stage shows step S110, which involves providing a buffer region. This step corresponds to step S112, in which a resist 250 is provided on the back surface 23 of the transistor section 70 and ions are implanted from the back surface 23 side, and step S114, in which a peak of hydrogen atom concentration is provided in the diode section 80 as the peak on the outermost surface 21 side of the buffer region. That is, a resist 250 is provided on the back surface 23 of the transistor section 70 and hydrogen ions are implanted from the back surface 23 side, and a peak of hydrogen atom concentration is provided in the diode section 80 as the peak 202a on the outermost surface 21 side. A peak 222a on the outermost surface 21 side of the transistor section 70 may also be provided at the same time. In this case, the peak 222a on the outermost surface 21 side of the transistor section 70 may also be a peak of hydrogen atom concentration.

[0170] The sides of the resist 250 may have a tapered shape. The angle θ between the side and back surface 23 of the resist 250 may be 45 degrees or more and 90 degrees or less.

[0171] The third stage shows step S110, in which a buffer region is provided. This step corresponds to step S112, in which a resist 250 is provided on the back surface 23 of the transistor section 70 and ions are implanted from the back surface 23 side. In this step, peaks 202b and 222b may be provided. The implanted ions may be hydrogen ions, and peaks 202b and 222b may be peaks of hydrogen atom concentration. However, the type of ions implanted is not limited to hydrogen.

[0172] The fourth stage shows step S110, in which a buffer region is provided. This step corresponds to step S112, in which a resist 250 is provided on the back surface 23 of the transistor section 70 and ions are implanted from the back surface 23 side. In this step, peaks 202c and 222c may be provided. The implanted ions may be hydrogen ions, and peaks 202c and 222c may be peaks of hydrogen atom concentration. However, the type of ions implanted is not limited to hydrogen.

[0173] The fifth stage shows step S110, in which a buffer region is provided. In this step, the resist 250 does not need to be provided. In this step, peaks 202d and 222d may be provided. By ion implantation without providing the resist 250, the peak 202d on the furthest back surface 23 side of the diode section 80 and the peak 222d on the furthest back surface 23 side of the transistor section 70 may be provided at the same depth. The implanted ions may be hydrogen ions, and peaks 202d and 222d may be peaks of hydrogen atom concentration. However, the type of ions to be implanted is not limited to hydrogen. As another example, the implanted ions may be phosphorus ions.

[0174] In this example, although the process shown in the fifth stage does not involve the provision of the resist 250, the resist 250 may also be provided in the fifth stage. In this case, it may be provided at different depths than peaks 202d and 222d, and a semiconductor device 100 like the one shown in the embodiment of Figure 8 can be manufactured.

[0175] Furthermore, before the process shown in the second stage, a step of ion implantation may be performed only in the diode portion 80. In this case, a peak 202 without a peak 222 corresponding to the second buffer region 220 may be provided, and a semiconductor device 100 as shown in the embodiment of Figure 9 can be manufactured.

[0176] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0177] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.

[0178] 10... Semiconductor substrate, 12... Emitter region, 14... Base region, 15... Contact region, 16... Storage region, 17... Well region, 18... Drift region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Collector electrode, 25... Connection portion, ... 30... Dummy trench portion, 31... Stretched portion, 32... Dummy insulating film, 33... Connection portion, 34... Dummy conductive portion, 38... Interlayer insulating film, 40... Gate trench portion, 41... Stretched portion, 42... Gate insulating film, 43... Connection portion, 44... Gate conductive portion, 50... Gate metal layer, 52... Emitter electrode, 54... Contact hole, 55 ...Contact hole, 56...Contact hole, 70...Transistor section, 71...Mesa section, 80...Diode section, 81...Mesa section, 82...Cathode region, 85...Extension region, 90...Boundary region, 91...Mesa section, 100...Semiconductor device, 105...Edge, 112...Gate pad, 130...Outer perimeter gate wiring, 131...Active side gate wiring, 140...Edge termination structure, 160...Active section, 200...First buffer region, 202...Peak, 204...Peak group, 220...Second buffer region, 222...Peak, 224...Peak group, 240...Connection region, 242...Connecting section, 250...Resist

Claims

1. A semiconductor device comprising a transistor section and a diode section, wherein the semiconductor substrate having a front surface and a back surface comprises: a drift region of a first conductivity type provided on the semiconductor substrate; a collector region of a second conductivity type provided on the back surface of the semiconductor substrate in the transistor section; a cathode region of a first conductivity type provided on the back surface of the semiconductor substrate in the diode section, having a doping concentration higher than that of the drift region; a first buffer region provided above the cathode region, having a doping concentration higher than that of the drift region; a second buffer region provided above the collector region, having a doping concentration higher than that of the drift region; and a plurality of trench sections arranged in a predetermined arrangement direction on the front surface, wherein the peak of the first buffer region in the diode section closest to the front surface is closer to the front surface than the peak of the second buffer region in the transistor section closest to the front surface, and the peak of the first buffer region in the diode section closest to the front surface is the peak of hydrogen atom concentration.

2. The semiconductor device according to claim 1, wherein the integral concentration is defined as the concentration obtained by integrating the doping concentration from the upper end of the drift region in the direction toward the back surface, and the critical position is defined as the position where the integral concentration in the transistor portion reaches the critical integral concentration of the semiconductor substrate, wherein, in the direction from the upper end of the drift region to the back surface, the integral concentration in the diode portion is higher than the integral concentration in the transistor portion at a first depth, and equal to the integral concentration in the transistor portion at a second depth, and the second depth is the critical position or is located on the front surface side of the critical position.

3. The semiconductor device according to claim 2, wherein the second depth is located on the front side of the critical position, the integrated concentration in the diode portion has a region on the front side of the second depth that is higher than the integrated concentration in the transistor portion, and a region between the second depth and the critical position that is lower than the integrated concentration in the transistor portion.

4. The semiconductor device according to claim 2, wherein the second depth is located on the front side of the critical position, the integrated concentration in the diode portion has a region on the front side of the second depth that is higher than the integrated concentration in the transistor portion, and has a region between the second depth and the critical position where it is equal to the integrated concentration in the transistor portion.

5. The semiconductor device according to claim 1, further comprising a connection region connecting the first buffer region and the second buffer region, wherein the connection region has a connecting portion that continuously connects at least one peak of the first buffer region and one peak of the second buffer region.

6. The semiconductor device according to claim 5, wherein the connecting portion is not provided in the transistor portion.

7. The semiconductor device according to claim 6, wherein, in the direction of arrangement, the connecting portion is provided within the thickness of the semiconductor substrate from the end of the diode portion.

8. The semiconductor device according to claim 5, wherein at least a portion of the connecting portion is provided in the transistor portion.

9. The semiconductor device according to claim 8, wherein the transistor portion has a boundary region provided adjacent to the diode portion, and the end of the connecting portion on the second buffer region side is provided in the boundary region.

10. The semiconductor device according to claim 1, wherein the first buffer region has a group of peaks having peaks corresponding to the second buffer region, the second buffer region has a group of peaks having peaks corresponding to the first buffer region, and at least one of the peaks included in the group of peaks of the first buffer region is closer to the front side than the corresponding peak included in the group of peaks of the second buffer region.

11. The semiconductor device according to claim 10, wherein the dopants of the peaks included in the peak group of the first buffer region and the corresponding peaks included in the peak group of the second buffer region are the same.

12. The semiconductor device according to claim 11, wherein the dopant is hydrogen.

13. The semiconductor device according to claim 10, wherein the number of peaks included in the peak group of the first buffer region is equal to the number of peaks included in the peak group of the second buffer region.

14. The semiconductor device according to claim 10, wherein the peaks included in the peak group of the first buffer region are continuously connected to the corresponding peaks included in the peak group of the second buffer region.

15. The semiconductor device according to claim 10, wherein the distance in the depth direction of the semiconductor substrate between at least one peak included in the peak group of the first buffer region and the corresponding peak included in the peak group of the second buffer region is 1 μm or more and half the thickness of the semiconductor substrate or less.

16. The semiconductor device according to claim 15, wherein the distance in the depth direction of the semiconductor substrate between at least one peak included in the peak group of the first buffer region and the corresponding peak included in the peak group of the second buffer region is 40 μm or less.

17. The doping concentration of the peak on the outermost side of the first buffer region is 5E + 13 cm⁻¹. －３ Above, 7E+14cm －３ The semiconductor device according to any one of claims 1 to 16 below.

18. The semiconductor device according to any one of claims 1 to 16, wherein, in the depth direction of the semiconductor substrate, the peak on the back side of the first buffer region in the diode portion and the peak on the back side of the second buffer region in the transistor portion are provided at the same depth.

19. The semiconductor device according to claim 18, wherein the distance between the peak on the back side of the first buffer region and the second peak from the back side is greater than the distance between the other peaks in the first buffer region.

20. The semiconductor device according to any one of claims 1 to 16, wherein the peak on the back side of the first buffer region in the diode portion is closer to the front side than the peak on the back side of the second buffer region in the transistor portion.

21. The semiconductor device according to any one of claims 1 to 16, wherein the number of peaks in the first buffer region in the diode portion is equal to the number of peaks in the second buffer region in the transistor portion.

22. The semiconductor device according to any one of claims 1 to 16, wherein the number of peaks in the first buffer region in the diode portion is greater than the number of peaks in the second buffer region in the transistor portion.

23. The semiconductor device according to any one of claims 1 to 16, wherein, in the depth direction of the semiconductor substrate, the distance from the back surface to the peak on the front side of the first buffer region in the diode portion is 1.1 times or more and 3 times or less the distance from the back surface to the peak on the front side of the second buffer region in the transistor portion.

24. The semiconductor device according to any one of claims 1 to 16, wherein, in the depth direction of the semiconductor substrate, the peak on the front side of the first buffer region is located below the center of the semiconductor substrate.

25. A method for manufacturing a semiconductor device comprising a transistor portion and a diode portion, comprising the steps of: providing the transistor portion and the diode portion on a semiconductor substrate of a first conductivity type having a front surface and a back surface; implanting ions from the back surface to provide a buffer region of the first conductivity type having a higher doping concentration than that of the semiconductor substrate, wherein the step of providing the buffer region comprises: providing a resist on the back surface of the transistor portion and implanting ions from the back surface; and providing a peak of hydrogen atom concentration in the diode portion as the peak on the front surface side of the buffer region.

26. The method for manufacturing a semiconductor device according to claim 25, wherein the angle between the side surface and the back surface of the resist is 45 degrees or more and 90 degrees or less.

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