Semiconductor device

Abstract

A semiconductor device (1) having a vertical MOS transistor (10) comprises: a source electrode (11); a source pad (111), which is a portion of the source electrode (11) exposed on the upper surface of the semiconductor device (1); a gate electrode (21); a low-concentration impurity layer (43) of a first conductivity type; a body region (18) of a second conductivity type formed in the low-concentration impurity layer (43), the second conductivity type being different from the first conductivity type; a trench (17) formed to a depth extending from the upper surface of the low-concentration impurity layer (43) through the body region (18) into a portion of the low-concentration impurity layer (43); a first conductor (15) embedded on the lower side inside the trench (17); and a second conductor (25) embedded on the upper side inside the trench (17). The first conductor (15) is connected to the source electrode (11). The second conductor (25) is connected to the gate electrode (21). The first conductor (15) has a portion connected to the source electrode (11) immediately below the source pad (111).

Description

Semiconductor device

[0001] The present disclosure relates to a semiconductor device.

[0002] Conventionally, semiconductor devices have been known (see, for example, Patent Document 1).

[0003] Japanese Unexamined Patent Application Publication No. 2024-1723

[0004] In vertical MOS transistors, it is required to stably improve the breakdown voltage.

[0005] To solve the above problems, the semiconductor device according to the present disclosure is a semiconductor device including a vertical MOS transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first conductivity type at a first concentration; a low-concentration impurity layer of the first conductivity type formed in contact with the semiconductor substrate and containing an impurity of the first conductivity type at a second concentration lower than the first concentration; a body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer; a source region of the first conductivity type formed in the body region; a trench formed from the upper surface of the low-concentration impurity layer to a depth penetrating the body region to a part of the low-concentration impurity layer; an insulating film formed on the inner surface of the trench; a first conductor formed in contact with the insulating film and embedded on the lower side inside the trench; a second conductor formed in contact with the insulating film and embedded on the upper side inside the trench; an intermediate insulating film formed between the first conductor and the second conductor; and a conductor formed on the upper surface of the low-concentration impurity layer The semiconductor device comprises a source electrode in contact with the body region and the source region, a source pad on which the source electrode is exposed on the upper surface of the semiconductor device, a gate electrode formed on the upper surface of the low-concentration impurity layer, a gate pad on which the gate electrode is exposed on the upper surface of the semiconductor device, a surface drain electrode formed on the upper surface of the low-concentration impurity layer, and a drain pad on which the surface drain electrode is exposed on the upper surface of the semiconductor device, wherein the first conductor is connected to the source electrode, the second conductor is connected to the gate electrode, the first conductor embedded in the trench has a portion where it is connected to the source electrode directly below the source pad, in a plan view of the semiconductor device the semiconductor device is rectangular, the semiconductor device has a first region and a second region which are two parts of the area of ​​the semiconductor device that do not overlap each other, the source pad and the gate pad are located in the first region, and the drain pad is located in the second region.

[0006] The purpose of this disclosure is to provide a semiconductor device equipped with a vertical MOS transistor that has stably improved breakdown voltage.

[0007] Figure 1A is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. Figure 1B is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. Figure 2A is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 1. Figure 2B is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 1. Figure 2C is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 1. Figure 3A is a schematic plan view showing an example of a substantially unit configuration of a transistor according to Embodiment 1. Figure 3B is a schematic perspective view showing an example of a substantially unit configuration of a transistor according to Embodiment 1. Figure 4A is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 1. Figure 4B is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 1. Figure 5 is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 2 of Embodiment 1. Figure 6A is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 2. Figure 6B is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 2. Figure 6C is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 2.

[0008] Hereinafter, a specific example of a semiconductor device according to one aspect of this disclosure will be described with reference to the drawings. The embodiments shown here are all examples of this disclosure. Therefore, the numerical values, shapes, components, arrangement of components, and connection configurations shown in the following embodiments are examples and are not intended to limit this disclosure. In addition, each figure is a schematic diagram and is not necessarily a strict illustration. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified.

[0009] (Embodiment 1) [1. Structure of Semiconductor Device] Figures 1A and 1B are schematic plan views showing an example of the structure of the semiconductor device 1 according to Embodiment 1. Figure 2A is a schematic cross-sectional view when Figure 1A is cut along line I-I. Figure 2B is a schematic cross-sectional view when Figure 1A is cut along line II-II. Figure 2C is a schematic cross-sectional view when Figure 1A is cut along line III-III.

[0010] In Figure 1B, the passivation layer 45 and the interlayer insulating layer 44, which will be described later, are shown as if they were transparent, allowing the underlying structure to be seen through. Also in Figure 1B, the pads, which would otherwise be invisible, are shown with dotted lines for clarity.

[0011] As shown in Figures 1A and 1B, in a plan view, the semiconductor device 1 is divided into a first region A1 and a second region A2, which are two parts of the semiconductor device 1's area, without overlapping. In Figures 1A and 1B, a dotted line represents a hypothetical boundary line 90 separating the first region A1 and the second region A2. For clarity, the dotted line representing the boundary line 90 is shown extending to the outside of the semiconductor device 1, but the actual boundary line 90 terminates at the outer perimeter of the semiconductor device 1 in a plan view. The boundary line 90 will be described later.

[0012] In Figures 1A and 1B, the dashed lines indicating the first region A1 and the second region A2 are not precisely aligned with the outer perimeter and boundary line 90 of the semiconductor device 1 for clarity, but are shown slightly inward with some margin. However, the outer perimeters of the first region A1 and the second region A2 substantially coincide with the outer perimeter and boundary line 90 of the semiconductor device 1. In the semiconductor device 1 according to Embodiment 1, in a plan view, there are no regions that are neither the first region A1 nor the second region A2.

[0013] Furthermore, as shown in Figures 1A and 1B, in a plan view, the semiconductor device 1 is rectangular, and the boundary line 90 separating the first region A1 and the second region A2 may divide the semiconductor device 1 in a straight line. In this case, in a plan view, both the first region A1 and the second region A2 are rectangular.

[0014] As shown in Figure 2A, the semiconductor device 1 includes a semiconductor substrate 42, a metal layer 41, and a low-concentration impurity layer 43 formed on the semiconductor substrate 42. In this disclosure, the semiconductor substrate 42 and the low-concentration impurity layer 43 together are referred to as the semiconductor layer 40.

[0015] The semiconductor substrate 42 is located on the back side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities of a first conductivity type at a first concentration. The low-concentration impurity layer 43 is located on the front side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 42, and is of the first conductivity type containing impurities of a first conductivity type at a second concentration lower than the first concentration. The low-concentration impurity layer 43 may be formed on the semiconductor substrate 42 by, for example, epitaxial growth.

[0016] The metal layer 41 is formed in contact with the back side of the semiconductor layer 40 (semiconductor substrate 42) and may be a multilayer structure including a layer made of, for example, silver (Ag) or copper (Cu). The metal layer 41 may also contain trace amounts of elements other than metals that are introduced as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 41 may be formed over the entire back surface of the semiconductor layer 40 (semiconductor substrate 42). The thickness of the metal layer 41 is, for example, 3 [μm] to 50 [μm].

[0017] As shown in Figure 2A, the semiconductor device 1 has a vertical MOS (Metal Oxide Semiconductor) transistor 10 (hereinafter also referred to as transistor 10) formed in the semiconductor layer 40.

[0018] In a plan view, the semiconductor layer 40 (low-concentration impurity layer 43) in the first region A1 contains impurities of a second conductivity type different from the first conductivity type, forming a body region 18 that is of the second conductivity type. A source region 14 that is of the first conductivity type is selectively formed above the body region 18, containing impurities of the first conductivity type.

[0019] In a plan view, a trench 17 is formed in the semiconductor layer 40 (low-concentration impurity layer 43) in the first region A1, extending from the upper surface of the semiconductor layer 40, through the source region 14 and the body region 18, to a depth D1 to a part of the low-concentration impurity layer 43. The trench 17 extends in the Y direction and is arranged parallel to the X direction.

[0020] In this disclosure, the Y direction is the direction in which the trench 17 extends, parallel to the upper surface of the semiconductor layer 40. The X direction is the direction parallel to the upper surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction is perpendicular to both the X and Y directions and indicates the height direction of the semiconductor device 1. In this disclosure, the Y direction may also be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction.

[0021] Figure 1B schematically shows a portion of the multiple trenches 17 with a thick line. In the semiconductor device 1 according to Embodiment 1, in a plan view, the Y direction in which the trenches 17 extend is perpendicular to the boundary line 90.

[0022] An insulating film 16, for example, made of a silicon oxide film, is formed on the inner surface of the trench 17, and the first conductor 15 and the second conductor 25 are formed in contact with the insulating film 16 inside the trench 17. The first conductor 15 and the second conductor 25 are embedded electrodes embedded inside the semiconductor layer 40. The first conductor 15 and the second conductor 25 are, as an example without limitation, polysilicon containing impurities.

[0023] The trench 17 has a so-called split structure, and in addition to the insulating film 16 formed on the inner surface of the trench 17, an intermediate insulating film 26 is formed inside the trench 17 at the point where it separates the first conductor 15 on the lower side from the second conductor 25 on the upper side. The intermediate insulating film 26 is formed at a position where the depth from the upper surface of the semiconductor layer 40 is D2 (D1 > D2). The depth D2 is deeper than the depth from the upper surface of the semiconductor layer (low-concentration impurity layer 43) to the lower surface of the body region 18.

[0024] The source electrode 11 of the transistor 10 is formed in the first region A1 in a plan view, as shown in Figure 2A, on the upper surface of the semiconductor layer 40 (low-concentration impurity layer 43), connected to the body region 18 and the source region 14 (see Figures 3A and 3B described later). The source electrode 11 is also connected to source wiring 19, which is formed along at least two sides parallel to the boundary line 90 on the outer periphery of the rectangular first region A1 in a plan view, excluding the installation margin, and extends almost the entire length.

[0025] As shown in Figure 2A, the source electrode 11 consists of a portion 12 and a portion 13, with portion 12 connected to the source region 14 and the body region 18 via portion 13. Portion 12 of the source electrode 11 is a layer that is joined to the solder during reflow in face-down mounting, and may be composed of a metallic material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 12 may be plated with gold or the like.

[0026] The portion 13 of the source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40, and may be made of a metallic material including one or more of aluminum, copper, gold, and silver, as an example without limitation. The thickness of the source electrode 11, including portions 12 and 13, is, for example, 2 [μm] or more and 13 [μm] or less. The source wiring 19 and the portion 13 of the source electrode 11 may be made of the same material.

[0027] As shown in Figure 1B, the gate electrode 21 of the transistor 10 is formed on the upper surface of the semiconductor layer 40 (low-concentration impurity layer 43) in the first region A1 in a plan view. The gate electrode 21 is also connected to gate wiring 29, which is formed adjacent to the source wiring 19 along at least two sides of the outer perimeter of the rectangular first region A1 in a plan view that are parallel to the boundary line 90.

[0028] Although not shown in Figure 2A, the gate electrode 21 consists of a lower layer and an upper layer. The upper layer of the gate electrode 21 is the layer that is joined to the solder during reflow in face-down mounting, and may be composed of a metallic material containing one or more of nickel, titanium, tungsten, and palladium, as an example, though not limited to this. The surface of the upper layer of the gate electrode 21 may be plated with gold or the like.

[0029] The lower portion of the gate electrode 21 may be made of a metallic material including, but not limited to, one or more of aluminum, copper, gold, and silver. The thickness of the gate electrode 21, including the upper and lower portions, is, for example, 2 [μm] to 13 [μm]. The gate wiring 29 and the lower portion of the gate electrode 21 may be made of the same material.

[0030] The schematic cross-sectional view shown in Figure 2B includes the point in the first region A1 where the trench 17 extends in the Y direction and terminates (hereinafter also referred to as the termination point or vicinity of the termination). The second conductor 25 formed inside the trench 17 is connected to the gate wiring 29 at the point where the trench 17 terminates. In Figure 1B, the square marks at both ends of the thick line representing the trench 17 indicate the connection points between the second conductor 25 and the gate wiring 29. Since the gate wiring 29 is connected to the gate electrode 21, the potential of the gate electrode 21 is transmitted to the second conductor 25. For this reason, the second conductor 25 is sometimes also called the gate conductor 25.

[0031] As shown in Figure 2B, the first conductor 15 formed inside the trench 17 is connected to the source wiring 19 at the point where the trench 17 terminates. In Figure 1B, the circular marks at both ends of the thick line representing the trench 17 indicate the connection points between the first conductor 15 and the source wiring 19. Since the source wiring 19 is connected to the source electrode 11, the potential of the source electrode 11 is transmitted to the first conductor 15. For this reason, the first conductor 15 is sometimes also called the source conductor 15.

[0032] As shown in Figure 1B, the surface drain electrode 31 of the transistor 10 is formed in a plan view in the second region A2, on the upper surface of the semiconductor layer 40 (low-concentration impurity layer 43), connected to the drain pull-up region 38. The drain pull-up region 38 is a region formed in a plan view in the second region A2, as shown in Figure 2B, extending from the upper surface of the semiconductor layer 40 (low-concentration impurity layer 43) to a depth that penetrates the low-concentration impurity layer 43 to a part of the semiconductor substrate 42, and is a region that contains a first conductivity type impurity at a third concentration higher than the second concentration.

[0033] As shown in Figure 2B, the surface drain electrode 31 consists of a portion 32 and a portion 33, with portion 32 connected to the drain pull-up region 38 via portion 33. Portion 32 of the surface drain electrode 31 is a layer that is joined to the solder during reflow in face-down mounting, and may be composed of a metallic material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 32 may be plated with gold or the like.

[0034] The portion 33 of the surface drain electrode 31 is a layer connecting the portion 32 and the drain pulling region 38, and may be made of a metallic material including, but not limited to, one or more of aluminum, copper, gold, and silver. The thickness of the surface drain electrode 31, including portions 32 and 33, is, for example, 2 [μm] to 13 [μm].

[0035] With the above configuration of the transistor 10, the semiconductor substrate 42 functions as the drain region of the transistor 10. Furthermore, the metal layer 41 may also function as the drain electrode on the back side of the transistor 10; therefore, in this disclosure, the surface drain electrode 31 is given the modifier "surface" to distinguish it from the metal layer 41.

[0036] Let me explain the boundary line 90 again. As shown in Figure 1B, the boundary line 90 between the first region A1 and the second region A2 can be considered as a virtual line that, in a plan view, traces the midpoint of the distance between the portion 13 of the first source electrode 11 or the portion of the source wiring 19 closest to the second region A2 and the portion 33 of the surface drain electrode 31. Alternatively, the distance itself, although having a finite width, can be considered as the boundary line 90. Even in the case of this distance, it can be recognized as a line with the naked eye or at low magnification. Furthermore, in a plan view, if an EQR (EQUI Potential Ring) is installed on the outer periphery of the first region A1, the portion of this EQR closest to the second region A2 can be considered as the boundary line 90 between the first region A1 and the second region A2.

[0037] As shown in Figure 2A, the semiconductor layer 40 is covered with an interlayer insulating layer 44 having an opening, and a portion 13 of the source electrode 11 is provided through the opening in the interlayer insulating layer 44, which is connected to the source region 14 and the body region 18. The interlayer insulating layer 44 and the portion 13 of the source electrode 11 are covered with a passivation layer 45 having an opening, and a portion 12 is provided through the opening in the passivation layer 45, which is connected to the portion 13 of the source electrode 11.

[0038] Therefore, each of the multiple source pads 111 refers to a region where the source electrode 11 is partially exposed on the surface of the semiconductor device 1, i.e., a terminal portion. Similarly, the gate pad 121 refers to a region where the gate electrode 21 is partially exposed on the surface of the semiconductor device 1, i.e., a terminal portion. Similarly, the drain pad 131 refers to a region where the surface drain electrode 31 is partially exposed on the surface of the semiconductor device 1, i.e., a terminal portion.

[0039] As shown in Figure 1A, in the semiconductor device 1 according to Embodiment 1, a plurality of source pads 111 are arranged in a striped pattern at equal intervals in a direction perpendicular to the boundary line 90 when viewed from above. In a plan view, the plurality of source pads 111 are rectangular ovals with their longitudinal direction parallel to the boundary line 90, and furthermore, the length of each source pad 111 in the longitudinal direction is the length that occupies almost the entire length of the semiconductor device 1 along its long side, excluding the installation margins at both ends. In this disclosure, a rectangular oval refers to a rectangle with semicircular ends.

[0040] In plan view, the gate pad 121 is circular, and in the first region A1, it is positioned so that no other pads are sandwiched between the gate pad 121 and one of the corners of the first region A1 that does not touch the boundary line 90 (the lower left corner in the example of Figure 1A).

[0041] In a plan view, the drain pad 131 is installed in the second region A2. In the example of FIG. 1A, two types, namely a rectangular oval and a circular shape, are formed. The width of the rectangular oval drain pad 131 is equal to the width of the rectangular oval source pad 111, and furthermore, the closest distance between the rectangular oval drain pad 131 and the rectangular oval source pad 111 is set to be equal to the closest distance between the rectangular oval source pads 111. Also, the circular drain pad 131 has the same diameter as the circular gate pad 121. Therefore, as shown in FIG. 1A, the pads of the semiconductor device 1 are arranged in a point-symmetrical relationship with the center of the semiconductor device 1 as the center of symmetry.

[0042] FIG. 2C shows a schematic cross-sectional view near the center where the trench 17 extends in the Y direction in the first region A1. The first conductor 15 formed inside the trench 17 penetrates the intermediate insulating film 26 and the second conductor 25 and is exposed on the upper surface of the semiconductor layer 40 directly below the source pad 111 in the middle of the direction in which the trench 17 extends, and is connected to the portion 13 of the source electrode 11 (hereinafter referred to as the source electrode 13). Therefore, the first conductor 15 has a location where it is directly connected to the source electrode 13 without passing through the source wiring 19. In FIG. 1B, the round mark near the center of the thick line simulating the trench 17 indicates the connection location between the first conductor 15 and the source electrode 13.

[0043] In the semiconductor device 1, for example, assuming the first conductivity type is N-type and the second conductivity type is P-type, the source region 14, the semiconductor substrate 42, the low-concentration impurity layer 43, and the drain pull-up region 38 may be N-type semiconductors, and the body region 18 may be a P-type semiconductor.

[0044] Also, in the semiconductor device 1, for example, assuming the first conductivity type is P-type and the second conductivity type is N-type, the source region 14, the semiconductor substrate 42, the low-concentration impurity layer 43, and the drain pull-up region 38 may be P-type semiconductors, and the body region 18 may be an N-type semiconductor.

[0045] [2. Operation of Vertical MOS Transistor] In the following description, the conduction operation of the semiconductor device 1 will be described for the case where the transistor 10 is a so-called N-channel transistor with the first conductivity type being N-type and the second conductivity type being P-type.

[0046] FIGS. 3A and 3B are a plan schematic view and a perspective schematic view, respectively, of a substantially unit configuration of the transistor 10 repeatedly formed in the X direction and the Y direction of the semiconductor device 1. In FIGS. 3A and 3B, for clarity, the semiconductor substrate 42 on the lower surface side of the semiconductor layer 40, the metal layer 41, and a part of the passivation layer 45, the source electrode 11, and the interlayer insulating layer 44 on the upper surface side of the semiconductor layer 40 are not shown.

[0047] As shown in FIGS. 3A and 3B, the transistor 10 includes a connection portion 18a that electrically connects the body region 18 and the source electrode 11. The connection portion 18a is a region in the body region 18 where the source region 14 is not formed, and contains impurities of the same second conductivity type as the body region 18 and is of the second conductivity type. The source region 14 and the connection portion 18a are alternately and periodically arranged along the Y direction.

[0048] In the semiconductor device 1, when a high voltage is applied to the surface drain electrode 31 and a low voltage is applied to the source electrode 11, and a voltage equal to or higher than the threshold value is applied to the gate electrode 21 with respect to the source electrode 11, a conduction channel is formed in the vicinity of the insulating film 16 in the body region 18. As a result, current flows through the path of the surface drain electrode 31 - drain pull-up region 38 - semiconductor substrate 42 - metal layer 41 - semiconductor substrate 42 - low-concentration impurity layer 43 - conduction channel formed in the body region 18 - source region 14 - source electrode 11, and the semiconductor device 1 becomes conductive. There is a PN junction at the contact surface between the body region 18 and the low-concentration impurity layer 43 in this conduction path, which functions as a body diode.

[0049] [3. Consideration] Hereinafter, the effects exhibited by the semiconductor device 1 according to the first embodiment will be described.

[0050] In the semiconductor device 1, the potential difference between the surface drain electrode 31 and the source electrode 11 of the transistor 10 is called the drain-source voltage, or simply the drain voltage (VDS [V]). Although usually stated in the product specifications, the maximum specified voltage (BVDS [V]) that guarantees the safe operation of the transistor 10 when applied between the drain and source is sometimes referred to in this disclosure as the drain breakdown voltage, or simply the breakdown voltage.

[0051] A PN junction is provided at the boundary between the body region 18 and the low-concentration impurity layer 43, and a depletion layer is formed on either side of the PN junction. In order to increase the drain breakdown voltage, a structure is required in which the depletion layer expands sufficiently when the transistor 10 is off, thereby reducing the electric field strength generated within the depletion layer.

[0052] For example, in order for the depletion layer to expand sufficiently, it is useful to either lower the carrier concentration (increase the resistivity) or increase the thickness of the low-concentration impurity layer 43. However, such measures are undesirable because they increase the conductivity resistance when passing through the low-concentration impurity layer 43.

[0053] In contrast, the transistor 10 according to Embodiment 1 has a structure in which a first conductor 15, to which the potential of the source electrode 11 is transmitted, is embedded in the lower side of the trench 17. Therefore, when the transistor 10 is off, the potential of the first conductor 15 embedded in the lower side of the trench 17 contributes to pushing down the lower end of the depletion layer. As a result, the breakdown voltage of the transistor 10 is improved compared to the case in which the first conductor 15 is not embedded in the trench 17.

[0054] To obtain the effect of improved voltage resistance, it is desirable that the potential of the source electrode 11 be rapidly transmitted along the entire length of the first conductor 15 embedded inside the trench 17. If the number of points where the first conductor 15 connects to the source electrode 11 or source wiring 19 is small compared to the length of the trench 17 in the direction of extension, or if the positions of these connections are excessively biased, the potential of the source electrode 11 may not be rapidly transmitted to the first conductor 15, and the effect of improved voltage resistance may not be stably obtained.

[0055] In contrast, in the transistor 10 according to Embodiment 1, as shown in Figures 1B and 2B, the first conductor 15 is connected to the source wiring 19 at both ends of the trench 17, and as shown in Figure 2C, there is a point where the first conductor 15 is connected to the source electrode 13 directly below the source pad 111 located in the middle of the direction in which the trench 17 extends.

[0056] In a single trench 17, if there are three points where the first conductor 15 is connected to the source electrode 13 or source wiring 19—at both ends of the trench 17 and in between—then the potential can be transmitted over the entire length of the trench 17 in a time sufficient to transmit the potential over a distance shorter than at least half the length of the trench 17. This is equivalent to reducing the source resistance in the Y direction.

[0057] Furthermore, in the transistor 10 according to Embodiment 1, as shown in Figures 1B and 2C, the location where the first conductor 15 is connected to the source electrode 13 is formed directly below the source pad 111. The potential outside the semiconductor device 1 is transmitted via the source pad 111. Therefore, having the location where the first conductor 15 is connected to the source electrode 13 directly below the source pad 111 is desirable for quickly transmitting the potential of the source electrode 11 to the first conductor 15. In the transistor 10 according to Embodiment 1, the potential applied from the source pad 111 is transmitted to the first conductor 15 over the shortest distance. This is equivalent to reducing the source resistance in the Z direction.

[0058] In other words, the transistor 10 according to Embodiment 1 has a structure in which the source resistance in the Z and Y directions is reduced with respect to the first conductor 15 embedded inside the trench 17, thereby stably obtaining the effect of improved breakdown voltage.

[0059] Therefore, the semiconductor device 1 according to this embodiment 1 comprises a semiconductor substrate 42 of a first conductivity type containing impurities of a first conductivity type at a first concentration, a low-concentration impurity layer 43 of a first conductivity type formed in contact with the semiconductor substrate 42 and containing impurities of a first conductivity type at a second concentration lower than the first concentration, a body region 18 of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer 43, a source region 14 of a first conductivity type formed in the body region 18, and a portion of the low-concentration impurity layer 43 extending from the upper surface of the low-concentration impurity layer 43 through the body region 18 to a part of the low-concentration impurity layer 43. A semiconductor device 1 comprising a vertical MOS transistor 10 having a trench 17 formed to a depth of , an insulating film 16 formed on the inner surface of the trench 17, a first conductor 15 formed in contact with the insulating film 16 and embedded in the lower part of the trench 17, a second conductor 25 formed in contact with the insulating film 16 and embedded in the upper part of the trench 17, an intermediate insulating film 26 formed between the first conductor 15 and the second conductor 25, a source electrode 11 formed on the upper surface of the low-concentration impurity layer 43 and in contact with the body region 18 and the source region 14, a source pad 111 on which the source electrode 11 is exposed on the upper surface of the semiconductor device 1, a gate electrode 21 formed on the upper surface of the low-concentration impurity layer 43, a gate pad 129 on which the gate electrode 21 is exposed on the upper surface of the semiconductor device 1, a surface drain electrode 31 formed on the upper surface of the low-concentration impurity layer 43, and a drain pad 131 on which the surface drain electrode 31 is exposed on the upper surface of the semiconductor device 1, wherein in a plan view of the semiconductor device 1, the semiconductor device 1 is rectangular, and the semiconductor device 1 overlaps with each other. The semiconductor device 1 is characterized by having a first region A1 and a second region A2, which are two halves of the area of ​​the semiconductor device 1, with a source pad 111 and a gate pad 121 located in the first region A1, a drain pad 131 located in the second region A2, a first conductor 15 connected to a source electrode 11, a second conductor 25 connected to a gate electrode 21, and the first conductor 15 embedded inside the trench 17 having a location where it is connected to a source electrode 13 directly below the source pad 111.

[0060] As described above, if the point where the first conductor 15 is connected to the source electrode 13 is directly below the source pad 111, the source resistance can be reduced, and the potential can be quickly transmitted to the first conductor 15, thereby achieving a stable improvement in the breakdown voltage of the transistor 10.

[0061] Furthermore, in the semiconductor device 1 according to Embodiment 1, the location where the first conductor 15 embedded inside the trench 17 is connected to the source electrode 13 directly below the source pad 111 may include a position that bisects the trench 17 in the direction in which the trench 17 extends.

[0062] In a plan view, it is effective in shortening the potential transmission distance in the first conductor 15 if the point where the first conductor 15 embedded inside the trench 17 connects to the source electrode 13 includes a position that bisects the trench 17 in its extension direction.

[0063] If the first conductor 15 is connected to the source electrode 13 or source wiring 19 only at both ends of the trench 17, the distance over which the potential is transmitted from both ends of the trench 17 is half the length of the first conductor 15 in the direction in which the trench extends. In contrast, if the first conductor 15 is also connected to the source electrode 13 at a position that bisects the trench 17 in the direction of extension in a plan view, the potential is also transmitted from there toward both ends of the trench 17, so the distance over which the potential is transmitted from each connection point is only 1 / 4. This has the effect of transmitting the potential along the entire length of the first conductor 15 in half the time compared to the case where the first conductor 15 is connected to the source wiring 19 only at both ends of the trench 17.

[0064] Thus, it is preferable for the first conductor 15, embedded inside the trench 17, to be formed such that the point where it connects to the source electrode 13 directly below the source pad 111 is not merely in the middle of the extension direction of the trench 17 in a plan view, but also includes a position that bisects the trench 17 in the extension direction, in order to shorten the potential transmission distance of the first conductor 15.

[0065] Furthermore, the first conductor 15 embedded inside the trench 17 does not necessarily have to be connected to the source wiring 19 at both ends of the trench 17, as long as it can have a point of connection with the source electrode 13 directly below the source pad 111.

[0066] Incidentally, although it has been explained that the source electrode 11 portion 12, the upper layer portion of the gate electrode 21, and the surface drain electrode 31 portion 32 of the semiconductor device 1 according to Embodiment 1 are layers that are joined to solder during reflow in face-down mounting, the semiconductor device 1 may be a chip-size package type that is capable of face-down mounting.

[0067] A chip-size package, also known as a chip-scale package, is a type of semiconductor device that can be mounted at the size of the semiconductor device (chip) itself, without the need for wires or lead frames, or encapsulation with resin material at the time of mounting. The semiconductor device 1 according to Embodiment 1 is a chip-size package type semiconductor device that has a source pad 111, a gate pad 121, and a drain pad 131 on its upper surface, and can be mounted face-down on a mounting substrate via a bonding material such as solder to these pads.

[0068] In order to enable face-down mounting, the semiconductor device 1 according to Embodiment 1 is required to have a region in plan view that pulls the drain of the vertical MOS transistor 10 towards the surface. Therefore, the semiconductor device 1 according to Embodiment 1 has, in plan view, a first region A1 which is one half of the area of ​​the semiconductor device 1, and a second region A2 which is the other half. The first region A1 is provided with a trench 17 and a cell region of the vertical MOS transistor 10 (a region in which a conductive channel is formed and contributes to conductivity), and the second region A2 is provided with a region that pulls the drain of the vertical MOS transistor 10 towards the surface. The trench 17 may be formed only in the first region A1.

[0069] In a plan view of the semiconductor device, the areas of the first region and the second region are not equal. This is because, in order to reduce on-resistance, the area of ​​the first region where the trench is formed must be designed to be larger than the area of ​​the second region where the drain-pulling region is formed. As long as this restriction is observed, the boundary line separating the first region and the second region in a plan view may be set in any way, but it is desirable that it be set in a straight line parallel to the long side of the rectangular semiconductor device in a plan view.

[0070] This is because, in order to minimize mounting defects when mounting semiconductor devices face-down, the shape and arrangement of the pads on the semiconductor device must be as symmetrical as possible within the plane of the semiconductor device, without causing bias or local irregularities. Symmetry in the shape and arrangement of pads means that, in a plan view, the pads are point-symmetric with respect to the center of the semiconductor device as the center of symmetry, or that the pads are line-symmetric with respect to a central line passing through the center of the semiconductor device and parallel to one side of the outer perimeter of the semiconductor device as the axis of symmetry.

[0071] In semiconductor devices, even in a second region that must be installed with a relatively smaller area within the plane, it is necessary to secure enough area to properly form a drain pad. In a semiconductor device that is rectangular in plan view, if there are multiple rectangular pads installed at equal intervals in a striped pattern to maintain symmetry within the plane, it is easiest to divide the first and second regions as shown in Figure 1A, so that the pad at the very edge becomes the drain pad, and the rest become source pads or gate pads. The width and spacing of the pads should be adjusted so that the areas of the first and second regions are distributed as desired, taking into account the desired on-resistance and the size of the semiconductor device itself.

[0072] Therefore, as shown in Figure 1A, it is desirable that the source pad 111 and drain pad 131 be rectangular circles with their longitudinal direction parallel to the boundary line 90, and furthermore, that the source pad 111 and drain pad 131 are rectangular circles of the same width and are arranged so that the distance between the source pad 111 and drain pad 131 is equal to the distance between the source pads 111 themselves.

[0073] Figures 4A and 4B show a modified example of Embodiment 1, where, in a plan view, the boundary line separating the first region and the second region is not a straight line. Here, for transistor 10A according to Modified Example 1, the same reference numerals are used for components similar to those of transistor 10 according to Embodiment 1, assuming they have already been described, and their detailed explanations are omitted. The explanation will focus on the differences from transistor 10.

[0074] In the transistor 10A according to Modification 1, the first region A1, the second region A2, and the boundary line 90 in the transistor 10 according to Embodiment 1 are modified to the first region A1A, the second region A2A, and the boundary line 90A according to Modification 1, respectively.

[0075] Figures 4A and 4B show schematic plan views of a semiconductor device 1A (transistor 10A) according to a modification 1 of Embodiment 1. In Figure 4B, the passivation layer 45 and the interlayer insulating layer 44 are shown as if they were transparent, allowing the underlying structure to be seen through. Also in Figure 4B, pads that would otherwise be invisible are shown with dotted lines for clarity.

[0076] In a plan view, the virtual boundary line 90A between the first region A1A and the second region A2A of the semiconductor device 1A according to Modified Example 1 is not a straight line. However, the first region A1A includes a trench 17 and cell regions for vertical MOS transistors 10A, while the second region A2A includes a region that pulls the drains of vertical MOS transistors 10A towards the surface. Even with such an arrangement, the shape and arrangement of the pads can be adjusted to be as symmetrical as possible, and there is no impediment to obtaining the effects of this disclosure.

[0077] Now, regarding the effects of the semiconductor device 1 according to Embodiment 1, we will continue our explanation using the example shown in Figures 1A and 1B, where, in a plan view, the boundary line 90 between the first region A1 and the second region A2 is a straight line parallel to the long side direction of the rectangular semiconductor device 1.

[0078] As shown in Figure 1B, in a plan view of the semiconductor device 1, it is desirable that the trenches 17 are formed extending in a direction perpendicular to the boundary line 90. In other words, in a plan view of the semiconductor device 1, it is desirable that the longitudinal direction of the source pad 111 and the direction in which the trenches 17 extend are perpendicular to each other. By arranging the longitudinal direction of the source pad 111 and the direction in which the trenches 17 extend to be perpendicular to each other, it becomes possible to provide a relatively larger number of trenches 17 where the first conductor 15 embedded inside the trenches 17 is connected to the source electrode 13 directly below the source pad 111.

[0079] In a plan view of the semiconductor device 1, if the longitudinal direction of the source pads 111 and the direction in which the trenches 17 extend are parallel, then the first conductor 15 embedded inside the trenches 17 formed between the source pads 111 in a striped pattern may be connected to the source electrode 13 on the upper surface of the semiconductor layer 40, but the connection point cannot be directly below the source pads 111.

[0080] Thus, in the semiconductor device 1, it is preferable that the trench 17 is formed extending in a direction perpendicular to the boundary line 90 in order to transmit the potential applied from the source pad 111 to the first conductor 15 over the shortest distance and to stably obtain the effect of improving withstand voltage.

[0081] In the semiconductor device 1 according to Embodiment 1, as shown in Figures 1A and 1B, in a plan view, it is preferable that the gate pad 121 is installed such that no other pads are sandwiched between the gate pad 121 and one of the corners of the first region A1 that does not come into contact with the boundary line 90. The area where the gate pad 121 is installed, that is, where the gate electrode 21 is installed, is not a cell region (a region where a conductive channel is formed and contributes to conductivity), so it is preferable to install it as close to the edge of the first region A1 as possible.

[0082] Furthermore, as shown in Figure 1B, in a plan view, the source wiring 19 connected to the source electrode 11 is installed along two sides parallel to the boundary line 90 on the outer periphery of the first region A1, and the gate wiring 29 connected to the gate electrode 21 is installed along the source wiring 19 so that no other electrodes are sandwiched between the gate wiring 29 and the source wiring 19. When the source wiring 19 and the gate wiring 29 are formed in the above arrangement, the trench 17 extending in a direction perpendicular to the boundary line 90 can connect the first conductor 15 embedded inside the trench 17 to the source wiring 19 at the end of the direction in which the trench 17 extends, and connect the second conductor 25 embedded inside the trench 17 to the gate wiring 29 at both ends of the direction in which the trench 17 extends.

[0083] The connection between the gate wiring 29 and the second conductor 25 is particularly important. This is because, in the semiconductor device 1 according to Embodiment 1, the first conductor 15 embedded inside the trench 17 penetrates the intermediate insulating film 26 and the first conductor 15 directly below the source pad 111, is exposed on the upper surface of the semiconductor layer 40, and a point is formed where it is connected to the source electrode 13. In the trench 17, the second conductor 25 is interrupted in the direction in which the trench 17 extends, so at both ends in the direction in which the trench 17 extends, the second conductor 25 embedded inside the trench 17 needs to be connected to the gate wiring 29.

[0084] Figure 5 shows a schematic plan view of semiconductor device 1B (transistor 10B), which is a modified example 2 of semiconductor device 1 according to Embodiment 1.

[0085] Here, regarding the transistor 10B according to the modified example 2, the same reference numerals are used for components similar to those of the transistor 10 according to embodiment 1, as they have already been described, and their detailed explanations are omitted. The explanation will focus on the differences from transistor 10.

[0086] In the transistor 10B according to Modification 2, the source wiring 19, gate wiring 29, and trench 17 in the transistor 10 according to Embodiment 1 are replaced with source wiring 19B, gate wiring 29B, and trench 17B according to Modification 2, respectively.

[0087] As shown in Figure 5, in a plan view of the semiconductor device 1B, the trench 17B is formed extending in a direction parallel to the boundary line 90. In other words, in a plan view of the semiconductor device 1B, the longitudinal direction of the source pad 111 and the direction in which the trench 17B extends are parallel. Note that, according to the definition in this disclosure, the direction in which the trench 17B extends is the Y direction, so the coordinate system in Figure 5 is different from that in Figure 1B or Figure 4B.

[0088] Furthermore, in a plan view of the semiconductor device 1B, the source wiring 19B connected to the source electrode 11 is installed along two sides perpendicular to the boundary line 90 on the outer periphery of the first region A1, and the gate wiring 29B connected to the gate electrode 21 is installed along the source wiring 19B so that no other electrodes are sandwiched between the gate wiring 29B and the source wiring 19B. In addition, at the end of the trench 17B in the direction in which it extends, the first conductor 15 embedded inside the trench 17B is connected to the source wiring 19B, and at both ends of the trench 17B in the direction in which it extends, the second conductor 25 embedded inside the trench 17B is connected to the gate wiring 29B.

[0089] Compared to the semiconductor device 1 according to Embodiment 1, in semiconductor device 1B, where the longitudinal direction of the source pad 111 and the direction in which the trench 17B extends are parallel in a plan view, it is relatively difficult to stably obtain the effect of improved withstand voltage. This is because, in a plan view of semiconductor device 1B according to Modified Example 2, in the direction in which the source pads 111 are arranged in a striped pattern, the trenches formed between the source pads 111 can connect to the source electrode 13, but they cannot connect to the source electrode 13 directly below the source pad 111.

[0090] However, if the longitudinal direction of the source pad 111 and the direction in which the trench 17B extends are parallel, it becomes possible to maximize the use of the areas where the first region A1 and the second region A2 face each other for conductivity, thereby reducing the on-resistance. This is because it becomes unnecessary to install the source wiring 19 and gate wiring 29 in the first region A1 on the sides where the first region A1 and the second region A2 face each other.

[0091] Up to this point, a semiconductor device according to one aspect of the present disclosure has been described based on Embodiment 1 and its modified examples 1 and 2. However, not all trenches in the first region A1 must have the above-described features. In Figures 1B, 4B, and 5, there may be portions in which trenches are formed that do not cross directly beneath the source pad 111. Furthermore, in such trenches, the first conductor 15 may have a portion that penetrates the intermediate insulating film 26 and the second conductor 25 and is connected to the source electrode 13. Naturally, in that case, the connection portion does not have to be directly beneath the source pad 111.

[0092] In the semiconductor device 1 according to Embodiment 1 (or semiconductor device 1A according to Modification 1 or semiconductor device 1B according to Modification 2), it is sufficient for at least one trench 17 having the characteristics described above to exist in the trenches provided in the first region A1, but it is desirable to have as many trenches 17 having such characteristics as possible.

[0093] (Embodiment 2) Hereinafter, a semiconductor device 1C (transistor 10C) according to Embodiment 2 will be described, which has some configuration changes from the semiconductor device 1 (transistor 10) according to Embodiment 1.

[0094] Here, regarding the transistor 10C according to Embodiment 2, the same reference numerals are used for components similar to those of the transistor 10 according to Embodiment 1, assuming they have already been described, and their detailed explanations are omitted. The explanation will focus on the differences from transistor 10.

[0095] In the transistor 10C according to Embodiment 2, the source electrode 11 (part 13 of the source electrode 11) and gate wiring 29 in the transistor 10 according to Embodiment 1 are replaced with the source electrode 11C (part 13C of the source electrode 11C) and gate wiring 29C according to Embodiment 2.

[0096] [1. Structure of Semiconductor Device] Figures 6A and 6B are schematic plan views showing examples of the structure of semiconductor device 1C (transistor 10C) according to Embodiment 2. Figure 6C is a schematic cross-sectional view when cut along IV-IV in Figure 6A or Figure 6B. In Figures 6A and 6B, the passivation layer 45 and the interlayer insulating layer 44 are shown as if they were transparent, allowing the structure beneath to be seen. Also, pads that would otherwise be invisible are shown with dotted lines for clarity.

[0097] As shown in Figure 6A or Figure 6B, in the semiconductor device 1C according to Embodiment 2, similar to the semiconductor device 1 according to Embodiment 1, a plurality of source pads 111 are arranged in a striped pattern at equal intervals in a direction perpendicular to the boundary line 90 in a plan view. In Figure 6A, similar to the semiconductor device 1 according to Embodiment 1, the plurality of source pads 111 are rectangular ovals with their longitudinal direction parallel to the boundary line 90 in a plan view, and the length of each source pad 111 in the longitudinal direction occupies almost the entire length of the semiconductor device 1, excluding the installation margins at both ends along the long side. In Figure 6B, the plurality of source pads 111 are rectangular ovals with their longitudinal direction parallel to the boundary line 90 in a plan view, but the length of each source pad 111 in the longitudinal direction is relatively short, and they are arranged so that there is a place in the center of the long side of the semiconductor device 1 where no pads are installed.

[0098] As can be seen in both Figures 6A and 6B, in the semiconductor device 1C according to Embodiment 2, the gate wiring 29C extends in a direction parallel to the boundary line 90 between the source pads 111. Since the portion 13C of the source electrode 11C is arranged so as not to overlap with the gate wiring 29C, the portion 13C of the source electrode 11C and the gate wiring 29C are arranged opposite each other in a comb-like manner.

[0099] As schematically shown by the thick lines in Figure 6A or Figure 6B, in a plan view, the trench 17 extends in a direction perpendicular to the boundary line 90, and within the trench 17, there are not only places where the first conductor 15 is connected to the source wiring 19 at its termination, but also places where the first conductor 15 is connected to the source electrode 13C directly beneath each of the multiple source pads 111. Figure 6C is a schematic cross-sectional view of such a trench 17.

[0100] As shown in Figure 6A or Figure 6B and Figure 6C, the second conductor 25 embedded inside the trench 17 is connected to the gate wiring 29C at both ends of the trench 17 in a plan view, as well as to the gate wiring 29C that extends between the source pads 111 in a plan view.

[0101] [2. Discussion] The following describes the effects of the semiconductor device 1C (transistor 10C) according to Embodiment 2.

[0102] In semiconductor device 1C (transistor 10C), as shown in Figure 6C, a trench 17 forms a connection point between the first conductor 15 and the source electrode 13C directly beneath each of the multiple source pads 111. In the example in Figure 6C, since one trench 17 extends across directly beneath three source pads 111, the first conductor 15 is connected to the source wiring 19 or source electrode 13C at a total of five points: both ends and directly beneath the three source pads 111. Therefore, the potential can be transmitted along the entire length of the first conductor 15 in the time it takes for the potential to be transmitted over approximately 1 / 6 of the length of the trench 17. In comparison, this has the effect of transmitting the potential along the entire length of the first conductor 15 in 1 / 3 of the time compared to the case where the first conductor 15 is connected to the source wiring 19 only at both ends of the trench 17.

[0103] Furthermore, in the transistor 10C according to Embodiment 2, as shown in Figure 6A or 6B and Figure 6C, a location where the first conductor 15 is connected to the source electrode 13C is formed directly below the source pad 111 along the trench 17. Having a location where the first conductor 15 is connected directly below the source pad 111 is desirable in order to stably obtain the effect of improved breakdown voltage. In the transistor 10C according to Embodiment 2, the potential applied from the source pad 111 is transmitted to the first conductor 15 over the shortest distance, so the effect of improved breakdown voltage can be stably obtained.

[0104] However, if the first conductor 15 embedded inside the trench 17 is connected to the source electrode 13C at a location other than both ends of the trench 17, it will sever the second conductor 25 embedded inside the same trench 17. However, in the transistor 10C according to Embodiment 2, as shown in Figure 6A or Figure 6B, in a plan view, the gate wiring 29C extends between the source pads 111 parallel to the boundary line 90, and further, as shown in Figure 6C, it is connected to the second conductor 25. Therefore, no floating portion is created in the second conductor 25, and the potential of the gate electrode 21 is transmitted to the second conductor 25 embedded inside the trench 17 along its entire length in the direction in which the trench 17 extends.

[0105] As described above, in the semiconductor device 1C (transistor 10C) according to Embodiment 2, there are multiple source pads 111, and in a plan view, the multiple source pads 111 are arranged in a striped pattern at equal intervals, the trench 17 has multiple source pads 111 directly above it along the direction in which the trench 17 extends, and the first conductor 15 embedded inside the trench 17 may have a point where it is connected to the source electrode 13C directly below each of the multiple source pads 111.

[0106] Furthermore, the first conductor 15 embedded inside the trench 17 does not necessarily have to be connected to the source wiring 19 at both ends of the trench 17, as long as it has a point where it is connected to the source electrode 13C directly below the multiple source pads 111.

[0107] Furthermore, in a plan view, the gate pad 121 is positioned such that no other pads are sandwiched between it and one of the corners of the first region A1 that does not touch the boundary line 90 (the lower left corner in the example of Figure 6A). The source wiring 19, which connects to the source electrode 11C, is positioned along two sides of the outer periphery of the first region A1 that are parallel to the boundary line 90. The gate wiring 29C, which connects to the gate electrode 21, is positioned such that no other pads are sandwiched between the gate wiring 29C and the source wiring 19. The gate wiring 29C is installed along the source wiring 19 so that the poles are not pinched, and it is installed extending between the source pads 111 in a direction parallel to the boundary line 90. The second conductor 25 embedded inside the trench 17 connects to the gate wiring 29C at both ends in the direction in which the trench 17 extends and between the source pads 111, and the first conductor 15 embedded inside the trench 17 connects to the source wiring 19 at the end of the trench 17 in the direction in which it extends.

[0108] With the structure described above, the first conductor 15 can have connections with the source electrode 13C not only at the end of the trench 17, but also directly below the multiple source pads 111. This allows the potential of the source electrode 13C to be rapidly transmitted to the first conductor 15 along the entire length of the trench 17 in the direction in which it extends, and the effect of improving the breakdown voltage can be stably obtained. Furthermore, it is possible to prevent the second conductor 25 from becoming floating, so that the potential of the gate electrode 21 can be transmitted to the second conductor 25 along almost the entire length of the trench 17 in the direction in which it extends.

[0109] In this case, the semiconductor device 1C (transistor 10C) according to Embodiment 2 does not necessarily have to have all of the trenches in the first region A1 possess the above characteristics. In Figure 6A or Figure 6B, there may be portions in which trenches are formed that do not cross directly beneath the source pad 111. Furthermore, in such trenches, the first conductor 15 may penetrate the intermediate insulating film 26 and the second conductor 25 to reach the upper surface of the semiconductor layer 40 and have a portion where it is connected to the source electrode 13C. Naturally, in that case, the connection portion does not have to be directly beneath the source pad 111.

[0110] Furthermore, there may be a trench that extends across directly beneath multiple source pads 111, and in such a trench, there may not be a point where the first conductor 15 is connected to the source electrode 13C directly beneath each of the multiple source pads 111. For example, there may be a trench that extends across directly beneath three source pads 111, and in only one of those points, there may be a point where the first conductor 15 is connected to the source electrode 13C directly beneath one of the source pads 111.

[0111] In the semiconductor device 1C according to Embodiment 2, it is sufficient for at least one trench 17 having the characteristics described above to exist in the first region A1, but it is desirable to have as many trenches 17 having such characteristics as possible. In the example shown in Figure 6B, there is a region in the center of the long side direction of the semiconductor device 1C in a plan view where no pads are formed. In this part, it is not possible to form a trench 17 having the characteristics of the present disclosure, so the effect of improved withstand voltage is relatively reduced compared to the example shown in Figure 6A, with an increase in the number of trenches where stable improvement cannot be obtained. However, in the example shown in Figure 6B, it is possible to avoid the source pad 111 and drain pad 131 becoming unnecessarily long in the long side direction of the semiconductor device 1C, so the effect of reducing mounting defects such as solder formation defects during face-down mounting can be enjoyed.

[0112] Although a semiconductor device according to one aspect of the present disclosure has been described above based on Embodiments 1 and 2 and Modifications 1 and 2, the present disclosure is not limited to these embodiments and modifications. Without departing from the spirit of the present disclosure, various modifications that a person skilled in the art could conceive of these embodiments, or forms constructed by combining components from different embodiments and modifications, may also be included within the scope of one or more aspects of the present disclosure.

[0113] The semiconductor device equipped with a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path.

[0114] 1, 1A, 1B, 1C Semiconductor device 10, 10A, 10B, 10C Transistor, vertical MOS transistor 11, 11C Source electrode 12 Part 13, 13C Part, source electrode 14 Source region 15 First conductor, source conductor 16 Insulating film 17, 17B Trench 18 Body region 18a Connection region 19, 19B, 19C Source wiring 21 Gate electrode 25 Second conductor, gate conductor 26 Intermediate insulating film 29, 29B, 29C Gate wiring 31 Surface drain electrode 32, 33 Part 38 Drain pull-up region 40 Semiconductor layer 41 Metal layer 42 Semiconductor substrate 43 Low-concentration impurity layer 44 Interlayer insulating layer 45 Passivation layer 90, 90A Boundary line 111 Source pad 121 Gate pad 131 Drain pad A1, A1A: First region; A2, A2A: Second region

Claims

1. A semiconductor device including a vertical MOS transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first conductivity type at a first concentration; a low-concentration impurity layer of the first conductivity type formed in contact with the semiconductor substrate and containing an impurity of the first conductivity type at a second concentration lower than the first concentration; a body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer; a source region of the first conductivity type formed in the body region; a trench formed from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and to a part of the low-concentration impurity layer; an insulating film formed on the inner surface of the trench; a first conductor formed in contact with the insulating film and embedded on the lower side inside the trench; a second conductor formed in contact with the insulating film and embedded on the upper side inside the trench; an intermediate insulating film formed between the first conductor and the second conductor; a source electrode formed on the upper surface of the low-concentration impurity layer and in contact with the body region and the source region; and a source pad on which the source electrode is exposed on the upper surface of the semiconductor device. A semiconductor device comprising: a gate electrode formed on the upper surface of the low-concentration impurity layer; a gate pad on which the gate electrode is exposed on the upper surface of the semiconductor device; a surface drain electrode formed on the upper surface of the low-concentration impurity layer; and a drain pad on which the surface drain electrode is exposed on the upper surface of the semiconductor device, wherein the first conductor is connected to the source electrode, the second conductor is connected to the gate electrode, the first conductor embedded in the trench has a portion where it is connected to the source electrode directly below the source pad, in a plan view of the semiconductor device, the semiconductor device is rectangular, the semiconductor device has a first region which is one half of the area of ​​the semiconductor device and a second region which is the other half, the source pad and the gate pad are located in the first region, and the drain pad is located in the second region.

2. The semiconductor device is a chip-size package type that can be mounted face down, and in the plan view, the trench is formed in the first region, according to claim 1.

3. The semiconductor device according to claim 2, wherein, in the plan view, the location where the first conductor embedded inside the trench is connected to the source electrode directly below the source pad includes a position that bisects the trench in the extension direction.

4. The semiconductor device according to claim 2, wherein, in the plan view, the boundary line between the first region and the second region is a straight line, the source pad is a rectangular circle with its longitudinal direction parallel to the boundary line, and the trench extends in a direction perpendicular to the boundary line.

5. The semiconductor device according to claim 4, wherein, in the plan view, the gate pad is installed such that no other pads are sandwiched between the gate pad and one of the corners of the first region that does not touch the boundary line; a source wiring connected to the source electrode is installed along two sides of the outer periphery of the first region that are parallel to the boundary line; a gate wiring connected to the gate electrode is installed along the source wiring such that no other electrodes are sandwiched between the gate wiring and the source wiring; at the end of the trench in the direction of extension, the first conductor embedded inside the trench is connected to the source wiring; and at the end of the trench in the direction of extension, the second conductor embedded inside the trench is connected to the gate wiring.

6. The semiconductor device according to claim 2, wherein, in the plan view, the boundary line between the first region and the second region is a straight line, the source pad is a rectangular circle with its longitudinal direction parallel to the boundary line, and the trench extends in a direction parallel to the boundary line.

7. In the plan view, the gate pad is installed such that no other pads are sandwiched between the gate pad and one of the corners of the first region that does not touch the boundary line; the source wiring connected to the source electrode is installed along two sides of the outer periphery of the first region that are perpendicular to the boundary line; the gate wiring connected to the gate electrode is installed along the source wiring such that no other electrodes are sandwiched between the gate wiring and the source wiring; at the end of the trench in the direction of extension, the first conductor embedded inside the trench is connected to the source wiring; and at the end of the trench in the direction of extension, the second conductor embedded inside the trench is connected to the gate wiring.

8. The semiconductor device according to claim 5 or 7, wherein the source pads are plurality, and in a plan view, the plurality of source pads are arranged in a striped pattern at equal intervals, the trench has the plurality of source pads directly above it along the direction in which the trench extends, and the first conductor embedded inside the trench has a point of connection with the source electrode directly below each of the plurality of source pads.

9. The semiconductor device according to claim 8, wherein, in the plan view, the gate wiring is formed extending between the plurality of source pads in a direction parallel to the boundary line, and the second conductor embedded inside the trench is connected to the gate wiring at both ends in the direction of extension of the trench, and is also connected to the gate wiring formed between the plurality of source pads.

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