Use of DC / DC converter field effect transistor in solid state relay circuit

Abstract

A method, and apparatuses are disclosed for use of a field effect transistor (FET) from a DC / DC converter as part of a solid state relay (SSR) circuit. A solid state relay (SSR) includes a first field effect transistor (FET) and a second FET. The first FET is implemented as an ideal diode. The second FET is included in a DC / DC converter circuit. The first FET and the second FET are in electrical communication with one another. A battery management system comprising the SSR and a battery comprising the SSR are also disclosed.

Description

[0001] USE OF DC / DC CONVERTER FIELD EFFECT TRANSISTOR IN SOLID STATE RELAY CIRCUIT

[0002] TECHNICAL FIELD

[0003] This disclosure relates to a power circuits, and in particular to method and system for use of a field effect transistor (FET) from a DC / DC converter as part of a solid state relay (SSR) circuit.

[0004] BACKGROUND

[0005] Solid state relay (SSR) circuits are used in many applications, including, for example, in ultracapacitor batteries to provide both protection and to facilitate operation of the battery in buck and boost modes. These SSR circuits are typically provided separate and apart from other circuits and modules that form the electronics of the system, such as DC / DC converter circuits. FIG. 1 is a schematic diagram of a typical SSR 2. As shown, SSR 2 includes two field effect transistors (FET) 4a and 4b (referred to collectively as FET 4). In the most basic sense, FETs 4 are activated by applying a predetermined voltage to the gates (G) at connector 6. This allows current to flow bidirectionally through the source (S) - drain (D) signal path.

[0006] Devices, such as batteries that use DC / DC converters also include FETs in their circuits. Certain FETs in the DC / DC converters are controlled by a DC / DC controller, which, in conjunction with other elements in the DC / DC converter circuit, function to convert an input DC voltage to an output voltage. Some DC / DC converter circuits are bidirectional in that they can operate in a buck mode (high voltage to low voltage) or boost mode (low voltage to high voltage). Such operation in an ultracapacitor-based battery allows the capacitors to be charged or used as a power sink in buck mode by an external voltage supply, e.g., the vehicle voltage bus / supply, and allows the capacitors to be used in boost mode for power supply to the external voltage bus, e.g., the vehicle voltage bus / supply, when there is a need to maintain a particular external bus voltage.

[0007] The result of using an SSR and a DC / DC converter circuit in an application, e.g., an ultracapacitor battery, is that there are multiple FETs, e.g., metal oxide semiconductor FETS (MOSFETs), used to implement the SSR, and also FETs in the same signal path that are part of the DC / DC converter circuit. As such, there are expenses and circuit complexities associated with the use of so many FETs. SUMMARY

[0008] Some embodiments advantageously provide a method and system for a solid state relay such as may be used in a battery comprising one or more energy storage subsystems or components such as capacitors in which a field effect transistor is used in both a DC / DC converter and as part of the SSR circuit.

[0009] According to an aspect of the present disclosure, a solid state relay, SSR, includes a first field effect transistor (FET), the first FET being implemented as an ideal diode, and includes a second FET, the second FET being comprised in a DC / DC converter circuit. The first FET and the second FET are in electrical communication with one another. In accordance with an aspect of this embodiment,

[0010] In some embodiments, the first FET and the second FET are metal oxide field effect transistors, MOSFET. In some embodiments, the first FET is comprised in a protection circuit. In some embodiments, the second FET is controlled by a DC / DC controller and the first FET is controlled by an ideal diode controller.

[0011] According to another aspect of the present disclosure, battery management system, BMS, for controlling operation of a battery having at least one battery cell is provided. The BMS comprises a solid state relay (SSR). The SSR includes a first field effect transistor (FET). The first FET is implemented as an ideal diode. The BMS also comprises a DC / DC converter. The DC / DC converter includes a second FET. The second FET is in electrical communication with the first FET. The second FET is also comprised in the SSR. The BMS further includes a microprocessor control unit (MCU) in which the MCU is configured to cause the SSR to close to allow current to flow between the at least one battery cell and the vehicle bus and cause the SSR to open to prevent current from flowing between the at least one battery cell and a vehicle bus.

[0012] In some embodiments, the first FET is comprised in a protection circuit comprising an ideal diode controller, the DC / DC converter further comprises a DC / DC controller, and the MCU causes the SSR to close by signaling the ideal diode controller to activate the first FET and by signaling the DC / DC controller to allow operation of a DC / DC converter drive signal to the second FET. In some embodiments, the first FET comprises a first gate, and signaling the ideal diode controller to activate the first FET causes the ideal diode controller to provide a drive signal to the first gate of the first FET. In some embodiments, the second FET comprises a second gate, and signaling the signaling the DC / DC controller to allow operation of a DC / DC converter drive signal to the second FET causes the DC / DC controller to provide a drive signal to the second gate of the second FET. In some embodiments, the DC / DC convertor can operate in a boost mode or buck mode at the same time as the second FET is operating in the SSR. In some embodiments, the first FET and the second FET are metal oxide field effect transistors (MOSFET).

[0013] In accordance with another aspect of the present disclosure, a battery is connectable to a vehicle bus in which the battery comprises at least one battery cell. The battery also comprises a battery management system (BMS) in which the BMS is in communication with the at least one battery cell. The BMS comprises a solid state relay (SSR). The SSR includes a first field effect transistor (FET) in which the first FET is implemented as an ideal diode. The BMS also includes a DC / DC converter. The DC / DC converter includes a second FET. The second FET is in electrical communication with the first FET, and the second FET also comprised in the SSR. The BMS also includes a microprocessor control unit (MCU), in which the MCU is configured to cause the SSR to close to allow current to flow between the at least one battery cell and the vehicle bus and cause the SSR to open to prevent current from flowing between the at least one battery cell and a vehicle bus.

[0014] In some embodiments of this aspect, the first FET is comprised in a protection circuit comprising an ideal diode controller, the DC / DC converter further comprises a DC / DC controller, and the MCU causes the SSR to close by signaling the ideal diode controller to activate the first FET and by signaling the DC / DC controller to allow operation of a DC / DC converter drive signal to the second FET. In some embodiments, the first FET comprises a first gate, and signaling the ideal diode controller to activate the first FET causes the ideal diode controller to provide a drive signal to the first gate of the first FET. In some embodiments, the second FET comprises a second gate, and wherein signaling the signaling the DC / DC controller to allow operation of a DC / DC converter drive signal to the second FET causes the DC / DC controller to provide a drive signal to the second gate of the second FET. In some embodiments, the DC / DC convertor can operate in a boost mode or buck mode at the same time as the second FET is operating in the SSR. In some embodiments, the first FET and the second FET are metal oxide field effect transistors (MOSFET). In some embodiments, the at least one battery cell is an ultracapacitor.

[0015] In accordance with yet another aspect of the disclosure, a method of operating a solid state relay (SSR) is provided. The SSR comprises a first field effect transistor (FET) in which the first FET is implemented as an ideal diode. The SSR also comprises a second FET. The second FET is comprised in a DC / DC converter circuit. The first FET and the second FET are in electrical communication with one another. The method includes one or both: operating in an active mode by causing the SSR to close to allow current to flow between at least one battery cell and a vehicle bus, and operating in a protection mode by causing the SSR to open to prevent current from flowing between the at least one battery cell and the vehicle bus.

[0016] In some embodiments, causing the SSR to close comprises activating the first FET and allowing operation of a DC / DC converter drive signal to the second FET. In some embodiment, causing the SSR to open comprises deactivating the first FET and inhibiting operation of a DC / DC converter drive signal to the second FET. In some embodiments, the at least one battery cell is an ultracapacitor.

[0017] BRIEF DESCRIPTION OF THE DRAWINGS

[0018] A more complete understanding of embodiments described herein, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

[0019] FIG. 1 is a schematic diagram of an example known solid state relay (SSR);

[0020] FIG. 2 is a block diagram of a system using an SSR constructed in accordance with the principles of the present disclosure;

[0021] FIG. 3 shows an example battery constructed in accordance with the principles of the present disclosure;

[0022] FIG. 4 is a block diagram of an SSR constructed in accordance with the principles of the present disclosure;

[0023] FIG. 5 is a schematic diagram of a DC / DC converter having a field effect transistor (FET) used in the SSR circuit according to some embodiments of the present disclosure;

[0024] FIG. 6 is a schematic diagram of protection circuit having a field effect transistor (FET) used in the SSR circuit according to some embodiments of the present disclosure; and

[0025] FIG. 7 is a block diagram of a microcontroller unit (MCU) according to some embodiments of the present disclosure; and

[0026] FIG. 8 is a flowchart of an example method of SSR operation in accordance with the present disclosure. DETAILED DESCRIPTION

[0027] Before describing in detail exemplary embodiments, it is noted that the embodiments reside primarily in combinations of apparatus components and processing steps related to a capacitor battery system. Accordingly, the system and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

[0028] As used herein, relational terms, such as “first” and “second,” “top” and “bottom,” and the like, may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and / or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0030] In embodiments described herein, the joining term, “in communication with” and the like, may be used to indicate electrical or data communication, which may be accomplished by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling or optical signaling, for example. In some other embodiments, “in communication with” indicates the transmission and / or of signaling by the components that are in communication with each other. The signaling may cause one or more components to perform one or more actions based on the signaling. The term “in communication with” may also refer to being in fluid communication, such as where two spaces are in fluid communication with each other. One having ordinary skill in the art will appreciate that multiple components may interoperate, and modifications and variations are possible of achieving the electrical and data communication.

[0031] In some embodiments, the general description elements in the form of “one of A and B” corresponds to A or B. In some embodiments, at least one of A and B corresponds to A, B or AB, or to one or more of A and B. In some embodiments, at least one of A, B and C corresponds to one or more of A, B and C, and / or A, B, C or a combination thereof.

[0032] Referring again to the drawing figures, in which like elements are referred to by like reference numerals, there is shown in FIG. 2 a diagram of a system 10, according to an embodiment, which comprises one or more vehicles 12, e.g., a car, motorcycle, scooter, golf cart, light utility vehicle, etc. The vehicle 12 comprises battery 14 for powering at least one function of vehicle 12. In some embodiments, battery 14 (e.g., ultracapacitor battery) may include one or more energy storage modules / cells. Although an ultracapacitor battery is described herein, the teachings described herein are equally applicable to other battery types such as Lithium-Ion and lead acid batteries that may make use of DC / DC converters. Battery 14 may include one or more batteries such as a first battery 14a (not shown), second battery 14b (not shown), third battery 14c (not shown), fourth battery 14d (not shown), etc., e.g., electrically connected (e.g., in parallel, series, etc.) as part of a battery pack. Although battery 14 is shown in conjunction with a vehicle 12, battery 14 is not limited as such and may be used in conjunction with any other component (e.g., such as to power any other system component). Battery 14 may be connected to the vehicle voltage bus 15 within the vehicle, e.g., a 12 Volt DC supply bus.

[0033] Battery 14 may include battery management system (BMS) 16 that is configured to perform one or more battery management functions described herein. In some embodiments, the BMS 16 may measure / determine certain battery parameters, e.g., resistance (e.g., battery resistance), voltage (e.g., cell voltage), current, state of charge (SoC), a time parameter, a frequency parameter, etc., and transmit / receive data (and / or signals such as control signals) to / from another system / device. BMS 16 may also determine failures of battery components and perform actions such notify other components of system 10. A BMS 16 is configured to include a solid state relay (SSR) 18 that may be configured to perform one or more functions as described herein. BMS 16 may also be referred to herein as, or include, an energy management system (EMS).

[0034] In some embodiments (not shown), BMS 16 may include an EMS and / or be configured to perform EMS functions. In some other embodiments, the EMS may include BMS 16 and / or be configured to perform BMS functions. In some embodiments, the EMS is included in battery 14 and / or may be part of any other component of system 10 (e.g., vehicle 12) or standalone.

[0035] It is contemplated that one or more entities of system 10 are in communication with each other via one or more of wireless communication, power communication, wired communication, fluid communication, etc. For example, vehicle 12, battery 14, and BMS 16 (and / or any other device or server) may communicate with each other directly or indirectly using wireless communication, power communication, wired communication, etc. Further, while it may be assumed in one or more embodiments that there is no data or signal communication between BMS 16 and vehicle 12, the embodiments described herein are equally applicable to vehicles 12 where there are at least some data / signal communications between battery 14, BMS 16 and vehicle 12. Further, although battery 14 and BMS 16 are shown as part of vehicle 12 they may be standalone batteries / units, removably couplable to any component of system 10 such as vehicle 12, etc. In some embodiments, vehicle 12 may include a high voltage battery 19 used to support high voltage applications such as to provide motive power for drive motors, HVAC, and the like, such as may be used in a battery electric vehicle (BEV) or hybrid electric vehicle (HEV).

[0036] FIG. 3 shows an example battery 14 constructed in accordance with the principles of the present disclosure. Battery 14 includes a housing 22 into which one or more battery components may be positioned. The components may be electrically interconnected (not shown in the FIGS), such as via an electrically conductive bus bar system which electrically interconnects the components in an electrically serial, electrically parallel or combination of electrically serial and parallel manner, depending on the intended voltage and current requirements.

[0037] A battery monitoring system (BMS) 16 may be included. BMS 16 may include or be coupled to a connector 24 that allows for a removable external connection any other component of system 10 (e.g., to the vehicle’s data bus, voltage bus, to some other communication device, etc.) and / or internal connection, e.g., any components of battery 14 and / or BMS 16. Connector 24 may be comprised in BMS 16 and / or any other component of system 10. In some embodiments, connector 24 may be configured to removably couple and / or connect (electrically, physically) to another connector. The connector 24 can, in some embodiments, be integrated with the housing 22, such as in a cover 26 of the housing 22 or any other cover. Battery 14 also includes terminals, such as a positive terminal 28a and a negative terminal 28b (collectively referred to as terminals 28) to provide the contact points for electrical connection of the battery 14 (e.g., to power devices and / or the vehicle 12 and / or BMS 16). In some embodiments, terminals 28 are not used and the power and ground signals that would be provided via terminals 28 are integrated as part of connector 24. Battery 14 may also include cover 30 which may be arranged to couple to cover 26. Cover 26 may include one or more cover walls that may (e.g., along with cover 30) define cover space 32. Cover 26 may be arranged to receive BMS 16 in cover space 32 during assembly, e.g., such that BMS 16 is coupled to cover 26 and / or any other components of battery 14. Battery 14 may also have battery internal space 34, which may be defined by housing 22, cover 26, cover 30, etc. In some embodiments, battery internal space 34 may be determined to house a predetermined quantity of battery components such as cells 20, BMS 16, etc. Battery internal space 34 may be also determined to minimize unused space and to maximize the quantity or type of components it contains. Battery internal space 34 may also be arranged to contain additional battery components and to meet or exceed a predetermined internal used volume / space threshold.

[0038] In addition, terminals 28 may be arranged to protrude through housing 22, such as protruding through cover 26 and / or cover 30. Terminals 28 may be electrically connected to the bus bars inside housing 22 and / or directly connected to cells 20 (bus bars and direct connection not shown) and / or connected to BMS 16.

[0039] Further, battery 14 may be arranged to provide many power capacities and physical sizes, and to operate under various parameters and parameter ranges. It is also noted that implementations of battery 14 some can be scaled to provide various capacities. For example, in some embodiments, the power capacity of battery 14 can range from 25 Ah to 75Ah. It is noted, however, that this range is merely an example, and that it is contemplated that embodiments of battery 14 can be arranged to provide less than a 25 Ah capacity or more than a 75Ah capacity. Power capacity scaling can be accomplished, for example, by using higher or lower power capacity cells 20 in the housing 22, and / or by using fewer or more cells 20 in the housing 22. In some embodiments, battery 14 may be incorporated as part of a vehicle where battery power is needed. Other electrical parameters of the battery 14 can be adjusted / accommodated by using cells 20 that may cumulatively have the desired operational characteristics, e.g., current, voltage, charge, charging capacity / rate, discharge rate, etc. Thermal properties can be managed based on cell 20 characteristics, the use of heat sinks and / or thermal energy discharge plates, etc., within or external to the housing 24. Further, BMS 16 may be connected to at least one of the cells such as to determine / measure at least one parameter of battery 14 and / or cells 20. Links 36 couple cells 20 to BMS 16. In some arrangements, links 36 provide an electrical path to charge cells 20 and to use the stored energy in cells 20 for vehicle operation such as to boost the power on the vehicle bus 15. In some embodiments, cells 20 are ultracapacitor cells.

[0040] Referring now to FIG. 4, BMS 16 includes components and functionality for implementing SSR 18 using a protection circuit 38 and a DC / DC converter 40. As shown in FIG. 4, protection circuit 38 includes an ideal diode controller 42 and a protection circuit FET 44. In operation ideal diode controller 42 controls the operation of protection circuit FET 44 to allow or inhibit bidirectional flow of current based on the absence or presence of an activation signal from ideal diode controller 42. A function of ideal diode controller 42 is to cause the protection circuit FET 44 to operate as an “ideal diode” in the protection circuit 38 by controlling the on / off state of the protection circuit FET 44 based on the source to drain differential voltage polarity. In other words, protection circuit FET 44 is implemented as an ideal diode. When in a protection mode, e.g., where protection circuit FET 44 is not activated, ideal diode controller 42 prevents the flow of current from the vehicle bus 15 to the DC / DC converter, and hence the cells 20. When activated, ideal diode controller 42 allows the flow of between the vehicle bus 15 to / from the cells 20. The ideal diode controller 42 is controlled by microcontroller unit (MCU) 46 which sends an enablement, i.e., activation, signal to ideal diode controller 42 when it is desired to activate protection circuit FET 44.

[0041] For example, microcontroller unit 46 can open SSR 18 to inhibit current flow to / from cells 20 and the vehicle bus 15, by instructing ideal diode controller 42 to not activate protection circuit FET 44 and by instructing DC / DC controller 48 to not provide any drive a drive signal such as a pulse width modulated drive signal to the gate of DC / DC converter FET 50, thus preventing the flow of current through both protection circuit FET 44 and DC / DC converter FET 50. Conversely, microcontroller unit 46 can close SSR 18 to allow current flow to / from cells 20 and the vehicle bus 15, by signaling ideal diode controller 42 to activate protection circuit FET 44 and by signaling DC / DC controller 48 to allow operation of the DC / DC converter drive, e.g., pulse width modulated, signal to the gate of DC / DC converter FET 50, thus allowing the flow of current through both protection circuit FET 44 and DC / DC converter FET 50. Thus, “open” as used herein is used in the circuit sense to mean an incomplete electrical circuit that prevents current from flowing, and “closed” as used herein is used in the circuit sense to mean a complete electrical circuit that allows current to flow.

[0042] It is noted that the block diagram of FIG. 4 is a simplified diagram to aid understanding of the invention, and that the representations of protection circuit 38 and DC / DC converter 40 do not contain each and every electronic component, e.g., resistors, capacitors, other semi-conductors, etc., that may be implemented as part of those functional blocks. It is presumed that one of ordinary skill can add those other components needed for operation of protection circuit 38 and DC / DC converter 40 given the other descriptions herein.

[0043] Further, although FIG. 4 shows on a single protection circuit 38 and a single DC / DC converter 40, it is understood that implementation using more than one of either or both of the protection circuit 38 and DC / DC converter 40 is contemplated. Quantities of the protection circuit 38 and DC / DC converter 40 can be adjusted based on design need such as supporting a desired current capacity between cells 20 and the vehicle bus 15. For example, multiple protection circuits 38 can be electrically coupled in an electrical parallel arrangement at the inputs and outputs, to increase current capacity. The same can be done with multiple DC / DC converters 40.

[0044] FIG. 5 is a schematic diagram of a DC / DC converter 40 having a FET 50 used in the SSR 18 circuit. As shown, the gate (G) of DC / DC converter FET 50 is electrically coupled to DC / DC controller 48. This allows DC / DC controller 48 to apply a gate drive signal to initiate conduction of an electrical path from the source (S) to the drain (D) of the DC / DC converter FET 50. The conduction, i.e., activation of the electrical path is modulated by DC / DC controller 48 to, along with other electrical components such as resistors, capacitors and other semi-conductors, result in the desired DC output with respect to the DC / DC conversion function of DC / DC converter 40 as well as the operation of DC / DC converter FET 50 as part of SSR 18, as discussed above.

[0045] FIG. 6 is a block diagram of a protection circuit 38 having a FET 44 used in the SSR 18 circuit. As shown, the gate (G) of protection circuit FET 44 is electrically coupled to ideal diode controller 42. This allows ideal diode controller 42 to apply a gate drive signal to initiate conduction, i.e., activation, of an electrical path from the source (S) to the drain (D) of the protection circuit FET 44.

[0046] Example implementations, in accordance with an embodiment, of MCU 46 discussed in the preceding paragraphs will now be described with reference to FIG. 7. As noted above BMS 16 may include MCU 46 to control operation of the BMS 16, including controlling operation of SSR 18, DC / DC controller 48 and ideal diode controller 42. In one embodiment. MCU 46 has hardware 51 that may include a communication interface 52 that is configured to communicate with one or more elements in BMS 16 and / or system 10 via wired and / or wireless communication. The communication may or may not be or include protocol based communications. The hardware 51 includes processing circuitry 54. The processing circuitry 54 may include a processor 56 and memory 58. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 54 may comprise integrated circuitry for processing and / or control, e.g., one or more processors and / or processor cores and / or FPGAs (Field Programmable Gate Array) and / or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 56 may be configured to access (e.g., write to and / or read from) memory 58, which may include any kind of volatile and / or nonvolatile memory, e.g., cache and / or buffer memory and / or RAM (Random Access Memory) and / or ROM (Read-Only Memory) and / or optical memory and / or EPROM (Erasable Programmable Read-Only Memory). Hardware 51 may also have one or more circuit elements such as resistors, capacitors, inductors, diodes, transistors, ground connections, source elements, sink elements, sensors, flexible printed circuit (FPC), etc. The circuit elements may be arranged in any configuration or connection such as series, parallel, combinations thereof, etc.

[0047] Thus, the MCU 46 may further comprise software 60, which is stored in, for example, memory 58, or stored in external memory (e.g., database, etc.) accessible by the MCU 46. The software 60 may be executable by the processing circuitry 54.

[0048] The processing circuitry 54 may be configured to control any of the methods and / or processes described herein and / or to cause such methods, and / or processes to be performed, e.g., by MCU 46 and / or BMS 16. The processor 56 corresponds to one or more processors 56 for performing MCU 46 functions described herein. The MCU 46 includes memory 58 that is configured to store data, programmatic software code and / or other information described herein. In some embodiments, the software 60 may include instructions that, when executed by the processor 56 and / or processing circuitry 54, causes the processor 56 and / or processing circuitry 54 to perform the processes described herein with respect to MCU 46. For example, the processing circuitry 54 of the MCU 46 may include SSR control unit 62 that is configured to perform any step and / or task and / or process and / or method and / or feature described in the present disclosure associated with the control and operation of SSR 18, e.g., controlling and / or determining one or more parameters, steps, and / or processes associated with the operation of SSR 18 via protection circuit FET 44 and DC / DC converter FET 50. While SSR control unit 62 is illustrated as being part of MCU 46, SSR control unit 62 and associated functions described herein may be implemented in a device separate from MCU 46 such as in another device within BMS 16 or battery 14. Although the disclosure refers to a microcontroller unit, it is understood that other processing devices can be used, including but not limited to a central processing unit (CPU), embedded controller, system on a chip, programmable logic controller (PLC), etc.

[0049] Although FIG. 7 shows one or more “units” such as SSR control unit 62 as being within a respective processor, it is contemplated that these units may be implemented such that a portion of the unit is stored in a corresponding memory within the processing circuitry. In other words, the units may be implemented in hardware, software or in a combination of

[0050] FIG. 8 is a flowchart of an example method of operating an SSR 18. According to one embodiment, the SSR 18 comprises a first field effect transistor (FET) 44, the first FET 44 being implemented as an ideal diode, and SSR 18 comprises a second FET 50, the second FET 50 being comprised in a DC / DC converter circuit 40, the first FET 44 and the second FET 50 being in electrical communication with one another. The method includes one or both operating (Block S100) in an active mode by causing the SSR 18 to close to allow current to flow between at least one battery cell 20 and a vehicle bus 15, and operating (Block S102) in a protection mode by causing the SSR 18 to open to prevent current from flowing between the at least one battery cell 20 and the vehicle bus 15.

[0051] In accordance with one aspect, causing the SSR 18 to close comprises activating the first FET 44 and allowing operation of a DC / DC converter drive signal to the second FET 50. In accordance with another aspect, causing the SSR 18 to open comprises deactivating the first FET 44 and inhibiting operation of a DC / DC converter drive signal to the second FET 50.

[0052] In one aspect a solid state relay (SSR) 18 comprises a first field effect transistor (FET) implemented as an ideal diode and also comprises a second FET. The second FET 50 is comprised in a DC / DC converter circuit 40. The first FET 44 and the second FET 50 are in electrical communication with one another. In some embodiments, the first FET 44 and the second FET 50 are metal oxide field effect transistors, MOSFET. In some embodiments, the first FET 44 is comprised in a protection circuit 38. In some embodiments, the second FET 50 is controlled by a DC / DC controller 48, and wherein the first FET 44 is controlled by an ideal diode controller 42.

[0053] In another aspect, a battery management system (BMS) 16 for controlling operation of a battery having at least one battery cell 20 is provided. The BMS 16 comprises a solid state relay (SSR) 18. The SSR 18 has a first field effect transistor (FET) 44 implemented as an ideal diode. The BMS 16 also includes a DC / DC converter 40. The DC / DC converter 40 includes a second FET 50. The second FET 50 is in electrical communication with the first FET 44, and the second FET 50 is also comprised in the SSR. The BMS 16 also comprises a microprocessor control unit (MCU) 46 in which the MCU 46 is configured to: cause the SSR 18 to close to allow current to flow between the at least one battery cell 20 and the vehicle bus, and cause the SSR 18 to open to prevent current from flowing between the at least one battery cell 20 and a vehicle bus 15.

[0054] In some embodiments, the first FET 44 is comprised in a protection circuit 38 comprising an ideal diode controller 42, the DC / DC converter 40 further comprises a DC / DC controller 48, and the MCU 46 causes the SSR 18 to close by signaling the ideal diode controller 42 to activate the first FET 44 and by signaling the DC / DC controller 48 to allow operation of a DC / DC converter drive signal to the second FET 50. In some embodiments, the first FET 44 comprises a first gate, and wherein signaling the ideal diode controller 42 to activate the first FET 44 causes the ideal diode controller 42 to provide a drive signal to the first gate of the first FET 44. In some embodiments, the second FET 50 comprises a second gate, and signaling the DC / DC controller 48 to allow operation of a DC / DC converter drive signal to the second FET 50 causes the DC / DC controller 48 to provide a drive signal to the second gate of the second FET 50. In some embodiments, the DC / DC converter 40 can operate in a boost mode or buck mode at the same time as the second FET 50 is operating in the SSR 18. In some embodiments, the first FET 44 and the second FET 50 are metal oxide field effect transistors, MOSFET.

[0055] In another aspect, a battery 14 is connectable to a vehicle bus 15. The battery 14 comprises at least one battery cell 20 and a battery management system (BMS) 16. The BMS 16 is in communication with the at least one battery cell 20. The BMS 16 comprises a solid state relay (SSR) 18. The SSR 18 has a first field effect transistor (FET) 44 implemented as an ideal diode. The BMS 16 also includes a DC / DC converter 40. The DC / DC converter 40 comprises a second FET 50. The second FET 50 being in electrical communication with the first FET 44, and the second FET 50 is also comprised in the SSR 18;. The BMS 16 also comprises a microprocessor control unit (MCU) 46 in which the MCU 46 is configured to: cause the SSR 18 to close to allow current to flow between the at least one battery cell 20 and the vehicle bus 15, and cause the SSR 18 to open to prevent current from flowing between the at least one battery cell 20 and a vehicle bus 15.

[0056] In some embodiments, the first FET 44 is comprised in a protection circuit 38 comprising an ideal diode controller 42, the DC / DC converter 40 further comprises a DC / DC controller 48, and the MCU 46 causes the SSR 18 to close by signaling the ideal diode controller 42 to activate the first FET 44 and by signaling the DC / DC controller 48 to allow operation of a DC / DC converter drive signal to the second FET 50. In some embodiments, the first FET 44 comprises a first gate, and signaling the ideal diode controller 42 to activate the first FET 44 causes the ideal diode controller 42 to provide a drive signal to the first gate of the first FET 44. In some embodiments, the second FET 50 comprises a second gate, and signaling the signaling the DC / DC controller 48 to allow operation of a DC / DC converter drive signal to the second FET 50 causes the DC / DC controller 48 to provide a drive signal to the second gate of the second FET 50. In some embodiments, the DC / DC converter 40 can operate in a boost mode or buck mode at the same time as the second FET 50 is operating in the SSR 18. In some embodiments, the first FET 44 and the second FET 50 are metal oxide field effect transistors, MOSFET. In some embodiments, the at least one battery cell 20 is an ultracapacitor.

[0057] The SSR 18 provided herein has a benefit of being implementable in a device that results in fewer FETs than would be required if a separate DC / DC converter and SSR are implemented. For example, by using a stand-alone SSR and stand-alone DC / DC converter requires three FETs in the relevant part of the circuits, two FETs for the stand-alone SSR and another FET in the DC / DC converter circuit. In contrast, the disclosure herein provides structure and methods that provide both the SSR and the DC / DC converter using only two FETs in the relevant parts of circuits. This arrangement saves circuit board real estate, lowers circuit complexity, requires fewer steps to manufacture and reduces the number of parts needed, thus saving money.

[0058] It will be appreciated by persons skilled in the art that the present embodiments are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings without departing from the scope of the following claims.

Claims

Claims:

1. A solid state relay, SSR, (18) comprising: a first field effect transistor, FET, (44) the first FET (44) being implemented as an ideal diode; and a second FET (50), the second FET (50) being comprised in a DC / DC converter circuit (40), the first FET (44) and the second FET (50) being in electrical communication with one another.

2. The SSR (18) of Claim 1, wherein the first FET (44) and the second FET (50) are metal oxide field effect transistors, MOSFET.

3. The SSR (18) of any of Claims 1 and 2, wherein the first FET (44) is comprised in a protection circuit (38).

4. The SSR (18) of any one of Claims 1-3, wherein the second FET (50) is controlled by a DC / DC controller (48), and wherein the first FET (44) is controlled by an ideal diode controller (42).

5. A battery management system, BMS, (16) for controlling operation of a battery having at least one battery cell (20), the BMS (16) comprising: a solid state relay, SSR, (18) the SSR (18) comprising a first field effect transistor, FET, (44) the first FET (44) being implemented as an ideal diode; a DC / DC converter (40), the DC / DC converter (40) comprising a second FET (50), the second FET (50) being in electrical communication with the first FET (44), the second FET (50) also being comprised in the SSR; and a microprocessor control unit, MCU, (46) the MCU (46) being configured to: cause the SSR (18) to close to allow current to flow between the at least one battery cell (20) and the vehicle bus; and cause the SSR (18) to open to prevent current from flowing between the at least one battery cell (20) and a vehicle bus (15).

6. The BMS (16) of Claim 5, wherein the first FET (44) is comprised in a protection circuit (38) comprising an ideal diode controller (42), and wherein the DC / DC converter (40) further comprises a DC / DC controller (48), and wherein the MCU (46) causesthe SSR (18) to close by signaling the ideal diode controller (42) to activate the first FET (44) and by signaling the DC / DC controller (48) to allow operation of a DC / DC converter drive signal to the second FET (50).

7. The BMS (16) of Claim 6, wherein the first FET (44) comprises a first gate, and wherein signaling the ideal diode controller (42) to activate the first FET (44) causes the ideal diode controller (42) to provide a drive signal to the first gate of the first FET (44).

8. The BMS (16) of any one of Claims 6 and 7, wherein the second FET (50) comprises a second gate, and wherein signaling the signaling the DC / DC controller (48) to allow operation of a DC / DC converter drive signal to the second FET (50) causes the DC / DC controller (48) to provide a drive signal to the second gate of the second FET (50).

9. The BMS (16) of any one of Claims 5-8, wherein the DC / DC converter (40) can operate in a boost mode or buck mode at the same time as the second FET (50) is operating in the SSR (18).

10. The BMS (16) of any one of Claims 5-9, wherein the first FET (44) and the second FET (50) are metal oxide field effect transistors, MOSFET.

11. A battery (14) connectable to a vehicle bus (15), the battery (14) comprising: at least one battery cell (20); a battery management system, BMS (16), the BMS (16) being in communication with the at least one battery cell (20), the BMS (16) comprising: a solid state relay, SSR, (18) the SSR (18) comprising a first field effect transistor, FET, (44) the first FET (44) being implemented as an ideal diode; a DC / DC converter (40), the DC / DC converter (40) comprising a second FET (50), the second FET (50) being in electrical communication with the first FET (44), the second FET (50) also being comprised in the SSR (18); and a microprocessor control unit, MCU, (46) the MCU (46) being configured to: cause the SSR (18) to close to allow current to flow between the at least one battery cell (20) and the vehicle bus (15); and cause the SSR (18) to open to prevent current from flowing between the at least one battery cell (20) and a vehicle bus (15).

12. The battery (14) of Claim 11, wherein the first FET (44) is comprised in a protection circuit (38) comprising an ideal diode controller (42), and wherein the DC / DC converter (40) further comprises a DC / DC controller (48), and wherein the MCU (46) causes the SSR (18) to close by signaling the ideal diode controller (42) to activate the first FET (44) and by signaling the DC / DC controller (48) to allow operation of a DC / DC converter drive signal to the second FET (50).

13. The battery (14) of Claim 12, wherein the first FET (44) comprises a first gate, and wherein signaling the ideal diode controller (42) to activate the first FET (44) causes the ideal diode controller (42) to provide a drive signal to the first gate of the first FET (44).

14. The battery (14) of any one of Claims 12 and 13, wherein the second FET (50) comprises a second gate, and wherein signaling the signaling the DC / DC controller (48) to allow operation of a DC / DC converter drive signal to the second FET (50) causes the DC / DC controller (48) to provide a drive signal to the second gate of the second FET (50).

15. The battery (14) of any one of Claims 11-14, wherein the DC / DC converter (40) can operate in a boost mode or buck mode at the same time as the second FET (50) is operating in the SSR (18).

16. The battery (14) of any one of Claims 11-15, wherein the first FET (44) and the second FET (50) are metal oxide field effect transistors, MOSFET.

17. The battery (14) of any one of Claims 11-16, wherein the at least one battery cell (20) is an ultracapacitor.

18. A method of operating a solid state relay, SSR, (18) the SSR (18) comprising a first field effect transistor, FET, the first FET (44) being implemented as an ideal diode and comprising a second FET (50), the second FET (50) being comprised in a DC / DC converter circuit (40), the first FET (44) and the second FET (50) being in electrical communication with one another, the method comprising one or both: operating (S100) in an active mode by causing the SSR (18) to close to allow current to flow between at least one battery cell (20) and a vehicle bus (15); andoperating (S102) in a protection mode by causing the SSR (18) to open to prevent current from flowing between the at least one battery cell (20) and the vehicle bus (15).

19. The method according to Claim 18, wherein causing the SSR (18) to close comprises: activating the first FET (44); and allowing operation of a DC / DC converter drive signal to the second FET (50).

20. The method according to any one of Claims 18 and 19, wherein causing the SSR (18) to open comprises: deactivating the first FET (44); and inhibiting operation of a DC / DC converter drive signal to the second FET (50).

21. The method according to any one of Claims 18-20, wherein the at least one battery cell (20) is an ultracapacitor.

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