Semiconductor devices and manufacturing methods thereof

Abstract

A method for manufacturing a semiconductor device comprises providing a first structure. The first structure comprises a first substrate, a second substrate, and a multi-layer structure. The second substrate is disposed on the first substrate. The multi-layer structure comprises a first spacer layer and a sacrificial layer. The method comprises forming a first opening extending through the multi-layer structure to expose the second substrate. The method comprises forming a semiconductor pillar in the first opening. The method comprises forming a first source / drain region over the semiconductor pillar. The method comprises removing at least a portion of the sacrificial layer to expose at least a portion of the semiconductor pillar. The method comprises forming a gate structure surrounding the semiconductor pillar. The method comprises removing the first substrate. The method comprises removing a portion of the second substrate to form or expose a second source / drain region.

Description

47342.0002 final draft (PCT)20250911SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS THEREOFBACKGROUNDRelated Application

[0001] This application claims priority to U.S. Provisional Patent Application Ser. No. 63 / 693,212, filed on Sep. 11, 2024, entitled “Vertical Transistors and Manufacturing Methods Thereof,” which are incorporated herein by reference in its entirety.Field of the Invention

[0002] The present disclosure relates to semiconductor devices and manufacturing methods thereof. In particular, some embodiments of the present disclosure relate to vertical transistors and manufacturing methods thereof.Description of Related Art

[0003] In field-effect transistors (FETs), the channel length, which substantially corresponds to the gate length, is a critical factor for electrical performance. In conventional planar FETs, FinFETs, and gate- all- around (GAA) structures, the definition of the gate region relies on lithographic patterning in combination with photoresist properties and etching conditions. Due to process variations, the gate length of individual devices may deviate by approximately ±1 nm across billions of transistors formed on a single die. As the device dimensions are further reduced, such deviations become more detrimental to device performance.

[0004] Accordingly, there remains a need in the art for methods and structures capable of achieving enhanced control of the channel length and positional accuracy of the gate structure.SUMMARY

[0005] According to the present disclosure, a method for manufacturing a semiconductor device is provided. The method comprises providing a first structure. The first structure comprises a first substrate, a second substrate, and a multi-layer structure. The second substrate is disposed on the first substrate. The second substrate comprises semiconductor material. The multi-layer structure is in contact with the second substrate. The second substrate is disposed between the first substrate and the multi-layer structure. The multi-layer structure comprises a first spacer layer and a sacrificial layer between the first spacer layer and the second substrate. The method comprises forming a first opening extending through the multi-layer structure to expose the second substrate.47342.0002 final draft (PCT) 20250911 The method comprises forming a semiconductor pillar in the first opening. The method comprises forming a first source / drain region over the semiconductor pillar and the first spacer layer. The method comprises removing at least a portion of the sacrificial layer to expose at least a portion of the semiconductor pillar. The method comprises forming a gate structure surrounding the semiconductor pillar. The gate structure comprises a gate dielectric and a gate electrode. The method comprises removing the first substrate. The method comprises removing a portion of the second substrate to form or expose a second source / drain region.

[0006] According to the present disclosure, a semiconductor device is provided. The semiconductor device comprises a first source / drain region, a semiconductor pillar, a second source / drain region, a gate structure, and a first spacer structure. The semiconductor pillar is vertically stacked on and in contact with the first source / drain region at a first end of the semiconductor pillar. The second source / drain region is vertically stacked on and in contact with the semiconductor pillar at a second end of the semiconductor pillar. The gate structure surrounds the semiconductor pillar. The gate structure comprises a gate dielectric and a gate electrode. The first spacer structure surrounds the semiconductor pillar at the first end of the semiconductor pillar. The first spacer structure is in contact with the semiconductor pillar, and the gate dielectric is deposited on an inner surface of the first spacer structure.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIGS. 1A to IS are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0008] FIGS. 2A to 2B are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0009] FIGS. 3 A to 3B are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0010] FIGS. 4A to 4E are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0011] FIG. 5 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0012] FIG. 6 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0013] FIG. 7 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure.47342.0002 final draft (PCT) 20250911

[0014] FIG. 8 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure.47342.0002 final draft (PCT) 20250911 DETAILED DESCRIPTION OF EMBODIMENTS

[0015] The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is used in conjunction with a detailed description of certain specific embodiments of the technology. Certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be specifically defined as such in this Detailed Description section. Components and achievement of a semiconductor structure or a device, according to the present disclosure may be illustrated in the following drawings and embodiments. However, the size and shape shown on drawings for the semiconductor structure(s) or the device(s) do not limit the features of the present disclosure.

[0016] The phrase “on” used in this application can mean directly on or indirectly on with intervening elements or layers. The spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0017] FIGS. 1A to IS are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0018] As shown in FIG. 1A, a processing substrate is provided. The processing substrate may comprise a first substrate 12 and a second substrate 14 on the first substrate 12. The first structure 10 may further comprise a debonding layer 16 between the first substrate 12 and the second substratel4. In the embodiment shown in FIG. 1A, the first structure 10 further comprises a first dielectric layer 17 between the debonding layer 16 and the second substrate 14.

[0019] The second substrate 14 comprises semiconductor material, such as silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the second substrate 14 comprises single crystalline semiconductor material. The second substrate 14 may be a thin substrate substantially made of semiconductor material. For example, the second substrate 14 may have a thickness in a range from about 5 nm to about 30 pm. In some embodiments, the second substrate 14 may have a thickness in a range from about 5 nm to about 10 pm, about 5 nm to about 5 pm, or from about 5 nm to about 200 nm. In some embodiments, the second substrate 14 may have a thickness in a range from about 5 nm to about 50 pm. These values are merely examples and are not intended to47342.0002 final draft (PCT) 20250911 be limiting. In the present embodiment, the second substrate 14 is doped with first conductivity type of dopants, e.g., p-type dopants, such as boron, aluminum, gallium, indium, the like, or combinations thereof, or n-type dopants, such as phosphorus, arsenic, antimony, bismuth, the like, or combinations thereof. A dopant activation process can be performed.

[0020] In some embodiments, the second substrate 14 may be unpattemed. The second substrate 14 may be doped uniformly across an entire layer. In other words, in some embodiments, no electric devices have been formed yet on the second substrate 14. In the embodiments where the processing substrate is a wafer-level structure, the second substrate 14 may be doped at least uniformly across an entire layer in usable die areas, and no electric devices have been formed yet in the usable die areas. However, embodiments of the present disclosure are not so limited.

[0021] At least a portion of the debonding layer 16 is detachable from the first substrate 12 by applying light or heat to the debonding layer 16. In some embodiments, the debonding layer 16 comprises compound semiconductor, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), aluminium gallium nitride (AlGaN), polymer, such as polyimide, the like, or combination thereof, and the first substrate 12 is light transmittable such that at least a portion of the debonding layer 16 is detachable from the first substrate 12 by exposing the debonding layer 16 to light passing through the first substrate 12. For example, the first substrate 12 may comprise sapphire or silicon carbide (SiC). In some embodiments, the debonding layer 16 comprises single crystalline silicon carbide, single crystalline gallium nitride, single crystalline aluminum nitride (AIN), and / or single crystalline aluminium gallium nitride (AlGaN), and the first substrate 12 comprises single crystalline sapphire or single crystalline silicon carbide. The debonding layer 16 may comprise composition of material the same or different from the first substrate 12. In some embodiments, the debonding layer 16 comprises compound semiconductor which can be epitaxially formed on the first substrate 12, wherein the substrate first substrate 12 is substantially made of single crystalline sapphire or single crystalline silicon carbide. The debonding layer 16 may be or include an epitaxial compound semiconductor layer formed on the first substrate 12. The debonding layer 16 may have a thickness in a range from about 5 nm to about 1 pm. The debonding layer 16 may be in direct contact with the first substrate 12 without material layer therebetween.

[0022] In some embodiments, the debonding layer 16 may comprise polycrystalline silicon carbide, polycrystalline gallium nitride, poly crystalline aluminum nitride (AIN), polycrystalline aluminium gallium nitride (AlGaN), and / or polymer, such as polyimide, the like, or combination thereof, and the first substrate 12 may comprise sapphire, silicon carbide, glass, or any other light transmittable material.47342.0002 final draft (PCT) 20250911

[0023] In some embodiments, a laser beam of applicable wavelength may pass through the first substrate 12 and apply to the debonding layer 16. For example, an excimer laser of a wavelength of 308 nm may be used. In some embodiments, an excimer laser of a wavelength of 248 nm beam may be used. However, embodiments of the present disclosure are not so limited. Laser or light of applicable wavelength and suitable energy density may be used. Applicable wavelength and / or energy density may vary depending on the material of the debonding layer 16, the light transmittance of the first substrate 12 and / or the characteristics of an interface between the debonding layer 16 and the first substrate 12 or an intermediate layer therebetween. The first substrate 12 may be light transmittable with respect to the applicable wavelength to the extent that at least a portion of the debonding layer 16 is detachable from the first substrate 12 by light passing through the first substrate 12.

[0024] In some embodiments, stress at the interface between the first substrate 12 and the debonding layer 16 may be increased by laser, such that the main portion of the debonding layer 16 can be detached from the first substrate 12 substantially from the interface. In some embodiments, a small portion of the debonding layer 16 near the first substrate 12 may undergo chemical change and / or phase transition caused by the laser or applicable light, such that the main portion of the debonding layer 16 can be detached from the first substrate 12. However, embodiments of the present disclosure are not so limited.

[0025] In some embodiments, the debonding layer 16 comprises polymer, such as polyimide and high temperature endurable glue; germanium dioxide; the like, or combination thereof, and at least a portion of the debonding layer 16 is detachable from the first substrate 12 by applying heat to the debonding layer 16. In some embodiments, the heat may cause chemical change and / or phase transition of the debonding layer 16, such that at least a portion of the debonding layer 16, for example, a portion of the debonding layer 16 can be detached from the first substrate 12. In some embodiments, heat may be applied to the debonding layer 16 by heating the processing substrate or heating the first substrate 12 by a hot plate. For example, the debonding layer 16 may be heated to a temperature from about 250 °C to 450 °C. Applicable temperature may vary depending on the material of the debonding layer 16.

[0026] The processing substrate may further comprise a first dielectric layer 17 between the debonding layer 16 and the second substrate 14. The first dielectric layer 17 may comprise silicon oxide, silicon nitride, the like, other applicable material, or combinations thereof. However, embodiments of the present disclosure are not so limited. The first dielectric layer 17 may be in direct contact with the second substrate 14. The first dielectric layer 17 may be in direct contact with the debonding layer 16. In some embodiments, the first dielectric layer 17 may have a47342.0002 final draft (PCT) 20250911 thickness in a range from about 1 nm to about 1 pm, for example, from about 1 nm to about 100 nm. The first dielectric layer 17 may be an unpattemed dielectric material layer without wiring structure(s) therein. In other words, no wiring structures exist between the second substrate 14 and the debonding layer 16. The first dielectric layer 17 may be used to bond the second substrate 14 to the debonding layer 16. However, embodiments of the present disclosure are not so limited.

[0027] As shown in FIG. IB, a first structure 10 is provided. The first structure 10 comprises the first substrate 12, the second substrate 14 on the first substrate 12, and a multi-layer structure 18 in contact with the second substrate 14. The second substrate 14 is disposed between the first substrate 12 and the multi-layer structure 18. In the embodiment shown in FIG. IB, the multi-layer structure 18 comprises a first spacer layer 18a and a sacrificial layer 18c between the first spacer layer 18a and the second substrate 14. The multi-layer structure 18 may further comprise a second spacer layer 18b, and the sacrificial layer 18c is disposed between the first spacer layer 18a and the second spacer layer 18b. In some embodiments, each of the first spacer layer 18a, the second spacer layer 18b, and the sacrificial layer 18c may have a multilayer structure.

[0028] The first spacer layer 18a and the second spacer layer 18b may each comprise material(s) suitable for gate spacer. In some embodiments, the first spacer layer 18a and the second spacer layer 18b comprises silicon nitride. However, embodiments of the present disclosure are not so limited. In some embodiments, the first spacer layer 18a may have a thickness in a range from about 2 nm to about 10 nm. In some embodiments, the second spacer layer 18b may have a thickness in a range from about 2 nm to about 10 nm. These values are merely examples and are not intended to be limiting. In some other embodiments, the second spacer layer 18b may be omitted.

[0029] The sacrificial layer 18c may comprise material having an etch selectivity with respect to the first spacer layer 18a and the second spacer layer 18b, for example, an etch rate of the sacrificial layer 18c may be substantially higher than etch rate of the first spacer layer 18a and the second spacer layer 18b under the same etching condition. In some embodiments, the sacrificial layer 18c comprises silicon dioxide. In some embodiments, the sacrificial layer 18c may be formed by atomic layer deposition (ALD). In some embodiments, the first spacer layer 18a and the second spacer layer 18b may be formed by atomic layer deposition (ALD). However, embodiments of the present disclosure are not so limited. In some embodiments, the sacrificial layer 18c may have a thickness substantially equal to Lg + 2Td, where Lg is a predetermined gate length of the transistor to be formed, and 2Td is twice a predetermined thickness of the gate dielectric to be formed. In47342.0002 final draft (PCT) 20250911 some embodiments, the sacrificial layer 18c may have a thickness in a range from about 5 nm to about 30 nm. These values are merely examples and are not intended to be limiting.

[0030] As shown in FIG. 1C, first openings 18oa and 18ob extending through the multi-layer structure 18 are formed. The first openings 18oa and 18ob are formed exposing the second substrate 14. In some embodiments, the first openings 18oa and 18ob may be formed by reactiveion etching (RIE).

[0031] As shown in FIG. ID, semiconductor pillars 106a and 106b are formed in the first openings 18oa and 18ob. The semiconductor pillars 106a and 106b may be formed on the exposed surface of the second substrate 14 and in contact with the second substrate 14. The semiconductor pillars 106a and 106b may comprise single crystalline semiconductor material. The semiconductor pillars 106a and 106b may comprise intrinsic semiconductor materials or may include dopants of a second conductivity type opposite to the first conductivity type with a concentration less than the second substrate 14. Each of the semiconductor pillars 106a and 106b may have a substantially cylindrical shape, an substantially elliptical cylindrical shape, a substantially square column shape, or a substantially rectangular column shape. In some embodiments, each of the semiconductor pillars 106a and 106b may have a height in a range from about 9 nm to about 50 nm. In some embodiments, each of the semiconductor pillars 106a and 106b may have a diameter in a range from about 3 nm to about 25 nm, wherein the diameter is determined by the diameter of a circular cross-section of a cylindrical shape, the major-axis diameter of an elliptical cross-section of an elliptical cylindrical shape, or a diagonal of a square or rectangular cross-section of a square column shape or a rectangular column shape. These values are merely examples and are not intended to be limiting.

[0032] The semiconductor pillars 106a and 106b may be formed by epitaxially growth. In some embodiments, the semiconductor pillars 106a and 106b are formed by selective epitaxial atomic layer deposition (ALD). In some embodiments, the semiconductor pillars 106a and 106b are formed by selective epitaxial chemical vapor deposition (CVD), for example, low-pressure CVD (LPCVD). In some embodiments, excess portions may be removed by suitable grinding process(es), such as a chemical-mechanical planarization (CMP) process, following the deposition process. By the methods disclosed herein, the height of the semiconductor pillars 106a and 106b can be better controlled. This allows improved control over the electrical characteristics of the device, and variability among devices can be reduced.

[0033] As shown in FIG. IE, first source / drain regions 102a and 102b are formed. The first source / drain regions 102a and 102b may be formed over the semiconductor pillars 106a and 106b47342.0002 final draft (PCT) 20250911 and the first spacer layer 18a. The first source / drain regions 102a and 102b may be formed in contact with the respective semiconductor pillars 106a and 106b. The first source / drain regions 102a and 102b may comprise single crystalline semiconductor material as discussed above. The first source / drain regions 102a and 102b may include dopants of the first conductivity type as discussed above. The first source / drain regions 102a and 102b may be formed by depositing semiconductor material(s) on the respective semiconductor pillars 106a and 106b. The first source / drain regions 102a and 102b may be epitaxially grown on top surfaces of the respective semiconductor pillars 106a and 106b. In some embodiments, the first source / drain regions 102a and 102b may be formed by selective CVD or selective ALD. In some embodiments, annealing process may be performed to diffuse dopants into the respective semiconductor pillars 106a and 106b.

[0034] FIG. IF is a schematic top view of the structure shown in FIG. IE. Referring to FIGS. IE and IF, the first source / drain region 102a is overlapped with the first spacer layer 18a. In other words, when viewed in a vertical direction (i.e., in a direction parallel to a normal vector of the surface of the substrates, as shown in FIG. IF), a projection of the first source / drain region 102a falls on the first spacer layer 18a. The first source / drain region 102a may have a diameter larger than that of the semiconductor pillar 106a. In some embodiments, the first source / drain region 102a may have a portion protruding with respect to the semiconductor pillar 106a, and the protruding portion may be in contact with the first spacer layer 18 a.

[0035] As shown in FIG. 1G, a conformal protective layer 22 is formed on the first source / drain regions 102a and 102b. The conformal protective layer 22 comprises dielectric material, such as silicon nitride. A sacrificial material layer 24 may also be formed on the conformal protective layer 22 filling the gap between the first source / drain region 102a and the first source / drain region 102b. In some embodiments, the sacrificial material layer 24 may comprise poly silicon or other suitable material(s). Openings 20o may be formed extending through the sacrificial material layer 24, the conformal protective layer 22, the first spacer layer 18a, and the sacrificial layer 18b.

[0036] As shown in FIG. 1H, an isolation structure 20 may be formed in the openings 20o. The isolation structure 20 may extend through the sacrificial layer 18b. The isolation structure 20 may comprise silicon dioxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, forming the isolation structure 20 may include first depositing a conformal etch stop layer (e.g., a silicon nitride layer) in the openings 20o.

[0037] As shown in FIG. II and 1J, at least a portion of the sacrificial layer 18b is removed and at least a portion of the semiconductor pillar 106a is exposed by removing the sacrificial layer 18b. In some embodiments, removing the sacrificial layer 18b comprises removing a portion of the first47342.0002 final draft (PCT) 20250911 spacer layer 18a to expose the sacrificial layer 18b. Openings (or trenches) 30oa and 30ob may be formed by removing a portion of the first spacer layer 18a as well as the sacrificial material layer 24 and the conformal protective layer 22.

[0038] Then, the at least a portion of the sacrificial layer 18b is removed by isotropic etching process. Suitable etchant, such as dilute HF (e.g., solvent having a weight ratio of water to hydrogen fluoride at about 100:1), may be used. Suitable solvent(s) and / or etching conditions can be selected depending on the materials of the sacrificial layer 18b, the first spacer layer 18a, the second spacer layer 18b, and / or the semiconductor pillars 106a and 106b.

[0039] As shown in FIG. 1J, an inner surface of the first spacer layer 18a (the surface oriented downward in the view depicted in the FIG. 1 J) is exposed after removing the at least a portion of the sacrificial layer 18b. In the embodiment shown in FIG. 1J, an inner surface of the second spacer layer 18b (the surface oriented upward in the view depicted in the FIG. 1J) is exposed after removing the at least a portion of the sacrificial layer 18b. As such, second openings 32oa and 32ob are formed. In some embodiments, the second opening 32oa exposes the semiconductor pillar 106a, the first spacer layer 18a, the second spacer layer 18b, and the isolation structure 20.

[0040] As shown in FIG. IK, gate dielectrics 108a and 108b are formed. The gate dielectric 108a is formed surrounding the semiconductor pillar 106a, and the gate dielectric 108b is formed surrounding the semiconductor pillar 106b. Specifically, the gate dielectrics 108a and 108b are formed on the respective walls of the second openings 32oa and 32ob.

[0041] As shown in FIG. IL and IM, conductive gate materials 109 are deposited surrounding the semiconductor pillars 106a and 106b. Specifically, the conductive gate materials 109 are deposited in the second openings 32oa and 32ob. In some embodiments, the excess conductive gate materials may be removed through suitable process, such as CMP process. In some embodiments, at least a portion of the conformal protective layer 22 may be exposed after a CMP process. The sacrificial material layer 24 exposed after the CMP process may be removed. As such, the gate electrodes 110a and 110b may be formed.

[0042] By the processes shown in FIGS. II to IM, gate structures 107a and 107b can be formed. The gate structure 107a surrounds the semiconductor pillar 106a and comprises the gate dielectric 108a and the gate electrode 110a. The gate structure 107b surrounds the semiconductor pillar 106b and comprises the gate dielectric 108b and the gate electrode 110b. By methods disclosed herein, the gate length of the semiconductor device can be better controlled, more accurate positioning of the gate structure may be achieved, and variations among the elements may be reduced.47342.0002 final draft (PCT) 20250911

[0043] As shown in FIG. IN, first contacts 116a and 116b are formed on the first source / drain regions 102a and 102b, respectively. First interconnect structures 120 can also be formed. In the present embodiment, the first contacts 116a and 116b and the first interconnect structures 120 are formed before removing the first substrate 12.

[0044] As shown in FIG. 10 and IP, the structure shown in FIG. IN is flipped and bonded to a third substrate 50. Then, at least a portion of the debonding layer 16 is detached from the first substrate 12 by applying light or heat to the debonding layer 16. After the detaching process, a remained portion 16’ of the debonding layer may be left on the second substrate 14. As such, the first substrate 12 is removed. The remained portion of the debonding layer 16’ and the first dielectric layer 17 are then removed to expose the second substrate 14. The entire contents of PCT Applications PCT / US2025 / 022256 and PCT / US2025 / 026714 are incorporated herein by reference.

[0045] As shown in FIG. IQ, a portion of the second substrate 14 is removed to form second source / drain regions 104a and 104b. Suitable etching process may be performed to remove a portion of the second substrate 14 and leaving the second source / drain regions 104a and 104b. The second source / drain region 104a may have a diameter larger than that of the semiconductor pillar 106a.

[0046] As shown in FIG. 1R, second contacts 118a and 118b are formed on the second source / drain regions 104a and 104b, respectively. Second interconnect structures 130 can also be formed. In the present embodiment, the second contacts 118a and 118b and the second interconnect structures 130 are formed after forming the second source / drain region 104a.

[0047] FIG. IS illustrates a schematic cross section view of the structure shown in FIG. 1R. Referring to FIGS. 1R and IS, a semiconductor devices 100a and 100b are provided. The semiconductor devices 100a and 100b may each be a vertical field-effect transistor. The semiconductor device 100a comprises a first source / drain region 102a, a semiconductor pillar 106a, a second source / drain region 104a, a gate structure 107a and a first spacer structure 112a. In the present embodiment, the semiconductor device further comprises a second spacer structure 114a.

[0048] The first source / drain region 102a may comprise single crystalline semiconductor material as discussed above. The first source / drain region 102a may comprise dopants of a first conductivity type as discussed above. The first source / drain region 102a may be formed by depositing a semiconductor material on the semiconductor pillar 106 as discussed above with respect to FIG. IE. As shown in FIG. 1R, the first source / drain region 102a may be overlapped with the first spacer structure 112a. In some embodiments, the first source / drain region 102a may47342.0002 final draft (PCT) 20250911 be in contact with the first spacer structure 112a at an outer surface (the surface oriented upward in the view depicted in the FIG. 1R) of the first spacer structure 112a.

[0049] The semiconductor pillar 106a is vertically stacked on and in contact with the first source / drain region 102a at a first end 1061a of the semiconductor pillar 106a. The term “vertically stacked” is used to indicate the stacking relationship of elements in a direction perpendicular to the substrate surface (i.e., substantially parallel to a normal vector of the substrate surface) and does not indicate a formation sequence in the manufacturing process. In practice, the structure described herein may be inverted upside down due to attachment to different substrate, or rotated together with the attached substrate, and still falls within the scope of the present disclosure.

[0050] The semiconductor pillar 106a may comprise single crystalline semiconductor material as discussed above. The semiconductor pillar 106a may comprise intrinsic semiconductor material or may comprise dopants of a second conductivity type as discussed above. The semiconductor pillar 106a may have dopant concentration smaller than that of the first source / drain region 102a.

[0051] The semiconductor pillar 106a may be formed by deposition such as selective CVD and / or selective ALD on the surface of the second source / drain region 104a as discussed above with respect to FIGS. 1C and ID. Specifically, the semiconductor pillar 106a is formed by depositing semiconductor material and filling a third opening 1122a extending through the first spacer structure 112a and a fourth opening 1142a extending through the second spacer structure 114a. As a result, the first spacer structure 112a surrounds the semiconductor pillar 106a at the first end 1061a of the semiconductor pillar 106a. The first spacer structure 112a may be in contact with the semiconductor pillar 106a. Similarly, the second spacer structure 114a surrounds the semiconductor pillar 106a at the second end 1062a of the semiconductor pillar 106a. The second spacer structure 114a may be in contact with the semiconductor pillar 106a.

[0052] The semiconductor pillar 106a may have a substantially cylindrical shape, a substantially elliptical cylindrical shape, a substantially square column shape, or a substantially rectangular column shape. However, embodiments of the present disclosure are not so limited.

[0053] The second source / drain region 104a is vertically stacked on and in contact with the semiconductor pillar 106a at a second end 1062a of the semiconductor pillar 106a. The second source / drain region 104a may comprise single crystalline semiconductor material as discussed above. The second source / drain region 104a may comprise dopants of a first conductivity type as discussed above. As shown in FIG. 1R, the second source / drain region 104a may be overlapped with the second spacer structure 114a.47342.0002 final draft (PCT) 20250911

[0054] The gate structure 107a surrounds the semiconductor pillar 106a. The gate structure comprise a gate dielectric 108a and a gate electrode 110a. The gate electrode 110a may comprise work function metal layer(s) (not shown), which may vary according to the conductivity type of the first source / drain region 102a and the second source / drain region 104a and design requirement. The gate dielectric 108a may be deposited on an inner surface 1121a and a side wall 1123a of the first spacer structure 112a, wherein the inner surface 1121a of the first spacer structure 112a is a surface facing the second source / drain region 104a. The gate dielectric 108a may be deposited on an inner surface 1141a of the second spacer structure 114a, wherein the inner surface 1141a of the second spacer structure 114a is a surface facing the first source / drain region 102a. The gate electrode 110a may be deposited on the gate dielectric 108a. Details discussed above with respect to FIGS. II to IM may apply here.

[0055] As shown in FIGS. 1R, the semiconductor device 100a may further comprises a first contact 116a. The first source / drain region 102a may be vertically stacked on the first contact 116a. The first contact 116a is in contact with the first source / drain region 102a. The first contact 116a may electrically connect the first source / drain region 102a to the first interconnect structures 120 below the first contact 116a.

[0056] As shown in FIGS. 1R, the semiconductor device 100a may further comprise a second contact 118a. The second contact 118a may be vertically stacked on the second source / drain region 104a. The second contact 118a is in contact with the second source / drain region 104a. The second contact 118a may electrically connect the second source / drain region 104a to second interconnect structures 130 over the second contact. The semiconductor device 100b may be substantially similar to the semiconductor device 100a, where like reference numerals indicate like elements.

[0057] FIGS. 2A to 2B are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure. As shown in FIGS. 2A to 2B, the semiconductor pillar 106a has a substantially square column shape. However, embodiments of the present disclosure are not so limited.

[0058] FIGS. 3 A to 3B are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure. As shown in FIGS. 3A to 3B, the semiconductor pillar 106a has a substantially rectangular column shape. It may be desired to form a semiconductor pillar 106a having a substantially rectangular column shape or a substantially elliptical cylindrical shape. The design may allow for improved gate control. However, embodiments of the present disclosure are not so limited.47342.0002 final draft (PCT) 20250911

[0059] FIGS. 4A to 4L are schematic diagrams illustrating intermediate stages in the manufacture of semiconductor devices according to one embodiment of the present disclosure.

[0060] As shown in FIG. 4A, semiconductor pillars 106a and 106b and first source / drain regions 102a and 102b may be formed by process substantially similar to that described above with respect to FIS. 1A to IE.

[0061] As shown in FIG. 4B, a conformal protective layer 22 is formed on the first source / drain regions 102a and 102b. The conformal protective layer 22 comprises dielectric material, such as silicon nitride. A sacrificial material layer 25 may also be formed on the conformal protective layer 22 filling the gap between the first source / drain region 102a and the first source / drain region 102b.

[0062] As shown in FIG. 4C to 4D, at least a portion of the sacrificial layer 18b is removed to expose at least a portion of the semiconductor pillar 106a. Specifically, as shown in FIG. 4C, a portion of the first spacer layer 18a and a portion of the sacrificial layer 18b are removed. The removing process exposes the sacrificial layer 18b. Mask and suitable etching process(es), e.g., RIE, may be used. Then, as shown in FIG. 4D, at least a portion of the sacrificial layer 18b is removed by isotropic etching process to expose at least a portion of the semiconductor pillar 106a. Details of the processes may be substantially similar to that discussed above with respect to FIGS. II and 1J.

[0063] As shown in FIG. 4E, a gate dielectric 108a may be formed. The gate dielectric 108a may be formed by depositing suitable material(s) surrounding the semiconductor pillar 106a. Specifically, the gate dielectric 108a may be formed by deposition on the exposed surface of the semiconductor pillar 106a, the first spacer layer 18a (the first spacer structure 112a), and the second spacer layer 18b.

[0064] As shown in FIG. 4F to 41, conductive gate materials are deposited surrounding the semiconductor pillar 106. Specifically, the conductive gate materials are deposited to form a conductive gate layer 109. One or more work function material layers may be formed. Suitable CMP and etching process(es), such as RIE, may be performed. Then, the conductive gate layer 109 may be defined to form the gate electrodes 110a and 110b. In some embodiments, work function material layer(s) may be defined before depositing a filling conductive material thereon. However, embodiments of the present disclosure are not so limited.

[0065] As such, a gate structure 107a surrounding the semiconductor pillar 106a can be formed, and a gate structure 107b surrounding the semiconductor pillar 106b can be formed. The gate structure 107a comprises the gate dielectric 108a and the gate electrode 110a. The gate structure47342.0002 final draft (PCT) 20250911 107b comprises the gate dielectric 108b and the gate electrode 110b. Details of the gate structures 107a and 107b described above with respect to FIGS. IL and IM may apply here.

[0066] As shown in FIG. 4J, an isolation structure 20 may be formed adjacent to the gate electrode 110a, e.g., by depositing dielectric material between gate electrodes 110a and 110b. First contacts 116a and 116b and first interconnect structures 120 may be formed before removing the first substrate 12. Details of the isolation structure 20, the first contacts 116a and 116b, and the first interconnect structures 120 described above may apply here.

[0067] As shown in FIGS. 4K to 4L, the first substrate 12 is removed, and a portion of the second substrate may be removed to form a second source / drain regions 104a and 104b. Second contacts 118a and 118b and second interconnect structures 130 may be formed after forming the second source / drain regions 104a and 104b. Process(es) similar to that described above with respect to FIGS. 10 to 1R may apply here.

[0068] The method(s) disclosed herein allows for better control of the “gate length”, the “channel length”, and gate positioning of the semiconductor device. The effect of process variations between the semiconductor devices can also be reduced.

[0069] As shown in FIG. 4L, semiconductor devices 100a and 100b are provided. The semiconductor device 100a may be a vertical field-effect transistor. The semiconductor device 100a comprises a first source / drain region 102a, a semiconductor pillar 106a, a second source / drain region 104a, a gate structure 107a and a first spacer structure 112a. In the present embodiment, the semiconductor device further comprises a second spacer structure 114a. The semiconductor device 100a shown in FIG. 4L may be substantially similar to the semiconductor device 100a described above with respect to FIGS. 1R and IS, where like reference numerals indicate like elements. The semiconductor device 100b may be substantially similar to the semiconductor device 100a, where like reference numerals indicate like elements.

[0070] FIG. 5 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure. Referring to FIG. 5, a first structure 10A is provided. The first structure 10A shown in FIG. 5 may be substantially similar to the first structure 10 described above with respect to FIG. 1A and IB where like reference numerals indicate like elements. The first structure 10A may comprise an etch stop layer 15 between the first substrate 12 and the second substrate 14. The etch stop layer 15 may comprise silicon germanium and may be formed by epitaxial growth or suitable deposition process. The second substrate 14 may be formed by epitaxial growth, suitable deposition process on the etch stop layer 15.47342.0002 final draft (PCT) 20250911

[0071] The first structure 10A may be used in processes similar to that described above with respect to FIGS. 1A to IS and / or FIGS. 4A to 4L. In the present embodiment, the first substrate 12 may be grinded to remove a portion of the first substrate 12, and the remained portion of the first substrate 12 may be removed by etching to expose the etch stop layer 15. The etch stop layer 15 may then be removed by suitable etching process to expose the second substrate 14.

[0072] FIG. 6 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure. Referring to FIG.6, a first structure 10B is provided. The first structure 10B shown in FIG. 6 may be substantially similar to the first structure 10 described above with respect to FIG. 1A and IB where like reference numerals indicate like elements. The first structure 10B may comprise a silicon oxide layer 19 between the first substrate 12 and the second substrate 14. The first structure 10B may be an SOI substrate.

[0073] The first structure 10B may be used in processes similar to that described above with respect to FIGS. 1A to IS and / or FIGS. 4A to 4L. In the present embodiment, the first substrate 12 may be grinded to remove a portion of the first substrate 12, and the remained portion of the first substrate 12 may be removed by etching to expose the silicon oxide layer 19. The silicon oxide layer 19 may then be removed by suitable etching process to expose the second substrate 14.

[0074] FIG. 7 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure. Referring to FIG.7, a first structure 10C is provided. The first structure 10C shown in FIG. 7 may be substantially similar to the first structure 10 described above with respect to FIG. 1A and IB where like reference numerals indicate like elements. The first structure 10C may further comprise a silicon oxide layer 19 and an etch stop layer 15. The silicon oxide layer 19 is disposed between the first substrate 12 and the second substrate 14. The etch stop layer 15 is disposed between the second substrate 14 and the silicon oxide layer 19.

[0075] The first structure 10C may be used in processes similar to that described above with respect to FIGS. 1A to IS and / or FIGS. 4A to 4L. In the present embodiment, the first substrate 12 may be removed by grinding or other suitable method. After removing the first substrate 12, a portion of the silicon oxide layer 19 may be removed by grinding, and the remained portion of the silicon oxide layer 19 may be removed by etching to expose the etch stop layer 15. The etch stop layer 15 may then be removed by suitable etching process to expose the second substrate 14.

[0076] FIG. 8 is a schematic diagram illustrating a first structure in the manufacture of semiconductor devices according to one embodiment of the present disclosure. Referring to FIG.47342.0002 final draft (PCT) 202509118, a first structure 10D is provided. The first structure 10D shown in FIG. 8 may be substantially similar to the first structure 10 described above with respect to FIG. 1A and IB where like reference numerals indicate like elements. In the present embodiment, the second substrate 14 may comprise a first material, such as silicon germanium, and the second source / drain regions 104a and 104b comprising a second material, e.g., silicon, different from the first material may be formed in the second substrate 14 at a top surface of the second substrate 14. The second source / drain regions 104a and 104b may be similar to that discussed above.

[0077] The first structure 10D may be used in processes similar to that described above with respect to FIGS. 1A to IS and / or FIGS. 4A to 4L. In the present embodiment, the first substrate 12 may be removed by grinding and / or suitable etching process expose the second substrate 14. A portion of the second substrate 14, e.g., the first material in the second substrate 14, may be removed by suitable etching process to expose the second source / drain regions 104a and 104b. In the present embodiment, the second contacts 118a and 118b and the second interconnect structures 130f may be formed after exposing the second source / drain regions 104a and 104b.

[0078] The foregoing description of embodiments is provided to enable any person skilled in the art to make and use the subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the novel principles and subject matter disclosed herein may be applied to other embodiments without the use of the innovative faculty. Various aspects of the embodiments may be used in different combinations and various different subcombinations of aspects of the embodiments may be used together in a single structure or method without departing from the invention. The claimed subject matter set forth in the claims is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. It is contemplated that additional embodiments are within the spirit and true scope of the disclosed subject matter. Thus, it is intended that the present invention covers modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A method for manufacturing a semiconductor device, comprising: providing a first structure comprising: a first substrate, a second substrate on the first substrate, the second substrate comprising semiconductor material, and a multi-layer structure in contact with the second substrate, the second substrate disposed between the first substrate and the multi-layer structure, the multi-layer structure comprising a first spacer layer and a sacrificial layer between the first spacer layer and the second substrate; forming a first opening extending through the multi-layer structure to expose the second substrate; forming a semiconductor pillar in the first opening; forming a first source / drain region over the semiconductor pillar and the first spacer layer; removing at least a portion of the sacrificial layer to expose at least a portion of the semiconductor pillar; forming a gate structure surrounding the semiconductor pillar, the gate structure comprising a gate dielectric and a gate electrode; removing the first substrate; removing a portion of the second substrate to form or expose a second source / drain region.

2. The method of claim 1, wherein the second substrate comprises single crystalline semiconductor material.

3. The method of claim 1, wherein the semiconductor pillar comprises single crystalline semiconductor material.

4. The method of claim 1, wherein the semiconductor pillar is formed by selective epitaxial atomic layer deposition (ALD) or selective epitaxial chemical vapor deposition (CVD).

5. The method of claim 1, wherein the semiconductor pillar has a substantially cylindrical shape, a substantially elliptical cylindrical shape, a substantially square column shape, or a substantially rectangular column shape.

6. The method of claim 1, wherein the first spacer layer and the sacrificial layer are formed by atomic layer deposition (ALD).

7. The method of claim 1, wherein the first source / drain region is vertically overlapped with the first spacer layer.

8. The method of claim 1, wherein the first spacer layer comprises silicon nitride.

9. The method of claim 1, wherein the sacrificial layer comprises silicon dioxide.

10. The method of claim 1, wherein an inner surface of the first spacer layer is exposed after removing the at least a portion of the sacrificial layer.

11. The method of claim 1, wherein removing the sacrificial layer comprises removing a portion of the first spacer layer to expose the sacrificial layer and removing the at least a portion of the sacrificial layer by isotropic etching process.

12. The method of claim 1, wherein the multi-layer structure further comprises a second spacer layer, the sacrificial layer is disposed between the first spacer layer and the second spacer layer.

13. The method of claim 1, wherein the sacrificial layer has a thickness substantially equal to Lg + 2Td, where Lg is a predetermined gate length of the semiconductor device, and 2Td is twice a predetermined thickness of the gate dielectric.

14. The method of claim 1 further comprising forming a first contact and first interconnect structures before removing the first substrate.

15. The method of claim 1 further comprising forming a second contact and second interconnect structures after forming or exposing the second source / drain region.

16. The method of claim 1, wherein forming the first source / drain region comprises depositing a semiconductor material on the semiconductor pillar.

17. The method of claim 1, wherein forming the gate structure comprises: forming the gate dielectric surrounding the semiconductor pillar; and depositing conductive gate materials surrounding the semiconductor pillar.

18. The method of claim 17, wherein forming the gate structure comprises depositing the conductive gate materials to form a conductive gate layer and defining the conductive gate layer to form the gate electrode.

19. The method of claim 17 further comprising forming an isolation structure adjacent to the gate electrode.

20. The method of claim 17 further comprising forming an isolation structure extending through the sacrificial layer.

21. The method of claim 17, wherein forming the gate structure comprises removing the at least a portion of the sacrificial layer to form a second opening and depositing the conductive gate materials in the second opening to form the gate electrode.

22. The method of claim 1, wherein the first structure further comprises a debonding layer between the first substrate and the second substrate, and removing the first substrate comprises detaching at least a portion of the debonding layer from the first substrate by applying light or heat to the debonding layer.

23. The method of claim 22, wherein the first structure further comprises a first dielectric layer between the debonding layer and the second substrate.

24. The method of claim 1, wherein the first structure further comprises an etch stop layer between the first substrate and the second substrate, and removing the first substrate comprises etching at least a portion of the first substrate to expose the etch stop layer.

25. The method of claim 1, wherein the first structure further comprises a silicon oxide layer and an etch stop layer, the silicon oxide layer is disposed between the first substrate and the second substrate, the etch stop layer is disposed between the second substrate and the silicon oxide layer, and the method comprises etching at least a portion of the silicon oxide layer to expose the etch stop layer after removing the first substrate.

26. A semiconductor device, comprising: a first source / drain region; a semiconductor pillar vertically stacked on and in contact with the first source / drain region at a first end of the semiconductor pillar;a second source / drain region vertically stacked on and in contact with the semiconductor pillar at a second end of the semiconductor pillar; a gate structure surrounding the semiconductor pillar, the gate structure comprising a gate dielectric and a gate electrode; and a first spacer structure surrounding the semiconductor pillar at the first end of the semiconductor pillar; wherein the first spacer structure is in contact with the semiconductor pillar, and the gate dielectric is deposited on an inner surface of the first spacer structure.

27. The semiconductor device of claim 26, wherein the first source / drain region and the second source / drain region comprises single crystalline semiconductor material.

28. The semiconductor device of claim 26, wherein the semiconductor pillar comprises single crystalline semiconductor material.

29. The semiconductor device of claim 26, wherein the semiconductor pillar is formed by selective epitaxial atomic layer deposition atomic layer deposition (ALD) or selective epitaxial chemical vapor deposition (CVD).

30. The semiconductor device of claim 26, wherein the semiconductor pillar has a substantially cylindrical shape, a substantially elliptical cylindrical shape, a substantially square column shape, or a substantially rectangular column shape.

31. The semiconductor device of claim 26, wherein the first source / drain region is formed by depositing a semiconductor material on the semiconductor pillar.

32. The semiconductor device of claim 26, wherein the first source / drain region is overlapped with the first spacer structure.

33. The semiconductor device of claim 26 further comprising a second spacer structure surrounding the semiconductor pillar at the second end of the semiconductor pillar, wherein the second spacer structure is in contact with the semiconductor pillar, and the gate dielectric is deposited on an inner surface of the second spacer structure .

34. The semiconductor device of claim 33, wherein the first source / drain region is overlapped with the first spacer structure, and the second source / drain region is overlapped with the second spacer structure.

35. The semiconductor device of claim 33, wherein the semiconductor pillar is formed by depositing semiconductor material and filling a third opening extending through the first spacer structure and a fourth opening extending through the second spacer structure.

36. The semiconductor device of claim 26, wherein the gate dielectric is deposited on a side wall of the first spacer structure.

37. The semiconductor device of claim 26 further comprising a first contact in contact with the first source / drain region, the first source / drain region vertically stacked on the first contact.

38. The semiconductor device of claim 37 further comprising a second contact in contact with the second source / drain region, the second contact vertically stacked on the second source / drain region.

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