Driver circuit, driving method, and display apparatus

Abstract

Provided are a driver circuit, a driving method, and a display apparatus. The driver circuit comprises a write-in circuit (11), a control circuit (12), and an output circuit (10); the write-in circuit (11), under the control of a first control clock signal (ECK), controls a potential of a control node (NC) according to an input signal (ESTV); the control circuit (12) controls a potential of an output control node (NS) according to the potential of the control node (NC); and the output circuit (10), under the control of the potential of the output control node (NS), controls a driver output terminal (OT) to output a drive signal.

Description

Driving circuit, driving method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a driving circuit, a driving method and a display device. BACKGROUND

[0002] In the related art, a driving circuit for providing a light-emitting control signal or a driving signal for an LTPO (low temperature polyoxide) pixel circuit adopts an LTPS (low temperature poly silicon) PTFT (P-type thin film transistor), and adopts a bootstrapping technology, so that a transistor in the driving circuit, whose gate is electrically connected to a first node, is subjected to a large gate bias stress, which easily causes abnormal transistor characteristics and increases the risk of display product failure. Moreover, the related driving circuit is a step output, i.e., a step output from a high level to a low level, and the number of TFTs and the number of capacitors used by the related driving circuit are relatively large, which is not conducive to realizing a narrow frame.

[0003] SUMMARY

[0004] In one aspect, the present disclosure provides a driving circuit, comprising a writing circuit, a control circuit and an output circuit;

[0005] The writing circuit is electrically connected to a first control clock signal end, an input end and a control node, respectively, and is configured to control a potential of the control node according to an input signal provided by the input end under control of a first control clock signal provided by the first control clock signal end;

[0006] The control circuit is electrically connected to the control node and an output control node, respectively, and is configured to control a potential of the output control node according to the potential of the control node;

[0007] The output circuit is electrically connected to the output control node and a driving output end, respectively, and is configured to control the driving output end to output a driving signal under control of the potential of the output control node.

[0008] Optionally, the writing circuit comprises a first writing sub-circuit and a second writing sub-circuit;

[0009] The first writing sub-circuit is electrically connected to the first control clock signal end and a first node, respectively, and is configured to control a potential of the first node under control of the first control clock signal;

[0010] The second writing sub-circuit is electrically connected to the input end, the first control clock signal end and the control node, respectively, and is configured to control the control node to be in communication or disconnected with the input end under control of the first control clock signal.

[0011] Optionally, the second write sub-circuit is electrically connected with the first node, for controlling the communication or disconnection between the control node and the input terminal under the control of the electric potential of the first node.

[0012] Optionally, the first write sub-circuit is electrically connected with a first voltage terminal and a second voltage terminal respectively, for controlling the communication or disconnection between the first node and the first voltage terminal, and controlling the communication or disconnection between the first node and the second voltage terminal under the control of the first control clock signal.

[0013] Optionally, the control circuit comprises a first control sub-circuit and a second control sub-circuit.

[0014] The first control sub-circuit is electrically connected with the first node, the first voltage terminal, the second voltage terminal, the control node, the first control clock signal terminal and the output control node respectively, for controlling the communication or disconnection between the control node and the first voltage terminal under the control of the electric potential of the first node and the electric potential of the output control node, and controlling the communication or disconnection between the control node and the second voltage terminal under the control of the first control clock signal and the electric potential of the output control node.

[0015] The second control sub-circuit is electrically connected with the control node, the first voltage terminal, the second voltage terminal and the output control node respectively, for controlling the communication or disconnection between the output control node and the first voltage terminal under the control of the electric potential of the control node, and controlling the communication or disconnection between the output control node and the second voltage terminal under the control of the electric potential of the control node.

[0016] Optionally, the control circuit comprises a first control sub-circuit and a second control sub-circuit.

[0017] The first control sub-circuit is electrically connected with the control node, the first control clock signal terminal, the second voltage terminal, the first voltage terminal, the second control clock signal terminal and the output control node respectively, for controlling the communication or disconnection between the control node and the second voltage terminal under the control of the first control clock signal and the electric potential of the output control node, and controlling the communication or disconnection between the control node and the first voltage terminal under the control of the second control clock signal provided by the second control clock signal terminal and the electric potential of the output control node.

[0018] The second control sub-circuit is electrically connected with the control node, the first voltage terminal, the second voltage terminal and the output control node respectively, for controlling the communication or disconnection between the output control node and the first voltage terminal under the control of the electric potential of the control node, and controlling the communication or disconnection between the output control node and the second voltage terminal under the control of the electric potential of the control node.

[0019] Optionally, the write circuit is configured to control the communication or disconnection between the input terminal and the control node under the control of the first control clock signal.

[0020] Optionally, the output circuit is further electrically connected with a first voltage terminal and a second voltage terminal respectively, and configured to control the communication or disconnection between the driving output terminal and the first voltage terminal, and control the communication or disconnection between the driving output terminal and the second voltage terminal under the control of the potential of the output control node.

[0021] Optionally, the first write sub-circuit comprises a first transistor and a second transistor.

[0022] The gate of the first transistor is electrically connected with the first control clock signal terminal, the first pole of the first transistor is electrically connected with the first voltage terminal, and the second pole of the first transistor is electrically connected with the first node.

[0023] The gate of the second transistor is electrically connected with the first control clock signal terminal, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the second voltage terminal.

[0024] Optionally, the second write sub-circuit comprises a third transistor.

[0025] The gate of the third transistor is electrically connected with the first control clock signal terminal, the first pole of the third transistor is electrically connected with the input terminal, and the second pole of the third transistor is electrically connected with the control node.

[0026] Optionally, the second write sub-circuit comprises a third transistor and a fourth transistor.

[0027] The gate of the third transistor is electrically connected with the first control clock signal terminal, the first pole of the third transistor is electrically connected with the input terminal, and the second pole of the third transistor is electrically connected with the control node.

[0028] The gate of the fourth transistor is electrically connected with the first node, the first pole of the fourth transistor is electrically connected with the input terminal, and the second pole of the fourth transistor is electrically connected with the control node.

[0029] Optionally, the first control sub-circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor.

[0030] The gate of the fifth transistor is electrically connected with the first node, the first pole of the fifth transistor is electrically connected with the first voltage terminal, and the second pole of the fifth transistor is electrically connected with the first pole of the sixth transistor.

[0031] a gate of the sixth transistor is electrically connected with the output control node, and a second electrode of the sixth transistor is electrically connected with the control node;

[0032] a gate of the seventh transistor is electrically connected with the output control node, a first electrode of the seventh transistor is electrically connected with the control node, and a second electrode of the seventh transistor is electrically connected with a first electrode of the eighth transistor;

[0033] a gate of the eighth transistor is electrically connected with the first control clock signal end, and a second electrode of the eighth transistor is electrically connected with the second voltage end.

[0034] Optionally, the second control sub-circuit includes a ninth transistor and a tenth transistor;

[0035] a gate of the ninth transistor is electrically connected with the control node, a first electrode of the ninth transistor is electrically connected with the first voltage end, and a second electrode of the ninth transistor is electrically connected with the output control node;

[0036] a gate of the tenth transistor is electrically connected with the control node, a first electrode of the tenth transistor is electrically connected with the output control node, and a second electrode of the tenth transistor is electrically connected with the second voltage end.

[0037] Optionally, the first control sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0038] a gate of the fifth transistor is electrically connected with the first control clock signal end, a first electrode of the fifth transistor is electrically connected with the second voltage end, and a second electrode of the fifth transistor is electrically connected with a first electrode of the sixth transistor;

[0039] a gate of the sixth transistor is electrically connected with the output control node, and a second electrode of the sixth transistor is electrically connected with the control node;

[0040] a gate of the seventh transistor is electrically connected with the output control node, a first electrode of the seventh transistor is electrically connected with the control node, and a second electrode of the seventh transistor is electrically connected with a first electrode of the eighth transistor;

[0041] a gate of the eighth transistor is electrically connected with the second control clock signal end, and a second electrode of the eighth transistor is electrically connected with the first voltage end.

[0042] Optionally, the write circuit includes a first transistor;

[0043] The gate of the first transistor is electrically connected with the first control clock signal end, the first pole of the first transistor is electrically connected with the input end, and the second pole of the first transistor is electrically connected with the control node.

[0044] Optionally, the output circuit comprises an eleventh transistor and a twelfth transistor.

[0045] The gate of the eleventh transistor is electrically connected with the output control node, the first pole of the eleventh transistor is electrically connected with the first voltage end, and the second pole of the eleventh transistor is electrically connected with the driving output end.

[0046] The gate of the twelfth transistor is electrically connected with the output control node, the first pole of the twelfth transistor is electrically connected with the driving output end, and the second pole of the twelfth transistor is electrically connected with the second voltage end.

[0047] In a second aspect, the embodiments of the present disclosure provide a driving method applied to the driving circuit, and the driving method comprises the following steps:

[0048] The write circuit obtains the potential of the control node according to the input signal provided by the input end under the control of the first control clock signal.

[0049] The control circuit controls the potential of the output control node according to the potential of the control node.

[0050] The output circuit controls the driving output end to output the driving signal under the control of the potential of the output control node.

[0051] Optionally, the write circuit comprises a first write sub-circuit and a second write sub-circuit; the control circuit comprises a first control sub-circuit and a second control sub-circuit; the driving period comprises a first write stage and a first latch stage arranged in sequence; and the driving method comprises the following steps:

[0052] In the first write stage, the first write sub-circuit writes the first voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit writes the second voltage signal provided by the input end into the control node under the control of the first control clock signal, the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the second voltage signal into the driving output end under the control of the potential of the output control node.

[0053] In the first latch stage, the first write sub-circuit writes the second voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit maintains the potential of the control node as the second voltage, the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the first control sub-circuit writes the second voltage signal into the control node under the control of the potential of the first node and the potential of the output control node; the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node;

[0054] Optionally, the driving cycle further comprises a second write stage and a second latch stage arranged in sequence after the first latch stage; and the driving method comprises:

[0055] In the second write stage, the first write sub-circuit writes the first voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit writes the first voltage signal provided by the input terminal into the control node under the control of the first control clock signal, the second control sub-circuit controls the writing of the second voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the first voltage signal into the driving output terminal under the control of the output control node;

[0056] In the second latch stage, the first write sub-circuit writes the second voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit maintains the potential of the control node as the first voltage under the control of the first control clock signal, the second control sub-circuit writes the second voltage signal into the output control node under the control of the potential of the control node, and the first control sub-circuit writes the first voltage signal into the control node under the control of the potential of the output control node and the potential of the first node; the output circuit writes the first voltage signal into the driving output terminal under the control of the output control node.

[0057] Optionally, the control circuit comprises a first control sub-circuit and a second control sub-circuit; the driving cycle comprises a first write stage and a first latch stage arranged after the first write stage; and the driving method comprises:

[0058] In the first write stage, the write circuit writes the second voltage signal provided by the input terminal into the control node under the control of the first control clock signal; the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, the first control sub-circuit maintains the potential of the control node under the control of the first control clock signal and the second control clock signal; and the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node;

[0059] In the first latch stage, the write circuit maintains the potential of the control node as the first voltage under the control of the first control clock signal, the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the first control sub-circuit writes the second voltage signal into the control node under the control of the potential of the output control node and the first control clock signal; and the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node.

[0060] Optionally, the driving cycle further comprises a second write stage and a second latch stage arranged in sequence; the second write stage is arranged after the first latch stage; and the driving method further comprises:

[0061] In the second write stage, the first write sub-circuit writes the first voltage signal provided by the input terminal into the control node under the control of the first control clock signal, the second control sub-circuit writes the second voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the first voltage signal into the driving output terminal under the control of the potential of the output control node.

[0062] In the second latch stage, the second control sub-circuit writes the second voltage signal into the output control node under the control of the potential of the control node, the first control sub-circuit maintains the potential of the control node, and the output circuit writes the first voltage signal into the driving output terminal under the control of the potential of the output control node.

[0063] Optionally, the driving cycle comprises a first write stage and a first latch stage arranged in sequence; and the driving method comprises:

[0064] In the first write stage, the write circuit writes the second voltage signal provided by the input terminal into the control node under the control of the potential of the first control clock signal; the control circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node.

[0065] In the first latch stage, the write circuit maintains the potential of the control node as the second voltage under the control of the potential of the first control clock signal, the control circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node.

[0066] Optionally, the driving cycle further comprises a second write stage and a second latch stage arranged in sequence and arranged after the first latch stage; and the driving method comprises:

[0067] In the second write stage, the write circuit writes the first voltage signal provided by the input terminal to the control node under the control of the potential of the first control clock signal; the control circuit writes the second voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node.

[0068] In the second latch stage, the write circuit maintains the potential of the control node as the first voltage under the control of the potential of the first control clock signal; the control circuit writes the second voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node.

[0069] In a third aspect, the embodiments of the present disclosure provide a display device, comprising the driving circuit. BRIEF DESCRIPTION OF DRAWINGS

[0070] FIG. 1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0071] FIG. 2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0072] FIG. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0073] FIG. 4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0074] FIG. 5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0075] FIG. 6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0076] FIG. 7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0077] FIG. 8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0078] FIG. 9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0079] FIG. 10A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0080] FIG. 10B is a timing diagram of at least one embodiment of the driving circuit shown in FIG. 10A;

[0081] FIGS. 10C, 10D, 10E, 10F, 10G and 10H are working state diagrams of at least one embodiment of the driving circuit shown in FIG. 10A;

[0082] FIG. 11A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0083] FIG. 11B is a timing diagram of the driving circuit of FIG. 11A according to at least one embodiment of the present disclosure;

[0084] FIGS. 11C, 11D, 11E, 11F, 11G, and 11H are state diagrams of the driving circuit of FIG. 11A according to at least one embodiment of the present disclosure;

[0085] FIG. 12A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0086] FIG. 12B is a timing diagram of the driving circuit of FIG. 12A according to at least one embodiment of the present disclosure;

[0087] FIGS. 12C, 12D, 12E, 12F, 12G, 12H, 121, 12J, 12K, 12L, and 12M are state diagrams of the driving circuit of FIG. 12A according to at least one embodiment of the present disclosure

[0088] FIG. 13A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0089] FIG. 13B is a timing diagram of the driving circuit of FIG. 13A according to at least one embodiment of the present disclosure;

[0090] FIGS. 14 and 15 are waveform diagrams of driving signals provided by driving outputs of various stages included in a driving module according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0091] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0092] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0093] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0094] As shown in FIG. 1, the driving circuit according to the embodiment of the present disclosure comprises a write circuit 11, a control circuit 12 and an output circuit 10.

[0095] The write circuit 11 is electrically connected with a first control clock signal terminal ECK, an input terminal ESTV and a control node NC respectively, and is configured to control the potential of the control node NC according to an input signal provided by the input terminal ESTV under the control of a first control clock signal provided by the first control clock signal terminal ECK.

[0096] The control circuit 12 is electrically connected with the control node NC and an output control node NS respectively, and is configured to control the potential of the output control node NS according to the potential of the control node NC.

[0097] The output circuit 10 is electrically connected with the output control node NS and a driving output terminal OT respectively, and is configured to control the driving output terminal OT to output a driving signal under the control of the potential of the output control node NS.

[0098] In at least one embodiment of the present disclosure, the driving signal output by the driving output terminal OT can be a light-emitting control signal or a gate driving signal.

[0099] In the related art, the driving circuit for providing a light-emitting control signal or a driving signal for an LTPO (low temperature polyoxide) pixel circuit adopts an LTPS (low temperature poly silicon) PTFT (P-type thin film transistor), and adopts a bootstrapping technology, so that the transistor with the gate electrically connected with the first node in the driving circuit is subjected to a large gate bias stress, which easily causes abnormal characteristics of the transistor and increases the risk of display product failure. Moreover, the related driving circuit is a step output, i.e., a step output from a high level to a low level, and the number of TFTs and the number of capacitors adopted by the related driving circuit are relatively large, which is not conducive to realizing a narrow frame.

[0100] Based on the above problems, the driving circuit according to the embodiment of the present disclosure adopts a write circuit to refresh the output state of the driving circuit, and adopts a control circuit to latch the write signal at the previous moment without adopting a capacitor, so as to reduce the space occupied by the driving circuit and facilitate realization of a narrow frame. Moreover, the driving circuit according to the embodiment of the present disclosure does not adopt a bootstrapping technology, and will not cause abnormal characteristics of the transistor due to high gate voltage, thereby improving the display failure phenomenon; and the driving circuit according to the embodiment of the present disclosure can realize a non-step output.

[0101] The driving circuit according to the embodiment of the present disclosure adopts an LTPO process, and adopts an LTPS PTFT and an Oxide (oxide) NTFT (N-type thin film transistor) to constitute the driving circuit.

[0102] The driving circuit has high noise tolerance, the control circuit for latching works at all times, the driving circuit has no floating state, and the anti-interference capability is strong.

[0103] The driving circuit does not use a capacitor, the Oxide NTFT in the driving circuit has a low drain current characteristic, and the static power consumption of the driving circuit is lower.

[0104] The driving circuit does not use a capacitor, and the TFT used has less data, and the CMOS (complementary metal-oxide-semiconductor) driving circuit only needs to meet the load of a small logic TFT.

[0105] In at least one embodiment of the present disclosure, the write circuit includes a first write sub-circuit and a second write sub-circuit.

[0106] The first write sub-circuit is electrically connected with the first control clock signal end and the first node, respectively, and is configured to control the potential of the first node under the control of the first control clock signal.

[0107] The second write sub-circuit is electrically connected with the input end, the first control clock signal end, and the control node, respectively, and is configured to control the communication or disconnection between the control node and the input end under the control of the first control clock signal.

[0108] In specific implementation, the write circuit can include a first write sub-circuit and a second write sub-circuit, the first write sub-circuit controls the potential of the first node under the control of the first control clock signal, and the second write sub-circuit controls the communication or disconnection between the control node and the input end under the control of the first control clock signal.

[0109] As shown in FIG. 2, on the basis of at least one embodiment of the driving circuit shown in FIG. 1, the write circuit includes a first write sub-circuit 21 and a second write sub-circuit 22.

[0110] The first write sub-circuit 21 is electrically connected with the first control clock signal end ECK and the first node N1, respectively, and is configured to control the potential of the first node N1 under the control of the first control clock signal.

[0111] The second write sub-circuit 22 is electrically connected with the input end ESTV, the first control clock signal end ECK, and the control node NC, respectively, and is configured to control the communication or disconnection between the control node NC and the input end ESTV under the control of the first control clock signal.

[0112] Optionally, the second write sub-circuit is further electrically connected with the first node, for controlling the communication or disconnection between the control node and the input terminal under the control of the electric potential of the first node.

[0113] In a specific implementation, the second write sub-circuit can also work under the electric potential of the first node.

[0114] As shown in FIG. 3, based on at least one embodiment of the driving circuit shown in FIG. 2, the second write sub-circuit 22 is further electrically connected with the first node N1, for controlling the communication or disconnection between the control node NC and the input terminal ESTV under the control of the electric potential of the first node N1.

[0115] In at least one embodiment of the present disclosure, the first write sub-circuit is further electrically connected with a first voltage terminal and a second voltage terminal respectively, for controlling the communication or disconnection between the first node and the first voltage terminal under the control of the first control clock signal, and controlling the communication or disconnection between the first node and the second voltage terminal under the control of the first control clock signal.

[0116] In a specific implementation, the first write sub-circuit can control the communication or disconnection between the first node and the first voltage terminal and the communication or disconnection between the first node and the second voltage terminal under the control of the first control clock signal.

[0117] Optionally, the first voltage terminal can be a high voltage terminal, and the second voltage terminal can be a low voltage terminal.

[0118] As shown in FIG. 4, based on at least one embodiment of the driving circuit shown in FIG. 3, the first write sub-circuit 21 is further electrically connected with a first voltage terminal V1 and a second voltage terminal V2 respectively, for controlling the communication or disconnection between the first node N1 and the first voltage terminal V1 under the control of the first control clock signal, and controlling the communication or disconnection between the first node N1 and the second voltage terminal V2 under the control of the first control clock signal.

[0119] In at least one embodiment of the present disclosure, the control circuit includes a first control sub-circuit and a second control sub-circuit.

[0120] The first control sub-circuit is electrically connected with the first node, the first voltage terminal, the second voltage terminal, the control node, the first control clock signal terminal and the output control node respectively, for controlling the communication or disconnection between the control node and the first voltage terminal under the control of the electric potential of the first node and the electric potential of the output control node, and controlling the communication or disconnection between the control node and the second voltage terminal under the control of the first control clock signal and the electric potential of the output control node.

[0121] The second control sub-circuit is electrically connected with the control node, the first voltage terminal, the second voltage terminal and the output control node respectively, and is configured to control the output control node to be connected with or disconnected from the first voltage terminal under the control of the potential of the control node, and control the output control node to be connected with or disconnected from the second voltage terminal under the control of the potential of the control node.

[0122] In specific implementation, the control circuit can include a first control sub-circuit and a second control sub-circuit. The first control sub-circuit controls the control node to be connected with or disconnected from the first voltage terminal under the control of the potential of the first node and the potential of the output control node, and controls the control node to be connected with or disconnected from the second voltage terminal under the control of the first control clock signal and the potential of the output control node. The second control sub-circuit controls the output control node to be connected with or disconnected from the first voltage terminal under the control of the potential of the control node, and controls the output control node to be connected with or disconnected from the second voltage terminal under the control of the potential of the control node.

[0123] As shown in FIG. 5, on the basis of at least one embodiment of the driving circuit shown in FIG. 4, the control circuit includes a first control sub-circuit 31 and a second control sub-circuit 32.

[0124] The first control sub-circuit 31 is electrically connected with the first node N1, the first voltage terminal V1, the second voltage terminal V2, the control node NC, the first control clock signal terminal ECK and the output control node NS respectively, and is configured to control the control node NC to be connected with or disconnected from the first voltage terminal V1 under the control of the potential of the first node N1 and the potential of the output control node NS, and control the control node NC to be connected with or disconnected from the second voltage terminal V2 under the control of the first control clock signal and the potential of the output control node NS.

[0125] The second control sub-circuit 32 is electrically connected with the control node NC, the first voltage terminal V1, the second voltage terminal V2 and the output control node NS respectively, and is configured to control the output control node NS to be connected with or disconnected from the first voltage terminal V1 under the control of the potential of the control node NC, and control the output control node NS to be connected with or disconnected from the second voltage terminal V2 under the control of the potential of the control node NC.

[0126] In at least one embodiment of the present disclosure, the control circuit includes a first control sub-circuit and a second control sub-circuit.

[0127] The first control sub-circuit is electrically connected with the control node, the first control clock signal end, the second voltage end, the first voltage end, the second control clock signal end and the output control node respectively, and is configured to control the control node to be connected or disconnected with the second voltage end under the control of the first control clock signal and the potential of the output control node, and control the control node to be connected or disconnected with the first voltage end under the control of the second control clock signal provided by the second control clock signal end and the potential of the output control node.

[0128] The second control sub-circuit is electrically connected with the control node, the first voltage end, the second voltage end and the output control node respectively, and is configured to control the output control node to be connected or disconnected with the first voltage end under the control of the potential of the control node, and control the output control node to be connected or disconnected with the second voltage end.

[0129] In a specific implementation, the control circuit can include a first control sub-circuit and a second control sub-circuit; the first control sub-circuit controls the control node to be connected or disconnected with the second voltage end under the control of the first control clock signal and the potential of the output control node, and controls the control node to be connected or disconnected with the first voltage end under the control of the second control clock signal provided by the second control clock signal end and the potential of the output control node; and the second control sub-circuit controls the output control node to be connected or disconnected with the first voltage end under the control of the potential of the control node, and controls the output control node to be connected or disconnected with the second voltage end.

[0130] As shown in FIG. 6, on the basis of at least one embodiment of the driving circuit shown in FIG. 1, the control circuit includes a first control sub-circuit 31 and a second control sub-circuit 32.

[0131] The first control sub-circuit 31 is electrically connected with the control node NC, the first control clock signal end ECK, the second voltage end V2, the first voltage end V1, the second control clock signal end ECB and the output control node NS respectively, and is configured to control the control node NC to be connected or disconnected with the second voltage end V2 under the control of the first control clock signal and the potential of the output control node NS, and control the control node NC to be connected or disconnected with the first voltage end V1 under the control of the second control clock signal provided by the second control clock signal end ECB and the potential of the output control node NS.

[0132] The second control sub-circuit 32 is electrically connected with the control node NC, the first voltage terminal V1, the second voltage terminal V2 and the output control node NS respectively, and is configured to control the output control node NS to be connected with or disconnected from the first voltage terminal V1 and to be connected with or disconnected from the second voltage terminal V2 under the control of the potential of the control node NC.

[0133] Optionally, the write circuit is configured to control the input terminal to be connected with or disconnected from the control node under the control of the first control clock signal.

[0134] In at least one embodiment of the present disclosure, the output circuit is further electrically connected with a first voltage terminal and a second voltage terminal respectively, and is configured to control the driving output terminal to be connected with or disconnected from the first voltage terminal and to be connected with or disconnected from the second voltage terminal under the control of the potential of the output control node.

[0135] In a specific implementation, the output circuit can control the driving output terminal to be connected with or disconnected from the first voltage terminal and to be connected with or disconnected from the second voltage terminal under the control of the potential of the output control node.

[0136] As shown in FIG. 7, on the basis of at least one embodiment of the driving circuit shown in FIG. 1, the output circuit 10 is further electrically connected with a first voltage terminal V1 and a second voltage terminal V2 respectively, and is configured to control the driving output terminal OT to be connected with or disconnected from the first voltage terminal V1 and to be connected with or disconnected from the second voltage terminal V2 under the control of the potential of the output control node NS.

[0137] As shown in FIG. 8, on the basis of at least one embodiment of the driving circuit shown in FIG. 5, the output circuit 10 is further electrically connected with a first voltage terminal V1 and a second voltage terminal V2 respectively, and is configured to control the driving output terminal OT to be connected with or disconnected from the first voltage terminal V1 and to be connected with or disconnected from the second voltage terminal V2 under the control of the potential of the output control node NS.

[0138] As shown in FIG. 9, on the basis of at least one embodiment of the driving circuit shown in FIG. 6, the output circuit 10 is further electrically connected with a first voltage terminal V1 and a second voltage terminal V2 respectively, and is configured to control the driving output terminal OT to be connected with or disconnected from the first voltage terminal V1 and to be connected with or disconnected from the second voltage terminal V2 under the control of the potential of the output control node NS.

[0139] Optionally, the first write sub-circuit includes a first transistor and a second transistor.

[0140] a gate of the first transistor is electrically connected with the first control clock signal end, a first pole of the first transistor is electrically connected with the first voltage end, and a second pole of the first transistor is electrically connected with the first node;

[0141] a gate of the second transistor is electrically connected with the first control clock signal end, a first pole of the second transistor is electrically connected with the first node, and a second pole of the second transistor is electrically connected with the second voltage end.

[0142] Optionally, the second write sub-circuit comprises a third transistor.

[0143] a gate of the third transistor is electrically connected with the first control clock signal end, a first pole of the third transistor is electrically connected with the input end, and a second pole of the third transistor is electrically connected with the control node.

[0144] Optionally, the second write sub-circuit comprises a third transistor and a fourth transistor.

[0145] a gate of the third transistor is electrically connected with the first control clock signal end, a first pole of the third transistor is electrically connected with the input end, and a second pole of the third transistor is electrically connected with the control node;

[0146] a gate of the fourth transistor is electrically connected with the first node, a first pole of the fourth transistor is electrically connected with the input end, and a second pole of the fourth transistor is electrically connected with the control node.

[0147] Optionally, the first control sub-circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor.

[0148] a gate of the fifth transistor is electrically connected with the first node, a first pole of the fifth transistor is electrically connected with the first voltage end, and a second pole of the fifth transistor is electrically connected with a first pole of the sixth transistor;

[0149] a gate of the sixth transistor is electrically connected with the output control node, and a second pole of the sixth transistor is electrically connected with the control node;

[0150] a gate of the seventh transistor is electrically connected with the output control node, a first pole of the seventh transistor is electrically connected with the control node, and a second pole of the seventh transistor is electrically connected with a first pole of the eighth transistor;

[0151] a gate of the eighth transistor is electrically connected with the first control clock signal end, and a second pole of the eighth transistor is electrically connected with the second voltage end.

[0152] Optionally, the second control sub-circuit comprises a ninth transistor and a tenth transistor;

[0153] The gate of the ninth transistor is electrically connected with the control node, the first pole of the ninth transistor is electrically connected with the first voltage terminal, and the second pole of the ninth transistor is electrically connected with the output control node.

[0154] The gate of the tenth transistor is electrically connected with the control node, the first pole of the tenth transistor is electrically connected with the output control node, and the second pole of the tenth transistor is electrically connected with the second voltage terminal.

[0155] Optionally, the first control sub-circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0156] The gate of the fifth transistor is electrically connected with the first control clock signal terminal, the first pole of the fifth transistor is electrically connected with the second voltage terminal, and the second pole of the fifth transistor is electrically connected with the first pole of the sixth transistor;

[0157] The gate of the sixth transistor is electrically connected with the output control node, and the second pole of the sixth transistor is electrically connected with the control node.

[0158] The gate of the seventh transistor is electrically connected with the output control node, the first pole of the seventh transistor is electrically connected with the control node, and the second pole of the seventh transistor is electrically connected with the first pole of the eighth transistor.

[0159] The gate of the eighth transistor is electrically connected with the second control clock signal terminal, and the second pole of the eighth transistor is electrically connected with the first voltage terminal.

[0160] Optionally, the write circuit comprises a first transistor;

[0161] The gate of the first transistor is electrically connected with the first control clock signal terminal, the first pole of the first transistor is electrically connected with the input terminal, and the second pole of the first transistor is electrically connected with the control node.

[0162] Optionally, the output circuit comprises an eleventh transistor and a twelfth transistor;

[0163] The gate of the eleventh transistor is electrically connected with the output control node, the first pole of the eleventh transistor is electrically connected with the first voltage terminal, and the second pole of the eleventh transistor is electrically connected with the driving output terminal.

[0164] The gate of the twelfth transistor is electrically connected with the output control node, the first pole of the twelfth transistor is electrically connected with the driving output terminal, and the second pole of the twelfth transistor is electrically connected with the second voltage terminal.

[0165] As shown in FIG. 10A, on the basis of at least one embodiment of the driving circuit shown in FIG. 7,

[0166] The write circuit comprises a first transistor M1;

[0167] The gate of M1 is electrically connected with the first control clock signal end ECK, the source of M1 is electrically connected with the input end ESTV, and the drain of M1 is electrically connected with the control node NC;

[0168] The control circuit comprises a thirteenth transistor M13 and a fourteenth transistor M14;

[0169] The gate of M13 is electrically connected with the control node NC, the source of M13 is electrically connected with the high voltage end VGH, and the drain of M13 is electrically connected with the output control node NS;

[0170] The gate of M14 is electrically connected with the control node NC, the source of M14 is electrically connected with the output control node NS, and the drain of M14 is electrically connected with the low voltage end VGL;

[0171] The output circuit comprises an eleventh transistor M11 and a twelfth transistor M12;

[0172] The gate of M11 is electrically connected with the output control node NS, the source of M11 is electrically connected with the high voltage end VGH, and the drain of M11 is electrically connected with the driving output end OT;

[0173] The gate of M12 is electrically connected with the output control node NS, the source of M12 is electrically connected with the driving output end OT, and the drain of M12 is electrically connected with the low voltage end VGL.

[0174] In at least one embodiment shown in FIG. 10A, M1 is a p-type transistor, M13 is a p-type transistor, M14 is an n-type transistor, M11 is a p-type transistor, and M12 is an n-type transistor;

[0175] M1 is an LTPS (low temperature polysilicon) transistor, M13 is an LTPS transistor, M14 is an oxide transistor, M11 is an LTPS transistor, and M12 is an oxide transistor.

[0176] FIG. 10B is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 10A.

[0177] As shown in Fig. 10B, in the first write stage t1, ECK provides a low voltage signal, the driving circuit realizes the function of the write signal, as shown in Fig. 10C, M1 is opened, ESTV provides a low voltage signal, ESTV writes the low voltage signal into NC, M13 is opened, M14 is closed, the potential of NS is high voltage, M11 is closed, M12 is opened, and OT outputs a low voltage signal; in the first latch stage t2, ECK provides a high voltage signal, the driving circuit realizes the function of keeping the write signal at the previous moment, as shown in Fig. 10D, M1 is closed, the potential of NC keeps the high voltage at the previous moment, M13 is opened, M14 is closed, the potential of NS is high voltage, M11 is closed, M12 is opened, and OT outputs a low voltage signal;

[0178] In the second write stage t3, ECK provides a low voltage signal, the driving circuit realizes the function of the write signal, as shown in Fig. 10E, M1 is opened, ESTV provides a high voltage signal, ESTV writes the high voltage signal into NC, M13 is closed, M14 is opened, the potential of NS is low voltage, M11 is opened, M12 is closed, and OT outputs a high voltage signal;

[0179] In the second latch stage t4, ECK provides a high voltage signal, the driving circuit realizes the function of keeping the write signal at the previous moment, as shown in Fig. 10F, M1 is closed, NC keeps the high potential at the previous moment, M13 is closed, M14 is opened, the potential of NS is low voltage, M11 is opened, M12 is closed, and OT outputs a high voltage signal;

[0180] In the third write stage t5, ECK provides a low voltage signal, the driving circuit realizes the function of the write signal, as shown in Fig. 10G, M1 is opened, ESTV provides a low voltage signal, ESTV writes the low voltage signal into NC, M13 is opened, M14 is closed, the potential of NS is high voltage, M11 is closed, M12 is opened, and OT outputs a low voltage signal;

[0181] In the third latch stage t6, ECK provides a high voltage signal, the driving circuit realizes the function of keeping the write signal at the previous moment, as shown in Fig. 10H, M1 is closed, NC keeps the low voltage at the previous moment, M13 is opened, M14 is closed, the potential of NS is high voltage, M11 is closed, M12 is opened, and OT outputs a low voltage signal.

[0182] As shown in Fig. 11A, on the basis of at least one embodiment of the driving circuit shown in Fig. 8,

[0183] The first write sub-circuit comprises a first transistor M1 and a second transistor M2;

[0184] A gate of the M1 is electrically connected with the first control clock signal terminal ECK, a source of the M1 is electrically connected with the high voltage terminal VGH, and a drain of the M1 is electrically connected with the first node N1;

[0185] A gate of the M2 is electrically connected with the first control clock signal terminal ECK, a source of the M2 is electrically connected with the first node N1, and a drain of the M2 is electrically connected with the low voltage terminal VGL;

[0186] The second write sub-circuit comprises a third transistor M3 and a fourth transistor M4;

[0187] A gate of the M3 is electrically connected with the first control clock signal terminal ECK, a source of the M3 is electrically connected with the input terminal ESTV, and a drain of the M3 is electrically connected with the control node NC;

[0188] A gate of the M4 is electrically connected with the first node N1, a drain of the M4 is electrically connected with the input terminal ESTV, and a source of the M4 is electrically connected with the control node NC;

[0189] The first control sub-circuit comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0190] A gate of the M5 is electrically connected with the first node N1, a source of the fifth transistor M5 is electrically connected with the high voltage terminal VGH, and a drain of the M5 is electrically connected with a source of the M6;

[0191] A gate of the M6 is electrically connected with the output control node NS, and a drain of the M6 is electrically connected with the control node NC;

[0192] A gate of the M7 is electrically connected with the output control node NS, a drain of the M7 is electrically connected with the control node NC, and a source of the M7 is electrically connected with a source of the M8;

[0193] A gate of the M8 is electrically connected with the first control clock signal terminal ECK, and a drain of the M8 is electrically connected with the low voltage terminal VGL;

[0194] The second control sub-circuit comprises a ninth transistor M9 and a tenth transistor M10;

[0195] A gate of the M9 is electrically connected with the control node NC, a source of the M9 is electrically connected with the high voltage terminal VGH, and a drain of the M9 is electrically connected with the output control node NS;

[0196] A gate of the M10 is electrically connected with the control node NC, a drain of the M10 is electrically connected with the output control node NS, and a source of the M10 is electrically connected with the low voltage terminal VGL;

[0197] The output circuit comprises an eleventh transistor M11 and a twelfth transistor M12;

[0198] The gate of the M11 is electrically connected with the output control node NS, the source of the M11 is electrically connected with the high voltage terminal VGH, and the drain of the M11 is electrically connected with the driving output terminal OT;

[0199] The gate of the M12 is electrically connected with the output control node NS, the drain of the M12 is electrically connected with the driving output terminal OT, and the source of the M12 is electrically connected with the low voltage terminal VGL.

[0200] FIG. 11B is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 11A.

[0201] As shown in FIG. 11B, at least one embodiment of the driving circuit shown in FIG. 11A works as follows,

[0202] In the first write stage t1, the ECK provides a low voltage signal, and the driving circuit realizes the function of writing signals, as shown in FIG. 11C, the M1 is opened, the M2 is closed, the potential of the N1 is high voltage, the M4 is opened, the M3 is opened, the ESTV provides a low voltage signal, the ESTV writes the low voltage signal into the NC, the M5 is closed, the M8 is closed, the M9 is opened, the M10 is closed, the potential of the NS is high voltage, the M11 is closed, the M12 is opened, and the OT outputs a low voltage signal;

[0203] In the first latch stage t2, the ECK provides a high voltage signal, and the driving circuit realizes the function of latching the signals written at the previous moment, as shown in FIG. 11D, the M1 is closed, the M2 is opened, the potential of the N1 is low voltage, the M4 is closed, the M3 is closed, the potential of the NC remains low voltage, the M9 is opened, the M10 is closed, the potential of the NS is high voltage, the NC remains the level at the previous moment, the NS remains the level at the previous moment, the M11 is closed, the M12 is opened, and the OT outputs a low voltage signal;

[0204] In the second write stage t3, the ECK provides a low voltage signal, and the driving circuit realizes the function of writing signals, as shown in FIG. 11E, the M1 is opened, the M2 is closed, the ESTV provides a high voltage signal, the potential of the N1 is high voltage, the M4 is opened, the M3 is opened, the potential of the NC is high voltage, the M5 and the M8 are closed, the M9 is closed, the M10 is opened, the potential of the NS is low voltage, the M11 is opened, the M12 is closed, and the OT outputs a high voltage signal;

[0205] In the second latch stage t4, the ECK provides a high voltage signal, and the driving circuit realizes the function of latching the signal written at the previous moment, as shown in FIG. 11F, M1 is closed, M2 is opened, the potential of N1 is low voltage, M3 and M4 are both closed, the potential of NC remains high voltage, M9 is closed, M10 is opened, the potential of NS is low voltage, M7 is closed, M5 and M6 are both opened, the high voltage signal is continuously written into NC, the potential of NS remains the level at the previous moment, the potential of NC remains the level at the previous moment, M11 is opened, M12 is closed, and OT outputs a high voltage signal.

[0206] In the third write stage t5, the ECK provides a low voltage signal, and the driving circuit realizes the function of writing the signal, the ECK provides a low voltage signal, as shown in FIG. 11G, M1 is opened, M2 is closed, the potential of N1 is high voltage, M3 and M4 are both opened, ESTV writes a low voltage signal into NC, M9 is opened, M10 is closed, the potential of NS is high voltage, M11 is closed, M12 is opened, and OT outputs a low voltage signal.

[0207] In the third latch stage t6, the ECK provides a high voltage signal, and the driving circuit realizes the function of latching the signal written at the previous moment, as shown in FIG. 11H, M1 is closed, M2 is opened, the potential of N1 is low voltage, M3 and M4 are closed, the potential of NC remains low voltage, M9 is opened, M10 is closed, the potential of NS is high voltage, M7 and M8 are both opened, the low voltage signal is continuously written into NS, the potential of NC remains the level at the previous moment, the potential of NS remains the level at the previous moment, M11 is closed, M12 is opened, and OT outputs a low voltage signal.

[0208] As shown in FIG. 12A, on the basis of at least one embodiment of the driving circuit shown in FIG. 9,

[0209] The writing circuit comprises a first transistor M1;

[0210] The gate of M1 is electrically connected with the first control clock signal end ECK, the source of M1 is electrically connected with the input end ESTV, and the drain of M1 is electrically connected with the control node NC;

[0211] The first control sub-circuit comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0212] The gate of the fifth transistor M5 is electrically connected with the first control clock signal end ECK, the drain of the fifth transistor M5 is electrically connected with the low voltage end VGL, and the source of the fifth transistor M5 is electrically connected with the drain of the sixth transistor M6;

[0213] A gate of the sixth transistor M6 is electrically connected with the output control node NS, and a source of the sixth transistor M6 is electrically connected with the control node NC;

[0214] A gate of the seventh transistor M7 is electrically connected with the output control node NS, a source of the seventh transistor M7 is electrically connected with the control node NC, and a drain of the seventh transistor M7 is electrically connected with a source of the eighth transistor M8;

[0215] A gate of the eighth transistor M8 is electrically connected with a second control clock signal end ECB, and a drain of the eighth transistor M8 is electrically connected with a high voltage end VGH;

[0216] The second control sub-circuit includes a ninth transistor M9 and a tenth transistor M10;

[0217] A gate of the ninth transistor M9 is electrically connected with the control node NC, a source of the ninth transistor M9 is electrically connected with the high voltage end VGH, and a drain of the ninth transistor M9 is electrically connected with the output control node NS;

[0218] A gate of the tenth transistor M10 is electrically connected with the control node NC, a drain of the tenth transistor M10 is electrically connected with the output control node NS, and a source of the tenth transistor M10 is electrically connected with a low voltage end VGL;

[0219] The output circuit includes an eleventh transistor M11 and a twelfth transistor M12;

[0220] A gate of the eleventh transistor M11 is electrically connected with the output control node NS, a source of the eleventh transistor M11 is electrically connected with the high voltage end VGH, and a drain of the eleventh transistor M11 is electrically connected with the driving output end OT;

[0221] A gate of the twelfth transistor M12 is electrically connected with the output control node NS, a drain of the twelfth transistor M12 is electrically connected with the driving output end OT, and a source of the twelfth transistor M12 is electrically connected with the low voltage end VGL.

[0222] In at least one embodiment shown in FIG. 12A, M1 is a p-type transistor, M5 and M6 are n-type transistors, M7 and M8 are p-type transistors, M9 is a p-type transistor, M10 is an n-type transistor, M11 is a p-type transistor, and M12 is an n-type transistor;

[0223] M1 is an LTPS transistor, M5 and M6 are oxide transistors, M7 and M8 are LTPS transistors, M9 is an LTPS transistor, M10 is an oxide transistor, M11 is an LTPS transistor, and M12 is an oxide transistor.

[0224] FIG. 12B is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 12A.

[0225] As shown in Fig. 12B, at least one embodiment of the driving circuit shown in Fig. 12A functions as follows when working,

[0226] At the first write stage t1, ECK provides a low voltage signal, ECB provides a high voltage signal, and the driving circuit functions to write a signal, as shown in Fig. 12C, M1 is on, ESTV provides a low voltage signal, the potential of NC is a low voltage, M9 is on, M10 is off, the potential of NS is a high voltage, M11 is off, M12 is on, and OT outputs a low voltage signal;

[0227] At the first first latch stage t11, ECK provides a high voltage signal, ECB provides a high voltage signal, and the potential of NC is a low voltage, and the driving circuit functions to latch the signal written at the previous moment, as shown in Fig. 12D, M1 is off, M5 and M6 are on, the potential of NC remains a low voltage, M9 is on, M10 is off, M7 is off, M8 is off, the potential of NS remains a high voltage, M11 is off, M12 is on, and OT outputs a low voltage signal;

[0228] At the second first latch stage t21, ECK provides a high voltage signal, ECB provides a low voltage signal, and the driving circuit functions to latch the signal written at the previous moment, as shown in Fig. 12E, M1 is off, the potential of NC remains a low voltage, M10 is off, M9 is on, a high voltage signal is continuously written into NS, M7 is off, M8 is on, M5 and M6 are both on, a low voltage signal is continuously written into NC; M11 is off, M12 is on, and OT outputs a low voltage signal;

[0229] At the second write stage t3, ECK provides a low voltage signal, ECB provides a high voltage signal, and the driving circuit functions to write a signal, as shown in Fig. 12F, M1 is on, ESTV provides a high voltage signal, the potential of NC is a high voltage, M9 is off, M10 is on, the potential of NS is a low voltage, M11 is on, M12 is off, and OT outputs a high voltage signal;

[0230] At the first second latch stage t12, ECK provides a high voltage signal, ECB provides a high voltage signal, as shown in Fig. 12G, M1 is off, the potential of NC remains a high voltage, M9 is off, M10 is on, the potential of NS remains a low voltage, M6 and M7 are off, the charging path from NS to NC is off, at this moment, NC is in a floating state, the potential of NC remains a high voltage; M12 is off, M11 is on, and OT outputs a low voltage signal;

[0231] In the second second latch stage t22, ECK provides a high voltage signal, ECB provides a low voltage signal, and the potential of NC is high voltage, the driving circuit realizes the function of latching the signal written at the previous moment; as shown in FIG. 12H, M1 is closed, the potential of NC remains high voltage, M9 is closed, M10 is opened, continuously writes low voltage signal into NS, M7 and M8 are both opened, continuously writes high voltage signal into NC, the potential of NS is low voltage, M11 is opened, M12 is closed, OT outputs high voltage signal;

[0232] In the third second latch stage t32, ECK provides a high voltage signal, ECB provides a high voltage signal, and the potential of NC is high voltage signal, the driving circuit realizes the function of keeping the signal written at the previous moment, as shown in FIG. 12I, M1 is closed, the potential of NC remains high voltage, M9 is closed, M10 is opened, continuously provides low voltage signal to NS, M6 and M8 are closed, the charging path of NS to NC is closed, NC is in floating state, the potential of NC remains high voltage, M11 is opened, M12 is closed, OT outputs high voltage signal;

[0233] In the third write stage t5, ECK provides a low voltage signal, ECB provides a high voltage signal, the driving circuit realizes the function of writing signal, as shown in FIG. 12J, M1 is opened, ESTV provides low voltage signal to NC, the potential of NC is low voltage, M9 is opened, M10 is closed, the potential of NS is high voltage, M5 and M8 are closed, M11 is closed, M12 is opened, OT outputs low voltage signal;

[0234] In the first third latch stage t13, ECK provides a high voltage signal, ECB provides a high voltage signal, and the potential of NC is low voltage, the driving circuit realizes the function of latching the signal written at the previous moment, as shown in FIG. 12K, M1 is closed, the potential of NC remains low voltage, M9 is opened, M10 is closed, the potential of NS is high voltage, M7 and M8 are closed, M5 and M6 are opened, continuously writes low voltage signal into NC, M11 is closed, M12 is opened, OT outputs low voltage signal;

[0235] In the second third latch stage t23, ECK provides a high voltage signal, ECB provides a low voltage signal, and the potential of NC is low voltage, the driving circuit realizes the function of latching the signal written at the previous moment, as shown in FIG. 12L, M1 is closed, M8 is opened, the potential of NC remains low voltage, M10 is closed, M9 is opened, continuously writes high voltage signal into NS, the potential of NS is high voltage, M7 is closed, M5 and M6 are both opened, continuously writes low voltage signal into NC, the potential of NC and the potential of NS remain the level at the previous moment, M11 is closed, M12 is opened, OT outputs low voltage signal;

[0236] In the third third latch stage t33, when ECK provides a high voltage signal, ECB provides a high voltage signal, and the potential of NC is a low voltage, the driving circuit realizes the function of latching the write signal at the previous moment, as shown in FIG. 12M, M1 is closed, M8 is closed, the potential of NC remains a low voltage, M10 is closed, M9 is opened, a high voltage signal is continuously written into NS, M7 is closed, M5 and M6 are opened, a first voltage signal is continuously written into NC, the potential of NC and the potential of NS remain the levels at the previous moment, M11 is closed, M12 is opened, and OT outputs a low voltage signal.

[0237] The difference between at least one embodiment of the driving circuit shown in FIG. 13A and at least one embodiment of the driving circuit shown in FIG. 11A is as follows:

[0238] The second write sub-circuit does not include a four-transistor M4.

[0239] FIG. 13B is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 13A.

[0240] In at least one embodiment of the driving circuit shown in FIG. 13A, the driving capability can be increased by increasing the width-length ratio of M3.

[0241] In at least one embodiment of the present disclosure, the driving module can include a plurality of stages of driving circuits; an input end of a first stage of driving circuits can be electrically connected with a starting voltage end STV, a driving output end of an nth stage of driving circuits can be electrically connected with an input end of an nth+m stage of driving circuits, and m can be a positive integer;

[0242] FIG. 14 is a working timing diagram of at least one embodiment of the driving module;

[0243] FIG. 15 is a working timing diagram of at least one embodiment of the driving module.

[0244] In FIGS. 14 and 15, the driving output end of the first stage of driving circuits is labeled as OT1, the driving output end of the second stage of driving circuits is labeled as OT2, the driving output end of the third stage of driving circuits is labeled as OT3, the driving output end of the fourth stage of driving circuits is labeled as OT4, the driving output end of the fifth stage of driving circuits is labeled as OT5, the driving output end of the sixth stage of driving circuits is labeled as OT6, the driving output end of the seventh stage of driving circuits is labeled as OT7, the driving output end of the eighth stage of driving circuits is labeled as OT8, the driving output end of the ninth stage of driving circuits is labeled as OT9, and the driving output end of the tenth stage of driving circuits is labeled as OT10.

[0245] As shown in FIGS. 14 and 15, by modulating the pulse width of the starting voltage provided by STV, the pulse width of the driving signal output by each stage of driving circuits can be controlled.

[0246] The driving method provided by the embodiments of the present disclosure is applied to the driving circuit, and the driving method comprises the following steps:

[0247] The write circuit writes the potential of the control node according to the input signal provided by the input terminal under the control of the first control clock signal;

[0248] The control circuit controls the potential of the output control node according to the potential of the control node;

[0249] The output circuit controls the driving output terminal to output the driving signal under the control of the potential of the output control node.

[0250] In at least one embodiment of the present disclosure, the write circuit comprises a first write sub-circuit and a second write sub-circuit; the control circuit comprises a first control sub-circuit and a second control sub-circuit; the driving period comprises a first write stage and a first latch stage arranged in sequence; and the driving method comprises the following steps:

[0251] In the first write stage, the first write sub-circuit writes the first voltage signal to the first node under the control of the first control clock signal, the second write sub-circuit writes the second voltage signal provided by the input terminal to the control node under the control of the first control clock signal, the second control sub-circuit writes the first voltage signal to the output control node under the control of the potential of the control node, and the output circuit writes the second voltage signal to the driving output terminal under the control of the potential of the output control node;

[0252] In the first latch stage, the first write sub-circuit writes the second voltage signal to the first node under the control of the first control clock signal, the second write sub-circuit maintains the potential of the control node as the second voltage, the second control sub-circuit writes the first voltage signal to the output control node under the control of the potential of the control node, the first control sub-circuit writes the second voltage signal to the control node under the control of the potential of the first node and the potential of the output control node, and the output circuit writes the second voltage signal to the driving output terminal under the control of the potential of the output control node.

[0253] In at least one embodiment of the present disclosure, the driving period further comprises a second write stage and a second latch stage arranged in sequence after the first latch stage; and the driving method comprises the following steps:

[0254] In the second write stage, the first write sub-circuit writes the first voltage signal to the first node under the control of the first control clock signal, the second write sub-circuit writes the first voltage signal provided by the input terminal to the control node under the control of the first control clock signal, the second control sub-circuit controls writing of the second voltage signal to the output control node under the control of the potential of the control node, and the output circuit writes the first voltage signal to the driving output terminal under the control of the output control node.

[0255] In the second write stage, the first write sub-circuit writes the first voltage signal to the first node under the control of the first control clock signal, the second write sub-circuit writes the first voltage signal provided by the input terminal to the control node under the control of the first control clock signal, the second control sub-circuit controls writing of the second voltage signal to the output control node under the control of the potential of the control node, and the output circuit writes the first voltage signal to the driving output terminal under the control of the output control node.

[0256] In at least one embodiment of the present disclosure, the control circuit includes a first control sub-circuit and a second control sub-circuit; the driving period includes a first write stage and a first latch stage arranged after the first write stage; and the driving method includes:

[0257] In the first write stage, the write circuit writes the second voltage signal provided by the input terminal to the control node under the control of the first control clock signal; the second control sub-circuit writes the first voltage signal to the output control node under the control of the potential of the control node; and the first control sub-circuit maintains the potential of the control node under the control of the first control clock signal and the second control clock signal; the output circuit writes the second voltage signal to the driving output terminal under the control of the potential of the output control node.

[0258] In the first write stage, the write circuit writes the second voltage signal provided by the input terminal to the control node under the control of the first control clock signal; the second control sub-circuit writes the first voltage signal to the output control node under the control of the potential of the control node; and the first control sub-circuit maintains the potential of the control node under the control of the first control clock signal and the second control clock signal; the output circuit writes the second voltage signal to the driving output terminal under the control of the potential of the output control node.

[0259] In at least one embodiment of the present disclosure, the driving period further includes a second write stage and a second latch stage arranged in sequence; the second write stage is arranged after the first latch stage; and the driving method further includes:

[0260] In the second write stage, the first write sub-circuit writes the first voltage signal provided by the input terminal to the control node under the control of the first control clock signal, the second control sub-circuit writes the second voltage signal to the output control node under the control of the potential of the control node, and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node.

[0261] In the second latch stage, the second control sub-circuit writes the second voltage signal to the output control node under the control of the potential of the control node, the first control sub-circuit maintains the potential of the control node, and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node.

[0262] In at least one embodiment of the present disclosure, the driving period includes a first write stage and a first latch stage arranged in sequence; and the driving method includes:

[0263] In the first write stage, the write circuit writes the second voltage signal provided by the input terminal to the control node under the control of the potential of the first control clock signal; the control circuit writes the first voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the second voltage signal to the driving output terminal under the control of the potential of the output control node.

[0264] In the first latch stage, the write circuit maintains the potential of the control node as the second voltage under the control of the potential of the first control clock signal; the control circuit writes the first voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the second voltage signal to the driving output terminal under the control of the potential of the output control node.

[0265] In at least one embodiment of the present disclosure, the driving period further includes a second write stage and a second latch stage arranged in sequence after the first latch stage; and the driving method includes:

[0266] In the second write stage, the write circuit writes the first voltage signal provided by the input terminal to the control node under the control of the potential of the first control clock signal; the control circuit writes the second voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node.

[0267] In the second latch stage, the write circuit maintains the potential of the control node as the first voltage under the control of the potential of the first control clock signal; the control circuit writes the second voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node.

[0268] The display device described in the embodiments of the present disclosure includes the driving circuit described above.

[0269] The above is the preferred embodiment of the present disclosure, it should be noted that for ordinary skilled in the art, without departing from the principles of the present disclosure described in the premise, can also be made several improvements and refinements, these improvements and refinements should also be considered the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a writing circuit, a control circuit and an output circuit; the writing circuit is electrically connected with a first control clock signal terminal, an input terminal and a control node respectively, for controlling a potential of the control node according to an input signal provided by the input terminal under control of a first control clock signal provided by the first control clock signal terminal; the control circuit is electrically connected with the control node and an output control node respectively, for controlling a potential of the output control node according to the potential of the control node; the output circuit is electrically connected with the output control node and a driving output terminal respectively, for controlling the driving output terminal to output a driving signal under control of the potential of the output control node.

2. The drive circuit of claim 1, wherein, the writing circuit comprises a first writing sub-circuit and a second writing sub-circuit; the first writing sub-circuit is electrically connected with the first control clock signal terminal and a first node respectively, for controlling a potential of the first node under control of the first control clock signal; the second writing sub-circuit is electrically connected with the input terminal, the first control clock signal terminal and the control node respectively, for controlling the control node to be in communication or disconnected with the input terminal under control of the first control clock signal.

3. The drive circuit of claim 2, wherein, the second writing sub-circuit is also electrically connected with the first node, for controlling the control node to be in communication or disconnected with the input terminal under control of the potential of the first node.

4. The drive circuit of claim 2 or 3, wherein, the first writing sub-circuit is also electrically connected with a first voltage terminal and a second voltage terminal respectively, for controlling the first node to be in communication or disconnected with the first voltage terminal and the second voltage terminal under control of the first control clock signal.

5. The drive circuit of claim 2 or 3, wherein, the control circuit comprises a first control sub-circuit and a second control sub-circuit; the first control sub-circuit is electrically connected with the first node, the first voltage terminal, the second voltage terminal, the control node, the first control clock signal terminal and the output control node respectively, for controlling the control node to be in communication or disconnected with the first voltage terminal under control of the potential of the first node and the potential of the output control node, and controlling the control node to be in communication or disconnected with the second voltage terminal under control of the first control clock signal and the potential of the output control node; the second control sub-circuit is electrically connected with the control node, the first voltage terminal, the second voltage terminal and the output control node respectively, for controlling the output control node to be in communication or disconnected with the first voltage terminal under control of the potential of the control node, and controlling the output control node to be in communication or disconnected with the second voltage terminal under control of the potential of the control node.

6. The drive circuit of claim 1, wherein, the control circuit comprises a first control sub-circuit and a second control sub-circuit; The first control sub-circuit is electrically connected with the control node, the first control clock signal end, the second voltage end, the first voltage end, the second control clock signal end and the output control node respectively, and is used for controlling the control node to be in communication or disconnection with the second voltage end under the control of the first control clock signal and the potential of the output control node, and controlling the control node to be in communication or disconnection with the first voltage end under the control of the second control clock signal provided by the second control clock signal end and the potential of the output control node. The second control sub-circuit is electrically connected with the control node, the first voltage end, the second voltage end and the output control node respectively, and is used for controlling the output control node to be in communication or disconnection with the first voltage end and the second voltage end under the control of the potential of the control node.

7. The drive circuit of claim 1 or 5, wherein, The write circuit is used for controlling the input end to be in communication or disconnection with the control node under the control of the first control clock signal.

8. The drive circuit of claim 1, 2, 3, or 6, wherein, The output circuit is further electrically connected with the first voltage end and the second voltage end respectively, and is used for controlling the driving output end to be in communication or disconnection with the first voltage end and the second voltage end under the control of the potential of the output control node.

9. The drive circuit of claim 2, wherein, The first write sub-circuit comprises a first transistor and a second transistor. The gate of the first transistor is electrically connected with the first control clock signal end, the first pole of the first transistor is electrically connected with the first voltage end, and the second pole of the first transistor is electrically connected with the first node. The gate of the second transistor is electrically connected with the first control clock signal end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the second voltage end.

10. The drive circuit of claim 2, wherein, The second write sub-circuit comprises a third transistor. The gate of the third transistor is electrically connected with the first control clock signal end, the first pole of the third transistor is electrically connected with the input end, and the second pole of the third transistor is electrically connected with the control node.

11. The drive circuit of claim 3, wherein, The second write sub-circuit comprises a third transistor and a fourth transistor. The gate of the third transistor is electrically connected with the first control clock signal end, the first pole of the third transistor is electrically connected with the input end, and the second pole of the third transistor is electrically connected with the control node. The gate of the fourth transistor is electrically connected with the first node, the first pole of the fourth transistor is electrically connected with the input end, and the second pole of the fourth transistor is electrically connected with the control node.

12. The drive circuit of claim 5, wherein, The first control sub-circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. The gate of the fifth transistor is electrically connected with the first node, the first pole of the fifth transistor is electrically connected with the first voltage end, and the second pole of the fifth transistor is electrically connected with the first pole of the sixth transistor. The gate of the sixth transistor is electrically connected with the output control node, and the second pole of the sixth transistor is electrically connected with the control node. The gate of the seventh transistor is electrically connected with the output control node, the first pole of the seventh transistor is electrically connected with the control node, and the second pole of the seventh transistor is electrically connected with the first voltage end. The gate of the eighth transistor is electrically connected with the output control node, the first pole of the eighth transistor is electrically connected with the control node, and the second pole of the eighth transistor is electrically connected with the second voltage end. A gate of the seventh transistor is electrically connected with the output control node, a first pole of the seventh transistor is electrically connected with the control node, and a second pole of the seventh transistor is electrically connected with a first pole of the eighth transistor; A gate of the eighth transistor is electrically connected with the first control clock signal end, and a second pole of the eighth transistor is electrically connected with the second voltage end.

13. The drive circuit of claim 5, wherein, The second control sub-circuit comprises a ninth transistor and a tenth transistor; A gate of the ninth transistor is electrically connected with the control node, a first pole of the ninth transistor is electrically connected with the first voltage end, and a second pole of the ninth transistor is electrically connected with the output control node; A gate of the tenth transistor is electrically connected with the control node, a first pole of the tenth transistor is electrically connected with the output control node, and a second pole of the tenth transistor is electrically connected with the second voltage end.

14. The drive circuit of claim 6, wherein, The first control sub-circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; A gate of the fifth transistor is electrically connected with the first control clock signal end, a first pole of the fifth transistor is electrically connected with the second voltage end, and a second pole of the fifth transistor is electrically connected with a first pole of the sixth transistor; A gate of the sixth transistor is electrically connected with the output control node, and a second pole of the sixth transistor is electrically connected with the control node; A gate of the seventh transistor is electrically connected with the output control node, a first pole of the seventh transistor is electrically connected with the control node, and a second pole of the seventh transistor is electrically connected with a first pole of the eighth transistor; A gate of the eighth transistor is electrically connected with the second control clock signal end, and a second pole of the eighth transistor is electrically connected with the first voltage end.

15. The drive circuit of claim 7, wherein, The write-in circuit comprises a first transistor; A gate of the first transistor is electrically connected with the first control clock signal end, a first pole of the first transistor is electrically connected with the input end, and a second pole of the first transistor is electrically connected with the control node.

16. The drive circuit of claim 8, wherein, The output circuit comprises an eleventh transistor and a twelfth transistor; A gate of the eleventh transistor is electrically connected with the output control node, a first pole of the eleventh transistor is electrically connected with the first voltage end, and a second pole of the eleventh transistor is electrically connected with the driving output end; A gate of the twelfth transistor is electrically connected with the output control node, a first pole of the twelfth transistor is electrically connected with the driving output end, and a second pole of the twelfth transistor is electrically connected with the second voltage end.

17. A driving method applied to the driving circuit in any one of claims 1 to 16, the driving method comprising: The write-in circuit obtains the potential of the control node according to the input signal provided by the input end under the control of the first control clock signal; The control circuit controls the potential of the output control node according to the potential of the control node; The output circuit controls the driving output end to output the driving signal under the control of the potential of the output control node.

18. The driving method of claim 17, wherein, The write circuit comprises a first write sub-circuit and a second write sub-circuit; the control circuit comprises a first control sub-circuit and a second control sub-circuit; the driving period comprises a first write stage and a first latch stage arranged in sequence; and the driving method comprises: In the first write stage, the first write sub-circuit writes the first voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit writes the second voltage signal provided by the input end into the control node under the control of the first control clock signal, the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the second voltage signal into the driving output end under the control of the potential of the output control node; In the first latch stage, the first write sub-circuit writes the second voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit maintains the potential of the control node as the second voltage, the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, the first control sub-circuit writes the second voltage signal into the control node under the control of the potential of the first node and the potential of the output control node, and the output circuit writes the second voltage signal into the driving output end under the control of the potential of the output control node.

19. The driving method of claim 18, wherein, The driving period further comprises a second write stage and a second latch stage arranged in sequence after the first latch stage; and the driving method comprises: In the second write stage, the first write sub-circuit writes the first voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit writes the first voltage signal provided by the input end into the control node under the control of the first control clock signal, the second control sub-circuit controls to write the second voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the first voltage signal into the driving output end under the control of the output control node; In the second latch stage, the first write sub-circuit writes the second voltage signal into the first node under the control of the first control clock signal, the second write sub-circuit maintains the potential of the control node as the first voltage under the control of the first control clock signal, the second control sub-circuit writes the second voltage signal into the output control node under the control of the potential of the control node, the first control sub-circuit writes the first voltage signal into the control node under the control of the potential of the output control node and the potential of the first node, and the output circuit writes the first voltage signal into the driving output end under the control of the output control node.

20. The driving method of claim 17, wherein, The control circuit comprises a first control sub-circuit and a second control sub-circuit; the driving period comprises a first write stage and a first latch stage arranged in sequence after the first write stage; and the driving method comprises: In the first write stage, the write circuit writes the second voltage signal provided by the input terminal into the control node under the control of the first control clock signal; the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the first control sub-circuit maintains the potential of the control node under the control of the first control clock signal and the second control clock signal; the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node. In the first latch stage, the write circuit maintains the potential of the control node as the second voltage under the control of the first control clock signal In the first write stage, the write circuit writes the second voltage signal provided by the input terminal into the control node under the control of the first control clock signal; the second control sub-circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the first control sub-circuit maintains the potential of the control node under the control of the first control clock signal and the second control clock signal; the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node.

21. The driving method of claim 20, wherein, The driving cycle further comprises a second write stage and a second latch stage arranged in sequence, and the second write stage is arranged after the first latch stage; the driving method further comprises: In the second write stage, the first write sub-circuit writes the first voltage signal provided by the input terminal into the control node under the control of the first control clock signal, the second control sub-circuit writes the second voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the first voltage signal into the driving output terminal under the control of the potential of the output control node. In the second latch stage, the second control sub-circuit writes the second voltage signal into the output control node under the control of the potential of the control node, the first control sub-circuit maintains the potential of the control node, and the output circuit writes the first voltage signal into the driving output terminal under the control of the potential of the output control node.

22. The driving method of claim 17, wherein, The driving cycle comprises a first write stage and a first latch stage arranged in sequence; the driving method comprises: In the first write stage, the write circuit writes the second voltage signal provided by the input terminal into the control node under the control of the potential of the first control clock signal; the control circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node. In the first latch stage, the write circuit maintains the potential of the control node as the second voltage under the control of the potential of the first control clock signal, the control circuit writes the first voltage signal into the output control node under the control of the potential of the control node, and the output circuit writes the second voltage signal into the driving output terminal under the control of the potential of the output control node.

23. The driving method of claim 22, wherein, The driving cycle further comprises a second write stage and a second latch stage arranged in sequence, and the second write stage is arranged after the first latch stage; the driving method comprises: In the second write stage, the write circuit writes the first voltage signal provided by the input terminal to the control node under the control of the potential of the first control clock signal; the control circuit writes the second voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node. In the second latch stage, the write circuit maintains the potential of the control node as the first voltage under the control of the potential of the first control clock signal; the control circuit writes the second voltage signal to the output control node under the control of the potential of the control node; and the output circuit writes the first voltage signal to the driving output terminal under the control of the potential of the output control node.

24. A display device comprising the driving circuit according to any one of claims 1 to 16.

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