Semiconductor device, electronic device, transistor stack, and manufacturing method therefor

Abstract

The present disclosure provides a semiconductor device, an electronic device, a transistor stack, and a manufacturing method therefor. The manufacturing method comprises: forming a stack structure by one etching on a semiconductor substrate; forming, on the semiconductor substrate, an oxide layer covering the stack structure; forming, within a gate region of the transistor stack, a dummy gate structure covering the oxide layer; forming a first transistor on the basis of a first active structure covered with the oxide layer; flipping the wafer and removing the semiconductor substrate; forming a second transistor on the basis of a second active structure covered with the oxide layer; and oxidizing a first portion of a first dummy gate structure to form a first gate isolation structure between a first gate structure and a second gate structure; and / or oxidizing a first portion of a second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure.

Description

Semiconductor device, electronic device, stacked transistors and methods of making the same

[0001] Cross Reference to Related Applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Application No. 202411306425.5, filed on September 19, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the field of semiconductor, and in particular, to a semiconductor device, an electronic device, stacked transistors and methods of making the same. BACKGROUND

[0004] In the context of Moore's Law deepening, it is a hot issue in the current industry to continue to promote the miniaturization of transistors. Stacked transistors, by integrating two or more layers of transistors in the vertical space, achieve further improvement of transistor integration density, and become one of the important technologies to continue the miniaturization of integrated circuits.

[0005] In some schemes for preparing stacked transistors, the active regions of the upper and lower homologous transistors are formed by etching, and the stacked transistors are fabricated on the front and back surfaces of the wafer by developing. This can also be referred to as a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, high aspect ratio processes need to be used multiple times, and it is difficult to control the etching height in the process of forming the gate isolation structure between the upper and lower gate structures. Therefore, there is a certain optimization space for the "self-aligned flip transistor" scheme. SUMMARY

[0006] The present disclosure provides a semiconductor device, an electronic device, stacked transistors and methods of making the same.

[0007] The first aspect of the present disclosure provides a method for manufacturing a stacked transistor. The method comprises: etching a semiconductor substrate to form a stack structure, wherein the stack structure comprises: a first active structure and a second active structure; the first active structure and the second active structure are stacked in a first direction, the first active structure is farther away from the semiconductor substrate than the second active structure, and the first direction is perpendicular to the semiconductor substrate; forming an oxide layer covering the stack structure on the semiconductor substrate; forming a dummy gate structure covering the oxide layer in a gate region of the stacked transistor; the dummy gate structure comprises a first dummy gate structure and a second dummy gate structure; based on the first active structure covered by the oxide layer, forming a first transistor, wherein the first transistor comprises: a first gate structure formed based on the first dummy gate structure; reversing and removing the semiconductor substrate; based on the second active structure covered by the oxide layer, forming a second transistor, wherein the second transistor comprises: a second gate structure formed based on the second dummy gate structure; performing an oxidation process on a first part of the first dummy gate structure to form a first gate isolation structure between the first gate structure and the second gate structure; and / or performing an oxidation process on a first part of the second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure; wherein the first part of the first dummy gate structure is a part of the first dummy gate structure close to the second dummy gate structure, the first part of the second dummy gate structure is a part of the second dummy gate structure close to the first dummy gate structure, and the oxide layer protects the stack structure during the oxidation process.

[0008] The second aspect of the present disclosure provides a stacked transistor. The stacked transistor can be manufactured using the method of any one of the first aspect. The stacked transistor comprises: a first transistor; a second transistor, the first transistor and the second transistor are arranged opposite to each other, and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned; the first gate structure is formed based on the first dummy gate structure; the second gate structure is formed based on the second dummy gate structure; wherein a gate isolation structure is formed between the first gate structure and the second gate structure, the gate isolation structure is obtained by performing an oxidation process on a first part of the first dummy gate structure and / or a first part of the second dummy gate structure, the first part of the first dummy gate structure is a part of the first dummy gate structure close to the second dummy gate structure, and the first part of the second dummy gate structure is a part of the second dummy gate structure close to the first dummy gate structure.

[0009] The third aspect of the present disclosure provides a semiconductor device. The semiconductor device comprises the stacked transistor of any one of the first aspect.

[0010] The fourth aspect of the present disclosure provides an electronic device, comprising: a circuit board and the semiconductor device according to any one of the third aspect of the present disclosure.

[0011] Compared with the prior art, the present disclosure has the following beneficial effects:

[0012] In the embodiments of the present disclosure, by etching a stack structure on a semiconductor substrate at one time, the active regions of the first transistor and the second transistor in the stacked transistor can be self-aligned. Then, a pseudo-gate structure shared by the first transistor and the second transistor is formed. In the process of forming the front-side transistor and / or the back-side transistor, a part of the pseudo-gate structure is removed, and the remaining pseudo-gate structure is subjected to an oxidation treatment to form a gate isolation structure in the stacked transistor by using the pseudo-gate structure. Then, based on the active structure, a self-aligned gate structure can be formed, and finally the first transistor and the second transistor are completely self-aligned.

[0013] In this way, on the one hand, fewer high-aspect-ratio processes can be used to further optimize the "self-aligned flip-chip transistor" scheme to be more compatible with the complete self-alignment of various types of transistors; on the other hand, by oxidizing the pseudo-gate structure to form the gate isolation structure between the front-side transistor and the back-side transistor, the process difficulty can be reduced to some extent, and the quality of the gate isolation structure can be improved.

[0014] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of embodiments of the present disclosure.

[0016] FIG. 1 is an implementation flow diagram of a preparation method of a stacked transistor according to an embodiment of the present disclosure.

[0017] FIG. 2 is a structural schematic diagram of a stacked transistor according to an embodiment of the present disclosure.

[0018] FIGS. 3 to 37 are structural schematic diagrams of a stacked transistor in a preparation process according to an embodiment of the present disclosure.

[0019] FIGS. 38 to 55 are structural schematic diagrams of a stacked transistor in a preparation process according to an embodiment of the present disclosure.

[0020] Reference numerals in the figures: Stacked transistor 10; First transistor 11; Second transistor 12; First source / drain structure 112; First interlayer dielectric layer 113; First gate structure 114; First source / drain metal 115; First metal interconnect layer 116; Second source / drain structure 122; Second interlayer dielectric layer 123; Second gate structure 124; Second source / drain metal 125; Second metal interconnect layer 126; Semiconductor substrate 20; Initial stacked structure 21; Initial barrier layer 22; Stacked structure 23; Barrier layer 24; Shallow trench isolation structure 25; Dummy gate structure 26; Dummy gate sidewall 27; First active structure 29; First sacrificial layer 30; Second active structure 31; Second sacrificial layer 32 ; Isolation structure 33; Sacrificial layer 34; Channel layer 35; Internal sidewall 36; Filling structure 37; First filling structure 37a; Second filling structure 37b; Isolation layer 38; First isolation structure 41; First dielectric layer 42; Insulating layer 43; Carrier wafer 44; Polysilicon structure 45; Second dielectric layer 46; Second isolation structure 47; First deep trench 48; Oxide layer 50; First pseudo-gate structure 51; First part of the first pseudo-gate structure 511; Second part of the first pseudo-gate structure 512; Second pseudo-gate structure 52; First part of the second pseudo-gate structure 521; Second part of the second pseudo-gate structure 522; First gate isolation structure 53; Second gate isolation structure 54. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure.

[0022] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments disclosed herein. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0023] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0024] In an embodiment, there are two options for the fabrication process of the stacked transistors, the first option is a monolithic option, and the second option is a sequential option.

[0025] The first option is to fabricate an N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET) on the same substrate by repeating the processes of exposure, etching, diffusion, etc., to vertically stack the two transistors. However, the fabrication process of the first option determines that the same-layer transistors of the stacked transistors must be of the same type, and the same-layer transistors must be strictly in the same plane space without alignment deviation. The advantage of the first option is better integration density. The disadvantages of the first option include the following two points: (1) complex process, which requires a large amount of development and optimization of process technology; (2) the polarity of the same-layer transistors is fixed, and the basic complementary metal-oxide-semiconductor (CMOS) circuit must be composed of two layers of transistors, which has poor design flexibility.

[0026] The second option is to fabricate a top-layer (top-layer) transistor on the upper part of a bottom-layer (bottom-layer) transistor that has been fabricated to vertically stack the two transistors. However, the second option currently has the following technical challenges: (1) fabrication of high-quality top-layer transistor active layer; (2) thinning and defect control of the top-layer transistor bonding wafer; (3) alignment error of the upper bottom-layer transistor, which requires extremely high photolithography precision.

[0027] The common technical difficulties faced by the above two options include: (1) thermal stability of the bottom-layer device when fabricating the top-layer device; (2) performance of the top-layer device under low thermal budget; (3) metal interconnection between the top-layer and the bottom-layer transistors.

[0028] To solve the technical problems of the above two options, a flip-chip option for implementing self-aligned stacked transistors is proposed, which forms the active regions of the upper and lower source transistors by etching, and realizes the fabrication of stacked transistors on the front and back surfaces of the wafer by flipping, to overcome the disadvantages of the above two options. This can also be called the "self-aligned flip-chip transistor" option.

[0029] However, in the "self-aligned flip-chip transistor" option, high-aspect-ratio processes need to be used multiple times, and it is difficult to control the etching height in the process of forming the gate isolation structure between the upper and lower gate structures. Therefore, there is a certain optimization space for the "self-aligned flip-chip transistor" option.

[0030] To solve the above technical problems, the present disclosure provides a semiconductor device, an electronic device, a stacked transistor and a preparation method thereof, to optimize the "self-aligned flip transistor" scheme.

[0031] In the present disclosure, the stacked transistor is a semiconductor device that can be applied to structures such as memories, processors, etc.

[0032] FIG. 1 is an implementation flowchart of a preparation method of a stacked transistor according to an embodiment of the present disclosure. Referring to FIG. 1, the preparation method of the stacked transistor can include:

[0033] Step S101: etching on a semiconductor substrate to form a stacked structure, wherein the stacked structure includes: a first active structure and a second active structure; the first active structure and the second active structure are stacked in a first direction, the first active structure is farther away from the semiconductor substrate than the second active structure, and the first direction is perpendicular to the semiconductor substrate;

[0034] Step S102: forming an oxide layer covering the stacked structure on the semiconductor substrate;

[0035] Step S103: forming a pseudo-gate structure covering the oxide layer in the gate region of the stacked transistor; the pseudo-gate structure includes a first pseudo-gate structure and a second pseudo-gate structure;

[0036] Step S104: forming a first transistor based on the first active structure covered with the oxide layer, wherein the first transistor includes: a first gate structure, the first gate structure is formed based on the first pseudo-gate structure;

[0037] Step S105: flip and remove the semiconductor substrate;

[0038] Step S106: forming a second transistor based on the second active structure covered with the oxide layer, wherein the second transistor includes: a second gate structure, the second gate structure is formed based on the second pseudo-gate structure;

[0039] Step S107: oxidizing the first part of the first pseudo-gate structure to form a first gate isolation structure between the first gate structure and the second gate structure; and / or oxidizing the first part of the second pseudo-gate structure to form a second gate isolation structure between the first gate structure and the second gate structure;

[0040] Wherein, the first part of the first pseudo-gate structure is a part of the first pseudo-gate structure close to the second pseudo-gate structure, the first part of the second pseudo-gate structure is a part of the second pseudo-gate structure close to the first pseudo-gate structure, and the oxide layer protects the stacked structure during the oxidation process.

[0041] It can be understood that the first direction in the embodiment of the present disclosure can be a direction perpendicular to the substrate, and the third direction can be a direction parallel to the surface of the substrate, for example, a width direction of the gate structure. The second direction can be a direction perpendicular to the third direction, for example, a length direction of the gate structure. In the third direction, the gate regions and the source-drain regions of the stacked transistors are arranged alternately in sequence, and the gate structures and the source-drain structures of the stacked transistors are arranged alternately in sequence.

[0042] In some embodiments, the material forming the dummy gate structure can be polysilicon.

[0043] It should be noted that the steps shown in FIG. 1 are not exclusive, and other steps can be performed before, after or between any of the steps shown; the order of the steps shown in FIG. 1 can be adjusted according to actual needs.

[0044] It can be understood that by etching on the semiconductor substrate to form a stacked structure, the active regions of the first transistor and the second transistor in the stacked transistor can be self-aligned. Subsequently, a dummy gate structure shared by the first transistor and the second transistor is formed. In the process of forming the front-side transistor and / or the back-side transistor, a part of the dummy gate structure is removed, and the remaining dummy gate structure is subjected to an oxidation treatment to form a gate isolation structure in the stacked transistor using the dummy gate structure. Subsequently, based on the active structure, a self-aligned gate structure can be formed, and finally the first transistor and the second transistor are completely self-aligned.

[0045] In this way, on the one hand, fewer high-aspect-ratio processes can be used to further optimize the "self-aligned flip transistor" scheme to be more compatible with various types of completely self-aligned flip stacked transistors; on the other hand, by oxidizing the dummy gate structure to form a gate isolation structure between the front-side transistor and the back-side transistor, the process difficulty can be reduced to some extent, and the quality of the gate isolation structure can be improved.

[0046] FIG. 2 is a structural schematic diagram of a stacked transistor according to an embodiment of the present disclosure. Referring to FIG. 2, only the nanosheet structure, the gate structure and the source-drain structure of the stacked transistor 10 are shown in the figure.

[0047] In an embodiment, the stacked transistor 10 includes a first transistor and a second transistor, and the first transistor and the second transistor are self-aligned, that is, the first source-drain structure of the first transistor and the second source-drain structure of the second transistor are self-aligned, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0048] In an embodiment, the first transistor and the second transistor can be the same type of transistor. For example, the first transistor and the second transistor can both be fin field effect transistors.

[0049] In an embodiment, the active structure in the stacked transistor 10 can be different according to the type of the stacked transistor. In an example, when the stacked transistor 10 is a fin field effect transistor, the active structure can be a fin structure. When the stacked transistor 10 is a gate-all-around nanosheet (GAA Nanosheet), the active structure can be a stacked nanosheet structure; wherein the stacked nanosheet structure can be formed by alternately deposited silicon layers and silicon germanium layers. When the stacked transistor 10 is a planar transistor, the active structure can be a bulk structure.

[0050] In an embodiment, the stacked transistor 10 shown in FIG. 2 is a gate-all-around nanosheet, and the active structure thereof is a stacked nanosheet structure.

[0051] FIGS. 3-37 are schematic diagrams of structures of a stacked transistor in a preparation process according to an embodiment of the present disclosure. For ease of understanding, (a) in FIGS. 3-37 shows a cross-sectional view along the direction of the dashed line A-A’ in FIG. 2, (b) in FIGS. 3-37 shows a cross-sectional view along the direction of the dashed line B-B’ in FIG. 2, and (c) in FIGS. 3-37 shows a cross-sectional view along the direction of the dashed line C-C’ in FIG. 2. The preparation method of the stacked transistor according to an embodiment of the present disclosure and the stacked transistor 10 prepared thereby will be exemplarily described below in combination with FIGS. 1-37.

[0052] In step S101, the stacked structure 23 is formed on the semiconductor substrate 20 at one time, as shown in FIG. 5.

[0053] It can be understood that on the semiconductor substrate 20, a process such as deposition, epitaxial growth, photolithography, etc. of a material layer can be performed to form a plurality of material layers. Subsequently, the plurality of material layers can be etched by a photolithography process to form the stacked structure 23 at one time.

[0054] In an embodiment, the step of the photolithography process in the present embodiment can include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove the material layer corresponding to the portion of the photoresist material, etc.

[0055] In an embodiment, the stacked structure 23 includes a first active structure 29 and a second active structure 31. The first active structure 29 and the second active structure 31 are sequentially stacked in a first direction. The first active structure 29 is farther away from the semiconductor substrate 20 than the second active structure 31. The first direction is a direction perpendicular to the semiconductor substrate 20.

[0056] It can be understood that the stack structure 23 includes a first active structure 29 and a second active structure 31, the first active structure 29 is used to form an active region of the first transistor 11 (front surface transistor) of the stack transistor 10; the second active structure 31 stacked along the first direction with the first active structure 29 is used to form an active region of the second transistor 12 (back surface transistor) of the stack transistor 10.

[0057] In an example, the first active structure 29 and the second active structure 31 are laminated nanosheet structures, and the first active structure 29 and the second active structure 31 can be formed by alternately deposited silicon layers and silicon germanium layers.

[0058] In some embodiments, a large etching depth can be used when the first active structure 29 and the second active structure 31 are formed by photolithography. For example, the height of the laminated nanosheet structure (which can also be a fin structure or a bulk structure) obtained by etching can be greater than 100 nm. It should be noted that the height of the laminated nanosheet structure can be set according to actual conditions, and the embodiments of the present disclosure do not limit this.

[0059] In some embodiments, after the first active structure 29 and the second active structure 31 are formed by photolithography, ion implantation can be performed in the middle part of the first active structure 29 and the second active structure 31 to electrically isolate the first active structure 29 and the second active structure 31.

[0060] In an embodiment, the ions implanted in the middle part of the first active structure 29 and the second active structure 31 include P-type ions, N-type ions or oxygen ions. In an example, the P-type ions include one or more of boron ions, gallium ions and indium ions; the N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0061] In some embodiments, the stack structure 23 located in the region on both sides of the stack transistor 10 can be removed by a fin cutting process, so that the active structures of the plurality of standard transistor units are disconnected with each other, and isolation between adjacent transistor units is completed.

[0062] In some embodiments, the step S101 includes: forming an initial stack structure 21 and an initial barrier layer 22 on the semiconductor substrate 20, wherein the initial barrier layer 22 is located between the initial stack structure 21 and the semiconductor substrate 20; etching the initial stack structure 21 and the initial barrier layer 22 once to form the stack structure 23 and the barrier layer 24; depositing an oxide material on the semiconductor substrate 20 to form a shallow trench isolation structure 25, and the shallow trench isolation structure 25 wraps the barrier layer 24.

[0063] It can be understood that the semiconductor substrate 20 can be deposited to form an initial barrier layer 22, and the initial barrier layer 22 can be deposited to form an initial stack structure 21. After the initial barrier layer 22 and the initial stack structure 21 are formed, the initial stack structure 21 and the initial barrier layer 22 can be etched from top to bottom at one time to form the stack structure 23 and the barrier layer 24 at one time. At this time, the barrier layer 24 is located between the stack structure 23 and the semiconductor substrate 20. The oxide material is deposited on the semiconductor substrate 20, and the oxide material forms a shallow trench isolation structure 25 that can wrap the barrier layer 24, and the stack structure 23 is exposed outside the shallow trench isolation structure 25.

[0064] It can be understood that the barrier layer 24 and the stack structure 23 are formed by using a one-time etching process, and the barrier layer 24 is opposite to the stack structure 23. After developing, the position of the active structure can be obtained according to the position of the barrier layer 24, which is beneficial to the alignment of the front and back surfaces of the stack transistor 10.

[0065] In an embodiment, the material of the barrier layer 24 formed can have a certain hardness. In an example, the material of the barrier layer 24 formed can be silicon germanium. In an example, the silicon germanium forming the barrier layer 24 is different from the silicon germanium forming the stacked nanosheet structure. For example, the atomic percentage of germanium in the silicon germanium can be different.

[0066] In an embodiment, the oxide forming the shallow trench isolation structure 25 can be a silicon-based oxide (SiO x , x is the number of oxygen atoms), for example, silicon dioxide (SiO2), etc.

[0067] In step S102, an oxide layer 50 covering the stack structure 23 is formed on the semiconductor substrate 20, as shown in FIG. 6.

[0068] It can be understood that the semiconductor material is deposited on the semiconductor structure formed in step S101, and the semiconductor material is subjected to a thermal oxidation process, so that the oxide layer 50 can be formed. The oxide layer 50 covers the surface of the semiconductor substrate 20 and the surface of the stack structure 23.

[0069] It can be understood that the oxide layer 50 is used to protect the stack structure 23 from high temperature.

[0070] In some embodiments, the semiconductor material forming the oxide layer 50 can be set according to actual needs, and the embodiments of the present disclosure are not limited thereto. In an example, the semiconductor material forming the oxide layer 50 can be silicon.

[0071] In step S103, a dummy gate structure 26 covering the oxide layer 50 is formed in the gate region of the stack transistor 10, as shown in FIG. 7.

[0072] It can be understood that based on the semiconductor structure formed in step S102, a semiconductor manufacturing process can be used to form a dummy gate structure 26 in the gate region of the stacked transistor 10. The dummy gate structure 26 is located in the gate region of the stacked transistor 10, and the dummy gate structure 26 can cover the oxide layer 50.

[0073] In an embodiment, the dummy gate structure 26 is a dummy gate structure shared by the first active structure 29 and the second dummy gate structure. The dummy gate structure 26 includes a first dummy gate structure 51 and a second dummy gate structure 52. The first dummy gate structure 51 is a dummy gate structure of the first active structure 29, and the second dummy gate structure 52 is a dummy gate structure of the second active structure 31.

[0074] In some embodiments, after the dummy gate structure 26 is formed, a dummy gate sidewall 27 can be deposited on the semiconductor substrate 20. In an embodiment, the dummy gate sidewall 27 covers the sidewall of the dummy gate structure 26. In an embodiment, the dummy gate sidewall 27 covers the structure in the source-drain region of the stacked transistor 10, for example, the dummy gate sidewall 27 can cover the oxide layer 50 in the source-drain region.

[0075] In step S104, based on the first active structure 29 covered with the oxide layer 50, a first transistor 11 is formed, as shown in FIGS. 8 to 25.

[0076] It can be understood that by removing the oxide layer 50 in the source-drain region, the first active structure 29 in the source-drain region can be exposed. Then, based on the first active structure 29 in the source-drain region, a first source-drain structure 112 can be formed. After the first source-drain structure 112 is formed, the first dummy gate structure 51 can be removed to form a first gate structure 114, thereby forming the first transistor 11.

[0077] It should be noted that the manufacturing process for forming the first source-drain structure 112 and the first gate structure 114 can be selected according to actual needs.

[0078] In some embodiments, in the case where the first gate isolation structure 53 is formed between the first gate structure 114 and the second gate structure 124, step S107 can be performed simultaneously with step S104. In an embodiment, in the source-drain region of the stacked transistor 10, based on the first active structure 29 covered with the oxide layer 50, a first source-drain structure 112 is formed; a second part 512 of the first dummy gate structure is removed, and a first part 511 of the first dummy gate structure is retained to expose the first active structure 29; the first part 511 of the first dummy gate structure is subjected to an oxidation process to form a first gate isolation structure 53; and a first gate structure 114 is formed on the first gate isolation structure 53, and the first gate structure 114 and the first source-drain structure 112 together constitute the first transistor 11.

[0079] It is appreciated that in the process of fabricating the first transistor 11, first, a first source-drain structure 112 can be formed in the source-drain region of the stacked transistor 10 based on the first active structure 29 covered with the oxide layer 50. Then, the second portion 512 of the first dummy gate structure can be removed, leaving only the first portion 511 of the first dummy gate structure. Here, after the second portion 512 of the first dummy gate structure is removed, the first active structure 29 can be exposed. Then, by performing an oxidation process on the remaining first portion 511 of the first dummy gate structure, the first gate isolation structure 53 can be formed. After the first gate isolation structure 53 is formed, the oxide layer 50 above the first active structure 29 can be removed, and a gate dielectric material and a metal material are sequentially deposited to form the first gate structure 114 covering the first active structure 29.

[0080] In some embodiments, the oxidation process can include a high-temperature oxidation process. In an embodiment, the dummy gate structure 26 can be a polysilicon structure formed of a polysilicon material. By performing a high-temperature oxidation on the polysilicon structure, an oxidized polysilicon structure, i.e., the first gate isolation structure 53, can be obtained.

[0081] It is appreciated that the first gate isolation structure 53 is an insulating structure, and the first gate isolation structure 53 is used to electrically isolate the first gate structure 114 and the second gate structure 124.

[0082] It is appreciated that when the first portion 511 of the first dummy gate structure is subjected to the oxidation process, the oxide layer 50 protects the first active structure 29 from being damaged.

[0083] In some embodiments, forming the first gate structure 114 above the first gate isolation structure 53 includes: depositing a gate dielectric material on the exposed first active structure 29 to form a first gate dielectric layer covering the first active structure 29; and depositing a metal material above the first gate dielectric layer to form a first gate electrode layer.

[0084] It is appreciated that the first gate dielectric layer and the first gate electrode layer together constitute the first gate structure 114.

[0085] In an embodiment, after the first source-drain structure 112 is formed, a dielectric material can be deposited above the first source-drain structure 112 to form a first interlayer dielectric layer 113.

[0086] It is appreciated that the first interlayer dielectric layer 113 wraps the first source-drain structure 112, and can electrically isolate the first source-drain structure 112 from other structures.

[0087] In some embodiments, when the stacked transistor 10 is a full wrap-around gate field effect transistor, the method further comprises: removing the sacrificial layer 34 within the first active structure 29 in the gate region, leaving the channel layer 35 within the first active structure 29, thereby fully exposing the channel layer 35 in the gate region.

[0088] In some embodiments, after the first active structure 29 in the gate region is exposed, a gate dielectric material can be deposited on the exposed first active structure 29 to form a first gate dielectric layer.

[0089] In an embodiment, the first gate dielectric layer is between the gate electrode layer and the active structure (channel). The first gate dielectric layer is used to prevent gate current from flowing directly into the channel.

[0090] In an embodiment, the gate dielectric material forming the first gate dielectric layer can be set according to actual needs, which is not limited in the embodiments of the present disclosure. In an example, the gate dielectric layer can be composed of a silicon oxide layer and a high-k hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the first transistor 11. In an example, the gate dielectric layer can include a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0091] In an embodiment, the gate dielectric material forming the gate electrode layer can be set according to actual needs, which is not limited in the embodiments of the present disclosure. In an embodiment, the gate electrode layer can be composed of multiple layers of electrode material, each layer of electrode material including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0092] In some embodiments, based on the first active structure 29 covered with the oxide layer 50, the first source / drain structure 112 is formed, including: removing the oxide layer 50 not covered by the dummy gate structure 26; etching the stacked structure 23 not covered by the dummy gate structure 26 to form a first deep trench 48; based on the first active structure 29 in the gate region, epitaxially growing the first source / drain structure 112 in and outside the first deep trench 48.

[0093] It can be understood that the dummy gate structure 26 covers the oxide layer 50 in the gate region and does not cover the oxide layer 50 in the source / drain region. By removing the oxide layer 50 in the source / drain region, the stacked structure 23 in the source / drain region can be exposed.

[0094] It can be understood that the dummy gate structure 26 covers the stacked structure 23 in the gate region and does not cover the stacked structure 23 in the source / drain region. By etching the stacked structure 23 not covered by the dummy gate structure 26, the first deep trench 48 can be formed at the source / drain region between two adjacent gate regions.

[0095] In some embodiments, the sidewall of the first deep trench 48 is formed by the stack structure 23 in the gate region, and the bottom of the first deep trench 48 is formed by a structure at the bottom of the stack structure 23.

[0096] In some embodiments, the active structure further includes: a first sacrificial layer 30, the first sacrificial layer 30 being located between the first active structure 29 and the second active structure 31.

[0097] It can be understood that the first sacrificial layer 30 and the first active structure 29 and the second active structure 31 can be formed by the same etching process.

[0098] In some embodiments, the material forming the first sacrificial layer 30 can be set according to actual needs, and the embodiments of the present disclosure do not make any limitation on this. In an embodiment, the material forming the first sacrificial layer 30 can be silicon germanium. In an embodiment, the silicon germanium forming the first sacrificial layer 30 is different from the silicon germanium forming the nanosheet structure, for example, the atomic percentage of germanium in the silicon germanium is different.

[0099] In some embodiments, the stack structure 23 includes a second sacrificial layer 32, the second sacrificial layer 32 being arranged between the active structure and the semiconductor substrate 20. The second sacrificial layer 32 can be removed in a subsequent step, and after the removal, the space originally occupied by the second sacrificial layer 32 is used to fill a metal material to form a second gate structure 124 of the second transistor 12.

[0100] In an embodiment, the second sacrificial layer 32 can be formed by a material different from the active structure; or, the second sacrificial layer 32 can be formed by a material same as the active structure. The embodiments of the present disclosure do not make any limitation on the material of the second sacrificial layer 32.

[0101] In some embodiments, after etching the stack structure 23 not covered by the dummy gate structure 26 to form the first deep trench 48, the method further includes: removing the first sacrificial layer 30; and depositing an insulating material at the position where the first sacrificial layer 30 is removed to form an isolation structure 33.

[0102] It can be understood that the stack structure 23 in the source-drain region is not covered by the dummy gate structure 26, and the first deep trench 48 can be formed by etching the first active structure 29, the first sacrificial layer 30, the second active structure 31 and the second sacrificial layer 32 in the source-drain region in sequence. Here, after etching the first active structure 29 in the source-drain region, the first sacrificial layer 30 can be exposed; then, by continuing to etch the first sacrificial layer 30 in the source-drain region, the second active structure 31 can be exposed. Then, by etching the second active structure 31 in the source-drain region, the second sacrificial layer 32 can be exposed. Then, by etching the second sacrificial layer 32 in the source-drain region, the first deep trench 48 can be formed.

[0103] It can be understood that by removing the first sacrificial layer 30 between the first active structure 29 and the second active structure 31 in the gate region, an unfilled space can be formed between the first active structure 29 and the second active structure 31 in the gate region. Subsequently, by filling the unfilled space with an insulating material, the isolation structure 33 can be formed.

[0104] In some embodiments, the isolation structure 33 is used to electrically isolate the first active structure 29 and the second active structure 31 in the gate region.

[0105] In some embodiments, before epitaxially growing the first source / drain structure 112 in the first deep trench 48 based on the first active structure 29 in the gate region, the method comprises: depositing an oxide material in the first deep trench 48 to form a first filling structure 37a. Depositing an insulating material on the first filling structure 37a to form an isolation layer 38.

[0106] It can be understood that the first active structure 29 and the second active structure 31 can be formed before and after the stripping, respectively. Then, before forming the first active structure 29, an oxide material can be deposited in the first deep trench 48 to form a first filling structure 37a. The height of the first filling structure 37a is less than the height of the first active structure 29 and greater than the height of the second active structure 31. The first filling structure 37a completes the shielding of the second active structure 31 in the gate region, thereby ensuring that only the first active structure 29 is formed in the source / drain region before the stripping. Subsequently, an insulating material is deposited on the first filling structure 37a to form an isolation layer 38. The isolation layer 38 is used to isolate the subsequently generated first source / drain structure 112 and the second source / drain structure 122.

[0107] In some embodiments, when the barrier layer 24 is formed between the stack structure 23 and the semiconductor substrate 20, after step S103, the method comprises: etching the barrier layer 24 at the bottom of the first deep trench 48 to form an etched barrier layer 24. Depositing an oxide material at the position where the barrier layer 24 is etched to form a second filling structure 37b.

[0108] It can be understood that when the barrier layer 24 is formed on the semiconductor substrate 20, the barrier layer 24 at the bottom of the first deep trench 48 (the barrier layer 24 in the source / drain region) can be etched after the first deep trench 48 is formed to form an etched barrier layer 24. The etched barrier layer 24 is located in the gate region. Subsequently, by depositing an oxide material at the position where the barrier layer 24 is etched, a second filling structure 37b can be formed.

[0109] In an embodiment, after the stripping, the position of the gate region can be located according to the position of the etched barrier layer 24, facilitating the self-alignment of the stack transistor 10.

[0110] In some embodiments, the oxide material is deposited in the first deep trench 48, and the first fill structure 37a and the second fill structure 37b are formed simultaneously.

[0111] In some embodiments, when the stacked transistor 10 is a full-enclosed gate field effect transistor, the first active structure 29 and the second active structure 31 are both formed by the channel layer 35 and the sacrificial layer 34 stacked alternately. In step S104, the sacrificial layer 34 in the active structure in the gate region is etched laterally to a preset depth. Insulating material is deposited at the position where the sacrificial layer 34 is etched to form the inner sidewall 36.

[0112] It can be understood that, when the stacked transistor 10 is a full-enclosed gate field effect transistor, the first deep trench 48 is formed to expose the active structure in the gate region. Then, the sacrificial layer 34 in the exposed active structure can be etched to a preset depth. Insulating material can be deposited at the position where the sacrificial layer 34 is etched to form the inner sidewall 36 of the full-enclosed gate transistor.

[0113] In some embodiments, the inner sidewall 36 of the full-enclosed gate transistor is used to electrically isolate the source-drain structure and the gate structure, and ensure the stability of the transistor structure.

[0114] In some embodiments, the inner sidewall 36 includes a first inner sidewall and a second inner sidewall, the first inner sidewall is opposite to the first active structure 29, and the second inner sidewall is opposite to the second active structure 31.

[0115] It can be understood that, after the first deep trench 48 is formed, the inner sidewall 36 in the first transistor 11 and the second transistor 12 can be formed simultaneously. The first inner sidewall of the first transistor 11 is used to isolate the first source-drain structure 112 and the first gate structure 114. The second inner sidewall of the second transistor 12 is used to isolate the second source-drain structure 122 and the second gate structure 124.

[0116] In an embodiment, the material forming the inner sidewall 36 is the same as the material forming the dummy gate sidewall 27.

[0117] In some embodiments, after the first deep trench 48 is formed, the first source-drain structure 112 can be epitaxially grown based on the first active structure 29 in the gate region. Here, the direction of epitaxial growth is perpendicular to the first direction, and the direction of epitaxial growth is the direction from the gate region to the source-drain region. After the epitaxial growth is completed, the first source-drain structure 112 can be formed in the first deep trench 48.

[0118] In some embodiments, step S104 comprises: depositing a dielectric material on the first gate structure 114 and the first interlayer dielectric layer 113 to form the first dielectric layer 42; etching the first dielectric layer 42 and the first interlayer dielectric layer 113 until the first source-drain structure 112 is exposed to form a first via; and depositing a metal material in the first via to form the first source-drain metal 115.

[0119] It can be understood that after the first gate structure 114 is formed, the first dielectric layer 42 can also be formed on the first gate structure 114 and the first interlayer dielectric layer 113, and the first dielectric layer 42 is used to electrically isolate the source-drain metal and the gate oxide (e.g., the gate dielectric layer), so as to eliminate the adverse electrical effects caused by the direct contact between the source-drain metal and the gate oxide layer. After the first dielectric layer 42 is formed, the first dielectric layer 42 and the first interlayer dielectric layer 113 in the source-drain region can be etched to form a source-drain metal via. Then, a metal material can be deposited in the source-drain metal via to form the first source-drain metal 115.

[0120] In some embodiments, step S104 comprises: after the first gate structure 114 is formed, removing the third gate structure in the first gate structure 114 by using a gate cut process, and depositing an insulating material at a position where the third gate structure is removed to form the first isolation structure 41.

[0121] In an embodiment, in the second direction, the third gate structure is located at two ends of the first gate structure 114.

[0122] It can be understood that after the first gate structure 114 is formed, the third gate structure in the first gate structure 114 can be removed, and the third gate structure is a structure located at two ends of the first gate structure 114 in the second direction, which can also be understood as a structure located at two ends of the stacked transistor 10 in the second direction. After the third gate structure is removed, an insulating material can be deposited at a position where the third gate structure is removed to form the first isolation structure 41.

[0123] In some embodiments, the insulating material used to form the first isolation structure 41 can be selected according to actual needs, and the embodiments of the present disclosure do not limit this.

[0124] In some embodiments, while the third gate structure in the first gate structure 114 is removed by using the gate cut process, the third interlayer dielectric layer in the first interlayer dielectric layer 113 can also be removed at the same time, and the projection of the third interlayer dielectric layer in the third direction and the projection of the third gate structure in the third direction coincide. After the third interlayer dielectric layer is removed, an insulating material can also be deposited at a position where the third interlayer dielectric layer is removed to form the first isolation structure 41 which is continuous in the third direction.

[0125] In an embodiment, after the first gate structure 114 and the first source-drain metal 115 are formed, the first metal interconnection layer 116 can be formed on the first gate structure 114 and the first source-drain metal 115 by using standard post-processes of semiconductor manufacturing (such as interconnection medium deposition, metal line formation, lead pad formation, etc.).

[0126] In some embodiments, after the first metal interconnection layer 116 is formed, the first transistor 11 can be formed.

[0127] It should be noted that, for the sake of convenience, the first source-drain structure mentioned in the embodiments of the present disclosure is a short form, which refers to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain recess, and the "source-drain" therein is a short form of "source and / or drain".

[0128] In step S105, the semiconductor substrate 20 is flipped and removed, as shown in FIGS. 26-28.

[0129] It can be understood that, after the first transistor 11 is obtained, the first transistor 11 can be flipped so that the first transistor 11 that is completely manufactured is located at the bottom, and the second active structure 31 of the second transistor 12 that is not completely manufactured can be located at the top, facilitating subsequent manufacturing of the second transistor 12.

[0130] In an embodiment, after the post-process of the first transistor 11 is completed, the first transistor 11 can be bonded with the carrier wafer 44. For example, an insulating material (such as silicon oxide) can be deposited on the first transistor 11 to form an insulating layer 43, and the insulating layer 43 can be bonded with the carrier wafer 44. Then, the flipping is performed, and after the flipping, the first transistor 11 is located at the bottom.

[0131] In the embodiments of the present disclosure, the carrier wafer 44 after the bonding can provide physical support for the flipped first transistor 11 after the flipping, effectively preventing the first transistor 11 from being broken by external force during the manufacturing of the second transistor 12.

[0132] In some embodiments, when the barrier layer 24 is arranged between the stacked structure 23 and the semiconductor substrate 20, step S105 includes: flipping and removing the semiconductor substrate 20 to expose the etched barrier layer 24 and the shallow trench isolation structure 25. The shallow trench isolation structure 25 is removed, and the etched barrier layer 24 is retained.

[0133] It can be understood that, after the flipping, the semiconductor substrate 20 can be removed by using a polishing process or a chemical mechanical planarization process to expose the etched barrier layer 24 and the shallow trench isolation structure 25, and then the shallow trench isolation structure 25 can be selectively etched to expose the etched barrier layer 24.

[0134] It can be understood that the etched barrier layer 24 is located in the gate region, so that the etched barrier layer 24 can protect the structure in the gate region from being affected by etching.

[0135] It can be understood that the gate region of the stacked transistor 10 can be positioned by the etched barrier layer 24, so as to realize self-alignment of the gate region and the source-drain region of the positive and negative transistors.

[0136] In step S106, the second transistor 12 is formed based on the second active structure 31 covered with the oxide layer 50, as shown in FIGS. 27 to 29.

[0137] It can be understood that after the semiconductor substrate 20 is developed and removed, the second active structure 31 covered with the oxide layer 50 can be exposed. Then, the second transistor 12 can be formed based on the second active structure 31 covered with the oxide layer 50.

[0138] In some embodiments, step S107 can be performed simultaneously with step S106 in the case where the second gate isolation structure 54 is formed between the first gate structure 114 and the second gate structure 124. In an embodiment, in the source-drain region of the stacked transistor 10, the second source-drain structure 122 is formed based on the second active structure 31 covered with the oxide layer 50; the second part 522 of the second dummy gate structure is removed, and the first part 521 of the second dummy gate structure is retained to expose the second active structure 31; the first part 521 of the second dummy gate structure is subjected to an oxidation process to form the second gate isolation structure 54; and the second gate structure 124 is formed on the second gate isolation structure 54, and the second gate structure 124 and the second source-drain structure 122 together constitute the second transistor 12.

[0139] It can be understood that in the process of preparing the second transistor 12, first, the second source-drain structure 122 can be formed in the source-drain region of the stacked transistor 10 based on the second active structure 31 covered with the oxide layer 50. Then, the second part 522 of the second dummy gate structure can be removed, and only the first part 521 of the second dummy gate structure is retained. Here, after the second part 522 of the second dummy gate structure is removed, the second active structure 31 can be exposed. Then, by subjecting the retained first part 521 of the second dummy gate structure to an oxidation process, the second gate isolation structure 54 can be formed. After the second gate isolation structure 54 is formed, the oxide layer 50 on the second active structure 31 can be removed, and the gate dielectric material and the metal material are sequentially deposited to form the second gate structure 124 covering the second active structure 31.

[0140] In an embodiment, the step of forming the second source-drain structure 122 is the same as the step of forming the first source-drain structure 112, which will not be described herein for the sake of simplicity of the description.

[0141] In some embodiments, during the process of fabricating the first transistor 11, if the first filling structure 37a is filled in the first deep trench 48, before the step S106, the method further comprises: removing the first filling structure 37a in the first deep trench 48 to expose the second active structure 31 in the gate region.

[0142] It can be understood that, by removing the first filling structure 37a in the first deep trench 48, the second active structure 31 in the gate region can be exposed, so that the second source-drain structure 122 can be formed based on the exposed active structure.

[0143] In some embodiments, before the step S106, the method comprises: etching the second filling structure 37b and the first filling structure 37a successively, which are not covered by the etched barrier layer 24, until the isolation layer 38 is exposed.

[0144] It can be understood that, the second filling structure 37b and the first filling structure 37a, which are not covered by the etched barrier layer 24, can be etched during the etching process. During this process, the etched barrier layer 24 serves as a hard mask to protect the structure covered by the etched barrier layer 24.

[0145] In some embodiments, after the second active structure 31 in the gate region is exposed, a dielectric material can be deposited on the exposed second active structure 31 to form a second gate dielectric layer. A metal material can be deposited on the second gate dielectric layer to form a second gate electrode layer.

[0146] In an embodiment, the second gate dielectric layer and the second gate electrode layer are used together to form a second gate structure 124. The second gate structure 124 is a gate structure in the second transistor 12.

[0147] In some embodiments, the step S106 further comprises: depositing a dielectric material on the second gate structure 124 and the second interlayer dielectric layer 123 to form a second dielectric layer 46; etching the second dielectric layer 46 and the second interlayer dielectric layer 123 until the second source-drain structure 122 is exposed to form a second via hole; and depositing a metal material in the second via hole to form a second source-drain metal 125.

[0148] It can be understood that after the second gate structure 124 is formed, a second dielectric layer 46 can also be formed on the second gate structure 124 and the second interlayer dielectric layer 123, and the second dielectric layer 46 has the same function as the first dielectric layer 42. After the second dielectric layer 46 is formed, the second dielectric layer 46 and the second interlayer dielectric layer 123 in the source-drain region can be etched to form a source-drain metal via. Then, a metal material can be deposited in the source-drain metal via to form a second source-drain metal 125.

[0149] In some embodiments, step S106 further includes: after the second gate structure 124 is formed, removing the fourth gate structure in the second gate structure 124 by using a gate cut process, and depositing an insulating material at a position where the fourth gate structure is removed to form a second isolation structure 47.

[0150] In an embodiment, in the second direction, the fourth gate structure is located at both ends of the second gate structure 124.

[0151] It can be understood that after the second gate structure 124 is formed, the fourth gate structure in the second gate structure 124 can be removed, and the fourth gate structure is a structure located at both ends of the second gate structure 124 in the second direction, and can also be understood as a structure located at both ends of the stacked transistor 10 in the second direction. After the fourth gate structure is removed, an insulating material can be deposited at a position where the fourth gate structure is removed to form a second isolation structure 47.

[0152] In some embodiments, the insulating material forming the second isolation structure 47 can be selected according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0153] In some embodiments, while the fourth gate structure in the second gate structure 124 is removed by using the gate cut process, the fourth interlayer dielectric layer in the second interlayer dielectric layer 123 can also be removed at the same time, and the projection of the fourth interlayer dielectric layer toward the third direction and the projection of the fourth gate structure toward the third direction coincide. After the fourth interlayer dielectric layer is removed, an insulating material can also be deposited at a position where the fourth interlayer dielectric layer is removed to form a second isolation structure 47 that is continuous in the third direction.

[0154] In some embodiments, the first isolation structure 41 and the second isolation structure 47 are oppositely arranged.

[0155] In an embodiment, after the second gate structure 124 and the second source-drain metal 125 are formed, a second metal interconnection layer 126 can be formed on the second gate structure 124 and the second source-drain metal 125 by using standard post-processes of semiconductor preparation (such as interconnection line dielectric deposition, metal line formation, lead-out pad formation, etc.).

[0156] In some embodiments, after the second metal interconnection layer 126 is formed, the second transistor 12 can be formed.

[0157] So far, the preparation of the stacked transistor is completed. It should be noted that the first source-drain structure and the first gate structure jointly constitute the first transistor, and the second source-drain structure and the second gate structure jointly constitute the second transistor; the first transistor or the second transistor is any one of the following: fin field effect transistor, fully surrounding gate field effect transistor, vertical field effect transistor, complementary field effect transistor, plate crystal transistor and planar field effect transistor, and the embodiments of the present disclosure do not limit this.

[0158] In the embodiments of the present disclosure, by etching to form a stacked structure on a semiconductor substrate at one time, the active regions of the first transistor and the second transistor in the stacked transistor can be self-aligned. Subsequently, a dummy gate structure shared by the first transistor and the second transistor is formed. In the process of forming the front-side transistor and / or the back-side transistor, part of the dummy gate structure is removed, and the remaining dummy gate structure is subjected to an oxidation treatment to form a gate isolation structure in the stacked transistor by using the dummy gate structure. Subsequently, based on the active structure, a self-aligned gate structure can be formed, and finally the first transistor and the second transistor are completely self-aligned.

[0159] In this way, on the one hand, fewer high aspect ratio processes can be used to further optimize the “self-aligned flip stacked transistor” scheme to be more compatible with the complete self-alignment of various types of transistors; on the other hand, by oxidizing the dummy gate structure to form the gate isolation structure between the front-side transistor and the back-side transistor, the process difficulty can be reduced to some extent, and the quality of the gate isolation structure can be improved.

[0160] The preparation method of the stacked transistor in the embodiments of the present disclosure will be described below in the first embodiment in combination with the preparation process of the stacked transistor shown in FIGS. 2 to 37.

[0161] In an example, the preparation process of the stacked transistor can include the following steps:

[0162] First step: epitaxial silicon germanium material and silicon material are formed on a semiconductor substrate 20 (formed of silicon) to form an initial stacked structure 21 and an initial barrier layer 22, and a structure as shown in FIG. 3 is obtained.

[0163] It can be understood that the initial barrier layer 22 is located between the semiconductor substrate 20 and the initial stacked structure 21.

[0164] Here, the initial stacked structure 21 is formed by alternately arranging a silicon germanium layer formed of silicon germanium material and a silicon layer formed of silicon material.

[0165] Second step: by lithography, a stacked structure 23 and a barrier layer 24 are etched at one time to obtain a structure as shown in FIG. 4.

[0166] It can be understood that in the sectional view along the A-A' direction and the sectional view along the B-B' direction, the portions on both sides of the initial stack structure 21 are etched, so as to form a stack structure 23 for preparing a full-surrounding gate field effect transistor.

[0167] In some embodiments, the material forming the barrier layer 24 can have a certain hardness, so that the barrier layer 24 can serve as an etching barrier after the film is developed.

[0168] Referring to FIG. 4, the stack structure 23 includes a first active structure 29, a second active structure 31, a first sacrificial layer 30, and a second sacrificial layer 32.

[0169] In a third step, an oxide material is deposited on the semiconductor substrate 20 and etched to a preset height, so as to form a shallow trench isolation structure 25, and a structure as shown in FIG. 5 is obtained.

[0170] Here, the shallow trench isolation structure 25 wraps the barrier layer 24, and the stack structure 23 is exposed outside the shallow trench isolation structure 25.

[0171] In a fourth step, an oxide layer 50 is formed, and a structure as shown in FIG. 6 is obtained.

[0172] It can be understood that the oxide layer 50 can be formed by depositing a silicon layer on the semiconductor substrate 20 and performing a thermal oxidation process on the silicon layer. The oxide layer 50 covers the upper surface of the stack structure 23 and the semiconductor substrate 20.

[0173] In a fifth step, a pseudo-gate structure 26 wrapping the stack structure 23 is formed, and after the pseudo-gate structure 26 is formed, a pseudo-gate sidewall 27 is deposited, and a structure as shown in FIG. 7 is obtained.

[0174] It can be understood that the pseudo-gate structure 26 is a pseudo-gate structure shared by the positive and negative layers of crystals. The pseudo-gate structure 26 includes a first pseudo-gate structure 51 and a second pseudo-gate structure 52. When the pseudo-gate sidewall 27 is formed by using an isotropic deposition process, the pseudo-gate sidewall 27 can cover the sidewall of the pseudo-gate structure 26 in the gate region, and the stack structure 23 in the source-drain region.

[0175] In a sixth step, the pseudo-gate sidewall 27 is etched until the first active structure 29 and the first sacrificial layer 30 in the stack structure 23 in the source-drain region are exposed, and a structure as shown in FIG. 8 is obtained.

[0176] It can be understood that the first active structure 29 and the first sacrificial layer 30 covered by the oxide layer 50 can be exposed by using an anisotropic etching process.

[0177] It should be noted that, as shown in FIG. 7, after the first active structure 29 and the first sacrificial layer 30 covered by the oxidized layer 50 are exposed, in the cross-sectional view along the direction of C-C', part of the dummy gate sidewall 27 remains on the sidewall of the dummy gate structure 26. The dummy gate sidewall 27 can be used as a hard mask in subsequent manufacturing processes.

[0178] In a seventh step, the first active structure 29 in the source / drain region is etched to obtain the structure shown in FIG. 9.

[0179] It can be understood that, by using the dummy gate structure 26 and the dummy gate sidewall 27 as a hard mask, the first active structure 29 in the source / drain region can be selectively etched.

[0180] In an eighth step, the isolation structure 33 between the first active structure 29 and the second active structure 31 formed in the gate region is formed to obtain the structure shown in FIG. 12.

[0181] It can be understood that the isolation structure 33 is a medium dependent interface (MDI).

[0182] In an embodiment, forming the isolation structure 33 can include: selectively removing the first sacrificial layer 30 to isolate the first active structure 29 and the second active structure 31 to obtain the structure shown in FIG. 10. An insulating material such as silicon nitride is deposited, and a mechanical planarization process is performed on the isolation structure 33 formed of the silicon nitride material to obtain the structure shown in FIG. 11. An anisotropic etching process is used to remove the excess isolation structure 33, and the isolation structure 33 between the first active structure 29 and the second active structure 31 in the gate region is retained to obtain the structure shown in FIG. 12.

[0183] In a ninth step, the sacrificial layer 34 in the first active structure 29 is laterally etched to a certain depth. An insulating material such as silicon nitride is deposited at the position where the sacrificial layer 34 is removed to form the inner sidewall 36 of the first transistor 11 to obtain the structure shown in FIG. 13.

[0184] It can be understood that, in the present embodiment, the stacked transistor 10 is a fully-enclosed gate field effect transistor, and therefore, the inner sidewall 36 needs to be formed. When the stacked transistor 10 is a fin field effect transistor, a planar field effect transistor, or the like, the inner sidewall 36 does not need to be formed.

[0185] In a tenth step, the second active structure 31 in the source / drain region is etched by using an anisotropic etching process to form the first deep trench 48. Subsequently, the second sacrificial layer 32 at the bottom of the second active structure 31 is etched by using an anisotropic etching process to obtain the structure shown in FIG. 14.

[0186] In the tenth step, the barrier layer 24 and the shallow trench isolation structure 25 in the source-drain region are etched by anisotropic etching to obtain the structure shown in Fig. 15.

[0187] It can be understood that the barrier layer 24 in the source-drain region is etched by anisotropic etching to form an etched barrier layer 24. The etched barrier layer 24 is in the gate region, and after developing, the position of the gate region can be obtained based on the etched barrier layer 24.

[0188] In the twelfth step, a filling material is deposited in the source-drain region to form a filling structure 37 to obtain the structure shown in Fig. 16.

[0189] In an embodiment, the filling structure 37 includes a first filling structure 37a opposite to the position of the second active structure 31 and a second filling structure 37b opposite to the position of the etched barrier layer 24.

[0190] In an embodiment, as shown in Fig. 16, the height of the top surface of the filling structure 37 is lower than the height of the top surface of the isolation structure 33 and higher than the height of the bottom surface of the isolation structure 33.

[0191] In the thirteenth step, an insulating material is deposited in the source-drain region and etched back to a preset height to form an isolation layer 38 to obtain the structure shown in Fig. 17.

[0192] It can be understood that the isolation layer 38 is used to electrically isolate the first source-drain structure 112 and the second source-drain structure 122.

[0193] In the fourteenth step, the first source-drain structure 112 is formed by epitaxy in the source-drain region based on the first active structure 29 in the gate region to obtain the structure shown in Fig. 18.

[0194] In the fifteenth step, an interlayer gate dielectric material is deposited in the source-drain region to form a first interlayer dielectric layer 113 to obtain the structure shown in Fig. 19.

[0195] In the sixteenth step, the second part 512 of the first dummy gate structure is removed, and the first part 511 of the first dummy gate structure is retained to obtain the structure shown in Fig. 20.

[0196] In the seventeenth step, the first part 511 of the first dummy gate structure is subjected to oxidation treatment to form a first gate isolation structure 53 to obtain the structure shown in Fig. 21.

[0197] It should be noted that when the first part 511 of the first dummy gate structure is subjected to oxidation treatment, the oxide layer 50 can protect the first active structure 29 from damage.

[0198] In the eighteenth step, the oxide layer 50 in the gate region is removed, and the gate dielectric material and the metal material are deposited on the first active structure 29 to form the first gate structure 114, and a structure as shown in Fig. 22 is obtained.

[0199] In the nineteenth step, the first isolation structure 41 is formed, and a structure as shown in Fig. 23 is obtained.

[0200] It can be understood that in the cross-sectional view in the A-A' direction and the cross-sectional view in the B-B' direction, the first isolation structure 41 is located on both sides.

[0201] In the twentieth step, the dielectric material is deposited on the first interlayer dielectric layer 113 and the first gate structure 114 to form the first dielectric layer 42. Then, the first dielectric layer 42 and the first interlayer dielectric layer 113 are etched according to the photoetching pattern until the first source-drain structure 112 is exposed, and then the first source-drain metal 115 is deposited, and a structure as shown in Fig. 24 is obtained.

[0202] In the twenty-first step, the first metal interconnection layer 116 is formed, and a structure as shown in Fig. 25 is obtained.

[0203] In the twenty-second step, the insulating material (such as silicon oxide) is deposited on the first metal interconnection layer 116 to form the insulating layer 43, and the insulating layer 43 is bonded with the carrier wafer 44. Then, the wafer is developed, and after the development, a structure as shown in Fig. 26 is obtained.

[0204] In the twenty-third step, the semiconductor substrate 20 is removed, and a structure as shown in Fig. 27 is obtained.

[0205] It can be understood that after the semiconductor substrate 20 is removed, the etched barrier layer 24 and the filling structure 37 in the source-drain region can be exposed.

[0206] In the twenty-fourth step, the shallow trench isolation structure 25 wrapping the etched barrier layer is selectively etched, and a structure as shown in Fig. 28 is obtained.

[0207] In the twenty-fifth step, the polysilicon is deposited at the position where the shallow trench isolation structure 25 is removed to form the polysilicon structure 45, and a structure as shown in Fig. 29 is obtained.

[0208] In the twenty-sixth step, the filling structure 37 in the source-drain region is removed until the isolation layer 38 is exposed, and a structure as shown in Fig. 30 is obtained.

[0209] It can be understood that the etched barrier layer 24 is located in the gate region, and according to the position of the etched barrier layer 24, the position of the source-drain region can be determined.

[0210] In the twenty-seventh step, the sacrificial layer 34 in the second active structure 31 is etched laterally to a certain depth. Insulating material such as silicon nitride is deposited at the positions where the sacrificial layer 34 is removed to form the inner sidewall 36 of the second transistor 12, and a structure as shown in FIG. 31 is obtained.

[0211] In the twenty-eighth step, based on the second active structure 31 in the gate region, a second source-drain structure 122 is epitaxially grown in the source-drain region, and a dielectric material is deposited above the second source-drain structure 122 to form a second interlayer dielectric layer 123, and a structure as shown in FIG. 32 is obtained.

[0212] In the twenty-ninth step, the second dummy gate structure 52 is etched with the etched barrier layer 24 as a hard mask until the first gate isolation structure 53 is exposed, and a structure as shown in FIG. 33 is obtained.

[0213] In the thirtieth step, the etched barrier layer 24 and the second sacrificial layer 32 are removed to expose the second active structure 31. Subsequently, a second gate structure 124 is formed on the second active structure, and a structure as shown in FIG. 34 is obtained.

[0214] It can be understood that the second gate structure 124 includes a second gate dielectric layer and a second gate electrode layer.

[0215] In the thirty-first step, a second isolation structure 47 is formed, and a structure as shown in FIG. 35 is obtained.

[0216] It can be understood that in the cross-sectional view in the A-A' direction and the cross-sectional view in the B-B' direction, the second isolation structure 47 is located on both sides.

[0217] In the thirty-second step, a dielectric material is deposited above the second interlayer dielectric layer 123 and the second gate structure 124 to form a second dielectric layer 46. Subsequently, the second dielectric layer 46 and the second interlayer dielectric layer 123 are etched until the second source-drain structure 122 is exposed, and then a second source-drain metal 125 is deposited to form, and a structure as shown in FIG. 36 is obtained.

[0218] In the thirty-third step, a second metal interconnection layer 126 is formed, and a structure as shown in FIG. 37 is obtained.

[0219] It can be understood that after the second metal interconnection layer 126 is formed, the stacked transistor 10 in the embodiment of the present disclosure is prepared.

[0220] In the embodiments of the present disclosure, the complementary flip stacked transistors can be formed by preparing the first transistor before film reversing and preparing the second transistor after film reversing. The dummy gate structures of the first transistor and the second transistor are integrally formed, so that the fully self-aligned flip stacked transistors of various forms can be realized with fewer high aspect ratio processes and more compatibility. In some embodiments, during the process of forming the front surface transistor, a part of the dummy gate structure is removed, and the remaining dummy gate structure is subjected to an oxidation treatment, so as to reduce the process difficulty to a certain extent and form a good gate isolation structure.

[0221] FIGS. 38-55 are structural schematic diagrams of a stacked transistor in a preparation process according to an embodiment of the present disclosure. For ease of understanding, (a) in FIGS. 38-55 shows a cross-sectional view along the direction of dashed line A-A' in FIG. 2, (b) in FIGS. 38-55 shows a cross-sectional view along the direction of dashed line B-B' in FIG. 2, and (c) in FIGS. 38-55 shows a cross-sectional view along the direction of dashed line C-C' in FIG. 2. The preparation method of the stacked transistor in the embodiments of the present disclosure will be described below in a second embodiment in combination with the preparation process of the stacked transistor shown in FIGS. 38-55.

[0222] The first step is the same as the first step to the seventeenth step in the first embodiment described above. For the sake of brevity of the description, the structures shown in FIGS. 3-19 will not be described again here.

[0223] The second step is to remove the first dummy gate structure 51 to obtain the structure shown in FIG. 38.

[0224] The third step is to remove the oxide layer 50 in the gate region and deposit gate dielectric material and metal material on the first active structure 29 to form a first gate structure 114, so as to obtain the structure shown in FIG. 39.

[0225] The fourth step is the same as the twenty-first step to the thirtieth step in the first embodiment described above. The structures shown in FIGS. 40-49 can be obtained.

[0226] The fifth step is to etch the second part 522 of the second dummy gate structure with the etched barrier layer 24 as a hard mask, and retain the first part 521 of the second dummy gate structure, so as to obtain the structure shown in FIG. 50.

[0227] The sixth step is to perform an oxidation treatment on the first part 521 of the second dummy gate structure to form a second gate isolation structure 55, so as to obtain the structure shown in FIG. 51.

[0228] The seventh step is the same as the thirty-second step to the thirty-fifth step in the first embodiment described above. The structures shown in FIGS. 52-55 can be obtained.

[0229] In the embodiments of the present disclosure, in the process of forming the back-side transistor, a part of the dummy gate structure is removed, and the remaining dummy gate structure is subjected to an oxidation treatment, which to some extent reduces the process difficulty and forms a gate isolation structure with good quality.

[0230] It should be noted that in the embodiments of the present disclosure, the gate isolation structure can also be formed by oxidizing the dummy gate structure in the process of forming the front-side transistor and the back-side transistor. The process can refer to the description in the first embodiment described above. For the sake of brevity of the description, it will not be described here.

[0231] In the embodiments of the present disclosure, a stacked transistor is provided, which can be prepared by the method in one or more embodiments corresponding to FIG. 1. Referring to FIG. 37 and FIG. 55, the stacked transistor 10 includes:

[0232] The first transistor 11 and the second transistor 12 are arranged back to back, and the first active structure 29 of the first transistor 11 and the second active structure 31 of the second transistor 12 form an active structure. The first transistor 11 includes a first gate structure 114, and the second transistor 12 includes a second gate structure 124. The first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 are self-aligned.

[0233] In some embodiments, a gate isolation structure is formed between the first gate structure 114 and the second gate structure 124, and the gate isolation structure is obtained by oxidizing a first part 511 of a first dummy gate structure and / or a first part 521 of a second dummy gate structure. The first part 511 of the first dummy gate structure is a part of the first dummy gate structure 51 close to the second dummy gate structure 52, and the first part 521 of the second dummy gate structure is a part of the second dummy gate structure 52 close to the first dummy gate structure 51. An oxide layer 50 protects the stacked structure 23 during the oxidation process.

[0234] In some embodiments, the first transistor 11 or the second transistor 12 is any one of a fin field effect transistor, a fully wrapped gate field effect transistor, a vertical field effect transistor, a complementary field effect transistor, a plate crystal transistor, and a planar field effect transistor, which is not limited in the embodiments of the present disclosure.

[0235] It can be understood that the flip-chip stacked transistor scheme in the embodiments of the present disclosure has self-alignment. On the one hand, it solves the long-term problems of process complexity and alignment difficulty existing in the existing mainstream technical scheme of the stacked transistor, and realizes the industrialization of the transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are connected through the stacked transistor interconnection, which greatly releases the metal wiring resources.

[0236] Finally, the scheme of realizing the up-and-down transistors by flip-chip is compatible with the mainstream device architecture, and can realize the front-and-back stacking of planar transistors, fin field effect transistors, fully-enclosed gate field effect transistors, fork sheet transistors (Forksheet) and even vertical transistors (VTFET), without special process development for specific device architecture, and has strong flexibility and strong extendibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicability and extensive development prospects.

[0237] The semiconductor device provided by the embodiments of the present disclosure includes the stacked transistor as described above. The structure of the stacked transistor can refer to the stacked transistor shown in FIG. 37 and FIG. 55, which will not be repeated here.

[0238] The electronic device provided by the embodiments of the present disclosure includes a circuit board and the semiconductor device as described above, and the semiconductor device is arranged on the circuit board. The semiconductor device includes the stacked transistor as described above. The structure of the stacked transistor can refer to the structure shown in FIG. 37 and FIG. 55, which will not be repeated here.

[0239] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can refer to the related description of other embodiments.

[0240] The above describes only a specific implementation of the present disclosure in an embodiment, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a stacked transistor, the method comprising: forming a stack structure on a semiconductor substrate by one-time etching, wherein the stack structure comprises: a first active structure and a second active structure; the first active structure and the second active structure are stacked in a first direction, the first active structure is farther away from the semiconductor substrate than the second active structure, and the first direction is perpendicular to the semiconductor substrate; forming an oxide layer covering the stack structure on the semiconductor substrate; forming a dummy gate structure covering the oxide layer in a gate region of the stacked transistor; the dummy gate structure comprises a first dummy gate structure and a second dummy gate structure; forming a first transistor based on the first active structure covered by the oxide layer, wherein the first transistor comprises: a first gate structure formed based on the first dummy gate structure; developing and removing the semiconductor substrate; forming a second transistor based on the second active structure covered by the oxide layer, wherein the second transistor comprises: a second gate structure formed based on the second dummy gate structure; performing an oxidation process on a first part of the first dummy gate structure to form a first gate isolation structure between the first gate structure and the second gate structure; and / or performing an oxidation process on a first part of the second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure; wherein the first part of the first dummy gate structure is a part of the first dummy gate structure close to the second dummy gate structure, the first part of the second dummy gate structure is a part of the second dummy gate structure close to the first dummy gate structure, and the oxide layer protects the stack structure during the oxidation process.

2. The method of claim 1, wherein, In the case of forming the first gate isolation structure between the first gate structure and the second gate structure, the forming of the first transistor based on the first active structure covered by the oxide layer comprises: forming a first source-drain structure based on the first active structure covered by the oxide layer in a source-drain region of the stacked transistor; forming the first gate structure on the first gate isolation structure, and the first gate structure and the first source-drain structure together constitute the first transistor.

3. The method of claim 2, wherein, The forming of the first gate structure on the first gate isolation structure comprises: depositing a gate dielectric material on the exposed first active structure to form a first gate dielectric layer covering the first active structure; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, and the first gate dielectric layer and the first gate electrode layer together constitute the first gate structure.

4. The method of claim 2, wherein, The forming of the first source-drain structure based on the first active structure covered by the oxide layer comprises: removing the oxide layer not covered by the dummy gate structure; etching the stack structure not covered by the dummy gate structure to form a first deep trench; epitaxially growing the first source-drain structure in and outside the first deep trench based on the first active structure in the gate region.

5. The method of claim 4, wherein, The stack structure further comprises a first sacrificial layer between the first active structure and the second active structure; After etching the stack structure not covered by the dummy gate structure to form the first deep trench, the method further comprises: removing the first sacrificial layer; depositing an insulating material at the position where the first sacrificial layer is removed to form an isolation structure.

6. The production method according to claim 4, wherein When the stack transistor is a full-surrounding-gate field effect transistor, the first active structure and the second active structure are both formed by channel layers and sacrificial layers stacked alternately; After etching the stack structure not covered by the dummy gate structure to form the first deep trench, the method further comprises: laterally etching the sacrificial layer in the first active structure within the gate region to a preset depth; depositing an insulating material at the position where the sacrificial layer is etched to form an inner sidewall.

7. The method of claim 4, wherein, Before epitaxially growing the first source-drain structure in the first deep trench based on the first active structure within the gate region, the method further comprises: depositing an oxide material in the first deep trench to form a first filling structure, the height of the first filling structure being less than the height of the first active structure and greater than the height of the second active structure; depositing an insulating material on the first filling structure to form an isolation layer, the isolation layer being used to isolate the first source-drain structure and the second source-drain structure.

8. The production method according to claim 7, wherein The once etching on the semiconductor substrate to form a stack structure comprises: forming an initial stack structure and an initial barrier layer on a semiconductor substrate, wherein the initial barrier layer is between the initial stack structure and the semiconductor substrate; once etching the initial stack structure and the initial barrier layer to form the stack structure and the barrier layer; After etching the stack structure not covered by the dummy gate structure to form the first deep trench, the method further comprises: etching the barrier layer at the bottom of the first deep trench to form an etched barrier layer, wherein the etched barrier layer is located in the gate region; The film reversal and removal of the semiconductor substrate comprises: film reversal and removal of the semiconductor substrate to expose the etched barrier layer; Before forming a second transistor based on a second active structure covered with the oxide layer, the method further comprises: etching the first filling structure not covered by the etched barrier layer until the isolation layer is exposed.

9. The method according to any one of claims 1 to 8, wherein, In the case of forming the second gate isolation structure between the first gate structure and the second gate structure, forming a second transistor based on a second active structure covered with the oxide layer comprises: forming a second source-drain structure based on a second active structure covered with the oxide layer in the source-drain region of the stack transistor; forming a second gate structure on the second gate isolation structure, the second gate structure and the second source-drain structure together constituting the second transistor.

10. The production method according to claim 1, wherein, The method further comprises: After the first gate structure is formed, a gate cut process is used to remove a third gate structure in the first gate structure, and an insulating material is deposited at a position where the third gate structure is removed, to form a first gate isolation structure; wherein, in a second direction, the third gate structure is located at two ends of the first gate structure; the second direction is perpendicular to the first direction; and / or, After the second gate structure is formed, a gate cut process is used to remove a fourth gate structure in the second gate structure, and an insulating material is deposited at a position where the fourth gate structure is removed, to form a second gate isolation structure; wherein, in a second direction, the fourth gate structure is located at two ends of the second gate structure.

11. The production method according to claim 1, wherein The first transistor or the second transistor is any one of: a fin field effect transistor, a fully wrapped gate field effect transistor, a vertical field effect transistor, a complementary field effect transistor, a plate interdigital transistor, and a planar field effect transistor.

12. A stacked transistor, prepared using the preparation method of any one of claims 1 to 11, comprising: a first transistor; a second transistor, the first transistor and the second transistor are oppositely arranged, a first active structure of the first transistor and a second active structure of the second transistor are formed using a same etching process; a first gate structure of the first transistor and a second gate structure of the second transistor are self-aligned; the first gate structure is formed based on the first dummy gate structure; the second gate structure is formed based on the second dummy gate structure; wherein, a gate isolation structure is formed between the first gate structure and the second gate structure, the gate isolation structure is obtained by oxidizing a first part of the first dummy gate structure and / or a first part of the second dummy gate structure, the first part of the first dummy gate structure is a part of the first dummy gate structure close to the second dummy gate structure, and the first part of the second dummy gate structure is a part of the second dummy gate structure close to the first dummy gate structure.

13. A semiconductor device comprising: The stacked transistor of claim 12.

14. An electronic device comprising: A circuit board and the semiconductor device of claim 13, the semiconductor device is arranged on the circuit board. A circuit board and the semiconductor device of claim 13, the semiconductor device is arranged on the circuit board.

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