Driving circuit, DC-DC converter and driving method

Abstract

Disclosed in the present invention are a driving circuit, a DC-DC converter, and a driving method. The driving circuit comprises: a detection unit, a first delay control unit, a first driving unit, a second delay control unit, and a second driving unit; the detection unit generates a detection signal on the basis of a detection voltage and a preset voltage; the first delay control unit generates a first delay control signal on the basis of the detection signal and a first driving signal; the first driving unit generates, on the basis of the first delay control signal and a control signal, a second driving signal for driving a second transistor; the second delay control unit generates a second delay control signal on the basis of the second driving signal; and the second driving unit generates the first driving signal on the basis of the second delay control signal and the control signal. According to the driving circuit, the DC-DC converter and the driving method of the present invention, adaptive dead-time control can be added to a first transistor and the second transistor, dead time can be adapted and adjusted more flexibly, and external transistors having a wider range of gate charges can be compatible.

Description

Drive circuit, DC-DC converter and drive method

[0001] The present application claims priority to the Chinese patent application No. 202411315207.8, filed on September 19, 2024, and entitled "Drive circuit, DC-DC converter and drive method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application belongs to the technical field of integrated circuits, and particularly relates to a drive circuit, a DC-DC converter and a drive method. BACKGROUND

[0003] For the control of DC-DC, the gate charge range of the MOS tube used by the customer can be from several nC to several tens of nC, and we cannot make specific predictions, although the chip has made some dead time processing to prevent the simultaneous conduction of the upper and lower tubes to burn the chip, but the application of MOS tubes with a large range of unknown gate charge in the periphery still has the risk of through.

[0004] The common method to prevent through in the prior art is that the chip internally detects the first drive signal HO and the second drive signal LO, and considers making a dead time according to the feedback signal generated after detection.

[0005] For the MOS tube with unknown gate charge, the first drive signal HO and the second drive signal LO can be very slow or very fast; and the feedback signal has a fixed logic transmission, which is extremely easy to be out of synchronization with the first drive signal HO and the second drive signal LO, resulting in the possibility of overlap of the effective levels of the first drive signal HO and the second drive signal LO, and then the phenomenon of through occurs, and the chip is burned.

[0006] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present application and should not be regarded as an acknowledgment or any form of suggestion that this information forms prior art that is publicly known. SUMMARY

[0007] The purpose of the present application is to provide a drive circuit, a DC-DC converter and a drive method, which can set up a delay to ensure sufficient dead time and prevent the chip from being burned.

[0008] In order to achieve the above-mentioned purpose, a specific embodiment of the present application provides a drive circuit for driving a first transistor and a second transistor, a first end of the first transistor and a second end of the second transistor being connected to form a detection point, the drive circuit comprising: a first delay control unit, a first drive unit, a second delay control unit and a second drive unit.

[0009] The first delay control unit is connected with the detection point and the control end of the first transistor, so as to generate the first delay control signal based on the detection voltage of the detection point and the first driving signal of the control end of the first transistor; the first driving unit is connected with the output end of the first delay control unit, the control end of the second transistor and the control signal, so as to generate the second driving signal for driving the second transistor based on the first delay control signal and the control signal; the second delay control unit is connected with the control end of the second transistor, so as to generate the second delay control signal based on the second driving signal; and the second driving unit is connected with the output end of the second delay control unit, the control end of the first transistor and the control signal, so as to generate the first driving signal based on the second delay control signal and the control signal.

[0010] In one or more embodiments of the present application, the driving circuit further comprises a detection unit connected with the detection point and a preset voltage, so as to generate a detection signal based on the detection voltage of the detection point and the preset voltage; the first delay control unit is connected with the output end of the detection unit and the control end of the first transistor, so as to generate the first delay control signal based on the detection signal and the first driving signal of the control end of the first transistor; and the detection unit comprises a comparator, a first input end of the comparator is connected with the detection point, and a second input end of the comparator is used for receiving the preset voltage.

[0011] In one or more embodiments of the present application, the preset voltage is the threshold voltage of the first transistor or the second transistor.

[0012] In one or more embodiments of the present application, the first delay control unit comprises a first logic module and a first delay module; a first input end of the first logic module is connected with the detection point; a second input end of the first logic module is connected with the control end of the first transistor; the first logic module is used for performing logic operation on the detection voltage of the detection point and the first driving signal; an output end of the first logic module is connected with an input end of the first delay module; and an output end of the first delay module is used for outputting the first delay control signal.

[0013] In one or more embodiments of the present application, the first driving unit comprises a first inverter and a second logic module; an input end of the first inverter is used for receiving the control signal; a first input end of the second logic module is connected with an output end of the first inverter; a second input end of the second logic module is used for receiving the first delay control signal; an output end of the second logic module is connected with the control end of the second transistor; and the second logic module is used for performing logic operation on the inverted signal generated by the first inverter and the first delay control signal to generate the second driving signal.

[0014] In one or more embodiments of the present application, the second delay control unit comprises a second inverter and a second delay module, an input end of the second inverter is connected with a control end of the second transistor, an output end of the second inverter is connected with an input end of the second delay module, and an output end of the second delay module is used for outputting the second delay control signal.

[0015] In one or more embodiments of the present application, the second drive unit comprises a third logic module, a first input end of the third logic module is connected with the control signal, a second input end of the third logic module is used for receiving the second delay control signal, an output end of the third logic module is connected with the control end of the first transistor, and the third logic module is used for performing logic operation on the control signal and the second delay control signal to generate the first drive signal.

[0016] In one or more embodiments of the present application, the drive circuit further comprises a third delay module, an input end of the third delay module is used for receiving the control signal, and an output end of the third delay module is used for generating a characteristic signal representing the minimum turn-on time of the first transistor.

[0017] The present application further discloses a DC-DC converter comprising the drive circuit.

[0018] The present application further discloses a driving method for driving the first transistor and the second transistor, a first end of the first transistor and a second end of the second transistor are connected to form a detection point, and the driving method comprises the following steps based on the drive circuit:

[0019] generating the first delay control signal based on the detection voltage of the detection point and the first drive signal of the control end of the first transistor, and the first edge of the first delay control signal has a first delay time with the first edge of the control signal;

[0020] generating the second drive signal for driving the second transistor based on the first delay control signal and the control signal, the first edge of the control signal is used for generating the first edge of the second drive signal, and the second edge of the first delay control signal is used for generating the second edge of the second drive signal;

[0021] generating the second delay control signal based on the second drive signal, and the first edge of the second delay control signal has a first delay time with the first edge of the second drive signal;

[0022] generating the first drive signal based on the second delay control signal and the control signal, the first edge of the second delay control signal is used for generating the first edge of the first drive signal, and the second edge of the control signal is used for generating the second edge of the first drive signal.

[0023] In one or more embodiments of the present application, the second edge of the first delay control signal has a delay time greater than the second delay time from the second edge of the control signal.

[0024] Compared with the prior art, the driving circuit, the DC-DC converter and the driving method of the present application can detect the detection point by the detection unit, and make the first driving unit and the second driving unit generate corresponding driving signals through the delay control of the first delay control unit and the second delay control unit, so as to increase the adaptive dead-time control of the first transistor and the second transistor, and more flexibly adapt and adjust the dead-time, so as to be compatible with a wider range of external transistors with gate charges. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0026] Fig. 1 is a circuit schematic diagram of a driving circuit in an embodiment.

[0027] Fig. 2 is a timing diagram between signals in the driving circuit in an embodiment. DETAILED DESCRIPTION

[0028] In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0029] In the specification, “coupling” or “connection” or “connection” includes both direct connection and indirect connection. Indirect connection is the connection through an intermediate medium, such as the connection through an electrically conductive medium, which can have a parasitic inductance or a parasitic capacitance; indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through circuits or components such as switches, follower circuits, etc. In addition, in the present application, words such as “first”, “second” are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0030] In the detailed description of the application, reference is made to the accompanying drawings, which form a part hereof, in which like numerals designate like parts throughout the various figures and in which by way of illustration, one or more exemplary embodiments are shown. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0031] Various operations can be described as multiple discrete actions or operations in a manner that is most beneficial for understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order-dependent. In particular, these operations can not be performed in the order of presentation. Operations described can be performed in a different order than the described embodiment. Various additional operations can be performed and / or described operations can be omitted in additional embodiments.

[0032] For purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0033] Various components, devices, etc. can be referred to herein in singular form, or in the plural form, but this is merely for convenience and brevity, and in no way should be construed as limiting the scope of this disclosure to only a single item. For example, a component can include plurality of such components, and vice versa.

[0034] The specification describes using the phrases "in one embodiment" or "in other embodiments" or "in some embodiments," which can each refer to one or more embodiments among the same or different embodiments. In addition, the terms "comprising," "including," "having" and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0035] As shown in FIG. 1, a driving circuit in an embodiment of the present application is used to drive a first transistor M1 and a second transistor M2, a first end of the first transistor M1 and a second end of the second transistor M2 are connected to form a detection point P. The driving circuit includes a detection unit 10, a first delay control unit 20, a first driving unit 30, a second delay control unit 40, and a second driving unit 50. In one embodiment, the first transistor M1 and the second transistor M2 are N-channel MOS transistors, the first end of the first transistor M1 and the first end of the second transistor M2 are sources, the second end of the first transistor M1 and the second end of the second transistor M2 are drains, and the control end of the first transistor M1 and the control end of the second transistor M2 are gates. In other embodiments, the first transistor M1 and / or the second transistor M2 are P-channel MOS transistors.

[0036] The detection unit 10 is connected with the detection point P and a preset voltage Vth to generate a detection signal SW_REG based on a detection voltage SW of the detection point P and the preset voltage Vth.

[0037] The first delay control unit 20 is connected with an output terminal of the detection unit 10 and a control terminal of the first transistor M1 to generate a first delay control signal HS_BBM based on the detection signal SW_REG and a first drive signal HO of the control terminal of the first transistor M1.

[0038] The first drive unit 30 is connected with an output terminal of the first delay control unit 20, a control terminal of the second transistor M2 and a control signal PWM to generate a second drive signal LO for driving the second transistor M2 based on the first delay control signal HS_BBM and the control signal PWM.

[0039] The second delay control unit 40 is connected with the control terminal of the second transistor M2 to generate a second delay control signal LO_BBM based on the second drive signal LO.

[0040] The second drive unit 50 is connected with an output terminal of the second delay control unit 40, a control terminal of the first transistor M1 and the control signal PWM to generate the first drive signal HO based on the second delay control signal LO_BBM and the control signal PWM.

[0041] In an embodiment, the detection unit 10 comprises a comparator CMP, a first input terminal of the comparator CMP is connected with the detection point P, and a second input terminal of the comparator CMP is used to receive the preset voltage Vth. The preset voltage Vth is a threshold voltage of the first transistor M1 or the second transistor M2, preferably, the preset voltage Vth is a threshold voltage of the first transistor M1, and the threshold voltage is about 0.5V. When the detection voltage SW of the detection point P is greater than the preset voltage Vth, the detection signal SW_REG is high, and when the detection voltage SW of the detection point P is less than the preset voltage Vth, the detection signal SW_REG is low.

[0042] The first delay control unit 20 comprises a first logic module 21 and a first delay module 22. The first input end of the first logic module 21 is connected with the output end of the detection unit 10, and the second input end of the first logic module 21 is connected with the control end of the first transistor M1. The first logic module 21 is used for performing logic operation on the detection signal SW_REG and the first driving signal HO. The output end of the first logic module 21 is connected with the input end of the first delay module 22, and the output end of the first delay module 22 is used for outputting the first delay control signal HS_BBM. In an embodiment, the first logic module 21 is a NOR gate. The NOR gate performs or logic and non logic operation on the detection signal SW_REG and the first driving signal HO to generate a logic signal HO_REG. The first delay module 22 performs rising edge delay on the logic signal HO_REG to generate the first delay control signal HS_BBM. In other embodiments, the first delay module 22 can also perform falling edge delay or be used for performing rising edge delay and falling edge delay.

[0043] The first delay control unit 20 can adjust its delay time based on the trim code TRIM. In an embodiment, the first delay module 22 can adjust its rising edge delay time under the control of the trim code TRIM, so as to control the dead time.

[0044] The first driving unit 30 comprises a first inverter NOT1 and a second logic module 31. The input end of the first inverter NOT1 is used for receiving the control signal PWM. The first input end of the second logic module 31 is connected with the output end of the first inverter NOT1. The second input end of the second logic module 31 is used for receiving the first delay control signal HS_BBM. The output end of the second logic module 31 is connected with the control end of the second transistor M2. The second logic module 31 is used for performing logic operation on the inverse signal generated by the first inverter NOT1 and the first delay control signal HS_BBM to generate the second driving signal LO. In an embodiment, the second logic module 31 is a first AND gate AND1. The first inverter NOT1 is used for inverting the control signal PWM. The first AND gate AND1 performs and logic operation on the inverse signal of the control signal PWM and the first delay control signal HS_BBM to generate the second driving signal LO.

[0045] The second delay control unit 40 comprises a second inverter NOT2 and a second delay module 41. The input terminal of the second inverter NOT2 is connected with the control terminal of the second transistor M2. The output terminal of the second inverter NOT2 is connected with the input terminal of the second delay module 41. The output terminal of the second delay module 41 is used for outputting the second delay control signal LO_BBM. In an embodiment, the second inverter NOT2 is used for inverting the second drive signal LO. The second delay module 41 is used for delaying the rising edge of the inverted signal of the second drive signal LO to generate the second delay control signal LO_BBM. In other embodiments, the second delay module 41 can also delay the falling edge or be used for delaying the rising edge and the falling edge.

[0046] The second delay control unit 40 adjusts the delay time of itself based on the trimming code TRIM. In an embodiment, the second delay module 41 can adjust the delay time of itself under the control of the trimming code TRIM, so as to control the dead time.

[0047] The second drive unit 50 comprises a third logic module. The first input terminal of the third logic module is connected with the control signal PWM. The second input terminal of the third logic module is used for receiving the second delay control signal LO_BBM. The output terminal of the third logic module is connected with the control terminal of the first transistor M1. The third logic module is used for performing logical operation on the control signal PWM and the second delay control signal LO_BBM to generate the first drive signal HO. In an embodiment, the third logic module is a second AND gate AND2. The second AND gate AND2 is used for performing AND logical operation on the control signal PWM and the second delay control signal LO_BBM to generate the first drive signal HO.

[0048] As shown in FIG. 2, when the control signal PWM flips to high level, the second drive signal LO flips to low level, the second transistor M2 is turned off, and the second delay control signal LO_BBM flips to high level after the inversion and the rising edge delay of the second drive signal LO in the second delay control unit 40. Here, the first delay time is t1. At this time, the second delay control signal LO_BBM in high level and the control signal PWM in high level perform AND operation, the first drive signal HO flips to high level, and the first transistor M1 is turned on.

[0049] When the first drive signal HO flips to high level, the logic signal HO_REG and the first delay control signal HS_BBM flip to low level. The first transistor M1 is turned on, which causes the detection voltage SW of the detection point P to rise. When the detection voltage SW is greater than the preset voltage Vth, the detection signal SW_REG flips to high level, and the logic signal HO_REG and the first delay control signal HS_BBM continuously remain low level, and the second drive signal LO continuously remains low level.

[0050] When the control signal PWM flips to low level, the first drive signal HO flips to low level, the first transistor M1 is turned off, the detection voltage SW drops, and when the detection voltage SW drops to the preset voltage Vth, the detection signal SW_REG flips to low level, the logic signal HO_REG flips to high level, and the time when the detection voltage SW drops to the preset voltage Vth is recorded as tk; after the rising edge delay of the first delay module 22, the first delay control signal HS_BBM flips to high level, and the second delay time is recorded as t2. The inverting signal of the control signal PWM and the high-level first delay control signal HS_BBM are subjected to AND logic operation, the second drive signal LO flips to high level, and the second transistor M2 is turned on.

[0051] As shown in FIG. 2, the first delay time t1 and the second delay time t2 are set to ensure sufficient dead time and prevent the first transistor M1 and the second transistor M2 from being turned on at the same time. The first delay time t1 and the second delay time t2 can be flexibly adjusted as needed, so that the dead time can be flexibly adjusted.

[0052] The first transistor M1 and the second transistor M2 set externally will cause the conversion rate of the first drive signal HO and the second drive signal LO to be different. If the intermediate value of the first drive signal HO or the second drive signal LO, i.e., 1 / 2*HO or 1 / 2*LO, is used as the feedback detection value, it is easy to cause the first transistor M1 and the second transistor M2 to be turned on at the same time. In an embodiment, the threshold voltage of the first transistor M1 or the second transistor M2 is set to the preset voltage Vth. When the detection voltage SW at the detection point P rises and drops to the threshold voltage, the subsequent logic flip is triggered, ensuring that the second transistor M2 is turned on after the first transistor M1 is fully turned off. In other embodiments, if the conversion rate of the first drive signal HO and the second drive signal LO is not considered, the detection unit 10 can also not be set.

[0053] As shown in FIG. 1, the drive circuit further includes a third delay module 60. The input end of the third delay module 60 is used to receive the control signal PWM, and the output end of the third delay module 60 is used to generate a characteristic signal TON_MIN representing the minimum on time of the first transistor M1. In an embodiment, the third delay module 60 performs rising edge delay on the control signal PWM to generate the characteristic signal TON_MIN. The delay time is also t1. Through monitoring of the characteristic signal TON_MIN by the subsequent circuit, the minimum on time of the first transistor M1 can be obtained, and a suitable minimum on time ensures that the first transistor M1 can work normally. In other embodiments, the third delay module 60 can also perform falling edge delay or rising edge delay and falling edge delay as needed.

[0054] As can be seen from FIG. 2 and FIG. 1, because the delay module (such as the second delay module 41) is arranged in the drive circuit, when the control signal PWM flips to high level, the first drive signal HO does not flip to high level immediately, but flips to high level after the delay time t1, so that a delay error is caused in testing the minimum conduction time of the first transistor M1, therefore, the third delay module 60 is arranged to delay the rising edge of the control signal PWM, and the representation signal TON_MIN flips to high level after the control signal PWM flips to high level and delays t1, so as to offset the delay error and obtain the accurate minimum conduction time of the first transistor M1.

[0055] The application further discloses a DC-DC converter comprising the drive circuit, the first transistor M1, the second transistor M2, the inductor L, the first capacitor C1 and the second capacitor C2, the first end of the inductor L is connected with the detection point P, the second end of the inductor L is connected with the first end of the second capacitor C2 to form an output end VOUT, the second end of the second capacitor C2 is connected with the ground voltage, the first end of the first capacitor C1 is connected with the second end of the first transistor M1 to form an input end VIN connected with the power supply voltage, and the second end of the first capacitor C1 is connected with the ground voltage.

[0056] The application further discloses a driving method for driving the first transistor M1 and the second transistor M2, the first end of the first transistor M1 and the second end of the second transistor M2 are connected to form the detection point P, and the driving method comprises the following steps of:

[0057] The first delay control unit 20 generates the first delay control signal HS_BBM based on the detection voltage SW of the detection point P and the first drive signal HO of the control end of the first transistor M1, and the first edge (falling edge) of the first delay control signal HS_BBM has the first delay time t1 with the first edge (rising edge) of the control signal PWM. In an embodiment, the second edge (rising edge) of the first delay control signal HS_BBM has the delay time greater than the second delay time t2 with the second edge (falling edge) of the control signal PWM.

[0058] The first drive unit 30 generates the second drive signal LO for driving the second transistor M2 based on the first delay control signal HS_BBM and the control signal PWM, the first edge (falling edge) of the control signal PWM is used to generate the first edge (falling edge) of the second drive signal LO, and the second edge (rising edge) of the first delay control signal HS_BBM is used to generate the second edge (rising edge) of the second drive signal LO.

[0059] The second delay control unit 40 generates a second delay control signal LO_BBM based on the second drive signal LO, and a first edge (rising edge) of the second delay control signal LO_BBM has a first delay time t1 from a first edge (falling edge) of the second drive signal LO.

[0060] The second drive unit 50 generates the first drive signal HO based on the second delay control signal LO_BBM and a control signal PWM, and a first edge (rising edge) of the second delay control signal LO_BBM is used to generate a first edge (rising edge) of the first drive signal HO, and a second edge (falling edge) of the control signal PWM is used to generate a second edge (falling edge) of the first drive signal HO.

[0061] Further, in an embodiment, the detection unit 10 is arranged to generate a detection signal based on a detection voltage SW of the detection point P and a preset voltage Vth, and then the first delay control unit 20 generates the first delay control signal HS_BBM based on the detection signal SW_REG and the first drive signal HO of the control end of the first transistor M1. The specific method can refer to the circuit description part.

[0062] It is apparent for those skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, and the present application can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to encompass all changes falling within the meaning and range of equivalents of the claims. Any reference signs in the claims should not be considered as limiting the claims involved.

[0063] In addition, it should be understood that, although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments that those skilled in the art can understand.

Claims

1. A drive circuit for driving a first transistor and a second transistor, a first terminal of the first transistor and a second terminal of the second transistor being connected to form a detection point, characterized by, The driving circuit comprises: a first delay control unit connected to the detection point and the control end of the first transistor to generate a first delay control signal based on the detection voltage of the detection point and the first driving signal of the control end of the first transistor; a first driving unit connected to the output end of the first delay control unit, the control end of the second transistor and the control signal to generate a second driving signal for driving the second transistor based on the first delay control signal and the control signal; a second delay control unit connected to the control end of the second transistor to generate a second delay control signal based on the second driving signal; and a second driving unit connected to the output end of the second delay control unit, the control end of the first transistor and the control signal to generate the first driving signal based on the second delay control signal and the control signal.

2. The drive circuit according to claim 1, characterized in that The driving circuit further comprises a detection unit connected to the detection point and a preset voltage to generate a detection signal based on the detection voltage of the detection point and the preset voltage, the first delay control unit is connected to the output end of the detection unit and the control end of the first transistor to generate the first delay control signal based on the detection signal and the first driving signal of the control end of the first transistor, and the detection unit comprises a comparator, a first input end of the comparator is connected to the detection point, and a second input end of the comparator is used to receive the preset voltage.

3. The drive circuit according to claim 2, characterized in that The preset voltage is a threshold voltage of the first transistor or the second transistor.

4. The drive circuit according to claim 1, characterized by The first delay control unit comprises a first logic module and a first delay module, a first input end of the first logic module is connected to the detection point, a second input end of the first logic module is connected to the control end of the first transistor, the first logic module is used to perform logical operation on the detection voltage of the detection point and the first driving signal, an output end of the first logic module is connected to an input end of the first delay module, and an output end of the first delay module is used to output the first delay control signal.

5. The drive circuit according to claim 1, characterized by The first driving unit comprises a first inverter and a second logic module, an input end of the first inverter is used to receive the control signal, a first input end of the second logic module is connected to an output end of the first inverter, a second input end of the second logic module is used to receive the first delay control signal, an output end of the second logic module is connected to the control end of the second transistor, and the second logic module is used to perform logical operation on the inverted signal generated by the first inverter and the first delay control signal to generate the second driving signal.

6. The drive circuit according to claim 1, characterized by The second delay control unit comprises a second inverter and a second delay module, an input end of the second inverter is connected to the control end of the second transistor, an output end of the second inverter is connected to an input end of the second delay module, and an output end of the second delay module is used to output the second delay control signal.

7. The drive circuit according to claim 1, characterized by The second driving unit comprises a third logic module, a first input end of the third logic module is connected with the control signal, a second input end of the third logic module is used for receiving the second delay control signal, and an output end of the third logic module is connected with the control end of the first transistor. The third logic module is used for performing logical operation on the control signal and the second delay control signal to generate the first driving signal.

8. The drive circuit according to claim 1, characterized by The driving circuit further comprises a third delay module, an input end of the third delay module is used for receiving the control signal, and an output end of the third delay module is used for generating a characteristic signal representing the minimum turn-on time of the first transistor.

9. A DC-DC converter, characterized by The driving circuit comprises any one of claims 1-8.

10. A driving method for driving a first transistor and a second transistor, a first terminal of the first transistor and a second terminal of the second transistor being connected to form a detection point, the method comprising: The driving method is based on the driving circuit of any one of claims 1-8, and comprises: ​ generating the first delay control signal based on the detection voltage of the detection point and the first driving signal of the control end of the first transistor, the first edge of the first delay control signal having a first delay time with the first edge of the control signal; generating the second driving signal for driving the second transistor based on the first delay control signal and the control signal, the first edge of the control signal being used for generating the first edge of the second driving signal, and the second edge of the first delay control signal being used for generating the second edge of the second driving signal; generating the second delay control signal based on the second driving signal, the first edge of the second delay control signal having a first delay time with the first edge of the second driving signal; generating the first driving signal based on the second delay control signal and the control signal, the first edge of the second delay control signal being used for generating the first edge of the first driving signal, and the second edge of the control signal being used for generating the second edge of the first driving signal.

11. The driving method of claim 10, the second edge of the first delay control signal having a delay time greater than the second delay time with the second edge of the control signal.

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