Instruction processing method and apparatus, and processor, storage medium and program product

Abstract

Provided in the present disclosure are an instruction processing method and apparatus, and a processor, a storage medium and a computer program product. The instruction processing method is applied to a processor, which comprises a plurality of instruction execution ports, wherein each instruction execution port transmits one execution instruction or is in an idle state within one clock cycle. The instruction processing method comprises: specifying a corresponding register unit for each of a plurality of execution instructions that are transmitted in parallel and need to process the same input parameter; storing the input parameter in each register unit; and when a plurality of execution instructions are transmitted in parallel, controlling each of the plurality of execution instructions to acquire the input parameter from the corresponding register unit and process same. The present disclosure can implement the parallel transmission of a plurality of execution instructions, and makes better use of parallel-transmission characteristics, thereby improving the parallel performance of instructions, and achieving short overall time consumption and high efficiency of instruction execution.

Description

Instruction processing method and device, processor, storage medium and program product

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411310917.1, filed September 19, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of processors, and in particular to an instruction processing method, device, processor, storage medium and computer program product. BACKGROUND

[0004] At present, in order to improve the performance of a processor, the processor can adopt a multi-issue microarchitecture to issue multiple instructions in parallel in one clock cycle, such as two instructions, four instructions, etc. The processor core with the multi-issue microarchitecture has multiple instruction execution ports (Ports) and can issue multiple pipeline instructions in parallel on the basis of pipeline instructions. The multiple instruction execution ports can concurrently execute multiple execution instructions in one clock cycle, and the execution instructions can be data encryption execution instructions, etc. The multiple execution instructions issued in parallel need to process the same input parameter. Since only one copy of the input function is stored (transferred from the memory to a register unit), when one of the multiple execution instructions issued in parallel is executed, the register unit is occupied by the execution instruction, and the execution instruction obtains the input function and processes it. Before the execution instruction is executed, the other execution instructions in the multiple execution instructions issued in parallel are in a waiting state. After the execution instruction is executed, one of the other execution instructions in the multiple execution instructions issued in parallel can obtain the input parameter from the register unit and process it. Therefore, the parallel issue of the multiple execution instructions is actually partial or complete serial issue, the execution time of the execution instruction is increased, the running efficiency is reduced, and the performance of the processor is reduced. SUMMARY

[0005] The present disclosure provides an instruction processing method, device, processor, storage medium and computer program product.

[0006] According to a first aspect of the present disclosure, an instruction processing method is provided, applied to a processor, the processor comprising a plurality of instruction execution ports, each instruction execution port emitting one execution instruction in one clock cycle or being in an idle state, the instruction processing method comprising: respectively assigning a corresponding register unit for each of a plurality of execution instructions emitted in parallel and requiring to process the same input parameter; storing the input parameter in the register unit; and when the plurality of execution instructions are emitted in parallel, controlling each of the plurality of execution instructions to respectively acquire the input parameter from the corresponding register unit and process the input parameter.

[0007] Optionally, the input parameter comprises a processing result of an emitted execution instruction, and the assigning of the corresponding register unit for each of the plurality of execution instructions emitted in parallel and requiring to process the same input parameter comprises: assigning the corresponding register unit for each of the plurality of execution instructions after the emitted execution instruction is executed.

[0008] Optionally, the register unit comprises a second variable register unit and a first variable register unit corresponding to the emitted execution instruction, and the assigning of the corresponding register unit for each of the plurality of execution instructions comprises: assigning the first variable register unit for one of the plurality of execution instructions, and respectively assigning a corresponding second variable register unit for each of the other execution instructions of the plurality of execution instructions.

[0009] Optionally, the storing of the input parameter in the register unit comprises: storing the processing result in the first variable register unit and the second variable register unit.

[0010] Optionally, the storing of the processing result in the first variable register unit and the second variable register unit comprises: storing the processing result in the first variable register unit by the emitted execution instruction; and emitting a first copy execution instruction for storing the processing result in the second variable register unit after the emitted execution instruction is executed.

[0011] Optionally, the first copy execution instruction is emitted in a next clock cycle after a clock cycle corresponding to the emitted execution instruction.

[0012] Optionally, the input parameter comprises a parameter not processed by the emitted execution instruction, and the register unit comprises a third variable register unit, and the assigning of the corresponding register unit for each of the plurality of execution instructions emitted in parallel and requiring to process the same input parameter comprises: respectively assigning a corresponding third variable register unit for each of the plurality of execution instructions.

[0013] Optionally, the storing of the input parameter in the register unit comprises: storing an initial parameter in the third variable register unit.

[0014] Optionally, the storing the initial parameters in the third variable register unit comprises: before the plurality of execution instructions are emitted in parallel, emitting a second copy execution instruction for storing the parameters which are not processed by the emitted execution instructions in the third variable register unit.

[0015] Optionally, the execution instruction comprises an algorithm execution instruction for elliptic curve encryption, wherein the algorithm comprises a Montgomery ladder algorithm.

[0016] Optionally, the number of instruction execution ports comprises four, and the instruction processing method comprises: assigning the four instruction execution ports respectively with the algorithm execution instructions which need to be emitted; and assigning the four instruction execution ports respectively with the encryption processing data, wherein the encryption processing data comprises a first coordinate and a second coordinate of a first point on an elliptic curve in a projective coordinate system, and a first coordinate and a second coordinate of a second point on the elliptic curve in the projective coordinate system.

[0017] According to a second aspect of the present disclosure, an instruction processing apparatus is provided, applied to a processor, the processor comprising a plurality of instruction execution ports, each of the instruction execution ports emitting one execution instruction in one clock cycle or being in an idle state, the instruction processing apparatus comprising: an assigning module, configured to assign each of a plurality of execution instructions which are emitted in parallel and need to process the same input parameters with a corresponding register unit respectively; a storing module, configured to store the input parameters in the register units; and an executing module, configured to control each of the plurality of execution instructions to acquire the input parameters from the corresponding register units and process the input parameters when the plurality of execution instructions are emitted in parallel.

[0018] According to a third aspect of the present disclosure, a processor is provided, comprising the instruction processing apparatus as described above.

[0019] According to a fourth aspect of the present disclosure, a computer readable storage medium is provided, the computer readable storage medium storing computer instructions, the instructions being executed by a processor to perform the method as described above.

[0020] According to a fifth aspect of the present disclosure, a computer program product is provided, the computer program product storing computer instructions, the instructions being executed by a processor to perform the method as described above.

[0021] The instruction processing method, device, processor, storage medium and computer program product of the present disclosure can specify a register unit for each of the multiple execution instructions which are transmitted in parallel and need to process the same input parameter, store the input parameter in the register unit, and control each execution instruction to obtain the input parameter from the corresponding register unit and process the input parameter when the multiple execution instructions are transmitted in parallel. The parallel transmission of the multiple execution instructions can be realized, the concurrent characteristics can be better utilized, the instruction parallel performance is improved, and the overall time consumption of instruction running is short and the efficiency is high. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

[0023] Fig. 1 is a flowchart of some embodiments of the instruction processing method according to the present disclosure;

[0024] Fig. 2 is a flowchart of storing processing results in some embodiments of the instruction processing method according to the present disclosure;

[0025] Fig. 3 is a flowchart of implementing the Montgomery gradient algorithm in some embodiments of the instruction processing method according to the present disclosure;

[0026] Fig. 4 is a block diagram of some embodiments of the instruction processing device according to the present disclosure. DETAILED DESCRIPTION

[0027] In the following, exemplary embodiments of the present disclosure will be described with reference to the drawings. In the specification, not all of the features of the embodiments are described, for the sake of clarity and conciseness. It should be appreciated, however, that many implementation-specific settings must be made in order to implement the embodiments, in order to achieve the specific goals of the developers, such as compliance with those limitations related to the devices and businesses, and these limitations can vary from one implementation to another. In addition, it should be appreciated that, although the development work can be very complex and time-consuming, it is only a routine task for those skilled in the art who benefit from the present disclosure.

[0028] It should be noted that: unless otherwise specified, the relative arrangement, numerical expression and numerical value of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0029] Those skilled in the art can understand that the terms "first", "second" and the like in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, and do not represent any specific technical meaning, nor indicate their logical order.

[0030] It should also be understood that in the embodiments of the present disclosure, "multiple" can mean two or more, and "at least one" can mean one, two or more.

[0031] It should also be understood that for any component, data or structure mentioned in the embodiments of the present disclosure, it can be understood as one or more in general, without explicit limitation or in the context of the opposite indication.

[0032] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the front and rear associated objects.

[0033] It should also be understood that the description of the embodiments of the present disclosure focuses on the differences between the embodiments, and the same or similar parts can be referred to each other, and for the sake of brevity, will not be repeated.

[0034] At the same time, it should be understood that in order to facilitate the description, the size of each part shown in the drawings is not drawn according to the actual proportion relationship.

[0035] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application or uses.

[0036] The techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but in appropriate cases, the techniques, methods, and devices should be considered as part of the specification.

[0037] It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0038] In addition, in order to avoid obscuring the present disclosure due to unnecessary details, only the processing steps and / or device structures closely related to the scheme according to the present disclosure are shown in the drawings, and other details not closely related to the present disclosure are omitted. It should also be noted that similar reference numerals and letters in the drawings indicate similar items, and therefore once an item is defined in one drawing, it does not need to be discussed again for subsequent drawings.

[0039] Figure 1 is a flowchart of some embodiments of an instruction processing method according to the present disclosure, the instruction processing method shown in Figure 1 is applied to a processor, the processor includes a plurality of instruction execution ports, each instruction execution port emits one execution instruction in one clock cycle or is in an idle state. As shown in Figure 1, the instruction processing method includes steps S101 to S103.

[0040] Step S101, for each of a plurality of execution instructions emitted in parallel and requiring to process the same input parameters, a corresponding register unit is respectively specified.

[0041] In some embodiments, the processor can be a plurality of processors using a multi-emission microarchitecture. For example, the processor can be a four-emission microstructure processor, etc., four of the plurality of ports of the processor can be used as instruction execution ports, since one instruction execution port emits one execution instruction in the same clock cycle or is in an idle state, up to four instruction emissions can be completed in one clock cycle, which embodies four-way pipelining.

[0042] The execution instruction is the instruction of the execution stage in the pipeline, and the execution instruction can be a plurality of instructions, such as a function operation instruction, etc. The execution instruction is emitted through the instruction execution port, and after the execution instruction is emitted, the corresponding processing can be performed to obtain the corresponding execution and processing result. In the case where the input parameters of the plurality of execution instructions emitted in parallel are the same, a corresponding register unit is respectively specified for each of the plurality of execution instructions. The register unit can be a plurality of registers, a register group, etc.

[0043] Step S102, storing the input parameters in the register unit.

[0044] After a corresponding register unit is respectively specified for each of the plurality of execution instructions emitted in parallel and requiring to process the same input parameters, a plurality of methods can be used to store the input parameters in the corresponding register. The time consumed for storing the input parameters in the register unit is relatively short, which is usually much less than the time consumed for executing the instruction.

[0045] For example, a plurality of execution instructions emitted in parallel in one clock cycle are instruction 1 and instruction 2 respectively, the input parameters of instruction 1 are parameter a and parameter b, the input parameters of instruction 2 are parameter a and parameter c, and instruction 1 and instruction 2 require to process the same input parameter which is parameter a. A corresponding register unit is respectively specified for instruction 1 and instruction 2, wherein the register unit can store at least one parameter.

[0046] When instruction 1 and instruction 2 require to process the same input parameter which is parameter a, a corresponding register unit a and a register unit b are respectively specified for instruction 1 and instruction 2. Parameter a is stored in register unit a and register unit b, so that parameter a is saved in two copies.

[0047] In step S103, when multiple execution instructions are emitted in parallel, each execution instruction in the multiple execution instructions is controlled to obtain an input parameter from a corresponding register unit and perform processing.

[0048] For example, the input parameter of instruction 1 is parameter a and parameter b, and the input parameter of instruction 2 is parameter a and parameter c; when instruction 1 and instruction 2 are emitted in parallel, instruction 1 and instruction 2 are controlled to obtain parameter a from register unit a and register unit b, respectively, and at the same time, instruction 1 and instruction 2 are controlled to obtain parameter b and parameter c from the register units in which parameter b and parameter c are stored, respectively, instruction 1 performs corresponding processing based on parameter a and parameter b, and instruction 2 performs corresponding processing based on parameter a and parameter c.

[0049] Since parameter a is stored in register unit a and register unit b, respectively, there are two data of parameter a, and parameter b and parameter c are stored in corresponding registers, when obtaining parameter a, instruction 1 and instruction 2 can be obtained from register unit a and register unit b in parallel, without the need that one of instruction 1 and instruction 2 obtains parameter a and its parameters and executes, and then the other instruction can obtain parameter a, so that instruction 1 and instruction 2 can be truly emitted in parallel, better utilize the concurrency feature, make the running time of the instruction short and the efficiency high, and improve the performance of the processor.

[0050] In the existing technical solution of parallel execution of instructions by a processor using a multi-emission microarchitecture, multiple execution instructions emitted in parallel in the same clock cycle usually have the same input parameter, and the same input parameter is stored in a group of registers, at this time, other execution instructions wait until one execution instruction obtains the parameter in the register and completes the calculation, and then the parameter in the register can be called for calculation, and the efficiency of serial running is low.

[0051] The instruction processing method of the present disclosure can specify a register unit for each of multiple execution instructions emitted in parallel and needing to process the same input parameter, store the input parameter in the register unit, and control each execution instruction to obtain the input parameter from the corresponding register unit and perform processing when multiple execution instructions are emitted in parallel, so that multiple execution instructions needing to process the same input parameter can be emitted in parallel, the concurrency feature is better utilized, the parallel performance is improved, the overall running time of the instruction is short and the efficiency is high, and the performance of the processor is improved.

[0052] In some embodiments, the same input parameter required by the plurality of execution instructions for processing includes a processing result of the executed execution instruction, and a corresponding register unit can be specified for each of the plurality of execution instructions after the executed execution instruction is executed. The register unit includes a second variable register unit, a first variable register unit corresponding to the executed execution instruction, and the like. A first variable register unit can be specified for one of the plurality of execution instructions, and a corresponding second variable register unit can be specified for each of the other execution instructions of the plurality of execution instructions, and the processing result is stored in the second variable register unit and the first variable register unit.

[0053] For example, instruction 1 and instruction 2 require the same input parameter a as the processing result of instruction 3 executed before instruction 1 and instruction 2 are executed in parallel, and a corresponding register unit can be specified for instruction 1 and instruction 2 after instruction 3 is executed. A first variable register unit corresponding to the executed instruction 3 can be specified for instruction 1, and a second variable register unit can be specified for instruction 2, and parameter a is stored in the second variable register unit and the first variable register unit.

[0054] FIG. 2 is a flow diagram of storing a processing result in some embodiments of the instruction processing method according to the present disclosure. As shown in FIG. 2, the instruction processing method includes step S201 and step S202.

[0055] In step S201, a processing result is stored in a first variable register unit by an executed execution instruction. The processing result is the processing result of the executed execution instruction.

[0056] In step S202, after the executed execution instruction is executed, a first copy execution instruction is executed to store the processing result in a second variable register unit.

[0057] The first copy execution instruction can be executed in the next clock cycle after the clock cycle corresponding to the executed execution instruction.

[0058] The same input parameter required by the plurality of execution instructions for processing includes a parameter not processed by the executed execution instruction, and the parameter not processed by the executed execution instruction can be an initial parameter not processed by the executed execution instruction. The register unit includes a third variable register unit, and a corresponding third variable register unit can be specified for each of the plurality of execution instructions, and the initial parameter is stored in the third variable register unit. A second copy execution instruction can be executed before the plurality of execution instructions are executed in parallel to store the parameter not processed by the executed execution instruction in the third variable register unit.

[0059] For example, instruction 1 and instruction 2 need to process the same input parameter as parameter a, which is an initial parameter not processed by the executed execution instruction, and a corresponding third variable register unit 1 and a third variable register unit 2 can be respectively specified for instruction 1 and instruction 2 before instruction 1 and instruction 2. A second copy execution instruction can be transmitted before instruction 1 and instruction 2 are transmitted in parallel, to store parameter a in third variable register unit 1 and third variable register unit 2.

[0060] In some embodiments, the execution instruction includes an algorithm execution instruction for performing an elliptic curve encryption algorithm, which includes a Montgomery ladder algorithm (also known as a Montgomery ladder algorithm) and the like. Elliptic curve encryption has a large number of applications in technologies such as digital certificates, network communications, data security, blockchains, and privacy computing, and the elliptic curve encryption algorithm can be an elliptic curve random point scalar multiplication, which is the highest computational operator in elliptic curve encryption. Algorithms for implementing elliptic curve random point scalar multiplication include the Montgomery ladder algorithm and the like, and the Montgomery ladder algorithm has good performance.

[0061] The Montgomery ladder algorithm can be used in elliptic curve cryptography (ECC) to perform scalar multiplication of points on an elliptic curve, i.e., computing Q = k × P, where k is an integer (scalar) and P is a point on the curve. Scalar multiplication is the process of adding a point P to itself k times and is the basis for encryption, decryption, and digital signatures. In the Montgomery ladder algorithm, consistent point addition and point multiplication operations are maintained regardless of the value of k, enhancing the security of the scalar multiplication operation.

[0062] Each processor core of the multi-issue microarchitecture processor has multiple instruction execution ports, and the Montgomery ladder algorithm can be implemented in a multi-pipeline manner. By using the multi-issue microarchitecture processor to transmit algorithm execution instructions in parallel, good performance can be achieved.

[0063] For example, the number of instruction execution ports of the multi-issue microarchitecture processor is four, and the algorithm execution instructions of the Montgomery ladder algorithm to be transmitted are respectively allocated to the four instruction execution ports. Encryption processing data is respectively allocated to the four instruction execution ports, and the encryption processing data includes the first coordinate and the second coordinate of the first point on the elliptic curve in the projective coordinate system, and the first coordinate and the second coordinate of the second point on the elliptic curve in the projective coordinate system, and the like.

[0064] As shown in FIG. 3, the processor of the four-transmission micro-architecture includes four instruction execution ports, namely instruction execution port 1, instruction execution port 2, instruction execution port 3, and instruction execution port 4; the instruction execution port 1, the instruction execution port 2, the instruction execution port 3, and the instruction execution port 4 transmit one algorithm execution instruction of the Montgomery gradient algorithm or are in an idle state in one clock cycle.

[0065] The algorithm execution instruction of the Montgomery gradient algorithm is assigned to the four instruction execution ports for transmission, and a plurality of groups of register units are added. Two points, R0 and R1, can be set in the initialization process of the Montgomery gradient algorithm, and the values of the two points are updated in the subsequent n cycles. Since R0 and R1 are two points on an elliptic curve (the first point and the second point on the elliptic curve), the two points can be represented in affine coordinates (i.e., a plane Cartesian coordinate system): R0=(X2, Y2), R1=(X3, Y3).

[0066] Since performing elliptic curve point operation in affine coordinates will introduce too many finite field divisions (the calculation time of one finite field division is more than 200 times the calculation time of one finite field multiplication), in the Montgomery gradient algorithm, the points on the elliptic curve are represented in projective coordinates, i.e., R0=(x2, y2, z2), R1=(x3, y3, z3), where: i=2, 3.

[0067] Since the Montgomery gradient algorithm only uses the horizontal coordinates of the elliptic curve points, the y value can be ignored in the algorithm. FIG. 3 is a specific calculation flow and algorithm execution instruction in one cycle of the Montgomery gradient algorithm. By continuously updating the values of x2, z2, x3, and z3, the values of R0 and R1 can be continuously updated, and finally the horizontal coordinates of R0=k×P are obtained:

[0068] As shown in FIG. 3, the four instruction execution ports can be respectively assigned to process data x2, z2, x3, and z3, wherein x2 and z2 are the first coordinate and the second coordinate of the first point on the elliptic curve in the projective coordinate system, x3 and z3 are the first coordinate and the second coordinate of the second point on the elliptic curve in the projective coordinate system, and x2, z2, x3, and z3 represent two points on the elliptic curve. In each cycle of the Montgomery gradient algorithm, x1 is a fixed parameter, and x2, z2, x3, and z3 are the input and output of each cycle.

[0069] The finite field of the elliptic curve is usually a 256-bit large integer, and the register size of the four-emitting CPU micro-architecture is usually 64 bits, so each finite field large integer needs to be stored by four 64-bit registers, and the four 64-bit registers can be a register group. For each instruction configuration, a corresponding register is configured to store the processing result of the instruction; eight groups of registers t0, t1, t2, t3, r0, r1, r2, and r3 are configured to store the same input parameters required for processing multiple execution instructions.

[0070] Each cycle of the Montgomery gradient algorithm is provided with 9 layers of instructions, and the instructions of each layer can be sent in the same clock cycle. The functions performed by the instructions of each layer are various, wherein fe_mul() is a finite field multiplication function, fe_sqr() is a finite field square function, fe_const_mul() is a finite field constant multiplication function, fe_add() is a finite field addition function, fe_sub() is a finite field subtraction function, and fe_copy() is a finite field copy function.

[0071] As shown in FIG. 3, the first layer of instructions includes instructions E11, E12, E13, and E14; instruction E11 is t0=fe_copy(x2), instruction E12 is t1=fe_copy(z2), instruction E13 is t2=fe_copy(x3), and instruction E14 is t3=fe_copy(z3).

[0072] The second layer of instructions includes instructions E21, E22, E23, and E24; instruction E21 is x2=fe_add(x2,z2), instruction E22 is t0=fe_sub(t0,t1), instruction E23 is x3=fe_add(x3,z3), and instruction E24 is t2=fe_sub(t2,t3).

[0073] Among them, E21 and E22 need to process the same input parameters x2 and z2, which are parameters that have not been processed by the executed execution instructions. For E21, the corresponding register group 1 storing x2 and the register group 2 storing z2 (the register group 1 and the register group 2 are the third variable register unit) are specified, and before E21 and E22 are emitted in parallel, a (second) copy execution instruction can be emitted to store x2 in the register group 1 and z2 in the register group 1.

[0074] The register group t0 storing x2 and the register group t1 storing z2 corresponding to E22 are assigned (the register group 1 and the register group 2 are the third variable register unit), and the (second) copy execution instruction E11, E12 for storing x2 in the register group t0 and storing z2 in the register group t1 can be transmitted before E21 and E22 are transmitted in parallel. E21 and E22 can acquire the same input parameter from different register groups.

[0075] E23 and E24 need to process the same input parameters x3 and z3, which are parameters not processed by the transmitted execution instruction, and a similar method can be used to assign the third variable register unit to E23 and E24, and transmit the second copy execution instruction to store the parameters x3 and z3 in the third variable register unit before E23 and E24 are transmitted in parallel.

[0076] The third layer instruction includes instructions E31, E32; the instruction E31 is r0 = fe_copy(x2), and the instruction E32 is r1 = fe_copy(t0); the instruction execution port 3 and the instruction execution port 4 are in an idle state.

[0077] The fourth layer instruction includes instructions E41, E42, E43 and E44; the instruction E41 is z2 = fe_sqr(x2), the instruction E42 is t1 = fe_sqr(t0), the instruction E43 is t3 = fe_mul(r1, x3), and the instruction E44 is z3 = fe_mul(r0, t2).

[0078] Among them, E41 and E44 need to process the same input parameter x2, which is the processing result of the transmitted execution instruction E21, and the register unit 3 (the first variable register unit corresponding to the transmitted execution instruction E21) is assigned to E41, and the register unit r0 (the second variable register unit) is assigned to E44. The input parameter x2 is stored in the register unit 3 through the transmitted execution instruction E31; after the transmitted execution instruction E21 is executed, the (first) copy execution instruction E31 is transmitted to store the input parameter x2 in the register unit r0. E41 and E44 can acquire the same input parameter from different register groups.

[0079] The fifth layer instruction includes instructions E51, E52, E53 and E54; the instruction E51 is r2 = fe_copy(z2), the instruction E52 is r3 = fe_copy(t1), the instruction E53 is x3 = fe_copy(t3), and the instruction E54 is t2 = fe_copy(z3).

[0080] The sixth layer of instructions includes instructions E61, E62, E63 and E64; instruction E61 is x2 = fe_mul(z2, t1), instruction E62 is r3 = fe_sub(r2, r3), instruction E63 is t3 = fe_add(t3, t2), and instruction E64 is z3 = fe_sub(x3, z3).

[0081] The seventh layer of instructions includes instructions E71, E72 and E73; instruction E71 is t1 = fe_const_mul(121666, r3), instruction E72 is x3 = fe_sqr(t3), and instruction E73 is t2 = fe_sqr(z3); instruction execution port 1 is in an idle state.

[0082] The eighth layer of instructions includes instructions E81 and E82; instruction E81 is r2 = fe_add(r2, t1) or r2 = fe_add(x2, t1), and instruction E82 is z3 = fe_mul(t2, x1); instruction execution ports 1 and 3 are in idle states.

[0083] The ninth layer of instructions includes instruction E91; instruction E91 is z2 = fe_mul(r2, r3); instruction execution ports 1, 3 and 4 are in idle states.

[0084] In terms of time consumption of finite field operators, finite field multiplication > finite field squaring > finite field constant multiplication >> finite field addition = finite field subtraction > finite field copying, i.e., in terms of time consumption, fe_mul > fe_sqr > fe_const_mul >> fe_add = fe_sub > fe_copy.

[0085] As shown in FIG. 3, the four instruction execution ports in the first and second layers of instructions have substantially the same time consumption; although the third layer of instructions has only two instruction execution ports for copying operations, since each operator in the fourth layer depends on all parameters in the third layer, the two idle instruction execution ports also need to wait for the execution time of the copying operations in the third layer; the first two instruction execution ports in the fourth layer of instructions perform finite field squaring operations, and the last two instruction execution ports perform finite field multiplication operations, the first two instruction execution ports will be executed first and enter the copying operations in the fifth layer, at this time all other register groups have been occupied, therefore, the last two register groups r2 and r3 are introduced here to perform the copying operations in the fifth layer of the first two ports in advance.

[0086] For the fifth layer instruction, the data between the first two instruction execution ports and the last two instruction execution ports is no longer interacted and is isolated; for the two groups of ports, the layer is a copy operation. Since the time consumption of finite field multiplication is greater than the time consumption of finite field squaring plus the time consumption of finite field copying, after the fifth layer copy operation of the first two instruction execution ports is executed, the last two instruction execution ports are still executing the fourth layer finite field multiplication operation.

[0087] In the sixth layer instruction, the first instruction execution port executes the finite field multiplication operation and generates x2, and the second, third and fourth instruction execution ports all execute the finite field addition or subtraction operation. In the seventh layer instruction, the first instruction execution port is idle, the second instruction execution port executes the finite field constant multiplication operation, the last two instruction execution ports execute the finite field squaring operation, and the third instruction execution port generates x3 after the execution is completed.

[0088] In the eighth layer instruction, the first instruction execution port is idle, the second instruction execution port executes the finite field addition operation using the copy result in the fifth layer, the third instruction execution port is idle, and the fourth instruction execution port executes the finite field multiplication operation and generates z3. In the ninth layer instruction, the second instruction execution port executes the finite field multiplication operation and generates z2.

[0089] By setting the assignment path of the input and output of the register group in the Montgomery gradient algorithm, each instruction will not exist the case that the relevant register group is occupied by other instructions when executing, thereby maximizing the parallelism of instruction execution.

[0090] As shown in FIG. 3, from the fourth layer instruction, the execution time of each instruction execution port is not synchronized, and the height of the layer does not completely determine the time consumption of the final execution, but the second and fourth instruction execution ports become the key points of determining the performance: the second instruction execution port (instruction execution port 2) executes 1 time of finite field multiplication, 1 time of finite field squaring, 1 time of finite field constant multiplication, 1 time of finite field addition, 1 time of finite field subtraction and 1 time of finite field copying from the fourth layer instruction to the last; the fourth instruction execution port (instruction execution port 4) executes two times of finite field multiplication, 1 time of finite field squaring, 1 time of finite field subtraction and 1 time of finite field copying from the fourth layer instruction to the last. The time consumption of 1 time of finite field constant multiplication + 1 time of finite field addition is similar to the time consumption of 1 time of finite field multiplication, and the latter is slightly more time-consuming, so the operation speed of the fourth instruction execution port determines the operation performance of the entire algorithm.

[0091] The instruction processing method in the above embodiment can improve the execution performance of the Montgomery gradient algorithm, reduce the clock period of the algorithm (through relevant tests, the execution performance of the Montgomery gradient algorithm can be improved by 15% by applying the present application), better utilize the concurrency characteristics, improve the parallel performance, shorten the overall time consumption of instruction running, improve the efficiency, and improve the performance of the processor. The present disclosure can be implemented using an assembly language or other computer programming languages.

[0092] In some embodiments, the present disclosure provides an instruction processing apparatus applied to a processor, the processor including a plurality of instruction execution ports, each instruction execution port emitting one execution instruction in one clock period or being in an idle state. As shown in FIG. 4, the instruction processing apparatus 40 includes an allocation module 41, a storage module 42, and an execution module 43.

[0093] The allocation module 41 respectively specifies a corresponding register unit for each execution instruction in a plurality of execution instructions emitted in parallel and requiring to process the same input parameter. The storage module 42 stores the input parameter in the register unit. The execution module 43 controls each execution instruction in the plurality of execution instructions to respectively acquire the input parameter from the corresponding register unit and process the input parameter when the plurality of execution instructions are emitted in parallel.

[0094] In some embodiments, the input parameter includes a processing result of an emitted execution instruction, and the allocation module 41 respectively specifies a corresponding register unit for each execution instruction in the plurality of execution instructions after the emitted execution instruction is executed.

[0095] The register unit includes a second variable register unit, a first variable register unit corresponding to the emitted execution instruction, and the like. The allocation module 41 specifies the first variable register unit for one execution instruction in the plurality of execution instructions, and respectively specifies a corresponding second variable register unit for each other execution instruction in the plurality of execution instructions.

[0096] The storage module 42 stores the processing result in the first variable register unit and the second variable register unit. For example, the storage module 42 stores the input parameter in the first variable register unit through the emitted execution instruction. The storage module 42 emits a first copy execution instruction to store the input parameter in the second variable register unit after the emitted execution instruction is executed. The storage module 42 can emit the first copy execution instruction in the next clock period after the clock period corresponding to the emitted execution instruction.

[0097] In some embodiments, the input parameters include parameters that are not processed by the executed execution instructions, the register unit includes a third variable register unit, and the allocation module 41 respectively assigns a corresponding third variable register unit to each of the plurality of execution instructions. The storage module 42 stores the parameters that are not processed by the executed execution instructions in the third variable register unit. For example, the storage module 42 transmits a second copy execution instruction to store the parameters that are not processed by the executed execution instructions in the third variable register unit before the plurality of execution instructions are transmitted in parallel.

[0098] In some embodiments, the execution instructions include algorithm execution instructions for performing elliptic curve encryption, and the algorithm includes a Montgomery ladder algorithm or the like. The number of instruction execution ports includes four, and the allocation module 41 respectively assigns the algorithm execution instructions that need to be transmitted to the four instruction execution ports; and the allocation module 41 respectively assigns encryption processing data to the four instruction execution ports, wherein the encryption processing data includes first coordinates and second coordinates of a first point on an elliptic curve in a projective coordinate system, and first coordinates and second coordinates of a second point on the elliptic curve in the projective coordinate system.

[0099] In some embodiments, the present disclosure provides a processor including the instruction processing apparatus in any of the above embodiments.

[0100] In some embodiments, the present disclosure provides a computer readable storage medium storing computer instructions, which when executed by a processor, implement the method in any of the above embodiments.

[0101] The computer readable storage medium can take the form of one or more combinations of any type of readable media. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium can include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0102] Embodiments of the present disclosure can also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor executes the steps of the methods according to various embodiments of the present disclosure described in the above “Exemplary Methods” section of the present specification.

[0103] The instruction processing method, the device, the processor, the storage medium and the computer program product in the above embodiments can respectively specify a register unit for a plurality of execution instructions which are transmitted in parallel and need to process the same input parameter, store the input parameter in the register unit, control each execution instruction to obtain the input parameter from the corresponding register unit and process the input parameter when the plurality of execution instructions are transmitted in parallel. The parallel transmission of the plurality of execution instructions can be implemented, the concurrent characteristics are better utilized, the instruction parallel performance is improved, the overall time consumption of instruction running is short, the efficiency is high, the performance of the processor is improved, and the use experience of the user is improved.

[0104] The above describes the basic principles of the present disclosure in combination with specific embodiments. However, it should be noted that the advantages, advantages, effects and the like mentioned in the present disclosure are only examples and are not limiting. These advantages, advantages, effects and the like cannot be considered as the must-have of each embodiment of the present disclosure. In addition, the above specific details are only for the purpose of example and understanding, and are not limiting. The above details do not limit the present disclosure to the above specific details.

[0105] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between each embodiment can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0106] The block diagrams of the devices, apparatuses, equipment, systems involved in the present disclosure are only exemplary examples and are not intended to require or imply the connection, arrangement, configuration shown in the block diagram. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any way. Words such as "include", "contain", "have" and the like are open words, which means "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0107] It should also be noted that in the devices, apparatuses and methods of the present disclosure, each component or step can be decomposed and / or recombined. These decompositions and / or recombination should be considered as equivalent solutions of the present disclosure.

[0108] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0109] The above description has been given for the purposes of illustration and description. Furthermore, this description does not purport to be exhaustive or to limit the embodiments of the disclosure to the precise forms disclosed. Although several example aspects and embodiments have been discussed above, one skilled in the art will understand that the embodiments described above are merely illustrative and not limiting of the scope of the disclosure. One skilled in the art should appreciate that the above-described embodiments can be combined, modified, or replaced without departing from the scope and spirit of the disclosure.

Claims

1. An instruction processing method applied to a processor, the processor comprising a plurality of instruction execution ports, each instruction execution port emitting an execution instruction in one clock cycle or being idle, the instruction processing method comprising: specifying a corresponding register unit for each of a plurality of execution instructions to be emitted in parallel, which require the same input parameter to be processed; storing the input parameter in the register unit; and controlling each of the plurality of execution instructions to be emitted in parallel to retrieve the input parameter from the corresponding register unit and process it when the plurality of execution instructions are emitted in parallel. The input parameter comprises a processing result of an emitted execution instruction, and the specifying a corresponding register unit for each of a plurality of execution instructions to be emitted in parallel, which require the same input parameter to be processed comprises:

2. The instruction processing method of claim 1, wherein, specifying a corresponding register unit for each of the plurality of execution instructions after the emitted execution instruction is executed. The register unit comprises a second variable register unit, a first variable register unit corresponding to the emitted execution instruction, and the specifying a corresponding register unit for each of the plurality of execution instructions comprises:

3. The instruction processing method of claim 2, wherein, specifying the first variable register unit for one of the plurality of execution instructions, and specifying a corresponding second variable register unit for each of the other of the plurality of execution instructions. The storing the input parameter in the register unit comprises:

4. The instruction processing method of claim 3, wherein, storing the processing result in the first variable register unit and the second variable register unit. The storing the processing result in the first variable register unit and the second variable register unit comprises:

5. The instruction processing method of claim 4, wherein, storing the processing result in the first variable register unit by the emitted execution instruction; and emitting a first copy execution instruction to store the processing result in the second variable register unit after the emitted execution instruction is executed.

6. The instruction processing method of claim 5, wherein: the first copy execution instruction is emitted in a next clock cycle after a clock cycle corresponding to the emitted execution instruction. The input parameter comprises a parameter not processed by an emitted execution instruction, and the register unit comprises a third variable register unit, and the specifying a corresponding register unit for each of a plurality of execution instructions to be emitted in parallel, which require the same input parameter to be processed comprises:

7. The instruction processing method of claim 2, wherein, specifying a corresponding third variable register unit for each of the plurality of execution instructions. The storing the input parameter in the register unit comprises:

8. The instruction processing method of claim 7, wherein, storing the initial parameter in the third variable register unit. The storing the initial parameter in the third variable register unit comprises:

9. The instruction processing method of claim 8, wherein, emitting a second copy execution instruction to store the parameter not processed by the emitted execution instruction in the third variable register unit before the plurality of execution instructions are emitted in parallel. ​ 10. The instruction processing method of any one of claims 1 to 9, wherein the execution instruction comprises an algorithm execution instruction for performing elliptic curve encryption, and the algorithm comprises a Montgomery ladder algorithm. The number of instruction execution ports comprises four, and the instruction processing method comprises:

11. The instruction processing method of claim 10, wherein, allocating the algorithm execution instruction to be transmitted to each of the four instruction execution ports, respectively; and allocating encryption processing data to each of the four instruction execution ports, respectively, and the encryption processing data comprises first and second coordinates of a first point on an elliptic curve in a projective coordinate system, and first and second coordinates of a second point on the elliptic curve in the projective coordinate system.

12. An instruction processing apparatus applied to a processor, the processor comprising a plurality of instruction execution ports, each of the instruction execution ports transmitting one execution instruction in one clock cycle or being in an idle state, the instruction processing apparatus comprising: an allocation module configured to assign a corresponding register unit to each of a plurality of execution instructions which are transmitted in parallel and need to process the same input parameter, respectively; a storage module configured to store the input parameter in the register unit; and an execution module configured to control each of the plurality of execution instructions to obtain the input parameter from the corresponding register unit and process the input parameter when the plurality of execution instructions are transmitted in parallel.

13. A processor comprising: the instruction processing apparatus of claim 12.

14. A computer readable storage medium storing computer instructions, the instructions being executed by a processor to perform the method of any one of claims 1 to 11.

15. A computer program product storing computer instructions, the instructions being executed by a processor to perform the method of any one of claims 1 to 11. ​

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