A photonic entropy source co-integrated with a cryptographic device

Abstract

A cryptographic device comprising a Photonic Entropy Source, ES, and an electronic cryptographic module, CM, wherein both the ES and the CM are integrated into a single chip. Also, a method for fabricating an integrated cryptographic device using a VCSEL, the method comprising: fabricating a cryptographic module using CMOS technology; fabricating a VCSEL laser using III-V semiconductor technology; connecting the VCSEL laser to the cryptographic module via a direct contact to a waveguide; and integrating the VCSEL laser and the cryptographic module into a single chip assembly

Description

[0001] A PHOTONIC ENTROPY SOURCE CO-INTEGRATED WITH A CRYPTOGRAPHIC DEVICE

[0002] BACKGROUND OF THE DISCLOSURE

[0003] Cryptographic devices are everywhere in modern society, from the chip in a credit card to the secure messaging apps on a phone. Used to provide security and privacy, these devices are the foundations of security in the digital age.

[0004] For devices that require the maximum level of security, such as those used in banking, government, and military applications, the security of the cryptographic device itself is paramount. If an attacker can compromise the device, they can compromise the security of the entire system. To avoid this, cryptographic devices are often designed with a Root of Trust (RoT) that provides a secure foundation for the device's security. This RoT is a secure, tamper-resistant component that is used to securely store cryptographic keys and perform cryptographic operations.

[0005] However, the functionality of the RoT is not limited to just cryptographic operations. Among the many applications of the RoT is the generation of random numbers, which are used in a variety of cryptographic protocols, such as key generation, encryption, and digital signatures. The quality of the random numbers generated by the RoT is crucial to the security of the cryptographic device, as poor-quality random numbers can lead to vulnerabilities that can be exploited by attackers. Therefore, the inclusion of a high-quality entropy source in the RoT is essential to ensuring the security of the device.

[0006] The RoT is typically implemented as a hardware component, such as a secure element (SE) in the form of a secure enclave or a trusted platform module (TPM). These hardware components are designed to be tamper-resistant and secure, and are often used to store sensitive information, such as cryptographic keys, securely. However, the security of these hardware components is not guaranteed, and they can be vulnerable to a variety of attacks, such as side-channel attacks, fault injection attacks, and physical attacks. Therefore, it is essential to design the RoT with security in mind, and to implement it in a way that is resistant to these attacks.

[0007] Among those attacks, one of the most severe is supplanting the entropy source of the RoT. If an attacker can control the entropy source of the RoT, they can control the random numbers generated by the RoT, and potentially compromise the security of the entire system. Therefore, the co-integration of the RoT and its entropy source is crucial to ensuring the security of the device, and with it, the trustworthiness of the Root of Trust itself. There are multiple options for the entropy source of the RoT, such as hardware random number generators (HRNGs). However, these HRNGs are often external to the RoT, so it is difficult to ensure their security. In the cases in which such HRNGs are integrated into the RoT, they typically suffer from undesirable properties, such as low entropy, or impossibility to verify the quality of the generated random numbers.

[0008] Regarding entropy properties, photonic-based quantum random number generators (QRNGs) emerge as one of the most promising entropy sources available. Photonic QRNGs are based on the principles of quantum mechanics and generate random numbers by measuring the quantum properties of light. These devices are inherently random and can generate high-quality random numbers with high entropy. In addition, photonic-based QRNG provide the possibility of measuring the entropy quality from first principles. Furthermore, photonic QRNGs are resistant to a variety of attacks, such as side-channel attacks, fault injection attacks, and physical attacks, making them an ideal choice for the entropy source of the RoT. Moreover, some of them also show additional properties, such as high-speed (in the tenths of Gbps range), scalability, and low power consumption, which make them suitable for a wide range of applications.

[0009] However, this technology is still in its infancy, and there are many challenges that need to be addressed before photonic QRNGs can be widely deployed in cryptographic devices. One of the main challenges is the integration of the photonic QRNG with the RoT. Most of these devices are also external to the RoT, so it is also difficult to ensure their security.

[0010] Moreover, the integration of photonic components with the electronics of the RoT is by no means trivial. For CMOS-based (complementary metal-oxide semiconductor-based) RoTs, which are typically used in commercial applications, and made of silicon, the integration of photonic components is challenging due to the incompatibility of the CMOS technology with some of the components required for the operation of the photonic QRNGs.

[0011] As silicon is a material with an indirect bandgap, it is not suitable for the generation of light, which is required for the operation of the photonic QRNGs. Therefore, the integration of photonic components with CMOS technology requires the use of additional materials, such as lll-V semiconductors, which are not compatible with the CMOS technology, and require separate fabrication processes and packaging to operate.

[0012] Therefore, an approach that allows the integration of photonic QRNGs with CMOS-based RoTs, while ensuring the security of the device, is essential to the widespread adoption of this technology. SUMMARY OF THE DISCLOSURE

[0013] The disclosure herein relates to a cryptographic device that comprises a Photonic Entropy Source (ES), which preferably comprises or is a Quantum Entropy Source, and an electronic cryptographic module (CM), wherein both the ES and the CM are integrated into a single chip or a single chip assembly. Examples of photonic and / or quantum entropy sources include, but are not limited to, phase-diffusion, vacuum fluctuations, single-photon avalanche diodes (SPADs), and vertical-cavity surface-emitting lasers (VCSELs).

[0014] The disclosure herein also relates to a method for using a cryptographic device, and a method for fabricating a cryptographic device.

[0015] The cryptographic module according to the present disclosure is an electronic cryptographic module that performs cryptographic operations, including -but not limited to- key generation, encryption, and digital signatures. In preferred embodiments, the CM interfaces with the ES to receive random numbers generated by the ES, and to use them in cryptographic operations. In some embodiments, the CM also controls the operation of the ES and ensures that the random numbers generated by the ES are of high quality and have high entropy. In some embodiments, the CM is CMOS-based.

[0016] In some embodiments, the cryptographic device comprises a Root of Trust (RoT) that is used to provide a secure foundation for the security of the device. The RoT is typically implemented as a component such as, e.g., a secure, tamper-resistant component that is used to securely store cryptographic keys and perform cryptographic operations. In some embodiments, the RoT is used to securely generate and store cryptographic keys, and to protect them from unauthorized access. In this sense, the RoT may be a component that at least comprises at least one memory, and at least one circuit and / or processor configured to perform the cryptographic operations. The component is provided with an enclosure that preferably comprises means for precluding tampering

[0017] In some embodiments, the cryptographic device further comprises a secure element (SE), such as a secure enclave, that is used to securely store cryptographic keys and other sensitive information. The SE is typically integrated into the same chip as the ES and the CM and is used to provide a secure foundation for the security of the device. In some embodiments, the SE is used to securely store the cryptographic keys used by the CM, and to protect them from unauthorized access. In this sense, the SE may be a component that at least comprises at least one memory, and at least one circuit and / or processor configured to preclude reading, storing, modifying and / or removing data from the at least one memory unless authorized access is provided. In some embodiments, the cryptographic device further comprises an enclosure, preferably a tamper-resistant enclosure, that is used to protect the device from physical attacks. In some embodiments, the enclosure is designed to be tamper-evident, so that any attempts to tamper with the device can be detected.

[0018] A photonic entropy source according to the present disclosure produces random numbers by using at least one unpredictable physical phenomenon. Preferably, at least one of the unpredictable physical phenomena will have a quantum origin. Examples of said entropy sources include -but are not limited to- phase-diffusion entropy sources, vacuum fluctuations, and VCSEL entropy sources.

[0019] In some embodiments, the photonic entropy source comprises a light source that is used to generate photons, and a detector that is used to detect the photons. Examples of light sources include -but are not limited to- lasers, light-emitting diodes (LEDs), and VCSELs. The light sources may be, e.g., modulated such that they are capable of operating as entropy source. Examples of detectors include -but are not limited to- photodiodes.

[0020] In some embodiments, the light source and / or the detector are / is connected by an optical path that is used to guide the photons from the light source to the detector. The optical path is typically designed to be resistant to a variety of attacks, such as side-channel attacks, fault injection attacks, and physical attacks, and is used to ensure the security of the device. In some embodiments, the optical path is designed to be tamper-evident, so that any attempts to tamper with the device, and in particular with the optical device, can be detected. Examples of optical paths include -but are not limited to- waveguides and interferometers.

[0021] In some embodiments, the cryptographic device also comprises at least one polarizer. The at least one polarizer is used to distinguish the photons generated by the light source according to its polarization, or a related characteristic (such as wavelength, for VCSELs). In some embodiments, such at least one polarizer is used to select or discard photons according to their polarization, or a related characteristic. Examples of polarizers include - but are not limited to- linear polarizers, polarization-dependent isolators, discriminating gratings (either by polarization or by wavelength), and polarization beam splitters. In some embodiments, the at least one polarizer is placed in the optical path between the laser and the photodetector. In some embodiments, the at least one polarizer is integrated into the laser and / or the photodetector themselves. The at least one polarizer may comprise one polarizer or more than one polarizer.

[0022] In some embodiments, the cryptographic device comprises at least one substrate. The substrate provides mechanical support for one or more components of the device and may additionally provide electrical interconnections, thermal management, and / or optical routing. Examples of substrates include -but are not limited to- silicon substrates, silicon- on-insulator (SOI) substrates, glass substrates, ceramic substrates, and organic substrates. In some embodiments, the substrate serves as a base layer upon which components are fabricated, grown, or mounted. In some embodiments, multiple substrates are employed, including growth substrates for epitaxial growth of lll-V materials and carrier substrates for final device assembly.

[0023] In some embodiments, the entropy source and the cryptographic module are co-integrated by means of an interposer, that allows each module (i.e., the entropy source and the cryptographic module) to preserve its own fabrication process and individual interfaces. In some embodiments, the interposer is used to connect the ES and the CM, and to ensure that the random numbers generated by the ES are securely transmitted to the CM. In some embodiments, the interposer is used to provide a secure connection between the ES and the CM, and to protect the random numbers generated by the ES from unauthorized access. Examples of interposers include -but are not limited to- silicon interposers and glass interposers.

[0024] In some embodiments, the entropy source and the cryptographic module are connected by means of a direct connection, that allows each module (i.e., the entropy source and the cryptographic module) to preserve its own fabrication process and individual interfaces. Examples of direct connections include -but are not limited to- wire bonds and flip-chip connections.

[0025] In some embodiments, the entropy source and the cryptographic module are monolithically integrated, wherein different components of the entropy source (e.g., one, some or all) are provided in the same die as the cryptographic module. Examples of such components include -but are not limited to- the detector, and the at least one polarizer. In some embodiments, these components are fabricated using the same process as the cryptographic module, including -but not limited to- CMOS technology.

[0026] In some embodiments, the entropy source and the cryptographic module are heterogeneously integrated into the single chip or single chip assembly, wherein the cryptographic module is provided on a first die, at least one component of the entropy source is provided on a second die, and the first die and the second die are co-integrated into the single chip or single chip assembly. In some embodiments, at least one component is attached to the at least one substrate to provide mechanical support and / or thermal management for the single chip or single chip assembly. In some embodiments, at least one component of the entropy source is epitaxially grown on the at least one substrate before integration. In some embodiments, at least one component of the entropy source is transfer-printed onto the at least one substrate.

[0027] In some embodiments where heterogeneous integration is employed, the light source (e.g., laser, LED, VCSEL) is provided on a different die than the cryptographic module within the single chip or single chip assembly. In some embodiments, the light source is fabricated using a different process than the cryptographic module, including -but not limited to- lll-V semiconductor technology. In some embodiments, the light source is optically coupled to components on the cryptographic module die through at least one of: direct waveguide coupling, coupling through the polarizer, or coupling to the photodetector.

[0028] In some embodiments where monolithic integration is employed, the light source (e.g., laser) is provided in the same die as the cryptographic module. In some embodiments, the material required for the light source (e.g., laser) is deposited on top of the chip (e.g., CMOS chip), and the light source is fabricated using the same process as the cryptographic module. In some embodiments, the light source (e.g., laser) is connected to the cryptographic module by means of a direct contact to the waveguide, the polarizer, or the photodetector.

[0029] For the purposes of this description, “a direct contact to the waveguide” comprises any type of optical coupling in which the different optical components have direct contact between them. Examples include, but are not limited to, edge coupling, grating coupling, buttcoupling, evanescent coupling, and taper-based coupling.

[0030] In some embodiments, the bonding of components to the at least one substrate is performed using process-agnostic bonding. Examples include, but are not limited to, direct wafer bonding, micro-transfer printing, and through-silicon vias (TSVs).

[0031] It is one purpose of the present disclosure to provide a cryptographic device that comprises a Photonic Entropy Source (ES), and an electronic cryptographic module (CM), wherein both the ES and the CM are integrated into a single chip or single chip assembly, preferably providing CMOS-compatibility with as many parts as possible, thus reducing the complexity and costs of the fabrication process, and allowing for high-volume production.

[0032] Overall, the disclosure addresses the challenges of integrating photonic QRNGs with CMOS-based RoTs, enabling a scalable production of a trustworthy RoT with an integrated source for high-quality random numbers. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The details of the present application, both as to its structure and operation, can best be understood in reference to the accompanying drawings, in which like reference numerals refer to like parts and in which:

[0034] • Figure 1 shows a basic schematic of embodiments of the disclosure.

[0035] • Figure 2 shows an embodiment in which the ES and the CM are co-integrated by means of an interposer.

[0036] • Figure 3 shows an embodiment in which the ES and the CM are directly connected.

[0037] • Figure 4 shows an embodiment of the ES, in which all ES components are fabricated in the same chip.

[0038] • Figure 5 shows an embodiment of the ES, in which additional components are shown to be integrated within the same chip.

[0039] • Figure 6 shows an embodiment in which the laser is fabricated in a different chip, and the laser is connected to the cryptographic module by means of a direct contact to the waveguide.

[0040] • Figure 7 shows an embodiment in which the laser is fabricated in the same chip as the cryptographic module, and the laser is connected to the cryptographic module by means of a direct contact to the waveguide.

[0041] DETAILED DESCRIPTION

[0042] Figure 1 shows a basic schematic of embodiments of the disclosure. The cryptographic device 101 comprises at least one entropy source, in particular at least one Photonic Entropy Source (ES) 102, and at least one electronic cryptographic module (CM) 103, wherein both the at least one ES and the at least one CM are integrated into a single chip or single chip assembly 101 , in the following referred to as single chip for the sake of clarity only, but it will be noted that the term also encompasses the possibility of a single chip assembly. The ES 102 is used to generate random numbers, and the CM 103 is used to perform cryptographic operations.

[0043] In some embodiments, the at least one entropy source 102 comprises one or more Quantum Entropy Sources that utilize quantum effects for randomness. Quantum random number generators (QRNGs) exploit the inherent randomness of quantum processes. Examples of these Quantum Entropy Sources include -but are not limited to- phasediffusion processes, VCSELs, Photon polarization states, and vacuum fluctuations. In some embodiments, the at least one ES 102 comprises a VCSEL entropy source. In some embodiments, the VCSEL generates entropy by going from below threshold to above threshold, in such a way that the mode of the laser after each cycle is unpredictable, and thus, the output of the VCSEL is random. In some embodiments, the extraction of the random numbers is done by separating the different modes of the VCSEL and selecting one of them for digitization. In some embodiments, the extraction of the random numbers is done by filtering modes of the VCSEL, leaving those that are of interest for digitization. In some embodiments, these modes of the VCSEL are distinguishable by their polarization. In some embodiments, these modes of the VCSEL are distinguishable by their wavelength. In some embodiments, these modes of the VCSEL are distinguishable by their spatial distribution.

[0044] In some embodiments, this separation process is carried out by means of a polarizer. In some embodiments, the polarizer is used to select or discard photons according to their polarization, or a related characteristic. In some embodiments, the polarizer is used to distinguish the photons generated by the light source according to its polarization, or a related characteristic. Examples of polarizers include -but are not limited to- linear polarizers, polarization-dependent isolators, discriminating gratings (either by polarization or by wavelength), and polarization beam splitters.

[0045] In some embodiments, the at least one ES 102 comprises a phase-diffusion entropy source. In some embodiments, the phase-diffusion entropy source generates random numbers by measuring the phase of the light generated by at least one pulsed laser. In some embodiments, the phase of the light is measured by means of an interferometer and a photodetector.

[0046] In some embodiments, the at least one ES 102 comprises a vacuum fluctuation entropy source. In some embodiments, the vacuum fluctuation entropy source generates random numbers by measuring the fluctuations of the vacuum state of the electromagnetic field. In some embodiments, the vacuum fluctuations are measured by means of a beam splitter and a photodetector.

[0047] The cryptographic module 103 is an electronic cryptographic module that performs cryptographic operations, including -but not limited to- key generation, encryption, and digital signatures. In preferred embodiments, the CM interfaces with the ES to receive random numbers generated by the ES, and to use them in cryptographic operations. In some embodiments, the CM also controls the operation of the ES and ensures that the random numbers generated by the ES are of high quality and have high entropy. In some embodiments, the CM is CMOS-based.

[0048] In some embodiments, the cryptographic device 101 comprises a Root of Trust (RoT) that provides a hardware-based secure foundation for the device's security. The RoT is implemented as a dedicated, tamper-resistant hardware component with its own at least one processor and at least one memory, preferably at least one secure processor and at least one isolated memory to further improve establishing trust from the lowest levels of a device or system boot process. Unlike software-based security solutions, the hardware RoT cannot be modified by malware and provides immutable identity verification. In some embodiments, the RoT performs secure boot verification, ensuring only authenticated firmware runs on the device. In some embodiments, the RoT generates and stores the device's unique cryptographic identity keys in hardware-protected memory, providing attestation capabilities that prove the device's authenticity to external systems. The integration of the RoT with the quantum entropy source provides a critical advantage: the RoT can directly access truly random numbers for key generation without exposure to potentially compromised software layers, significantly enhancing the cryptographic strength compared to conventional RoT implementations that rely on pseudo-random number generators.

[0049] In some embodiments, the cryptographic device 101 comprises a secure element like a secure enclave that provides an isolated execution environment separate from the main processor. The SE is integrated into the same chip assembly as the ES and the CM, featuring its own at least one processor and at least one memory, preferably at least one dedicated processor and at least one memory that remains inaccessible even to the device's operating system. Unlike the RoT which primarily handles boot security and device identity, the SE actively manages runtime cryptographic operations for user applications, including biometric data processing, payment credentials, and secure communications. In some embodiments, the SE includes hardware-accelerated cryptographic engines optimized for specific algorithms. The direct integration with the photonic entropy source enables the SE to perform real-time key generation for session-based encryption without relying on the main system's potentially vulnerable random number generation, providing enhanced protection against side-channel attacks that could compromise software-based random number generators.

[0050] In some embodiments, the cryptographic device 101 comprises a tamper-resistant enclosure that is used to protect the device from physical attacks. In some embodiments, the enclosure is designed to be tamper-evident, so that any attempts to tamper with the device can be detected. The combination of physical tamper resistance with integrated photonic entropy generation provides multi-layer security: even if an attacker attempts physical access, the optical properties of the entropy source are inherently sensitive to mechanical disturbance, causing detectable changes in the random number output that can trigger security responses. This creates a synergistic security enhancement where the photonic components serve dual purposes as both entropy sources and intrusion detectors.

[0051] In some embodiments, the cryptographic device 101 comprises a Trusted Platform Module (TPM) that provides cryptographic functionality, preferably standardized cryptographic functionality, and preferably compliant with TCG (Trusted Computing Group) specifications. While the RoT provides the foundational hardware trust anchor and the SE handles userfacing secure operations, the TPM specifically enables platform integrity verification and remote attestation according to industry standards. The TPM includes Platform Configuration Registers (PCRs) that store device or system state measurements, enabling detection of unauthorized modifications to system firmware or configuration. In some embodiments, the TPM leverages the integrated photonic entropy source to enhance its random number generation beyond the minimum TCG requirements, providing higher entropy rates for cryptographic operations such as RSA key generation and nonce creation for attestation protocols. This integration eliminates the TPM's traditional reliance on lower- quality on-chip ring oscillator entropy sources.

[0052] It is an aspect of the present disclosure that the cryptographic device 101 and the photonic entropy source 102 are integrated. In some embodiments, this integration is carried out by means of an interposer that enables high-density interconnections between dies with different fabrication technologies. The interposer provides several critical technical advantages: it enables co-integration of lll-V photonic components with CMOS technology that cannot inherently support the same optical properties; it provides thermal isolation between the temperature-sensitive photonic entropy source and the heat-generating cryptographic processor, maintaining entropy quality even under elevated temperature operation; and it enables a high number of electrical interconnects between the ES and CM, supporting parallel random bit streams for increased throughput. Furthermore, in some embodiments, the interposer incorporates embedded shielding layers that provide electromagnetic isolation between the optical and electronic domains, preventing electronic noise from corrupting the quantum random signal. The interposer architecture also enables modular testing where each die can be validated independently before assembly, potentially improving manufacturing yield compared to monolithic approaches for complex designs. In some embodiments, the cryptographic device 101 and the photonic entropy source 102 are directly connected. This allows for different fabrication processes for the ES and the CM, whilst allowing for the integration of both devices in the same chip, without requiring intermediate coupling components.

[0053] In some embodiments, the cryptographic device 101 and the photonic entropy source 102 use different materials for their fabrication. Examples of these include, but are not limited to, silicon for the CM, and lll-V semiconductors for the ES.

[0054] In some embodiments, at least some parts of the photonic entropy source are fabricated in the same chip, preferably in the same die, as the cryptographic module. Examples of these include, but are not limited to, the detector, the waveguide, and the at least one polarizer, when one or more of these components are arranged. In some embodiments, these components are fabricated using the same process as the cryptographic module, including -but not limited to- CMOS technology.

[0055] In some embodiments employing heterogeneous integration, the light source (e.g., the laser) is fabricated in a different die than the cryptographic module within the single chip assembly. In some embodiments, the laser is fabricated using a different process than the cryptographic module, including -but not limited to- lll-V semiconductor technology. In some embodiments, the light source (e.g., the laser) is optically coupled to the cryptographic module through the waveguide, the at least one polarizer, or the photodetector.

[0056] In some embodiments employing monolithic integration, the light source (e.g., the laser) is fabricated in the same die as the cryptographic module. In some embodiments, the material required for the laser is deposited on top of the CMOS chip, and the laser is fabricated using the same process as the cryptographic module. In some embodiments, the light source (e.g., the laser) is connected to the cryptographic module by means of a direct contact to the waveguide, the at least one polarizer, or the photodetector.

[0057] Figure 2 shows an embodiment in which the ES and the CM are co-integrated by means of an interposer. The ES 201 is connected to the CM 202 by means of an interposer 203, which provides a secure connection 204 between the ES and the CM. The interposer 203 allows for different fabrication processes for the ES and the CM, whilst allowing for the integration of both devices in the same chip.

[0058] Examples of interposers 203 include -but are not limited to- silicon interposers and glass interposers. Examples of connections 204 include -but are not limited to- solder bumps and wire bonds. Figure 3 shows an embodiment in which the ES and the CM are directly connected. The ES 301 is connected to the CM 302 by means of a direct connection 303, which allows for different fabrication processes for the ES and the CM, whilst allowing for the integration of both devices in the same chip, without requiring intermediate coupling components. Examples of direct connections 304 include -but are not limited to- edge coupling and flipchip connections.

[0059] Figure 4 shows an embodiment of the ES, in which all ES components are fabricated in the same chip. The ES comprises a light source 401 that is used to generate photons, and a detector 402 that is used to detect the photons. The light source 401 and the detector 402 are connected by an optical path 403 that is used to guide the photons from the light source to the detector. In some embodiments, the optical path 403 is designed to be resistant to a variety of attacks, such as side-channel attacks, fault injection attacks, and physical attacks, and is used to ensure the security of the device. Examples of optical paths 403 include - but are not limited to- waveguides and interferometers.

[0060] In some embodiments, the optical path 403 is contained within a substrate 404. In some embodiments, the substrate 404 is made of silicon, SIO (Silicon Oxide), or SiN (Silicon Nitride). In some embodiments, the substrate 404 is made of glass. In some embodiments, the substrate 404 is made of a lll-V semiconductor, including -but not limited to- GaAs, InP, and GaN.

[0061] Figure 5 shows an embodiment of the ES, in which additional components are shown to be integrated within the same chip. The ES comprises a light source 501 that is used to generate photons, a detector 502 that is used to detect the photons, a waveguide 503 that is used to guide the photons from the light source to the detector, and a polarizer 504 that is used to distinguish the photons generated by the light source according to its polarization. The polarizer 504 is used to select or discard photons according to their polarization, or a related characteristic. Examples of polarizers 504 include -but are not limited to- linear polarizers, polarization-dependent isolators, discriminating gratings (either by polarization or by wavelength), and polarization beam splitters. In this embodiment, the polarizer 504 is used to select photons according to their polarization, sending those with a desired polarization to the detector 502, and other ones to a different path 505, ending in a termination 506. In some embodiments, the termination 506 is used to absorb the photons that are not of interest. In some embodiments, the termination 506 is a photodetector.

[0062] Figure 6 shows an embodiment employing heterogeneous integration, in which the light source, such as a laser, is fabricated in a different die than the cryptographic module, with both dies assembled into a single chip. The ES comprises a light source 601 (including - but not limited to- a VCSEL device) that is used to generate photons, a detector 602 that is used to detect the photons, and a polarized waveguide 603 that is used to select and guide the photons of interest from the light source to the detector. In the present embodiment, the photodetector 602 and the waveguide 603 are integrated in the same die as the cryptographic module 604.

[0063] Different coupling methods between the light source 601 and waveguide 603 provide distinct technical advantages: edge coupling typically enables high coupling efficiency with relaxed alignment tolerances suitable for high-volume manufacturing; flip-chip connections can provide self-aligned assembly with minimal optical path length, reducing propagation losses; grating coupling allows for wafer-level testing before assembly, improving yield; buttcoupling offers low insertion loss for single-mode applications; and hybrid bonding provides both optical and electrical connections simultaneously with high alignment accuracy, enabling dense integration. The choice of coupling method can be optimized based on the specific entropy source requirements, with phase-sensitive applications favoring low-loss direct coupling methods, while high-throughput manufacturing may prioritize self-aligned approaches.

[0064] Figure 7 shows an embodiment employing monolithic integration, in which the light source (e.g., a laser) is fabricated in the same die as the cryptographic module, and the light source is connected to the cryptographic module by means of a direct contact to the waveguide. In this case, a thin layer of lll-V semiconductor material 701 is deposited on top of the CMOS chip, and the light source 702 (e.g., laser) is fabricated out of such layer. The choice of III- V material system provides specific advantages for entropy generation: GaAs-based VCSELs can offer mode-hopping behavior at low threshold currents, ideal for low-power entropy generation; InP-based sources enable operation at telecom wavelengths where silicon is transparent, allowing for on-chip optical isolation; and GaN-based sources can provide high-temperature stability with reduced wavelength drift, critical for maintaining consistent entropy quality across operating conditions. The direct epitaxial growth or wafer bonding of lll-V materials onto the CMOS substrate eliminates packaging parasitics that could introduce correlations in the random output.

[0065] This monolithic approach provides superior performance compared to heterogeneous integration for certain applications: the intimate thermal coupling between the light source and CMOS circuitry enables precise temperature control for wavelength stability, critical for VCSEL-based entropy sources; the elimination of die-to-die interfaces reduces optical reflections that could compromise randomness quality; and the single-die fabrication eliminates alignment variations that could introduce deterministic bias in the entropy output. Furthermore, the monolithic integration enables tight synchronization between the entropy source and cryptographic module, allowing for higher random number generation rates compared to heterogeneous approaches limited by inter-die communication bandwidth.

[0066] In this embodiment, the light source 702 is connected to the photodetector 703 via the waveguide 704. The light source 702 connects with the waveguide 704 using a direct connection, built during the fabrication process. In this embodiment, the photodetector 703 and the waveguide 704 are fabricated using the same process as the cryptographic module 705. In other embodiments, the photodetector 703 and / or the waveguide 704 are fabricated using a different process than the cryptographic module 705. In some embodiments, the photodetector 703 and / or the waveguide 704 are fabricated using the same technology as the light source 702. Examples of these include, but are not limited to, lll-V semiconductor technology, such as GaAs, InP, and GaN.

[0067] It is one purpose of the present disclosure to provide a cryptographic device that comprises a Photonic Entropy Source (ES), and an electronic cryptographic module (CM), wherein both the ES and the CM are integrated into a single chip, providing CMOS-compatibility with as many parts as possible, thus reducing the complexity and costs of the fabrication process, and allowing for high-volume production.

[0068] It is one purpose of the present disclosure to provide an enabling device for securing communication methods, such that these methods employ the entropy source device disclosed for the generation of random numbers.

[0069] It should be noted that the above-described examples of the present solution are for the purpose of illustration. Although the solution has been described in conjunction with specific examples thereof, numerous modifications are possible without materially departing from the teachings of the subject matter described herein. Other substitutions, modifications and changes may be made without departing from the spirit of the present solution. It should also be noted that when functions or operations (for example, but without limitation, interfacing, reception, use, control, etc.) are described in relation to one or more components (e.g., the ES, the CM, etc.), the disclosure encompasses the relative component being configured to conduct such function or operation (e.g., the CM is configured to interface with the ES to receive the random numbers, etc.).

[0070] In this text, the term “includes”, “comprises” and derivations thereof (such as “including”, “comprising”, etc.) should not be understood in an excluding sense, that is, these terms should not be interpreted as excluding the possibility that what is described and defined may include further elements, steps, etc.

[0071] All the features and applications disclosed in the present disclosure (including any accompanying claims, abstract and drawings), and / or all the parts of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and / or parts are mutually exclusive.

Claims

CLAIMS1 . A cryptographic device comprising a Photonic Entropy Source, ES, and an electronic cryptographic module, CM, wherein both the ES and the CM are integrated into a single chip.

2. The cryptographic device of claim 1 , wherein the ES comprises a VCSEL as a light source for entropy generation.

3. The cryptographic device of any one of claims 1-2, wherein the ES and the CM are co-integrated by means of an interposer.

4. The cryptographic device of any one of claims 1-2, wherein the ES and the CM are connected via an edge coupling.

5. The cryptographic device of any one of claims 1-2, wherein the ES and the CM are connected via a flip-chip connection.

6. The cryptographic device of any one of claims 1-5, wherein the ES and the CM are fabricated using different materials or processes.

7. The cryptographic device of any one of claims 1-2, further comprising a detector, and a waveguide, wherein the detector and the waveguide are provided in the same die as the cryptographic module.

8. The cryptographic device of claim 7 when depending upon claim 2, wherein the VCSEL light source is provided on a die different than a die that the cryptographic module is provided on, within the single chip, and the VCSEL light source is connected to the cryptographic module by means of a direct contact to the waveguide.

9. The cryptographic device of claim 7, wherein the VCSEL light source is provided on the same die as the cryptographic module, and the VCSEL light source is connected to the cryptographic module by means of a direct contact to the waveguide.

10. The cryptographic device of any one of claims 1-9, wherein the cryptographic module is CMOS-based.11 . The cryptographic device of any one of claims 1-10, further comprising a hardware Root of Trust module comprising at least one processor and at least one isolated memory12. The cryptographic device of any one of claims 1-11 , further comprising a tamperresistant enclosure.

13. A method for fabricating an integrated cryptographic device, the integrated cryptographic device comprising a VCSEL, the method comprising:- Fabricating a cryptographic module using CMOS technology;- Fabricating a VCSEL laser using lll-V semiconductor technology;- Connecting the VCSEL laser to the cryptographic module by means of a direct contact to a waveguide; wherein the cryptographic module and the VCSEL laser are integrated in a single chip.

14. The method of claim 13, further comprising fabricating a photodetector and at least one polarizer using the same fabrication technology as the VCSEL laser.

15. The method of claim 13, further comprising fabricating a photodetector and a waveguide using the same fabrication technology as the cryptographic module.

16. The method of claim 13, wherein the cryptographic module and the VCSEL laser are fabricated in a same die of the single chip.

17. The method of claim 13, wherein the cryptographic module is fabricated in a first die of the single chip and the VCSEL laser is fabricated in a second die of the single chip.

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