Semiconductor device

Abstract

The present invention provides a semiconductor device that has a novel configuration. The semiconductor device includes a memory cell, a first sense amplifier, a product-sum operation circuit, a data holding circuit, and a second sense amplifier. The memory cell is electrically connected to the first sense amplifier via a first bit line. The first bit line is electrically connected to the product-sum operation circuit via the data holding circuit. The second sense amplifier is electrically connected to the first sense amplifier and the product-sum operation circuit via a second bit line. The first sense amplifier has a function of amplifying first data held by the memory cell selected by a word line selection signal, and a function of outputting the amplified first data to the second sense amplifier according to a column selection signal. The data holding circuit has a function of holding the amplified first data. The product-sum operation circuit has a function of executing a product-sum operation of the first data and the second data supplied from the second sense amplifier via the second bit line according to the column selection signal.

Description

Semiconductor equipment

[0001] This specification describes semiconductor devices and the like.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, imaging devices, display devices, light-emitting devices, energy storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them.

[0003] In recent years, the importance of addressing global warming has increased. Energy consumption continues to rise, and carbon dioxide emissions, a major contributor to global warming, have yet to be reduced. Simply reducing energy consumption can sometimes compromise convenience. To reduce energy consumption without sacrificing convenience, low-power consumption technologies are extremely important.

[0004] In Artificial Intelligence (AI) technology, power consumption is increasing with performance improvements, leading to active development of technologies for lower power consumption. AI technology repeatedly performs operations such as sequentially reading data stored in memory circuits, performing calculations using that data in arithmetic circuits, and storing the resulting data in memory. Therefore, the power consumption required for data transmission between the memory circuit and the arithmetic circuit becomes dominant. As a countermeasure, a technology called in-memory computing or near-memory computing has been proposed, for example, which integrates the memory circuit and the arithmetic circuit using an oxide semiconductor transistor (also called an OS transistor) (see, for example, Patent Document 1).

[0005] U.S. Patent Publication No. 2021 / 0024083

[0006] When data is transmitted between a memory circuit and an arithmetic circuit, a sense amplifier is required to read the data held in the arithmetic circuit. Therefore, in order to integrate the memory circuit and the arithmetic circuit to reduce the power consumption required for data transmission, a configuration in which the memory circuit, the sense amplifier, and the sense amplifier and the arithmetic circuit are arranged close to each other is effective. The memory circuit can be arranged close to the sense amplifier by arranging it directly above the sense amplifier. Also, the arithmetic circuit can be arranged close to the sense amplifier by arranging it side by side alternately with the sense amplifier.

[0007] The sense amplifier requires a signal for controlling the sense amplifier. Also, the arithmetic circuit requires a signal for controlling the arithmetic circuit. That is, a control circuit for controlling the sense amplifier and a control circuit for controlling the arithmetic circuit are required. Therefore, the circuit area increases. Also, when different signals are supplied to each of the sense amplifier and the arithmetic circuit, wiring for supplying the signals is required. Therefore, the circuit area increases. Also, with an increase in the number of wirings and the circuit area, there is a risk of an increase in power consumption and a decrease in arithmetic processing speed.

[0008] Also, since the arithmetic circuit provided close to the memory circuit has a limit in the area where the circuit can be arranged, there may be a limit in the arithmetic processing ability. In this case, the sense amplifier needs to be activated in order to continuously hold the data read from the memory circuit until the arithmetic processing is completed. Therefore, even if an increase in the number of wirings and the circuit area can be eliminated, there is a risk that an improvement in the arithmetic processing speed and a reduction in power consumption cannot be expected.

[0009] One aspect of the present invention has an object of providing a semiconductor device with reduced power consumption. Or, one aspect of the present invention has an object of providing a semiconductor device in which the arithmetic processing speed is improved. Or, one aspect of the present invention has an object of providing a miniaturized semiconductor device. Or, one aspect of the present invention has an object of providing a semiconductor device with a novel configuration.

[0010] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will become apparent from the descriptions in the specification, claims, drawings, etc., and it is possible to extract these other problems from the descriptions in the specification, claims, drawings, etc.

[0011] One aspect of the present invention includes a memory cell, a first sense amplifier, a sum-of-products operation circuit, a data holding circuit, and a second sense amplifier. The first sense amplifier, the second sense amplifier, and the sum-of-products operation circuit are provided in a first element layer, the memory cell and the data holding circuit are provided in a second element layer, the second element layer is provided above the first element layer, the memory cell is electrically connected to the first sense amplifier via a first bit line, the first bit line is electrically connected to the sum-of-products operation circuit via the data holding circuit, the second sense amplifier is electrically connected to the first sense amplifier and the sum-of-products operation circuit via a second bit line, the first sense amplifier has a function of amplifying first data held by the memory cell selected by a word line selection signal, and a function of outputting the amplified first data to the second sense amplifier according to a column selection signal, the data holding circuit has a function of holding the amplified first data, and the sum-of-products operation circuit has a function of performing a sum-of-products operation on the first data and second data supplied from the second sense amplifier via the second bit line according to a column selection signal.

[0012] In one aspect of the present invention, the memory cell preferably has a first transistor, and the first transistor has a first semiconductor layer having a channel formation region, and the first semiconductor layer has indium oxide.

[0013] In one aspect of the present invention, the second element layer preferably has a switch, and the switch has a function of dividing a plurality of first bit lines electrically connected to the memory cell into a plurality, and electrically connecting any one of the first bit lines divided into a plurality to the first sense amplifier.

[0014] In one embodiment of the present invention, a semiconductor device is preferred in which the first bit line has a portion provided between the memory cell and the first sense amplifier, and between the data holding circuit and the multiply-accumulate circuit, parallel to the direction perpendicular to the substrate surface on which the first element layer is provided.

[0015] In one embodiment of the present invention, a semiconductor device is preferred in which the first element layer has a second transistor, the second transistor has a second semiconductor layer having a channel formation region, and the second semiconductor layer has silicon.

[0016] In one embodiment of the present invention, a semiconductor device is preferred that has a column line-side drive circuit that outputs a column selection signal, the column line-side drive circuit is electrically connected to a column line that supplies the column selection signal, and the column line is alternately connected to a first sense amplifier and a multiply-accumulate circuit in the direction in which the column line extends.

[0017] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings.

[0018] One aspect of the present invention can provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a semiconductor device with improved processing speed. Alternatively, one aspect of the present invention can provide a miniaturized semiconductor device. Alternatively, one aspect of the present invention can provide a semiconductor device with a novel configuration.

[0019] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have to possess all of the exemplified effects. In addition, any problems, effects, and novel features of one embodiment of the present invention other than those described above will become clear from the description and drawings of this specification.

[0020] Figures 1A and 1B illustrate an example of the configuration of a semiconductor device. Figures 2A, 2B, and 2C illustrate an example of the configuration of a semiconductor device. Figures 3A and 3B illustrate an example of the configuration of a semiconductor device. Figures 4A and 4B illustrate an example of the configuration of a semiconductor device. Figures 5A and 5B illustrate an example of the configuration of a semiconductor device. Figures 6A, 6B, and 6C illustrate an example of the configuration of a semiconductor device. Figures 7A, 7B, 7C, 7D, 7E, 7F, and 7G illustrate an example of the configuration of a semiconductor device. Figures 8A, 8B, and 8C illustrate an example of the configuration of a semiconductor device. Figures 9A, 9B, and 9C illustrate an example of the configuration of a semiconductor device. Figures 10A and 10B illustrate an example of the configuration of a semiconductor device. Figure 11 illustrates an example of the configuration of a semiconductor device. Figure 12 illustrates an example of the configuration of a semiconductor device. Figure 13 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. Figure 14A illustrates an example of the configuration of a transistor included in a semiconductor device. Figure 14B is a diagram illustrating the equivalent circuit of a memory cell. Figures 15A, 15B, and 15C are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. Figure 16A is a plan view illustrating an example of the configuration of a transistor included in a semiconductor device. Figures 16B, 16C, and 16D are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. Figure 17A is a plan view illustrating an example of the configuration of a transistor included in a semiconductor device. Figures 17B, 17C, and 17D are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. Figure 18 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. Figure 19A is a diagram illustrating an example of the configuration of a transistor included in a semiconductor device. Figure 19B is a diagram illustrating the equivalent circuit of a memory cell. Figures 20A and 20B are plan views showing an example of the configuration of a transistor included in a semiconductor device, and Figure 20C is a cross-sectional view showing an example of the configuration of a transistor included in a semiconductor device. Figures 21A and 21B are cross-sectional views showing an example of the configuration of a transistor included in a semiconductor device. Figure 22 is a cross-sectional view showing an example of the configuration of a transistor included in a semiconductor device. Figures 23A and 23B are diagrams illustrating an example of an electronic component.Figures 24A, 24B, 24C, and 24D illustrate an example of an electronic component. Figures 25A and 25B illustrate an example of an electronic device. Figures 26A, 26B, and 26C illustrate an example of an electronic device. Figure 27 illustrates an example of a large computer. Figure 28 illustrates an embodiment of one aspect of the present invention. Figure 29 illustrates an embodiment of one aspect of the present invention. Figure 30 illustrates an embodiment of one aspect of the present invention. Figures 31A and 31B illustrate an embodiment of one aspect of the present invention. Figure 32 illustrates an embodiment of one aspect of the present invention. Figures 33A and 33B illustrate an embodiment of one aspect of the present invention. Figures 34A and 34B illustrate an embodiment of one aspect of the present invention. Figure 35 illustrates an embodiment of one aspect of the present invention.

[0021] Embodiments of the present invention are described below. However, it will be readily apparent to those skilled in the art that an embodiment of the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, an embodiment of the present invention is not to be interpreted as being limited to the contents of the embodiments shown below.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] In drawings, identical elements, elements with similar functions, elements of the same material, or elements formed simultaneously may be denoted by the same reference numeral, and repeated explanations may be omitted.

[0024] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0025] Furthermore, when the same symbol is used for multiple elements, especially when it is necessary to distinguish them, identification symbols such as "_1", "_2", "[n]", and "[m,n]" may be added to the symbol. For example, the second wiring GL is written as wiring GL[2].

[0026] (Embodiment 1) The configuration and operation of a semiconductor device according to one aspect of the present invention will be described.

[0027] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0028] (Example of the configuration of the semiconductor device 100) Figure 1A is a schematic diagram illustrating a semiconductor device 100 according to one aspect of the present invention. The semiconductor device 100 has the function of an accelerator that executes a program (also called a kernel or kernel program) called from a host program. The semiconductor device 100 can perform, for example, parallel processing of matrix operations in graphics processing, parallel processing of multiply-accumulate operations in neural networks, and parallel processing of floating-point operations in scientific and technical calculations.

[0029] The semiconductor device 100 has an element layer 10 and an element layer 40 stacked on the element layer 10. In the schematic diagram shown in Figure 1A, the element layers 10 and 40 are shown spaced apart to make the arrangement of each element constituting the semiconductor device 100 easier to understand. An element layer is a layer on which semiconductor elements such as transistors or capacitors are provided.

[0030] The element layer 10 includes a functional circuit section 11 in which multiple global sense amplifier sections 20 and multiply-accumulate operation circuit sections 30 are arranged in close proximity, as well as a data sense amplifier section 12, a global sense amplifier drive circuit 13, a column line side drive circuit 14, and a word line side drive circuit 15. The global sense amplifier section 20 may be referred to as the first sense amplifier section. The data sense amplifier section 12 may be referred to as the second sense amplifier section. The multiply-accumulate operation circuit section 30 may be referred to as the operation circuit section.

[0031] The schematic diagram shown in Figure 1A defines the Z-axis direction as perpendicular or approximately perpendicular to the surface of the element layer 10 (for example, the surface on which the interlayer insulating layer is provided) in order to explain the arrangement of each component. For ease of understanding, the Z-axis direction may be referred to as the direction perpendicular to the surface of the element layer 10 in the specification. "Approximately perpendicular" refers to a state in which the components are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0032] In this specification and in the drawings, the X, Y, and Z directions may be defined to explain the arrangement of each element. For example, in the schematic diagram shown in Figure 1A, the X, Y, and Z directions are defined to explain the arrangement of each element constituting the semiconductor device 100. The X, Y, and Z directions are perpendicular or approximately perpendicular to each other.

[0033] The device layer 10 has a transistor (Si transistor) made of silicon in a semiconductor layer having a channel formation region. The device layer 10 is a device layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or a device layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.

[0034] Although the substrate provided in the element layer 10 is described as a silicon substrate, this embodiment is not limited to this. A silicon substrate refers to a substrate that uses silicon as a semiconductor material, such as a single-crystal silicon substrate. Not limited to silicon, materials containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc., may also be used as the substrate.

[0035] The Si transistor in the element layer 10 is made of highly crystalline silicon, such as single-crystal silicon or polycrystalline silicon. By having highly crystalline silicon, the element layer 10 can achieve high field-effect mobility, enabling faster operation. Therefore, the element layer 10 can integrate a global sense amplifier section 20, a multiply-accumulate circuit section 30, a data sense amplifier section 12, a global sense amplifier drive circuit 13, a column line side drive circuit 14, and a word line side drive circuit 15.

[0036] The element layer 40 has a memory cell 41 and a data retention circuit 42.

[0037] The memory cell 41 has the function of holding data amplified by the global sense amplifier unit 20. The data stored (held) by the memory cell 41 is, for example, data corresponding to weight parameters used in the sum-of-accumulate operation of a neural network (weight data). By making the weight data digital, a semiconductor device that is resistant to noise and capable of high-speed calculations can be made. Alternatively, the weight data may be analog data.

[0038] The weight data may be configured to perform calculations using 1-bit data (i.e., data of '1' or '0'), or it may be configured to perform calculations using multi-bit data. In the case of multi-bit data (for example, n bits), the weight data can be supplied using a number of wires corresponding to the number of bits.

[0039] The data holding circuit 42 has the function of holding the data of the memory cell 41 that is amplified by the global sense amplifier unit 20. In other words, the data held in the data holding circuit 42 corresponds to the weight data held in the memory cell 41. The data holding circuit 42 can hold the data amplified by the global sense amplifier unit 20 in accordance with the data holding signal MS output by the word line side drive circuit 15. The data held in the data holding circuit 42 is used sequentially in calculation processing by the multiply-accumulate operation circuit unit 30 in accordance with the control of the multiply-accumulate operation circuit unit 30.

[0040] The element layer 40 has an oxide semiconductor transistor (OS transistor) in a semiconductor layer having a channel formation region. The element layer 40 having the OS transistor can be stacked on the element layer 10. By providing the element layer 40 on the element layer 10, the transistor density per unit area can be increased.

[0041] Examples of metal oxides applicable to OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). In addition, In-Zn oxide can be used as the metal oxide applied to the OS transistor. Furthermore, it is preferable that the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0042] Figure 1B is a block diagram illustrating the global sense amplifier section 20 and the sum-of-accumulate circuit section 30 of the semiconductor device 100.

[0043] In the functional circuit section 11, the global sense amplifier section 20 and the multiply-accumulate operation circuit section 30 are arranged in a row in the column direction (Y direction in the figure). The global sense amplifier section 20 has multiple global sense amplifiers GSA. The multiply-accumulate operation circuit section 30 has multiple multiply-accumulate operation circuits MAC. The global sense amplifier GSA may be referred to as the first sense amplifier. The multiply-accumulate operation circuit MAC may be referred to as the operation circuit.

[0044] The data sense amplifier section 12 has a plurality of data sense amplifiers DSA. The data sense amplifiers DSA process the input write data W. ＤＡＴＡThe data sense amplifier DSA amplifies the potential difference between the data bit line DBL (DBL_1 and DBL_2 are shown as examples in the figure) and the inverted data bit line DBLB (not shown) accordingly. The data sense amplifier DSA amplifies the potential difference between the data bit line DBL (DBL_1 and DBL_2 are shown as examples in the figure) and the inverted data bit line DBLB (not shown) and reads the data R ＤＡＴＡ It outputs as such. The data sense amplifier (DSA) is sometimes called the second sense amplifier.

[0045] Note that the data bit line DBL and the inverted data bit line DBLB are sometimes referred to as data bit line pair DBL-DBLB. As shown in Figure 1B, the data bit line DBL is sometimes illustrated, and the inverted data bit line DBLB is sometimes omitted. The data bit line DBL is sometimes referred to as the second bit line.

[0046] The data bit line pair DBL-DBLB is a wiring configuration for bidirectional data input and output between the data sense amplifier DSA and the global sense amplifier GSA. It also serves to input data from the data sense amplifier DSA to the multiply-accumulate circuit MAC, and output the resulting multiply-accumulate data back to the data sense amplifier DSA. If the data input and output via the data bit line pair DBL-DBLB consists of multiple bits, multiple wires will be required.

[0047] The column line drive circuit 14 supplies a column selection signal CSE to the global sense amplifier GSA and the multiply-accumulate operation circuit MAC via the column line CSEL. The column selection signal CSE is a signal that, for example, causes a transistor that functions as a switch to be conductive (selected) at an H level and non-conductive at an L level. The column line CSEL is connected to the column line drive circuit 14. The column line CSEL is also alternately connected to the global sense amplifier GSA of the global sense amplifier section 20 and the multiply-accumulate operation circuit MAC of the multiply-accumulate operation circuit section 30 in the direction in which the column line CSEL extends (Y direction).

[0048] The global sense amplifier drive circuit 13 outputs a sense amplifier control signal SAEN for driving the global sense amplifier GSA. The global sense amplifier drive circuit 13 is sometimes referred to simply as the sense amplifier drive circuit.

[0049] The word line drive circuit 15 outputs a word line selection signal WS for driving the word line connected to the memory cell 41. The word line drive circuit 15 also outputs a data holding signal MS for controlling the writing of data held in the data holding circuit 42.

[0050] The global sense amplifier GSA is positioned in close proximity to the memory cell 41, the data retention circuit 42, and the multiply-accumulate circuit MAC. The global sense amplifier GSA is connected to the memory cell 41 via the bit line BL and the inverting bit line BLB, which are provided in the Z direction. The global sense amplifier GSA is connected to the data retention circuit 42 via the bit line BL. The data retention circuit 42 is connected to the multiply-accumulate circuit MAC via the wiring BML, which is provided in the Z direction. The global sense amplifier GSA is controlled by the sense amplifier control signal SAEN and the column selection signal CSE.

[0051] The global sense amplifier GSA inputs and outputs data bidirectionally between the global sense amplifier GSA of the selected column and the data sense amplifier DSA, in response to the column selection signal CSE. Specifically, in response to the column selection signal CSE, the global sense amplifier GSA outputs the data held in the memory cell 41 to the data sense amplifier DSA. Also, in response to the column selection signal CSE, the data sense amplifier DSA outputs the written data W ＤＡＴＡ The signal is output to the global sense amplifier GSA.

[0052] The global sense amplifier GSA also has the function of amplifying the data held in the memory cell 41. The data held in the memory cell 41, amplified by the global sense amplifier GSA, can be held in the data holding circuit 42 by control using the data holding signal MS. By having the data holding circuit 42 hold the data, the global sense amplifier GSA can read out other data from the memory cell 41 and amplify the potential of the bit line BL according to that data. Therefore, the holding of the next data in the data holding circuit 42 only requires the operation of acquiring the amplified bit line BL potential by control using the data holding signal MS, thus enabling faster operation.

[0053] Furthermore, by having the data holding circuit 42 hold the data, when the global sense amplifier GSA reads other data from the memory cell 41, the other data can be held in a data holding circuit other than the data holding circuit 42 connected to the bit line BL (for example, a data holding circuit 42B connected to the inverting bit line BLB (see Figure 3A)), thereby increasing the number of parallel data supplied to the multiply-accumulate operation circuit MAC.

[0054] Note that the bit line BL and the inverted bit line BLB are sometimes referred to as bit line pair BL-BLB. Sometimes the bit line BL is illustrated, while the inverted bit line BLB is omitted. The global sense amplifier GSA is sometimes referred to as the first sense amplifier. The bit line BL is sometimes referred to as the first bit line.

[0055] The multiply-accumulate circuit MAC is a circuit that performs a multiply-accumulate operation on input data received via the data bit line DBL and weight data held in the data holding circuit 42. The multiply-accumulate circuit MAC is connected to the data holding circuit 42 via wiring BML provided in the Z direction (direction perpendicular to the substrate surface and parallel to the surface).

[0056] Furthermore, the multiply-accumulate circuit MAC can be controlled by the column selection signal CSE. The column selection signal CSE supplied to the multiply-accumulate circuit MAC functions as a selection signal that selectively supplies data held in the data holding circuit 42 to the multiply-accumulate circuit MAC. Specifically, the column selection signal CSE outputs data from the data holding circuit 42 connected to the corresponding global sense amplifier GSA to the multiply-accumulate circuit MAC. The column selection signal CSE supplied to the multiply-accumulate circuit MAC is also a control signal for performing multiply-accumulate operations. For example, it can function as a clock signal for performing multiply-accumulate operations, a control signal for performing quantization operations, an output control signal for multiply-accumulate data obtained by multiply-accumulate operations, and a reset signal for the register holding the multiply-accumulate data.

[0057] A semiconductor device according to one aspect of the present invention has a configuration in which a large number of global sense amplifiers GSA and multiply-accumulate circuits MAC are arranged directly below a memory cell 41 and a data holding circuit 42, and the column selection signal CSE of the global sense amplifier GSA is used as the control signal for the multiply-accumulate circuit MAC. As a result, the memory cell 41, the global sense amplifier GSA, and the multiply-accumulate circuit MAC can be arranged in close proximity. This enables near-memory computing and reduces the power consumption required for data transmission between the memory circuit and the arithmetic circuit.

[0058] Furthermore, in one aspect of the present invention, the semiconductor device can output a signal for controlling the multiply-accumulate circuit MAC from the column line-side drive circuit 14 for controlling the global sense amplifier GSA, thus reducing the drive circuit required to drive the multiply-accumulate circuit MAC. In addition, the wiring for supplying control signals to the multiply-accumulate circuit MAC can be shared with the column line CSEL that transmits the column selection signal, thus reducing the wiring for transmitting control signals to drive the multiply-accumulate circuit MAC. As a result, the semiconductor device in one aspect of the present invention can be miniaturized by suppressing an increase in circuit area, reduce power consumption, and improve the processing speed of calculations.

[0059] Furthermore, in one aspect of the present invention, the semiconductor device can store the data from the memory cell 41 read by the global sense amplifier GSA in the data holding circuit 42. Therefore, there is no need to select the global sense amplifier GSA to read the data from the memory cell 41 again, and the repeated data reading operation can be shortened. Also, by configuring the data holding circuit 42 to store the data from the memory cell 41 that has been read, the global sense amplifier GSA can read other data from the memory cell 41 and perform an amplification operation. Since this other data can be stored in a data holding circuit 42 separate from the data holding circuit 42 connected to the bit line BL, the number of parallel data supplied to the multiply-accumulate operation circuit MAC can be increased.

[0060] Figure 2A is a schematic diagram illustrating an example configuration of a memory cell 41, a data retention circuit 42, a multiply-accumulate circuit MAC, and a global sense amplifier GSA. In Figure 2A, an element layer 40 having the memory cell 41 and the data retention circuit 42 is provided above the region where the multiply-accumulate circuit MAC, global sense amplifier GSA (GSA_1 to GSA_28), column lines CSEL_1 to CSEL_31, and data bit line pairs DBL_1, DBLB_1, DBL_2, and DBLB_2, as described in Figure 1B, are provided. For improved visibility, Figure 2A shows only some of the memory cells 41 and data retention circuits 42 located on the global sense amplifiers GSA_1 to GSA_28 and the multiply-accumulate circuit MAC. The memory cell 41 is connected to the global sense amplifier GSA via the bit line pair BL-BLB. The data retention circuit 42 is connected to the global sense amplifier GSA via the bit line BL. The data holding circuit 42 is connected to the multiply-accumulate circuit MAC via wiring BML.

[0061] Figure 2A shows an example configuration for performing sum-of-products operations on 8-bit input data (A) and 8-bit weight data (W), as well as on bias data. The weight data W is assumed to undergo 3x3, or 27, types of filtering. The bias data is configured to add one type of bias value. In this case, since the weight data and bias data are output from eight pairs of bit lines, 27 + 1 = 28 global sense amplifiers (GSAs) are required to output the data necessary for filtering and bias data addition. Figure 2A illustrates global sense amplifiers GSA_1 to GSA_28. Global sense amplifier GSA_1 corresponds to eight bit lines (for example, bit lines BL[0] to BL[7] shown in Figure 2B) in the case of 8-bit weight data. Since the bit line BL consists of 8 bit lines and 8 bits of weight data, 28 x 8 = 224 bit line pairs BL-BLB are provided for global sense amplifiers GSA_1 to GSA_28.

[0062] Furthermore, the data bit line pair DBL-DBLB that transmits the 8-bit input data (A) also consists of eight data bit lines DBL[0] through DBL[7].

[0063] One aspect of the present invention is not limited to the number of bits, filters, or wires exemplified above. Furthermore, while a configuration for performing sum-of-accumulate operations will be described, other configurations for performing other operations are also possible.

[0064] Of the column lines CSEL_1 to CSEL_31 shown in Figure 2A, column lines CSEL_1 to CSEL_28 transmit column selection signals CSE_1 to CSE_28 to global sense amplifiers GSA_1 to GSA_28. The column selection signals CSE_1 to CSE_28 enable bidirectional data input and output between the global sense amplifiers GSA_1 to GSA_28 of the selected column and the data sense amplifier DSA_1 (not shown).

[0065] The column lines CSEL_1 to CSEL_31 shown in Figure 2A transmit column selection signals CSE_1 to CSE_31 to the multiply-accumulate circuit MAC. The column selection signals CSE_1 to CSE_28 supplied to the column lines CSEL_1 to CSEL_28 allow the selection of data (weight data W) to be supplied to the multiplication circuit (not shown) of the multiply-accumulate circuit MAC from the global sense amplifiers GSA_1 to GSA_28 of the selected column. The column selection signals CSE_29 to CSE_31 supplied to the column lines CSEL_29 to CSEL_31 are used as control signals for the multiply-accumulate circuit MAC.

[0066] Although not shown in Figure 2A, a number of global sense amplifiers GSAs corresponding to the column lines CSEL can be provided. For example, in the configuration of Figure 2A, global sense amplifiers GSA_29 to GSA_31 can be provided corresponding to column lines CSEL_29 to CSEL_31. Unlike global sense amplifiers GSA_1 to GSA_28, global sense amplifiers GSA_29 to GSA_31 do not supply data to the multiply-accumulate circuit MAC, but are global sense amplifiers that input and output data bidirectionally to and from the data bit line DBL.

[0067] Figure 2B illustrates a selector 50 in the MAC multiply-accumulate circuit for outputting weight data held by a data holding circuit 42, which is selected by column selection signals CSE_1 to CSE_28. The global sense amplifiers GSA_1 to GSA_28 shown in Figure 2B output the aforementioned 8-bit data to the data holding circuit 42 provided for each bit line BL. For example, global sense amplifier GSA_1 corresponds to the eight bit lines BL[0] to BL[7]. A data holding circuit 42 is connected to each of the eight bit lines BL[0] to BL[7]. The column selection signals CSE_1 to CSE_28 switch the selector 50 to select the data holding circuit corresponding to one of the global sense amplifiers GSA_1 to GSA_28, thereby outputting the desired 8-bit weight data W.

[0068] The data holding circuit 42, as an example, includes a transistor 43 and a capacitive element 44, as shown in Figure 2B. Transistor 43 is a transistor that functions as a switch. Transistor 43 can be controlled to be on or off depending on the signal applied to its gate. For example, the on or off state can be controlled by applying the data holding signal MS described above to the gate of transistor 43. By turning transistor 43 on, the potential of the bit line BL amplified by the global sense amplifier GSA can be supplied to the wiring BML connected to the capacitive element 44. Also, by turning transistor 43 off, the charge stored in the capacitive element 44 can be retained.

[0069] The data holding circuit 42 can be configured to sequentially hold other data read from the memory cell 41 when amplified by the global sense amplifier GSA, by increasing the number of transistors 43 and capacitive elements 44 connected to the bit line BL.

[0070] Since the transistor 43 in the data holding circuit 42 is a transistor provided in the element layer 40, an OS transistor can be applied. OS transistors have an extremely low off-current. Therefore, by turning the transistor 43 off, the charge that was charged in the capacitive element 44 when it was turned on can be retained. As a result, the wiring BML can retain a charge corresponding to the potential of the bit line BL.

[0071] The multiply-accumulate circuit MAC includes, for example, a selector controlled by the column selection signal CSE, as well as a multiplication circuit, an adder circuit, a register, a quantization circuit, an output circuit, and so on. Control signals for circuits such as the multiplication circuit, adder circuit, register, quantization circuit, and output circuit require a clock signal, a reset signal, an input control signal, an output control signal, and so on. In one embodiment of the present invention, the clock signal can be used by utilizing the logical OR of the column selection signals CSE_1 to CSE_28. Control signals such as the reset signal, input control signal, and output control signal can be the column selection signals CSE_29 to CSE_31 supplied via the column lines CSEL_29 to CSEL_31.

[0072] In one aspect of the present invention, the column line CSEL that transmits the column selection signal CSE can be shared between the multiply-accumulate circuit MAC and the global sense amplifier GSA. Therefore, the wiring that transmits the control signal for driving the multiply-accumulate circuit MAC can be reduced. As a result, miniaturization, reduced power consumption, and improved processing speed can be achieved by suppressing an increase in circuit area.

[0073] Figure 2C is a schematic diagram illustrating the stacking of the element layers 10 and 40 shown in Figure 1A, illustrating the transistor 51 provided on element layer 10 and the transistor 53 provided on element layer 40. Figure 2C also illustrates the bit line pair BL-BLB connecting the memory cell 41 shown in Figure 2A to the global sense amplifier GSA and the data holding circuit 42, and the wiring BML connecting the data holding circuit 42 shown in Figure 2A to the multiply-accumulate circuit MAC.

[0074] By making the semiconductor layer 52 of the transistor 51 an oxide semiconductor (metal oxide), it can be made into a memory cell 41 composed of the OS transistor described above.

[0075] By making the semiconductor layer 54 of the transistor 53 out of silicon, a multiply-accumulate circuit MAC and a global sense amplifier GSA can be provided on the element layer 10 composed of the Si transistors described above.

[0076] By placing the memory cell 41 on the same layer as the multiply-accumulate circuit MAC and global sense amplifier GSA, the memory capacity required for arithmetic processing in the semiconductor device functioning as an accelerator, i.e., the number of memory circuits, can be increased compared to the case where the memory cell 41, the multiply-accumulate circuit MAC, and the global sense amplifier GSA are arranged on the same layer. This increased memory capacity reduces the number of data transfers required for arithmetic processing from the external memory device to the semiconductor device, thereby lowering power consumption.

[0077] When memory circuits such as memory cells 41 and arithmetic circuits such as multiply-accumulate circuits MAC are on separate chips, the bus width is limited according to the number of pins on the chip. On the other hand, in a configuration in which memory cells 41 and multiply-accumulate circuits MAC are stacked, as in one embodiment of the present invention, the number of parallel data required for arithmetic processing can be increased according to the number of apertures that provide bit line pairs BL-BLB, making it possible to perform efficient arithmetic processing.

[0078] In the configurations shown in Figures 2A and 2B, the data holding circuit 42 is shown connected to the bit line BL, but it is also possible to connect it to the inverting bit line BLB.

[0079] Figure 3A shows a configuration in which the data holding circuit 42B is connected to the inverting bit line BLB in the schematic diagram shown in Figure 2A. In Figure 3A, the wiring between the data holding circuit 42B connected to the inverting bit line BLB and the multiply-accumulate operation circuit MAC is shown as wiring BMLB. The data holding circuit 42B holds the inverted signal of the data held by the data holding circuit 42. Note that wiring BML and wiring BMLB are sometimes referred to as wiring pair BML-BMLB.

[0080] Figure 3B shows selectors 50 and 50B provided in the multiply-accumulate circuit MAC shown in Figure 3A. Selectors 50 and 50B are selected by column selection signals CSE_1 to CSE_28. For example, the global sense amplifier GSA_1 shown in Figure 3B can output the above-mentioned 8-bit data to the data holding circuit 42 provided for each bit line BL[0] to BL[7], and can also output the above-mentioned 8-bit inverted data to the data holding circuit 42B provided for each inverted bit line BLB[0] to BLB[7].

[0081] In the data holding circuit 42B, other data read from the memory cell 41 is amplified by the global sense amplifier GSA, allowing it to be held in a separate data holding circuit 42B from the data holding circuit 42 connected to the bit line BL. Therefore, the number of parallel data supplied to the multiply-accumulate circuit MAC can be increased without increasing the number of data holding circuits 42 connected to the bit line BL. The data held in the data holding circuit 42 and the data holding circuit 42B can be output as 16-bit weight data W via wiring BML[0] to BML[7] and BMLB[0] to BMLB[7] by selecting selectors 50 and 50B with the column selection signal CSE_1.

[0082] The data retention circuit 42B, like the data retention circuit 42, has a transistor 43 and a capacitive element 44. Therefore, by turning off the transistor 43, the charge that was charged to the capacitive element 44 when the global sense amplifier GSA was activated when it was turned on can be retained. As a result, the wiring BMLB can retain a potential corresponding to the data of the memory cell 41 that was read out by activating the global sense amplifier GSA.

[0083] The semiconductor device 100A shown in Figure 4A is a modified example of the semiconductor device 100 shown in Figure 2A. The schematic diagram in Figure 4A illustrates a case where the element layer 40 of Figure 2A is stacked as multiple element layers 40_1, 40_2.

[0084] The semiconductor device 100A shown in Figure 4A has an element layer 40_1 on which multiple memory cells 41 and data retention circuits 42 are arranged, and an element layer 40_2 on which multiple memory cells 41 are arranged. With this configuration, the number of memory cells 41 per unit area can be increased in the multiple element layers 40_1 and 40_2. As a result, a semiconductor device with higher memory density can be made. Furthermore, the manufacturing process using the same photomask as for element layer 40_2 can be employed for the layers above element layer 40_2. As a result, memory cells 41 can be repeatedly manufactured using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs.

[0085] Figure 4B shows a schematic diagram in which element layers 40_1 to 40_n (where n is an integer of 2 or more), including the element layers 40_1 and 40_2 shown in Figure 4A, are provided. Also in Figure 4B, the bit line pair BL-BLB connecting the memory cell 41 shown in Figure 4A, the data retention circuit 42 and the global sense amplifier GSA, and the wiring BML connecting the data retention circuit 42 and the multiply-accumulate circuit MAC are shown. As shown in Figure 4B, in the semiconductor device 100A, a plurality of element layers 40_1 to 40_n are stacked vertically or approximately vertically on the surface of the element layer 10. This configuration allows for an increase in the number of memory cells 41 arranged per unit area. Therefore, the storage density can be increased.

[0086] The configuration shown in Figure 4B increases the number of memory cells 41 connected to the bit line pair BL-BLB, and shortens the bit line pair BL-BLB connecting the memory cells 41 to the multiply-accumulate circuit MAC and the global sense amplifier GSA. By shortening the wiring distance through the stacking of element layers 40, parasitic capacitance occurring in the bit line pair BL-BLB can be reduced, thus enabling lower power consumption. Furthermore, weight data can be read at high speed from the memory cells 41 to the global sense amplifier GSA and from the data holding circuit 42 to the multiply-accumulate circuit MAC, and the number of bits in the weight data can be increased.

[0087] The semiconductor device 100B shown in Figure 5A is a modified example of the semiconductor device 100A shown in Figure 4A. The schematic diagram in Figure 5A illustrates the case where multiple switches 45 are provided on the bit line pair BL-BLB in the element layers 40_1 and 40_2 of Figure 4A.

[0088] The multiple switches 45 provided on the bit line pair BL-BLB shown in Figure 5A can be selectively turned on or off. This configuration allows for the selection of an element layer 40 (for example, element layer 40_1 or 40_2) having a memory cell 41 for writing or reading data, and connecting it to the global sense amplifier GSA. When the element layers 40 are stacked, parasitic capacitance increases in the bit line pair BL-BLB. By using switches 45 provided on each layer to disconnect the memory cell 41, the parasitic capacitance occurring in the bit line pair BL-BLB can be reduced, thus enabling lower power consumption. Furthermore, weight data can be read from the memory cell 41 to the global sense amplifier GSA at high speed.

[0089] Figure 5B is a schematic diagram illustrating the operation of a semiconductor device 100B having the switch 45 shown in Figure 5A. Figure 5B shows circuit blocks 46_1, 46_2, and circuit blocks 46B_1, 46B_2, which have a bit line pair BL-BLB connected to a global sense amplifier GSA and memory cells 41 connected via the switch 45. Circuit blocks 46_1, 46_2 are shown as circuit blocks connected to the bit line BL, and circuit blocks 46B_1, 46B_2 are shown as circuit blocks connected to the inverting bit line BLB.

[0090] By turning on the switches 45 in circuit blocks 46_1 and 46B_1, and turning off the switches 45 in circuit blocks 46_2 and 46B_2, the bit line BL and inverting bit line BLB can be divided into wiring connected to the global sense amplifier GSA and other wiring. Since the bit line BL and inverting bit line BLB connected to the global sense amplifier GSA can be shortened, the number of memory cells 41 connected to the bit line BL and inverting bit line BLB can be reduced. The switches 45 provided in each layer can be configured to disconnect memory cells 41 that do not perform data writing or reading, thereby reducing the parasitic capacitance that occurs in the bit line pair BL-BLB. As a result, it is possible to reduce the power consumption required for charging and discharging the bit line pair BL-BLB. Furthermore, weight data can be read from the memory cells 41 to the global sense amplifier GSA at high speed.

[0091] (Example of Memory Cell Configuration 41) The following describes a circuit configuration of a memory cell that can be applied to memory cell 41. Note that memory cell 41 is a memory cell having an OS transistor. A memory having a memory cell with an OS transistor is sometimes called an "OS memory".

[0092] The OS transistor has an extremely low off-current. Therefore, it can retain the charge corresponding to the data written to the memory cell 41 for a long time. In other words, the memory cell 41 can retain data once it has been written for a long time. As a result, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device 100 according to one embodiment of the present invention can be reduced.

[0093] Figure 6A illustrates a memory cell array (MCA) having multiple memory cells 41. Figure 6A shows word lines WL_1 to WL_m and bit lines BL_1 to BL_n arranged in an m x n matrix (m and n are natural numbers greater than or equal to 2). It also shows the memory cells 41 connected to each word line WL and bit line BL.

[0094] Figure 6B is a circuit diagram illustrating an example of a circuit configuration applicable to the memory cell 41. The memory cell 41 has a transistor M1 and a capacitor C1 (also called a capacitive element). Transistor M1 is connected to the word line WL, the bit line BL, and the capacitor C1. Capacitor C1 is also connected to wiring PL, which functions as a capacitive line. For example, the voltage GND (low-level power supply potential) is input to wiring PL. Figure 6C is a circuit block corresponding to the circuit diagram in Figure 6B.

[0095] The memory cell 41 shown in Figure 6B can be a memory cell of a 1T1C type DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM refers to a RAM having a 1T (transistor) 1C (capacitance) type memory cell. DOSRAM is a DRAM formed using OS transistors, and it is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that takes advantage of the low off-current of OS transistors. Because DOSRAM is a 1T1C type memory cell, it can achieve a large storage capacity in a memory cell array (MCA). In addition, by using OS transistors, the data retention period can be extended compared to DRAM with Si transistors.

[0096] The circuit configurations applicable to the memory cell 41 are not limited to the 1T1C type DOSRAM shown in Figure 6B. For example, Figure 7A shows another example of a 1T1C type memory cell configuration applicable to DOSRAM. The memory cell 41A shown in Figure 7A differs from the memory cell 41 shown in Figure 6B in that the transistor M1 is an OS transistor with a back gate, and the back gate is connected to the wiring BGL. By having a configuration with wiring BGL, the transistor M1 can be a transistor with improved electrical characteristics.

[0097] The memory cell 41 having an OS transistor can be a NOSRAM (Nonvolatil Oxide Semiconductor Random Access Memory). In NOSRAM, the memory cell is a 2-transistor type (2T) or 3-transistor type (3T) gain cell. Since NOSRAM rewrites data by charging and discharging a capacitor, in principle there is no limit to the number of rewrites and it is low energy. Therefore, NOSRAM is a memory that can operate at high speed, consumes little power, and has high rewrite endurance. In addition, because NOSRAM can read written data non-destructively, it is suitable for long-term data retention.

[0098] The memory cell 41B shown in Figure 7B is a circuit corresponding to a 2T1C type NOSRAM. The memory cell 41B has transistors M1 and M2 and a capacitor C1, with transistors M1 and M2 being the write transistor and read transistor, respectively. Transistors M1 and M2 may be OS transistors with semiconductor layers arranged on different layers, or OS transistors with semiconductor layers arranged on the same layer. An example is shown in which the memory cell 41B is connected to the write bit line WBL, the read bit line RBL, the write word line WWL, the read word line RWL, and the source line SL.

[0099] The memory cell 41C shown in Figure 7C is a circuit corresponding to a 3T1C type NOSRAM. The memory cell 41C has transistors M1, M2, M3 and capacitor C1. Transistors M1, M2, and M3 are the write transistor, read transistor, and select transistor, respectively. Transistors M1, M2, and M3 may be OS transistors with semiconductor layers arranged on different layers, or they may be OS transistors with semiconductor layers arranged on the same layer.

[0100] Because the writing transistor is composed of OS transistors, the charge corresponding to the data can be retained by turning off the writing transistor. Therefore, memory cells 41B and 41C do not consume power to retain data. Consequently, memory cells 41B and 41C can function as low-power memory cells capable of retaining data for a long period of time. The gate of the reading transistor functions as a node that holds a charge corresponding to the data. The reading transistor is a transistor that has the function of flowing a current corresponding to the potential of the node that holds a charge corresponding to the data. The selection transistor is a transistor that controls the current flowing through the reading transistor.

[0101] Figure 7D shows another example of a 2T1C type gain cell configuration. The memory cell 41D shown in Figure 7D differs from the memory cell 41B shown in Figure 7B in that transistors M1 and M2 are OS transistors with back gates, and these back gates are connected to wiring BGL. For example, a voltage GND is input to wiring BGL. By having a configuration with wiring BGL, transistors M1 and M2 can be made into transistors with improved electrical characteristics.

[0102] Figure 7E shows another example of a 3T1C type gain cell configuration. The memory cell 41E shown in Figure 7E differs from the memory cell 41C shown in Figure 7C in that transistors M1, M2, and M3 are OS transistors with back gates, and these back gates are connected to wiring BGL. For example, a voltage GND is input to wiring BGL. By having a configuration with wiring BGL, transistors M1, M2, and M3 can be transistors with improved electrical characteristics.

[0103] Figure 7F shows another example of a 2T type gain cell configuration. The memory cell 41F shown in Figure 7F differs from the memory cell 41B shown in Figure 7B in that the capacitor C1 is omitted by using the gate capacitance of the read transistor, and the wiring PL is omitted.

[0104] The transistors M1 and M2 in the 2T type gain cell shown in Figure 7F are preferably vertical transistors in which the source electrode and drain electrode are located at different heights. In vertical transistors, current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer. That is, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), vertical channel transistor, vertical channel type transistor, or vertical transistor.

[0105] Compared to horizontal transistors (also called planar transistors) where the source and drain electrodes are at the same height, vertical transistors have a configuration where at least part of the source region, channel formation region, and drain region can overlap when viewed from above, thus reducing the occupied area (also called the footprint). Furthermore, because the structure allows for a smaller channel length and a larger channel width, the on-resistance can be reduced (and the on-current increased).

[0106] Figure 7G shows another example of a 3T type gain cell configuration. The memory cell 41G shown in Figure 7G differs from the memory cell 41C shown in Figure 7C in that the capacitor C1 is omitted by using the gate capacitance of the read transistor, and the wiring PL is omitted. The transistors M1, M2, and M3 in the 3T type gain cell shown in Figure 7G are vertical transistors with the source electrode and drain electrode at different heights, which reduces the occupied area (also called the footprint) and reduces the on-resistance (increases the on-current).

[0107] (Example of Global Sense Amplifier GSA Configuration) An example of the circuit configuration of the global sense amplifier GSA will be described. Figure 8A is a circuit diagram of the global sense amplifier GSA. Figure 8B shows the circuit block corresponding to the said circuit diagram. Figure 8C illustrates an example configuration combining the circuit block of the memory cell 41 shown in Figure 6C and the circuit block of the global sense amplifier GSA shown in Figure 8B.

[0108] The global sense amplifier GSA shown in Figure 8A includes a sense amplifier 61, a precharge circuit 62, a precharge circuit 63, and a switch circuit 64. Each of the sense amplifier 61, precharge circuit 62, precharge circuit 63, and switch circuit 64 is connected to the bit line pair BL-BLB.

[0109] The sense amplifier 61 has the function of outputting a potential corresponding to one of the binary data values ​​to the bit line BL and a potential corresponding to the other of the binary data values ​​to the inverting bit line BLB by applying a predetermined potential to each of the wiring SAP and wiring SAN. The sense amplifier 61 comprises transistors 61_1, 61_2, 61_3, and 61_4. Transistors 61_1 and 61_2 are p-channel transistors. Transistors 61_3 and 61_4 are n-channel transistors. Transistors 61_1 and 61_3 form an inverter circuit with the inverting bit line BLB as input, the bit line BL as output, wiring SAP as a high-potential power line, and wiring SAN as a low-potential power line. Transistors 61_2 and 61_4 form an inverter circuit with the bit line BL as input, the inverting bit line BLB as output, wiring SAP as a high-potential power line, and wiring SAN as a low-potential power line.

[0110] The precharge circuit 62 has the function of pre-charging the bit line pair BL-BLB to potential VPRE in accordance with the signal EQB. Specifically, the precharge circuit 62 has transistors 62_1, 62_2, and 62_3. Each of transistors 62_1, 62_2, and 62_3 is a p-channel type transistor. Transistor 62_1 has the function of making the bit line pair BL-BLB conduct or non-conductive in accordance with the signal EQB. Transistor 62_2 has the function of pre-charging the bit line BL to potential VPRE in accordance with the signal EQB. Transistor 62_3 has the function of pre-charging the inverting bit line BLB to potential VPRE in accordance with the signal EQB.

[0111] The precharge circuit 63 has the function of pre-charging the bit line pair BL-BLB to potential VPRE according to the signal EQ. Specifically, the precharge circuit 63 has transistors 63_1, 63_2, and 63_3. Each of transistors 63_1, 63_2, and 63_3 is an n-channel type transistor. Transistor 63_1 has the function of making the bit line pair BL-BLB conduct or non-conductive according to the signal EQ. Transistor 63_2 has the function of pre-charging the bit line BL to potential VPRE according to the signal EQ. Transistor 63_3 has the function of pre-charging the inverting bit line BLB to potential VPRE according to the signal EQ.

[0112] The switch circuit 64 has the function of making the bit line pair BL-BLB and the data bit line pair DBL-DBLB conduct or non-conductive in response to the column selection signal CSE. Specifically, the switch circuit 64 comprises transistors 64_1 and 64_2. Transistors 64_1 and 64_2 are each n-channel type transistors. Transistor 64_1 has the function of making the bit line BL and the data bit line DBL conduct or non-conductive in response to the column selection signal CSE. Transistor 64_2 has the function of making the data bit line DBL and the inverted data bit line DBLB conduct or non-conductive in response to the column selection signal CSE.

[0113] Figure 8B shows the circuit block corresponding to the circuit diagram of the global sense amplifier GSA described in Figure 8A. Figure 8C also illustrates an example configuration combining the circuit block of the global sense amplifier GSA shown in Figure 8B and the circuit block of the memory cell 41 shown in Figure 6C.

[0114] In the configuration of the global sense amplifier GSA shown in Figures 8A to 8C, the potential difference between the bit line BL and the inverting bit line BLB, which fluctuates according to the charge held in the memory cell 41 during the data reading operation from the memory cell 41, is amplified and output to the data bit line pair DBL-DBLB in accordance with the column selection signal CSE. Furthermore, in the configuration of the global sense amplifier GSA shown in Figures 8A to 8C, the potential difference between the data bit line pair DBL-DBLB is supplied to the bit line pair BL-BLB in accordance with the column selection signal CSE, and the amplified potential difference can be used to write data to the memory cell 41 connected to the bit line pair BL-BLB.

[0115] (Example of Data Sense Amplifier DSA Configuration) An example of the circuit configuration of the data sense amplifier DSA will be described. Figure 9A is a circuit diagram of the data sense amplifier DSA. Figure 9B shows the circuit block corresponding to the said circuit diagram. Figure 9C illustrates an example configuration in which the circuit block of the memory cell 41 shown in Figure 6C and the circuit block of the global sense amplifier GSA shown in Figure 8B are combined with the circuit block of the data sense amplifier DSA shown in Figure 9B.

[0116] The data sense amplifier DSA shown in Figure 9A includes a precharge circuit 65, a sense amplifier 66, a switch circuit 67, a transistor 68, an AND gate 69, and a latch circuit 70. The precharge circuit 65, the sense amplifier 66, and the switch circuit 67 are each connected to the data bit line pair DBL-DBLB.

[0117] The precharge circuit 65 has the function of precharging the data bit line pair DBL-DBLB to the potential of wiring DSAP in accordance with the signal DEQ_ENB. Wiring DSAP is a high-potential power line. Specifically, the precharge circuit 65 has transistors 65_1, 65_2, and 65_3. Each of transistors 65_1, 65_2, and 65_3 is a p-channel type transistor. Transistor 65_1 has the function of making the connection between the data bit line DBL and the inverted data bit line DBLB conductive or non-conductive in accordance with the signal DEQ_ENB. Transistor 65_2 has the function of precharging the data bit line DBL to the potential of wiring DSAP in accordance with the signal DEQ_ENB. Transistor 65_3 has the function of precharging the inverted data bit line DBLB to the potential of wiring DSAP in accordance with the signal DEQ_ENB.

[0118] The sense amplifier 66 has the function of outputting a potential corresponding to one of the binary data values ​​to the data bit line DBL and a potential corresponding to the other of the binary data values ​​to the inverted data bit line DBLB by applying predetermined potentials from the wiring DSAP and DSAN, respectively. The sense amplifier 66 comprises transistors 66_1, 66_2, 66_3, and 66_4. Transistors 66_1 and 66_2 are p-channel transistors, respectively. Transistors 66_3 and 66_4 are n-channel transistors, respectively. Transistors 66_1 and 66_3 take the inverted data bit line DBLB as input and output the data bit line DBL, with wiring DSAP being a high-potential power line and wiring DSAN being a low-potential power line, forming an inverter circuit. Transistors 66_2 and 66_4 form an inverter circuit with data bit line DBL as input, inverted data bit line DBLB as output, wiring SAP as a high-potential power line, and wiring SAN as a low-potential power line.

[0119] The potential supply of the wiring DSAN to the sense amplifier 66 is controlled by the signal DSA_EN supplied to the transistor 68. The signal DSA_EN controls the state of the sense amplifier 66. When the signal DSA_EN causes transistor 68 to conduct, the sense amplifier 66 is activated, and when it causes it to become non-conductive, the sense amplifier 66 is deactivated.

[0120] The switch circuit 67 writes data W to the data bit line pair DBL-DBLB according to the write control signals WE and WEB. ＤＡＴＡ , W ＤＡＴＡ It has the function of controlling the supply of _B. The write control signal WEB is the inverted signal of the write control signal WE. Write data W ＤＡＴＡ _B is the data W to be written ＤＡＴＡis the inverted signal. Specifically, the switch circuit 67 includes transistors 67_1 to 67_4. Transistors 67_1 and 67_3 are n-channel type transistors. Transistors 67_2 and 67_4 are p-channel type transistors. Transistors 67_1 and 67_2 function as analog switches that control the supply of write data W ＤＡＴＡ _B to the inverted data bit line DBLB. Transistors 67_3 and 67_4 function as analog switches that control the supply of write data W ＤＡＴＡ to the data bit line DBL.

[0121] The AND gate 69 has a function of outputting the potential of the data bit line DBL to the latch circuit 70 according to the control of the read control signal RE. Also, the latch circuit 70 takes in the output signal of the AND gate 69 according to the latch signal DLAT and outputs it as read data R ＤＡＴＡ with a function of outputting.

[0122] FIG. 9B shows circuit blocks corresponding to the circuit diagram of the data sense amplifier DSA described in FIG. 9A. Also, FIG. 9C shows a configuration example in which the circuit block of the data sense amplifier DSA shown in FIG. 9B is combined with the circuit blocks of the memory cell 41 and the global sense amplifier GSA shown in FIG. 8C.

[0123] In the configuration of the data sense amplifier DSA shown in FIGS. 9A to 9C, the potential difference of the data bit line pair DBL - DBLB that varies under the control of the column selection signal CSE is amplified, and read data R ＤＡＴＡ can be output according to the read control signal RE and the latch signal DLAT. Also, in the configuration of the data sense amplifier DSA shown in FIGS. 9A to 9C, write data W ＤＡＴＡ , W ＤＡＴＡThe potential difference resulting from the supply of _B is amplified, and the potential of the data bit line pair DBL-DBLB is applied to the bit line pair BL-BLB by controlling the column selection signal CSE. The potential difference amplified by the global sense amplifier GSA can then be written as data to the memory cell 41 connected to the bit line pair BL-BLB.

[0124] (Example of MAC configuration) An example of the MAC circuit configuration will be described. Figure 10A is a circuit diagram of the MAC circuit. Figure 10B shows the circuit block corresponding to the said circuit diagram. Figure 11 is a timing chart to explain an example of MAC operation. Figure 12 illustrates an example configuration combining the circuit block of the memory cell 41 shown in Figure 6C, the circuit block of the global sense amplifier GSA shown in Figure 8B, the circuit block of the data sense amplifier DSA shown in Figure 9B, and the circuit block of the MAC circuit shown in Figure 10B.

[0125] The multiply-accumulate circuit MAC shown in Figure 10A includes, as an example, a selector 50, a multiplier circuit 71, an adder circuit 72, an OR gate 73, a register 74, a quantization circuit 75, an AND gate 76, a register 77, a tristate buffer 78, and a buffer 79. In addition to the multiply-accumulate circuit MAC, Figure 10A also shows global sense amplifiers GSA_1 to GSA_28 connected to the selector 50 described in Figure 2B via a data holding circuit 42.

[0126] The data holding circuit 42 holds the data weight data W (shown as 8-bit data as an example) read out by the global sense amplifiers GSA_1 to GSA_28. The selector 50 switches the weight data W held in the data holding circuit 42 and supplies it to the multiplication circuit 71. In response to the column selection signals CSE_1 to CSE_28, the selector 50 activates one of the global sense amplifiers GSA_1 to GSA_28 connected to the memory cell that holds the corresponding weight data, and supplies the weight data W to the multiplication circuit 71.

[0127] The multiplication circuit 71 is supplied with the weight data W (including bias data) and input data A (illustrated as 8-bit data as an example) via the data bit line DBL. The multiplication circuit 71 outputs multiplied data A × W, which is the result of multiplying the input data A and the weight data W. The multiplied data A × W is, for example, 16-bit data.

[0128] The adder circuit 72 repeatedly adds the multiplication data A × W mentioned above with the data held in register 74. The added data is supplied to the input terminal D of register 74 and held in register 74. The data held in register 74 is supplied to the adder circuit 72 from the output terminal Q. The adder circuit 72 can repeatedly add the multiplication data A × W that is supplied sequentially. Register 74 can hold the weight data and the sum-of-accumulate data of the input data. Register 74 is reset by the column selection signal CSE_31 supplied to the reset terminal RS. The output terminal Q of register 74, that is, the data of node N1, that is, the sum-of-accumulate data, becomes, for example, 20 bits of data through repeated addition.

[0129] The signal for holding the data provided to input terminal D of register 74 in register 74 is provided by OR gate 73. OR gate 73 receives column selection signals CSE_1 to CSE_28 as input. Column selection signals CSE_1 to CSE_28 are selection signals that reach a high level at different timings. Therefore, the output signal of OR gate 73 can be used as a clock signal during the period when weight data W is switched and output.

[0130] The quantization circuit 75 is a circuit that performs processing using an activation function and quantization processing. Processing using an activation function is, for example, processing using a normalized linear function (ReLU). The quantization processing quantizes the sum-of-accumulate data of node N1, for example, converting 20-bit sum-of-accumulate data into 8-bit sum-of-accumulate data. As a result of the quantization processing, 8-bit sum-of-accumulate data is output to node N2.

[0131] The signal for controlling the quantization circuit 75 is provided by the AND gate 76. The AND gate 76 receives data supplied via the data bit line DBL, in addition to the column selection signal CSE_29. The column selection signal CSE_29 is a selection signal that reaches an H level at a different timing than CSE_1 to CSE_28 and CSE_31. Therefore, processing by the activation function and quantization processing can be performed at the timing when the sum-of-products operation data of the weight data and input data is obtained.

[0132] The sum-of-accumulate data of node N2, processed by the activation function and quantized, is supplied to the input terminal D of register 77 and held in register 77. The data held in register 77 is supplied to the tristate buffer 78 from the output terminal Q. Register 77 can hold the sum-of-accumulate data of node N2. Register 77 is reset by the column selection signal CSE_31 supplied to the reset terminal RS. The sum-of-accumulate data of node N3, at the output terminal Q of register 77, is switched at the timing of the column selection signal CSE_29. The timing of the column selection signal CSE_29 supplied to register 77 is delayed because it goes through buffer 79. Therefore, the timing of obtaining the sum-of-accumulate data in the quantization circuit 75 and the timing of holding the sum-of-accumulate data of node N2 in register 77 can be made different.

[0133] The tristate buffer 78 is a circuit that outputs the sum-of-accumulate data of node N3 to the data bit line DBL at the timing of the column selection signal CSE_30. The column selection signal CSE_30 is a selection signal that becomes high level at a different timing than CSE_1 to CSE_29 and CSE_31. Therefore, the sum-of-accumulate data that has been processed by the activation function and quantized can be output to the data bit line DBL at a predetermined timing.

[0134] The multiply-accumulate circuit MAC shown in Figure 10A, described above, can be connected to the data bit line DBL and global sense amplifiers GSA_1 to GSA_29, and controlled by column selection signals CSE_1 to CSE_31. Figure 10B is a circuit block corresponding to the multiply-accumulate circuit MAC in Figure 10A.

[0135] Figure 11 also shows a timing chart illustrating the operation of the multiply-accumulate circuit MAC shown in Figure 10A, and explains its operation. Figure 11 illustrates the signal changes of the column line CSEL, weight data W, data bit line DBL, inverted data bit line DBLB, node N1, node N2, and node N3. The column line CSEL shows the column selection signals CSE_1 to CSE_31 supplied to the column line CSEL. The weight data W shows the global sense amplifiers GSA_1 to GSA_28 that output the weight data. The data bit line DBL shows the input data IN_1 to IN_28 corresponding to input data A, the signal PARAM for controlling the quantization circuit 75, and the multiply-accumulate data DOUT. The inverted data bit line DBLB shows the inverted signal DOUT_B of the multiply-accumulate data that occurs when the data on the data bit line DBL is finalized. Node N1 illustrates the initial state Reset due to the reset signal and the sum-of-products data MAC_1 to MAC_28. Node N2 illustrates the data SCL after processing by the activation function and quantization. Node N3 illustrates the initial state Reset due to the reset signal, processing by the activation function, and the sum-of-products data DOUT. The hatched areas represent states where the data or potential does not affect the operation (Don't care).

[0136] The period T0 shown in Figure 11 is the reset operation. During the reset operation, the column selection signal CSE_31 is selected. As a result, the selection signal is supplied to the reset terminal RS of registers 74 and 77, and registers 74 and 77 are reset. Consequently, nodes N1 and N3 return to their initial state, Reset.

[0137] The period T1 to T28 shown in Figure 11 represents a sum-of-accumulate operation. In the sum-of-accumulate operation, column selection signals CSE_1 to CSE_28 are selected in sequence. The data holding circuit 42 holds the weight data W (including bias data) read out by the global sense amplifiers GSA_1 to GSA_28. During period T1, the column selection signal CSE_1 selects the weight data W read out by the global sense amplifier GSA_1 and supplies it to the sum-of-accumulate circuit MAC. At this time, input data IN_1 is provided to the data bit line DBL via the data sense amplifier DSA, etc., and the sum-of-accumulate operation is performed in the sum-of-accumulate circuit MAC. The sum-of-accumulate data is held in register 74 within the sum-of-accumulate circuit MAC, as the column selection signal CSE_1 functions as a control signal for register 74, and node N1 becomes the sum-of-accumulate data MAC_1.

[0138] The same multiply-accumulate operation is performed during periods T2 to T28. The data holding circuit 42 holds the weight data W read out by the global sense amplifiers GSA_1 to GSA_28. During periods T2 to T28, the column selection signals CSE_2 to CSE_28 select the weight data W read out by the global sense amplifiers GSA_2 to GSA_28 and supply it to the multiply-accumulate circuit MAC. At this time, the multiply-accumulate operation is performed in the multiply-accumulate circuit MAC by switching and supplying input data IN_2 to IN_28 from the data sense amplifier DSA via the data bit line DBL. The multiply-accumulate data is held in register 74 within the multiply-accumulate circuit MAC as the column selection signals CSE_2 to CSE_28 function as control signals for register 74, and the multiply-accumulate data is accumulated. As a result, multiply-accumulate data can be obtained by switching between input data and weight data or bias data.

[0139] The period T29 shown in Figure 11 is the operation of processing by the activation function and quantization processing. During the processing by the activation function and quantization processing, the column selection signal CSE_29 is selected. At this time, by applying the signal PARAM to the data bit line DBL via the data sense amplifier DSA, the output signal of the AND gate 76 becomes activated, activating the quantization circuit 75. Therefore, node N2 becomes data SCL that has been processed by the activation function and quantized by the column selection signal CSE_29. The column selection signal CSE_29 is delayed by the buffer 79 and supplied to the register 77. Node N3 becomes the multiply-accumulate operation data DOUT, which is data SCL that has been processed by the activation function and quantized.

[0140] During the period T30 shown in Figure 11, the sum-of-products data DOUT held in node N3 is output via the data bit line DBL. The tristate buffer 78 is selected by the column selection signal CSE_30, and the data bit line DBL becomes the sum-of-products data DOUT. As the data bit line DBL becomes the sum-of-products data DOUT, the data sense amplifier DSA is activated, and the inverted data bit line DBLB becomes the inverted signal DOUT_B of the sum-of-products data DOUT.

[0141] Figure 12 illustrates an example configuration combining the circuit block of the multiply-accumulate circuit MAC shown in Figure 10B with the circuit blocks of the memory cell 41, global sense amplifier GSA, and data sense amplifier DSA shown in Figure 9C. As shown in Figure 12, a data holding circuit 42 is provided between the bit line BL (bit lines BL[0] and BL[7] shown) connected to the global sense amplifier GSA and the multiply-accumulate circuit MAC1.

[0142] In the configuration of the multiply-accumulate circuit MAC shown in Figures 10A to 12, multiple column selection signals CSE can be used as control signals. Furthermore, in the configuration of the multiply-accumulate circuit MAC shown in Figures 9A to 9C, the weight data can be switched and the data input to the multiply-accumulate circuit can be used as the control signals for the multiply-accumulate circuit.

[0143] As described above, in one aspect of the present invention, the column line CSEL that transmits the column selection signal can be shared between the multiply-accumulate circuit MAC and the global sense amplifier GSA. Therefore, the wiring that transmits the control signal for driving the multiply-accumulate circuit MAC can be reduced. As a result, miniaturization, reduced power consumption, and improved processing speed can be achieved by suppressing an increase in circuit area.

[0144] The configurations, structures, and methods shown in this embodiment can be used in appropriate combination with the configurations, structures, and methods shown in other embodiments.

[0145] (Embodiment 2) This embodiment describes an example of a cross-sectional configuration of an element layer having stacked OS transistors that can be applied to semiconductor devices and the like. This embodiment describes an example of a schematic cross-sectional diagram that can be applied to circuit configurations such as NOSRAM and DOSRAM.

[0146] <Example of NOSRAM Configuration> Figure 13 shows an example of a cross-sectional configuration when a 3-transistor type NOSRAM circuit configuration is used. Figure 13 illustrates the case where element layers UF[1] to UF[3] are stacked on element layer LF. Figure 14A shows an example of the cross-sectional structure of element layer UF[k]. Figure 14B shows the equivalent circuit diagram of Figure 14A.

[0147] The element layer LF is the element layer 10 described in Embodiment 1 above. Element layer LF is provided with elements such as Si transistors. The element layer UF is the element layer 40 described in Embodiment 1 above. Element layer UF is provided with elements such as OS transistors.

[0148] Figure 13 also illustrates a transistor 550 having element layer LF. The transistor 550 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate electrode, an insulating layer 315, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region.

[0149] The transistor 550 may be either a p-channel or n-channel type.

[0150] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0151] Note that the transistor 550 shown in Figure 13 is just one example, and its structure is not limited to this example. Any suitable transistor can be used depending on the circuit configuration or driving method.

[0152] A wiring layer containing an interlayer film, wiring, and plugs may be provided between the element layer LF and the element layer UF, or between the k-th element layer UF and the (k+1)th element layer UF. In this embodiment, the k-th element layer UF may be denoted as element layer UF[k], and the (k+1)th element layer UF may be denoted as element layer UF[k+1]. Here, k is an integer between 1 and N. Also, in this embodiment, when "k+α (α is an integer of 1 or more)" or "k-α" is used, the solutions to "k+α" and "k-α" are integers between 1 and N, respectively.

[0153] Furthermore, the wiring layer can be provided in multiple layers depending on the design. Also, in this specification, the wiring and the plug connected to the wiring may be an integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0154] For example, on the transistor 550, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. A conductive layer 328 is embedded in insulating layers 320 and 322. A conductive layer 330 is embedded in insulating layers 324 and 326. The conductive layers 328 and 330 function as contact plugs or wiring.

[0155] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 13, insulating layers 350, 357, 352, and 354 are sequentially laminated on the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed on insulating layers 350, 357, and 352. The conductive layer 356 functions as a contact plug or wiring.

[0156] An insulating layer 514 of the element layer UF is provided on top of the insulating layer 354. A conductive layer 358 is embedded in the insulating layer 514 and the insulating layer 354. The conductive layer 358 functions as a contact plug or wiring. For example, wiring that functions as a bit line and the transistor 550 are connected via the conductive layer 358, conductive layer 356, and conductive layer 330, etc.

[0157] The memory cell 41E shown in Figure 13 has transistors M2, M3, and M1 on an insulating layer 514, as shown in Figure 14A.

[0158] As shown in Figures 13 and 14A, transistors M2 and M3 share a single island-shaped semiconductor layer 530. In other words, a portion of the island-shaped semiconductor layer 530 functions as the channel formation region for transistor M2, and the other portion functions as the channel formation region for transistor M3. Furthermore, the source of transistor M2 and the drain of transistor M3, or the drain of transistor M2 and the source of transistor M3, are shared. Therefore, the area occupied by the transistors is smaller than when transistors M2 and M3 are provided independently.

[0159] Furthermore, in the memory cell 41E shown in Figures 13 and 14A, it is possible to omit the transistor M1. The memory cell 41E without the transistor M1 can be a two-transistor type NOSRAM, which corresponds to the memory cell 41D shown in Figure 7D.

[0160] Here, the OS transistor will be described with reference to Figures 15A to 15C. Figures 15A and 15B are schematic cross-sectional views of transistor 500 applicable to transistors M1 to M3.

[0161] As shown in Figures 15A and 15B, an insulating layer 516 is placed on top of an insulating layer 514. The transistor 500 includes a conductive layer 503 placed so as to be embedded in the insulating layer 516, an insulating layer 522 placed on top of the insulating layer 516 and the conductive layer 503, an insulating layer 524 placed on top of the insulating layer 522, a semiconductor layer 530 placed on top of the insulating layer 524, conductive layers 542a and 542b placed spaced apart from each other on the semiconductor layer 530, an insulating layer 580 placed on the conductive layers 542a and 542b with an opening formed between them, an insulating layer 545 placed on the bottom and side surfaces of the opening, and a conductive layer 560 placed on the forming surface of the insulating layer 545. The conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 545 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a.

[0162] Furthermore, as shown in Figures 15A and 15B, an insulating layer 544 is placed between the semiconductor layer 530, the conductive layer 542a and the conductive layer 542b and the insulating layer 580. In addition, an insulating layer 574 is placed on top of the insulating layer 580, the conductive layer 560 and the insulating layer 545, and an insulating layer 581 is placed on top of the insulating layer 574.

[0163] In transistor 500, the conductive layer 560 functions as a gate electrode, the insulating layer 545 functions as a gate insulating film, and the conductive layers 542a and 542b function as source electrodes or drain electrodes, respectively. The conductive layer 560 may function as a first gate electrode. The conductive layer 503 may function as a second gate electrode. The insulating layers 522 and 524 function as second gate insulating films.

[0164] In the transistor 500 shown in Figures 15A and 15B, an insulating layer 522 and an insulating layer 524 are shown as a second gate insulating film consisting of a two-layer laminated structure. However, the second gate insulating film may be a single-layer structure or a laminated structure of three or more layers. In that case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials.

[0165] In the transistor 500, it is preferable to use an oxide semiconductor layer as the semiconductor layer 530 including the channel formation region. The oxide semiconductor layer that can be used as the semiconductor layer 530 will be described in Embodiment 3 below.

[0166] In transistors using oxide semiconductors for the semiconductor layer, the channel formation region has more oxygen vacancies (V) than the source and drain regions. Ｏ It is preferable that there are few (V) or low concentrations of impurities such as hydrogen, nitrogen, and metallic elements. Also, hydrogen near the oxygen vacancy is less likely to be present in a defect (hereinafter referred to as V) where hydrogen has entered the oxygen vacancy. Ｏ In the channel-forming region, V may form (sometimes called H) and generate electrons that become carriers. Ｏ It is preferable that H is also reduced. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be type i (intrinsic) or substantially type i.

[0167] Furthermore, the source and drain regions of a transistor using an oxide semiconductor for the semiconductor layer have more oxygen vacancies than the channel formation region. Ｏ This region has a high concentration of hydrogen (H), or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, resulting in increased carrier concentration and low resistance. In other words, the source and drain regions of a transistor are n-type regions with higher carrier concentration and lower resistance compared to the channel formation region.

[0168] The band gap of the oxide semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using an oxide semiconductor with a large band gap as the semiconductor layer, the off-current of the transistor can be reduced. By using a transistor with a small off-current in the memory cell, it is possible to retain the stored contents for a long period of time. In other words, since refresh operations are not required, or the frequency of refresh operations is extremely low, the power consumption of the semiconductor device can be significantly reduced.

[0169] Although Figures 15A and 15B show the semiconductor layer 530 as a single layer, the present invention is not limited to this. For example, the semiconductor layer 530 may be a stacked structure of two or more layers.

[0170] When an oxide semiconductor is used as the semiconductor layer 530, as shown in Figure 15A, a low-resistance region 543a may be formed at and near the interface of the semiconductor layer 530 with the conductive layer 542a. Similarly, a low-resistance region 543b may be formed at and near the interface of the semiconductor layer 530 with the conductive layer 542b. In this case, regions 543a and 543b function as a source region or a drain region, respectively. Furthermore, a channel-forming region is formed in the region sandwiched between regions 543a and 543b.

[0171] Furthermore, the semiconductor material that can be used for the semiconductor layer 530 is not limited to oxide semiconductors. Semiconductor materials other than oxide semiconductors may also be used for the semiconductor layer 530. Other semiconductor materials that can be used for the semiconductor layer 530 will be described later in the section [Other Semiconductor Materials].

[0172] In Figure 15A, conductive layers 542a and 542b are shown as single layers, but the present invention is not limited to this. For example, conductive layers 542a and 542b may each be laminated in a configuration of two or more layers.

[0173] In Figures 15A and 15B, the conductive layer 560 and the conductive layer 503 are shown as a two-layer laminated structure, but the present invention is not limited to this. For example, the conductive layer 560 and the conductive layer 503 may each be a single layer or a laminated structure of three or more layers.

[0174] The insulating layer 580 is provided on the conductive layers 542a and 542b via the insulating layer 544. The opening in the insulating layer 580 is formed superimposed on the region between the conductive layers 542a and 542b. As a result, the conductive layer 560 is formed to be embedded in the opening in the insulating layer 580 and in the region sandwiched between the conductive layers 542a and 542b.

[0175] When an oxide semiconductor is used as the semiconductor layer 530, it is preferable to use an insulator containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen) for the insulating layer 580. By heat-treating the insulating layer 580 containing excess oxygen, oxygen is supplied from the insulating layer 580 to the channel formation region of the semiconductor layer 530, thereby eliminating oxygen deficiencies and V Ｏ This allows for a reduction in H. This stabilizes the electrical characteristics of transistor 500 and improves its reliability.

[0176] In Figures 15A and 15B, the insulating layer 545 is shown as a single layer, but the present invention is not limited to this. For example, the insulating layer 545 may be a laminated structure of two or more layers.

[0177] The insulating layer 544 is provided so as to cover the conductive layer 542a and the conductive layer 542b. Preferably, the insulating layer 544 has barrier properties against oxygen. This configuration suppresses oxidation of the conductive layer 542a and the conductive layer 542b.

[0178] An insulating layer 571a is placed on the conductive layer 542a, and an insulating layer 571b is placed on the conductive layer 542b. By providing insulators 271a and 271b, when processing the semiconductor film that will become the semiconductor layer 530, and the conductive films that will become the conductive layers 242a and 242b, in an island-like manner, it is possible to prevent the edges of the conductive layers 242a and 242b from being excessively etched. Therefore, fine transistors can be processed with high precision.

[0179] Preferably, the insulating layer 574 has the function of suppressing the diffusion of impurities such as hydrogen. Furthermore, preferably, the insulating layer 574 has the function of capturing or fixing impurities such as hydrogen. This configuration suppresses the diffusion of hydrogen into the semiconductor layer 530. It also reduces the hydrogen concentration in the semiconductor layer 530.

[0180] A conductive layer 540a is placed in the openings formed in insulating layers 581, 574, 580, 544, and 571a, and a conductive layer 540b is placed in the openings formed in insulating layers 581, 574, 580, 544, and 571b. Conductive layers 540a and 540b are provided opposite each other with conductive layer 560 in between. Conductive layers 540a and 540b function as vias, contact plugs, or wiring.

[0181] In Figure 15A, conductive layers 540a and 540b are shown as a two-layer laminated structure, but the present invention is not limited to this. For example, conductive layers 540a and 540b may each be a single layer or a laminated structure of three or more layers.

[0182] The transistor 500 shown in Figures 15A and 15B is just one example, and the configuration is not limited to this; any appropriate transistor can be used depending on the circuit configuration, driving method, etc.

[0183] It should be noted that the transistors that can be used in the present invention are not limited to the transistors 500 shown in Figures 15A and 15B. For example, a transistor 500 with the structure shown in Figure 15C may be used. The transistor 500 shown in Figure 15C differs from the transistors 500 shown in Figures 15A and 15B in that the conductive layers 542a and 542b are each in a laminated structure, and that insulating layers 520 and 555 are provided.

[0184] In the transistor 500 shown in Figure 15C, the conductive layer 542a has a laminated structure of conductive layer 542a1 and conductive layer 542a2 on conductive layer 542a1, and the conductive layer 542b has a laminated structure of conductive layer 542b1 and conductive layer 542b2 on conductive layer 542b1. It is preferable to use a conductor that is resistant to oxidation, such as a metal nitride, for conductive layers 542a1 and conductive layer 542b1 that are in contact with the semiconductor layer 530. This prevents the conductive layers 542a and conductive layer 542b from being excessively oxidized by oxygen contained in the semiconductor layer 530. Furthermore, it is preferable to use a conductor that has higher conductivity than conductive layers 542a1 and conductive layer 542b1 for conductive layers 542a2 and conductive layer 542b2. This allows conductive layers 542a and conductive layer 542b to function as highly conductive wiring or electrodes. In this way, a semiconductor device can be provided in which conductive layers 542a and 542b, which function as wiring or electrodes, are provided in contact with the upper surface of the semiconductor layer 530.

[0185] As shown in Figure 15C, in a cross-sectional view of the transistor 500 in the channel length direction, the distance between conductive layer 542a1 and conductive layer 542b1 is smaller than the distance between conductive layer 542a2 and conductive layer 542b2. This configuration allows for a shorter distance between the source and drain, and consequently, a shorter channel length. Therefore, the frequency characteristics of transistor 500 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0186] The insulating layer 555 is provided in contact with the side surfaces of the conductive layer 542a2 and the conductive layer 542b2. Preferably, the insulating layer 555 has the function of suppressing the diffusion of oxygen. With this configuration, oxidation of the side surfaces of the conductive layer 542a2 and the conductive layer 542b2 can be suppressed.

[0187] The insulating layer 520 preferably has hydrogen barrier properties. This suppresses the diffusion of hydrogen into the semiconductor layer 530 and reduces the hydrogen concentration in the semiconductor layer 530.

[0188] By using this configuration, it is possible to achieve miniaturization or high integration in semiconductor devices using transistors having oxide semiconductors.

[0189] It should be noted that the transistors that can be used in the present invention are not limited to the transistor 500 shown in Figures 15A and 15C. Figures 16A to 16D describe a configuration different from the transistors shown in Figures 15A to 15C. Figure 16A is a plan view of transistor 500A applicable to the above transistors M1 to M3. Figures 16B to 16D are cross-sectional views of the transistor 500A.

[0190] Figure 16B is a cross-sectional view of the region indicated by the dashed line A1-A2 in Figure 16A, and is also a cross-sectional view of transistor 500A in the channel width direction. Figure 16C is a cross-sectional view of the region indicated by the dashed line A3-A4 in Figure 16A, and is also a cross-sectional view of transistor 500A in the channel width direction. Figure 16D is a cross-sectional view of the region indicated by the dashed line A5-A6 in Figure 16A, and is also a cross-sectional view of transistor 500A in the channel length direction. Here, the dashed line A5-A6 is perpendicular to the dashed lines A1-A2 and A3-A4, and the dashed lines A1-A2 and A3-A4 are parallel to each other. Note that in the plan view of Figure 16A, some elements have been omitted and some elements are shown transparently for clarity.

[0191] The transistor 500A includes an insulating layer 516 on a substrate (not shown), an insulator 521 on the insulating layer 516, an insulating layer 522 on the insulator 521, a semiconductor layer 530 on the insulating layer 522, conductive layers 542a and 542b on the semiconductor layer 530 and the insulating layer 522, an insulating layer 545 on the semiconductor layer 530, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) on the insulating layer 545. In the following, conductive layers 542a and 542b may be collectively referred to as conductive layer 542.

[0192] An insulator 575 is provided on the conductive layer 542, and an insulating layer 580 is provided on the insulator 575. The insulating layer 545 and the conductive layer 560 are arranged inside openings provided in the insulating layer 580 and the insulator 575. These openings reach the semiconductor layer 530, and within these openings, the insulating layer 545 is in contact with the semiconductor layer 530. An insulating layer 574 is also provided on the insulating layer 580 and the conductive layer 560. An insulator 583 is also provided on the insulating layer 574. An insulator 515 is also provided below the insulating layer 516.

[0193] An insulator 541a is provided in contact with the inner wall of an opening in the insulating layer 580, and a conductive layer 540a is provided in contact with the side surface of the insulator 541a. The lower surface of the conductive layer 540a is in contact with the upper surface of the conductive layer 542a. In addition, an insulator 541b is provided in contact with the inner wall of an opening in the insulating layer 580, and a conductive layer 540b is provided in contact with the side surface of the insulator 541b. The lower surface of the conductive layer 540b is in contact with the upper surface of the conductive layer 542b. In the following, the conductive layer 540a and the conductive layer 540b may be collectively referred to as conductive layer 540. Also, the insulator 541a and the insulator 541b may be collectively referred to as insulator 541.

[0194] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500A. The conductive layer 560 has a region that functions as the first gate electrode (upper gate electrode) of the transistor 500A. The insulating layer 545 has a region that functions as the first gate insulator of the transistor 500A.

[0195] The conductive layer 542a has a region that functions as either the source electrode or the drain electrode of the transistor 500A. The conductive layer 540a functions as a plug that connects to the conductive layer 542a. The conductive layer 542b has a region that functions as either the source electrode or the drain electrode of the transistor 500A. The conductive layer 540b functions as a plug that connects to the conductive layer 542b.

[0196] The semiconductor layer 530 is formed in contact with the insulating layer 522. In a cross-sectional view in the channel width direction, the semiconductor layer 530 has a shape with a high aspect ratio (a shape in which the length in the height direction (H) is greater than or equal to the length of the base (W) (H≧W)). A semiconductor layer 530 having a high aspect ratio shape may have a fin-like shape.

[0197] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the width L of the semiconductor layer 530 to the height H of the semiconductor layer 530. The aspect ratio of the semiconductor layer 530 is preferably as large as possible without the semiconductor layer 530 tipping over during the manufacturing process of the transistor 500A. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 should be greater than 1 times the width L of the semiconductor layer 530 and 400 times or less, preferably 2 times or more and 100 times or less, more preferably 5 times or more and 40 times or less, and even more preferably 10 times or more and 20 times or less. Alternatively, for example, the height H may be 2 times or more and 10 times or less the width L. For example, the width L should be 5 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 10 nm or more and 30 nm or less. For example, the height H may be 50 nm or more and 2000 nm or less, preferably 100 nm or more and 1000 nm or less.

[0198] Furthermore, in a cross-sectional view in the channel width direction, the angle between the side surface of the semiconductor layer 530 and the upper surface of the insulating layer 522 is preferably a right angle or approximately a right angle. For example, the angle between the side surface of the semiconductor layer 530 and the upper surface of the insulating layer 522 is preferably 80° or more and 100° or less, and more preferably 85° or more and 95° or less.

[0199] An insulating layer 545, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 with a high aspect ratio. In transistor 500A, a portion of the insulating layer 545 and the conductive layer 560 are provided so that they are folded in half with the semiconductor layer 530 in between. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 545 in between at the top, A1 side, and A2 side of the semiconductor layer 530. In other words, the top, A1 side, and A2 side of the semiconductor layer 530 each function as a channel formation region. Therefore, compared to the case where the semiconductor layer 530 is formed in a planar shape, the channel width of transistor 500A is larger by the amount of the A1 side and A2 side of the semiconductor layer 530.

[0200] As described above, increasing the channel width improves the on-current, transconductance, and frequency characteristics of transistor 500A. This makes it possible to provide a transistor with a high operating speed. Furthermore, it is possible to increase the operating speed of a memory device using this transistor. In addition, in the above structure, by providing the semiconductor layer 530, the channel width can be increased without increasing the occupied area of ​​transistor 500A. This makes it possible to miniaturize or highly integrate the transistor. Moreover, with the above structure, the area where the sides of the conductive layer 560 and the semiconductor layer 530 face each other is increased, so the threshold can be controlled to make transistor 500A normally off.

[0201] Furthermore, the upper part of the semiconductor layer 530 may have a curved shape. Having such a curved shape can prevent defects such as pores from forming in the insulating layer 545 and the conductive layer 542 near the upper part of the semiconductor layer 530.

[0202] Since the semiconductor layer 530 has a high aspect ratio shape, it is preferable to form it in a sidewall shape on the side surface of the pillar, which is made of an insulator. Therefore, it is preferable to form the semiconductor layer 530 using the ALD method, which has good coverage. Furthermore, when the semiconductor layer 530 is made into a laminated structure, it is preferable to deposit at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0203] By forming semiconductor layers 530 in a sidewall shape adjacent to the sides of multiple pillars, multiple semiconductor layers 530 can be formed simultaneously, as shown in Figure 16A. By forming multiple semiconductor layers 530 in this way, the distance between each semiconductor layer 530 can be set according to the size and shape of the pillar. Therefore, the distance between each semiconductor layer 530 can be reduced, the occupied area of ​​the transistor 500A can be reduced, and the integration of transistors can be increased.

[0204] Since the semiconductor layer 530 is formed in a sidewall shape in contact with the pillar, as shown in Figure 16A, the upper surface shape of the semiconductor layer 530 is circumferential (which can also be described as frame-shaped, annular, donut-shaped, or closed curve-shaped) with both ends coinciding. The semiconductor layer 530 can also have an opening in the center. In Figure 16A, the upper surface shape of the semiconductor layer 530 is symmetrical with respect to A1-A2, but the present invention is not limited to this. For example, the upper surface shape of the semiconductor layer 530 may be asymmetrical.

[0205] The structure shown in Figure 16A has two pillars arranged in the A1-A2 direction, with a circumferential semiconductor layer 530 formed in contact with the side surface of each pillar. As shown in Figure 16A, it is preferable that the semiconductor layer 530 overlaps with the conductive layer 560 in two or more places when viewed from above. In other words, there are two or more regions where the semiconductor layer 530 and the conductive layer 560 overlap. With this structure, as shown in Figure 16B, multiple fin-shaped semiconductor layers 530 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped semiconductor layers 530 functions as a channel formation region. In other words, the transistor 500A functions as a multi-channel transistor. Therefore, the channel width of the transistor 500A can be further increased.

[0206] Furthermore, the configuration of transistor 500A applicable to the transistors M1 to M3 described in Figures 16A to 16D may be such that a conductive layer 503 is provided beneath the insulator 521, as shown in Figures 17A to 17D as transistor 500B. The conductive layer 503 has a region that functions as the second gate electrode (lower gate electrode) of transistor 500B. The insulating layer 522 and the insulator 521 each have regions that function as the second gate insulator of transistor 500B. Here, Figures 17A to 17D correspond to Figures 16A to 16D, so for detailed configurations, refer to the above.

[0207] In transistor 500B, the conductive layer 503 is arranged to overlap with the semiconductor layer 530 and the conductive layer 560. Here, it is preferable that the conductive layer 503 is embedded in an opening formed in the insulating layer 516. Furthermore, it is preferable that the conductive layer 503 extends in the channel width direction, as shown in Figures 17A and 17B. With this configuration, when multiple transistors are provided, the conductive layer 503 functions as wiring.

[0208] As shown in Figures 17B and 17D, it is preferable that the conductive layer 503 has a conductive layer 503a and a conductive layer 503b. The conductive layer 503a is provided in contact with the bottom surface and side wall of the opening. The conductive layer 503b is provided so as to fill the recess of the conductive layer 503a formed along the opening. Here, the height of the upper surface of the conductive layer 503 is equal to or approximately equal to the height of the upper surface of the insulating layer 516.

[0209] Here, the conductive layer 503a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, it is preferable to have a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0210] By using a conductive material having the function of reducing hydrogen diffusion in the conductive layer 503a, it is possible to prevent impurities such as hydrogen contained in the conductive layer 503b from diffusing into the semiconductor layer 530 via the insulating layer 516, etc. Furthermore, by using a conductive material having the function of suppressing oxygen diffusion in the conductive layer 503a, it is possible to suppress oxidation of the conductive layer 503b and a decrease in conductivity. Examples of conductive materials having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 503a can be a single-layer structure or a laminated structure of the above conductive material. For example, it is preferable that the conductive layer 503a has titanium nitride.

[0211] Furthermore, it is preferable that the conductive layer 503b is made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, it is preferable that the conductive layer 503b contains tungsten.

[0212] The conductive layer 503 can function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 500B can be controlled by changing the potential applied to the conductive layer 503 independently of the potential applied to the conductive layer 560. In particular, by applying a negative potential to the conductive layer 503, it is possible to increase the Vth of transistor 500B and reduce the off-current. Therefore, applying a negative potential to the conductive layer 503 reduces the drain current when the potential applied to the conductive layer 560 is 0V compared to not applying a negative potential.

[0213] Furthermore, the electrical resistivity of the conductive layer 503 is designed considering the potential applied to the conductive layer 503, and the film thickness of the conductive layer 503 is set to match this electrical resistivity. The film thickness of the insulating layer 516 is approximately the same as that of the conductive layer 503. Here, it is preferable to make the film thicknesses of the conductive layer 503 and the insulating layer 516 as thin as is permitted by the design of the conductive layer 503. By making the film thickness of the insulating layer 516 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 516 can be reduced, thereby suppressing the diffusion of these impurities into the semiconductor layer 530.

[0214] Although the above describes a laminated structure of conductive layer 503a and conductive layer 503b, the present invention is not limited thereto, and the conductive layer 503 may be a single layer or a laminated structure of three or more layers. For example, when the conductive layer 503 is a laminated structure of three layers, the above laminated structure of conductive layer 503a and conductive layer 503b can be further configured by providing a conductor made of the same material as conductive layer 503a on top of conductive layer 503b. In this case, the conductor may be formed so that the upper surface of conductive layer 503b is lower than the uppermost part of conductive layer 503a, and the conductor fills the recess formed by conductive layer 503a and conductive layer 503b.

[0215] <Example of DOSRAM Configuration> Figure 18 shows an example of a cross-sectional configuration using the DOSRAM circuit configuration. Figure 18 illustrates a case where element layers UF[1] to UF[3] are stacked on top of element layer LF. Figure 19A shows an example of the cross-sectional structure of element layer UF[k]. Figure 19B shows the equivalent circuit diagram of Figure 19A.

[0216] In Figure 18, each of the multiple element layers UF has multiple memory cells 41. In each of the element layers UF[1] to UF[3] shown in Figure 18, an example is shown in which two memory cells 41 are connected to one bit line BL. The memory cell 41 shown in Figure 18 has a transistor M1 and a capacitor C1. In the memory cell 41 shown in Figure 18, the capacitor C1 is provided below the transistor M1. An OS transistor can be used as the transistor M1.

[0217] Furthermore, conductive layers 363a, 363b, and 363c are embedded in the interlayer film between the element layer LF and the element layer UF[1]. In addition, a conductive layer 365 is embedded in the insulating layer 180, which will be described later, in each of the multiple element layers UF. Furthermore, a conductive layer 366 is embedded in the insulating layer 180 and insulating layer 280, which will be described later, in each of the multiple element layers UF. Furthermore, a conductive layer 367 is embedded in the semiconductor layer 270, insulating layer 250, and insulating layer 285, which will be described later, in each of the multiple element layers UF. Conductive layers 363a, 363b, 363c, 365, 366, and 367 function as vias, contact plugs, or wiring.

[0218] Next, we will describe an example of the configuration of memory cells 41 included in the multiple element layers UF shown in Figure 18.

[0219] Figure 20A is a plan view showing an example configuration of a memory cell 41 and its surroundings contained in each of the multiple element layers UF. Figure 20B is a plan view in which some of the components shown in Figure 20A are omitted. Figure 20C is a cross-sectional view along the dashed line A1-A2 shown in Figure 20A. Note that in Figure 20A, some of the components of transistor VM1, such as the insulating layer 250, are omitted. Similarly, in the plan views of subsequent transistors, some of the components, such as the insulating layer, are omitted.

[0220] In Figures 20A to 20C, transistor VM1 corresponds to transistor M1 in Figure 18, and capacitor VC1 corresponds to capacitor C1 in Figure 18.

[0221] In Figure 20C, an insulating layer 160 is placed on a substrate (not shown), an insulating layer 180 is placed on top of the insulating layer 160, an insulating layer 280 is placed on top of the insulating layer 180, and an insulating layer 285 is placed on top of the insulating layer 280.

[0222] A conductive layer 110 is provided on the insulating layer 160. The conductive layer 110 can, for example, be a wiring PL extending in the Y direction.

[0223] An opening 601 is provided in the region of the insulating layer 180 that overlaps with the conductive layer 110. The conductive layer 115 is provided so as to be in contact with the bottom surface and side walls of the opening 601. In other words, the conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 and a region in contact with the side surface of the insulating layer 180 at the opening 601. Note that in Figure 20C, the conductive layer 115 has a region in contact with the upper surface of the insulating layer 180.

[0224] An insulating layer 130 is provided on the insulating layer 180 and the conductive layer 115. A conductive layer 220 is also provided on the insulating layer 130. The conductive layer 220 is provided so as to fill the opening 601.

[0225] Capacitor VC1 has a conductive layer 115, a conductive layer 220, and an insulating layer 130.

[0226] In capacitor VC1, the conductive layer 115 functions as one of a pair of electrodes, the conductive layer 220 functions as the other of a pair of electrodes, and the insulating layer 130 functions as a dielectric sandwiched between the pair of electrodes.

[0227] A transistor VM1 is provided above the capacitor VC1. The transistor VM1 has a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0228] In transistor VM1, the conductive layer 260 functions as the gate electrode, and the insulating layer 250 functions as the gate insulating film. The conductive layers 220 and 240 function as the source electrode or drain electrode, respectively. As mentioned above, the conductive layer 220 also functions as the other electrode of the pair of electrodes in capacitor VC1.

[0229] Within the semiconductor layer 270, the entire region facing the gate electrode via the gate insulating film between the source electrode and the drain electrode functions as a channel formation region. Furthermore, within the semiconductor layer 270, the region in contact with the source electrode functions as the source region, and the region in contact with the drain electrode functions as the drain region.

[0230] The insulating layer 280 can function as an interlayer insulating layer. Here, the interlayer insulating layer can be an interlayer film that separates the source electrode and gate electrode in the transistor VM1.

[0231] A conductive layer 240 is provided on the insulating layer 280. The insulating layer 280 has an opening 602 that reaches the conductive layer 220. The conductive layer 240 has an opening 603 that reaches the opening 602. In other words, the opening 603 has a region that overlaps with the opening 602.

[0232] Figure 20A shows the components of transistor VM1 as conductive layer 220, conductive layer 240, conductive layer 260, opening 602, and opening 603. Here, Figure 20B shows an example configuration in which conductive layer 260 is omitted from the components shown in Figure 20A. In other words, Figure 20B shows conductive layer 220, conductive layer 240, opening 602, and opening 603.

[0233] Figures 20A and 20B show examples where the shapes of openings 602 and 603 are circular in plan view. By making the planar shapes of openings 602 and 603 circular, the processing accuracy when forming openings 602 and 603 can be improved, and openings 602 and 603 of minute size can be formed. Therefore, miniaturization or high integration of memory cells can be achieved. In this specification, the term "circular" is not limited to a perfect circle. For example, the planar shapes of openings 602 and 603 may be elliptical, or include curves, or be polygonal, or have rounded corners.

[0234] The description of the shapes of openings 602 and 603 can also be applied to opening 601.

[0235] It is preferable that the conductive layer 240 is not provided inside the opening 602. In other words, it is preferable that the conductive layer 240 does not come into contact with the side surface of the insulating layer 280 on the opening 602 side. With this configuration, the openings 603 and 602 can be formed at once, simplifying the process.

[0236] Figure 20C shows an example where the lower edge of the conductive layer 240 at opening 603 coincides with, or approximately coincides with, the upper edge of the insulating layer 280 at opening 602. In this specification, the lower surface of the conductive layer 240 refers to the surface on the insulating layer 280 side, and the upper surface of the insulating layer 280 refers to the surface on the conductive layer 240 side.

[0237] Furthermore, when we say that the edges match or roughly match, we can also say that the edges are aligned or roughly aligned. When the edges are aligned or roughly aligned, and the planar shapes match or roughly match, it can be said that, in a plan view, at least a portion of the contours overlap between the stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case as well, the edges are said to be roughly aligned, or the planar shapes roughly match.

[0238] Hereafter, the opening including openings 602 and 603 may be referred to as opening 290. In other words, the insulating layer 280 and the conductive layer 240 are provided with openings 290 that reach the conductive layer 220. Furthermore, opening 602 is a part of opening 290, and opening 603 is another part of opening 290.

[0239] At least a portion of the semiconductor layer 270 is placed in the opening 290. The semiconductor layer 270 has a region in contact with the side surface of the conductive layer 240, a region in contact with the side surface of the insulating layer 280, and a region in contact with the upper surface of the conductive layer 220 in the opening 290. The semiconductor layer 270 has a region in contact with the upper surface of the conductive layer 240.

[0240] At least a portion of the insulating layer 250 is placed in the opening 290. The insulating layer 250 is provided on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region in contact with the upper surface of the semiconductor layer 270, a region in contact with the side surface of the semiconductor layer 270, a region in contact with the side surface of the conductive layer 240, and a region in contact with the upper surface of the insulating layer 280.

[0241] The conductive layer 260 is provided on the insulating layer 250 and has a region in contact with the upper surface of the insulating layer 250. The conductive layer 260 is provided so as to fill the opening 290. The conductive layer 260 is provided so as to fill the recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270 via the insulating layer 250.

[0242] Figure 20C shows an example in which the conductive layer 260 has a region that overlaps with the conductive layer 240 via the insulating layer 250 and the semiconductor layer 270, but the present invention is not limited to this. For example, the conductive layer 260 may be provided so as not to overlap with the conductive layer 240. By using such a configuration, the parasitic capacitance that occurs between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operating speed of the memory cell can be improved.

[0243] The transistor VM1 has a channel length that is not substantially parallel to the substrate (not shown), but rather aligned with the side wall of the opening 602 provided in the insulating layer 280. In this specification, such a transistor is sometimes referred to as a vertical transistor.

[0244] Vertical transistors have a configuration in which at least part of the source region, channel formation region, and drain region can overlap when viewed from above, thus reducing the occupied area (also called the footprint). Furthermore, because the structure allows for a smaller channel length and a larger channel width, the on-resistance can be reduced (and the on-current increased).

[0245] Figure 20A shows an example in which the conductive layer 240 extends in a direction perpendicular to the conductive layers 110 and 260.

[0246] Here, an enlarged view of the semiconductor layer 270 and its vicinity in Figure 20C is shown in Figure 21A. Furthermore, a cross-sectional view in the XY plane, including the conductive layer 240, is shown in Figure 21B.

[0247] As shown in Figure 21A, the semiconductor layer 270 has a region 270i and regions 270na and 270nb that are provided so as to sandwich region 270i.

[0248] Region 270na is the region of the semiconductor layer 270 that is in contact with the conductive layer 220. Region 270nb is the region of the semiconductor layer 270 that is in contact with the conductive layer 240. Regions 270na and 270nb function as the source region or drain region of the transistor VM1, respectively. As shown in Figure 21B, the conductive layer 240 is in contact with the entire outer periphery of the semiconductor layer 270. Therefore, the source region or drain region of the transistor VM1 can be formed on the entire outer periphery of the portion of the semiconductor layer 270 that is formed in the same layer as the conductive layer 240.

[0249] Region 270i is the region in the semiconductor layer 270 sandwiched between region 270na and region 270nb. Region 270i functions as the channel formation region of transistor VM1. In other words, the channel formation region of transistor VM1 is formed in a part of the semiconductor layer 270 located in the region between the conductive layer 220 and the conductive layer 240. Alternatively, the channel formation region of transistor VM1 can be said to be located in the semiconductor layer 270 in the region in contact with the insulating layer 280 or in a region near it.

[0250] The channel length of transistor VM1 is the distance between the source region and the drain region. In other words, the channel length of transistor VM1 is determined by the thickness of the insulating layer 280 on the conductive layer 220. Figure 21A shows the channel length L of transistor VM1 with a dashed double arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the semiconductor layer 270 and the conductive layer 220 are in contact and the edge of the region where the semiconductor layer 270 and the conductive layer 240 are in contact. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 602 side in a cross-sectional view.

[0251] In planar transistors, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in the present invention, the channel length can be set by the thickness of the insulating layer 280. Therefore, the channel length of transistor VM1 can be made into an extremely fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-current of transistor VM1, improving the frequency characteristics. Therefore, a semiconductor device with a high operating speed can be provided.

[0252] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. This reduces the area occupied by the transistor VM1 compared to a planar transistor where the channel formation region, source region, and drain region are provided separately on the XY plane. As a result, the semiconductor device can be highly integrated, and the memory capacity per unit area can be increased.

[0253] Furthermore, in the XY plane including the channel formation region of the semiconductor layer 270, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged concentrically, similar to Figure 21B. Therefore, the side surface of the conductive layer 260 located at the center faces the side surface of the semiconductor layer 270 via the insulating layer 250. In other words, in a top view, the entire perimeter of the semiconductor layer 270 becomes the channel formation region. In this case, for example, the channel width of the transistor VM1 is determined by the length of the outer perimeter of the semiconductor layer 270. That is, the channel width of the transistor VM1 can be said to be determined by the size of the maximum width of the opening 602. Figures 21A and 21B show the maximum width D of the opening 602 with double-headed arrows. Figure 21B shows the channel width W of the transistor VM1 with double-headed arrows.

[0254] When forming the aperture 602 using photolithography, the maximum width D of the aperture 602 is limited by the exposure limit of the photolithography. The maximum width D of the aperture 602 is also determined by the film thickness of the semiconductor layer 270, insulating layer 250, and conductive layer 260 provided in the aperture 602. The maximum width D of the aperture 602 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the aperture 602 is circular in a top view, the maximum width D of the aperture 602 corresponds to the diameter of the aperture 602, and the channel width W can be calculated as "D × π".

[0255] The maximum width D of the opening 602 should be calculated appropriately according to the shape of the opening 602 in plan view. For example, if the opening 602 is rectangular in plan view, the maximum width of the opening 602 should be the length of the diagonal of the rectangle. Alternatively, for example, if the opening 602 is elliptical, polygonal, or has rounded corners in plan view, the maximum width of the opening 602 should be the diameter of the smallest circle (also called the smallest enclosing circle) that encloses the shape of the opening 602 in plan view.

[0256] Furthermore, in a semiconductor device according to one aspect of the present invention, it is preferable that the channel length L of the transistor VM1 is at least smaller than the channel width W of the transistor VM1. In one aspect of the present invention, the channel length L of the transistor VM1 is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, the channel width W of the transistor VM1. By adopting such a configuration, a transistor with good electrical characteristics and high reliability can be realized.

[0257] Furthermore, by forming the opening 602 so that it is roughly circular when viewed from above, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged concentrically. As a result, the distance between the conductive layer 260 and the semiconductor layer 270 becomes roughly uniform, so that the gate electric field can be applied to the semiconductor layer 270 roughly uniformly.

[0258] In Figure 21A and other figures, the opening 602 is provided such that its side surface is perpendicular to the upper surface of the conductive layer 220, but the present invention is not limited to this. For example, the side surface of the opening 602 may be tapered.

[0259] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface (also called the taper angle) is less than 90°.

[0260] As shown in Figure 20C, a portion of the insulating layer 250 is located outside the opening 603, that is, on top of the insulating layer 280. In this case, it is preferable that the insulating layer 250 covers the side edge of the conductive layer 240. This prevents the conductive layer 260 and the conductive layer 240 from short-circuiting.

[0261] The semiconductor layer 270 can be made of a semiconductor applicable to the semiconductor layer 530 described above, either as a single layer or stacked. Furthermore, the configuration of the semiconductor layer 270 can also be referenced from the configuration of the semiconductor layer 530 described above.

[0262] The semiconductor layer 270 preferably has layered crystals that are generally parallel to the side surface of the insulating layer 280 at the opening 602. With this configuration, the layered crystals of the semiconductor layer 270 are formed generally parallel to the channel length direction of the transistor VM1, so that the on-current of the transistor can be increased.

[0263] When the semiconductor layer 270 and the conductive layer 220 come into contact, a metal compound or oxygen vacancy is formed, reducing the resistance of region 270na in the semiconductor layer 270. This reduced resistance in the semiconductor layer 270 in contact with the conductive layer 220 reduces the contact resistance between the semiconductor layer 270 and the conductive layer 220. Similarly, when the semiconductor layer 270 and the conductive layer 240 come into contact, the resistance of region 270nb in the semiconductor layer 270 is reduced. Therefore, the contact resistance between the semiconductor layer 270 and the conductive layer 240 can be reduced.

[0264] The conductive layer 240 can have a laminated structure of a first conductive layer and a second conductive layer on the first conductive layer. In this case, the first conductive layer can be formed using a highly conductive material, and the second conductive layer can be formed using an oxygen-containing conductive material. When an oxide semiconductor is used as the semiconductor layer 270, by using an oxygen-containing conductive material as the second conductive layer of the conductive layer 240 that is in contact with the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced, and the decrease in the on-current of the transistor VM1 caused by the contact resistance can be suppressed. For example, tungsten can be used as the first conductive layer of the conductive layer 240, and indium tin oxide containing silicon can be used as the second conductive layer of the conductive layer 240.

[0265] The conductive layer 220 has a recess that overlaps with the opening 602. The semiconductor layer 270 is in contact with the bottom and side surfaces of the recess in the conductive layer 220. The recess in the conductive layer 220 may be considered as part of the opening 290.

[0266] By having a recess in the conductive layer 220 at a position overlapping the opening 602, the height of the lower surface of the insulating layer 250 and the lower surface of the conductive layer 260 at the opening 290 can be made lower than the height of the upper surface of the conductive layer 220 that is in contact with the insulating layer 280, relative to the upper surface of the insulating layer 160, compared to the case where there is no recess. Here, the height of each surface can be determined relative to the surface on which the memory cell or transistor is formed. Here, the upper surface of the insulating layer 160 is used as the reference. The surface used as the reference is not particularly limited, and for example, the upper surface of the substrate on which the memory cell or transistor is provided may be used as the reference.

[0267] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby lowering the contact resistance between the conductive layer 220 and the semiconductor layer 270. Consequently, the decrease in the on-current of the transistor VM1 caused by the contact resistance between the conductive layer 220 and the semiconductor layer 270 can be suppressed. Furthermore, the gate electric field becomes more easily applied to the channel formation region of the semiconductor layer 270, improving the electrical characteristics of the transistor VM1. In addition, the gate electric field becomes more easily applied to the region of the semiconductor layer 270 in contact with the conductive layer 220, thereby increasing the on-current of the transistor VM1. Moreover, the electrical characteristics of the transistor VM1 can be improved regardless of whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode.

[0268] Furthermore, it is preferable to use an oxygen-containing conductive material for the conductive layer 220. When an oxide semiconductor is used as the semiconductor layer 270, using an oxygen-containing conductive material for the conductive layer 220 can lower the contact resistance between the semiconductor layer 270 and the conductive layer 220.

[0269] Alternatively, the conductive layer 220 may have a structure in which tungsten is laminated beneath a conductive material containing oxygen. By laminating tungsten in this way, the conductivity of the conductive layer 220 can be improved.

[0270] Since insulating layers 280 and 285 function as interlayer films, it is preferable that they have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the capacitance value of parasitic capacitance that occurs between wiring can be reduced.

[0271] Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 280 is reduced. This makes it possible to suppress the incorporation of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 270.

[0272] Furthermore, it is preferable to use an insulator containing excess oxygen for the insulating layer 280. By heat-treating the insulating layer 280 containing excess oxygen, oxygen is supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, thereby eliminating oxygen deficiencies and V Ｏ This allows for a reduction in H. This stabilizes the electrical characteristics of transistor VM1 and improves its reliability.

[0273] It should be noted that the transistors that can be used in the present invention are not limited to the transistor VM1 shown in Figure 20C. For example, a transistor VM2 having the structure shown in Figure 22 may be used. The transistor VM2 shown in Figure 22 differs from the transistor VM1 shown in Figure 20C in that it is provided with a conductive layer 215 and an insulating layer 225.

[0274] The configuration shown in Figure 22 corresponds to the memory cell 41A shown in Figure 7A. In the memory cell 41A shown in Figure 22, the transistor VM2 is located above the capacitor VC1.

[0275] As shown in Figure 22, a conductive layer 215 is provided on top of an insulating layer 280. Furthermore, an insulating layer 281 is placed on top of both the insulating layer 280 and the conductive layer 215. Additionally, a conductive layer 240 is provided on top of the insulating layer 281.

[0276] The insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240 are provided with openings 604 that reach the conductive layer 220. The openings 604 include openings in the insulating layer 280, openings in the conductive layer 215, openings in the insulating layer 281, and openings in the conductive layer 240. The side walls of the openings 604 include the sides of the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240.

[0277] Each of the insulating layer 225, semiconductor layer 270, insulating layer 250, and conductive layer 220 is provided such that at least a portion of it is located in the opening 604. Specifically, the insulating layer 225 is provided to cover a portion of the bottom and side walls of the opening 290, the semiconductor layer 270 is provided to cover the other portion of the bottom of the opening 290 and the insulating layer 225, and the insulating layer 250 is provided to cover the semiconductor layer 270. The conductive layer 260 is provided to fill the recess in the insulating layer 250 that reflects the shape of the opening 604.

[0278] The insulating layer 225 is in contact with a portion of the upper surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 215, the side surface of the insulating layer 281, and the side surface of the conductive layer 240 at the opening 604.

[0279] In the transistor VM2 shown in Figure 22, the semiconductor layer 270 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating film, the conductive layer 215 functions as a second gate electrode, the insulating layer 225 functions as a second gate insulating film, and the conductive layers 220 and 240 function as a source electrode or drain electrode, respectively.

[0280] By changing the potential applied to the conductive layer 215 independently of the potential applied to the conductive layer 260, the threshold voltage V of the transistor can be controlled. ｔｈ This can be controlled. In particular, by applying a negative potential to the conductive layer 215, the V of the transistor can be controlled. ｔｈThis makes it possible to increase the potential and reduce the off-current. Therefore, applying a negative potential to the conductive layer 215 reduces the drain current when the potential applied to the conductive layer 260 is 0V compared to when no potential is applied. In addition, the conductive layer 260 may function as a second gate electrode and the conductive layer 215 may function as a first gate electrode.

[0281] Alternatively, the conductive layer 215 may be connected to the conductive layer 260. By connecting the conductive layer 215 and the conductive layer 260 and applying the same potential, it is possible to increase the on-current, reduce initial characteristic variations, suppress deterioration of electrical characteristics in negative GBT (Gate Bias-Temperature) stress tests, and suppress DIBL (Drain Induced Barrier Lowering).

[0282] As described above, the transistor VM2 shown in Figure 22 has a first gate electrode and a second gate electrode, which improves the electrical characteristics of the transistor in the semiconductor device.

[0283] <Materials for semiconductor devices> The following describes the materials that can be used in semiconductor devices.

[0284] [Substrate] When a transistor is mounted on a substrate, there are no major restrictions on the material used for the substrate. Depending on the purpose, the material can be determined by considering factors such as whether or not it is translucent and its heat resistance to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.

[0285] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the above semiconductor substrate, such as SOI (Silicon On Insulator) substrates. In addition, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0286] [Insulating Layer] An inorganic insulating film is used for each insulating layer. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films. Examples of oxide insulating films include silicon oxide film, aluminum oxide film, magnesium oxide film, gallium oxide film, germanium oxide film, yttrium oxide film, zirconium oxide film, lanthanum oxide film, neodymium oxide film, hafnium oxide film, tantalum oxide film, cerium oxide film, zinc gallium oxide film, and hafnium aluminate film. Examples of nitride insulating films include silicon nitride film and aluminum nitride film. Examples of oxidative nitride insulating films include silicon oxide nitride film, aluminum oxide nitride film, gallium oxide nitride film, yttrium oxide nitride film, and hafnium oxide nitride film. Examples of nitride oxide insulating films include silicon oxide nitride film and aluminum oxide nitride film. In addition, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0287] In this specification, "oxide nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0288] [Conductive Layer] For the conductive layer used in the transistor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements, or an alloy combining the above metal elements. As an alloy containing the above metal elements, nitrides of the alloy or oxides of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0289] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, silicon-added indium tin oxide (also known as ITSO), indium zinc oxide (also known as IZO®), and indium zinc oxide containing tungsten oxide. In this specification, a conductive layer formed using an oxygen-containing conductive material may be referred to as an oxide conductive layer.

[0290] Conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.

[0291] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0292] [Semiconductor Layer] As the semiconductor layer, single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used individually or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors may also be used. As compound semiconductors, organic materials with semiconductor properties or metal oxides with semiconductor properties (also called oxide semiconductors) can be used. These semiconductor materials may contain impurities as dopants.

[0293] Furthermore, a semiconductor made of a single element or a compound semiconductor may be used as the semiconductor layer. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. Furthermore, these semiconductor materials may contain impurities as dopants.

[0294] When silicon is used as a semiconductor layer, examples of silicon that can be used for the semiconductor layer include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As an example of polycrystalline silicon, low-temperature polysilicon (LTPS) is used.

[0295] A two-dimensional material that functions as a semiconductor may be used as the semiconductor layer of a transistor. Two-dimensional materials, also called layered materials, are a general term for a group of materials that have a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity as the semiconductor layer, it is possible to provide a transistor with a large on-current.

[0296] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a semiconductor layer in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0297] When using an oxide semiconductor, a type of metal oxide, as the semiconductor layer, the band gap of the metal oxide is preferably 2.0 eV or higher, and more preferably 2.5 eV or higher. By using a metal oxide with a large band gap as the semiconductor layer, the off-current of the transistor can be significantly reduced. Because the off-current of the OS transistor is small, the power consumption of the semiconductor device can be reduced. The oxide semiconductor will be described in detail in Embodiment 3, which will be described later.

[0298] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0299] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer as described in Embodiment 2, and a crystalline indium oxide film will be described.

[0300] <Oxide Semiconductor Layer> In one aspect of the present invention, the oxide semiconductor layer preferably has a crystalline metal oxide. Examples of structures of the crystalline metal oxide include CAAC (c-axis aligned crystal) structure, polycrystalline (Poly-crystal) structure, and microcrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect level density in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor using the oxide semiconductor layer in one aspect of the present invention can be improved, and the reliability of a memory device on which the transistor is mounted can be improved.

[0301] In one aspect of the present invention, the oxide semiconductor layer preferably has a metal oxide having a CAAC structure. A CAAC structure is a crystalline structure in which a plurality of microcrystals (typically a plurality of microcrystals having a hexagonal crystal structure) are oriented along the c axis, and in the a-b plane, the plurality of microcrystals are linked together without orientation. Furthermore, when a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in layers in the crystalline portion. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having a layered crystalline portion.

[0302] The crystallinity of an oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for the analysis.

[0303] The crystallinity of the semiconductor material in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more amorphous semiconductors (semiconductors with an amorphous structure), single-crystal semiconductors (semiconductors with a single-crystal structure), or semiconductors with crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in part). The crystallinity of the oxide semiconductor layer may suppress the degradation of transistor characteristics.

[0304] Examples of metal oxides in an oxide semiconductor layer according to one aspect of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one aspect of the present invention preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is a metal or metalloid element with a high bond energy to oxygen; for example, a metal or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M present in the metal oxide is gallium, the metal oxide according to one aspect of the present invention preferably has one or more selected from indium, gallium, and zinc. In this specification, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.

[0305] Examples of metal oxides according to one aspect of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also written as IGTO), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), and indium Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. can be used. Alternatively, silicon-containing indium tin oxide (also called ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0306] <Indium Oxide Film> In one embodiment of the present invention, a crystalline indium oxide film can be used as the oxide semiconductor layer.

[0307] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0308] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0309] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon.

[0310] The range of carrier concentrations suitable for the channel formation region of a transistor is when the carrier concentration value is 1 × 10⁻⁶ １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0311] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, and cadmium. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0312] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0313] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, tin, and silicon. It is especially preferable to use elements in which the oxide is conductive or semiconducting.

[0314] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called N-I-N junction (a junction between an N-type region, an I-type region, and an N-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0315] The indium oxide film is preferably crystalline (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for the indium oxide film, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using a single-crystal film, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by the crystal grain boundaries.

[0316] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0317] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0318] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0319] Impurities in indium oxide can act as carrier scattering sources, potentially leading to a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in indium oxide films include boron and silicon. In indium oxide films, lower concentrations of these impurities in the channel-forming regions are preferable. Preferably, the concentration of each of these impurity elements in the indium oxide film is 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0320] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0321] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0322] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0323] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, as mentioned above, it reacts with oxygen contained in the film and is released as water molecules.

[0324] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Additionally, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0325] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0326] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0327] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0328] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0329] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0330] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0331] (Embodiment 4) This embodiment describes electronic components, electronic devices, and large computers that can use the semiconductor device described in the above embodiment. Electronic components, electronic devices, and large computers using a semiconductor device according to one aspect of the present invention are effective in achieving high performance, such as low power consumption.

[0332] [Electronic Components] Figure 23A shows a perspective view of a substrate (mounted substrate 704) on which an electronic component 709 is mounted. The electronic component 709 shown in Figure 23A has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 23A to show the inside of the electronic component 709. The electronic component 709 has a land 712 on the outside of the mold 711. The land 712 is connected to an electrode pad 713, and the electrode pad 713 is connected to the semiconductor device 710 via a wire 714. The electronic component 709 is mounted on a printed circuit board 702, for example. Multiple such electronic components are combined and connected on the printed circuit board 702 to complete the mounted substrate 704.

[0333] Furthermore, the semiconductor device 710 includes a layer 715 having an arithmetic core and a layer 716 having memory. The layer 716 having memory has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the layer 715 having an arithmetic core and the layer 716 having memory can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By configuring the layer 715 having an arithmetic core and the layer 716 having memory in a monolithic stack configuration, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0334] Furthermore, by using an on-chip memory configuration, it is possible to reduce the size of connection wiring and other components compared to technologies that use through-hole electrodes such as TSVs, thus increasing the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0335] Furthermore, it is preferable to form multiple memory cell arrays in the memory-containing layer 716 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either the memory bandwidth or the memory access latency, or both. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory-containing layer 716, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0336] Furthermore, the semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0337] Next, a perspective view of the electronic component 730 is shown in Figure 23B. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0338] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0339] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also has the function of connecting integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0340] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0341] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0342] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as described above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0343] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0344] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 23B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0345] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0346] Figures 24A to 24D illustrate a configuration example different from the electronic components 709 and 730 described in Figures 23A and 23B above. The electronic components 730A to 730D shown in Figures 24A to 24D have a configuration in which a layer 715 having a processing core and a layer 716 having memory are provided within a mold 711 on an interposer 731 on which the electrodes 733 described above are provided.

[0347] In the configuration of the electronic component 730A shown in Figure 24A, the layer 715 having the arithmetic core is provided on the interposer 731 and connected to electrode pads (not shown) via wires 714. The layer 716 having memory, formed on the layer 715 having the arithmetic core, has the monolithic stack configuration described above. In the monolithic stack configuration, the layer 716 having memory and the layer 715 having the arithmetic core are connected. Therefore, the wiring between the layer 716 having memory of each layer and the interposer 731 can be combined with the wires 714 between the interposer 731 and the layer 715 having the arithmetic core, thus reducing the number of wires.

[0348] Although Figure 24A describes a configuration example where there is only one monolithic stacked structure, the monolithic stacked electronic components may also be stacked on top of other electronic components. For example, as shown in Figure 24B, a configuration can be made in which multiple layers are stacked, such as a layer 716A having memory and a layer 715A having an arithmetic core, and a layer 716B having memory and a layer 715B having an arithmetic core. The monolithic stacked structure stacked on top of other electronic components is fixed to the resin sheet 744 by an adhesive layer 743. This configuration allows for the stacking of multiple memory cell arrays having different circuit configurations. Having different circuit configurations allows for semiconductor devices with different memory bandwidths and memory access latencies, and is suitable for application to configurations with a hierarchical structure, such as cache memory.

[0349] Furthermore, the configuration example in Figure 24A can be provided in stacked form with other electronic components. For example, as shown in Figure 24C, an electronic component 730C can be formed by stacking an electronic component, such as a layer 715C having a processing core like a processor, which is provided in a mold 711 between interposers 731A and 731B, with the aforementioned electronic component 730A. The circuits can be connected via conductors such as electrodes 733. This configuration makes it possible to speed up the operation of the interface between the processor and the memory. In addition, since a gap (space) can be provided between the mold containing the layer 715C with the processing core and the electronic component 730A and the mold, it is possible to make it difficult for heat generated in the layer 715C with the processing core to be transferred to the electronic component 730A.

[0350] Furthermore, in the configuration example shown in Figure 24C, a memory layer having an OS transistor may be provided on a layer 715C having an arithmetic core such as a processor. For example, as shown in Figure 24D, a layer 716C having memory can be provided on a layer 715C having an arithmetic core, and the electronic component 730A can be stacked on top of it. This configuration makes it possible to speed up the operation of the interface portion between a so-called on-chip memory configuration, in which memory is directly formed on the processor, and a semiconductor device configuration having stacked memory layers.

[0351] [Electronic Devices] Figure 25A is an external view showing an example of a portable electronic device. Figure 25B is a simplified diagram of data exchange within the portable electronic device. The portable electronic device 595 includes a printed circuit board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0352] In the portable electronic device 595, the electronic component 709 can be provided on the printed circuit board 596. The portable electronic device 595 can improve user convenience by processing and analyzing multiple data obtained from the speaker 597, camera 598, microphone 599, etc., using the electronic component 709. It can also be used in systems that perform voice guidance, image search, etc.

[0353] The electronic component 709 can perform calculations such as neural network processing on the obtained image data, enabling processes such as image resolution enhancement, image noise reduction, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range enhancement), image restoration of lensless image sensors, positioning, character recognition, and reduction of reflections.

[0354] The portable game console 1100 shown in Figure 26A includes a housing 1101, housing 1102, housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, etc. Housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on housing 1101 to housing 1108, the video output from the display unit 1104 can be output to another video device. On the other hand, by attaching housings 1102 and 1103 to housing 1109, housings 1102 and 1103 are integrated and function as an operation unit. The above-mentioned electronic components 709 can be incorporated into chips, etc., provided on the circuit boards of housings 1102 and 1103.

[0355] Figure 26B shows a USB-connected stick-type electronic device 1120. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a circuit board 1124. The circuit board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are mounted on the circuit board 1124. The above-mentioned electronic components 709 can be incorporated into the controller chip 1126, etc., on the circuit board 1124.

[0356] Figure 26C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the above-mentioned electronic component 709.

[0357] [Large-scale computer] Instead of embedding the above-mentioned electronic component 709 in the electronic device, it can also be used in a system 3000 that includes a large-scale computer that communicates with the electronic device. In this case, the electronic device and the large-scale computer constitute a computing system. Figure 27 shows an example of the configuration of system 3000.

[0358] System 3000 consists of electronic equipment 3001 and a mainframe computer 3002. Communication between the electronic equipment 3001 and the mainframe computer 3002 can be performed via an internet connection 3003.

[0359] The mainframe computer 3002 has multiple racks 3004. Multiple circuit boards 3005 are provided in the multiple racks, and the electronic components 709 described in the above embodiment can be mounted on the circuit boards 3005. This configures a neural network in the mainframe computer 3002. The mainframe computer 3002 can then perform calculations on the neural network using data input from the electronic device 3001 via the internet connection 3003. The results of the calculations performed by the mainframe computer 3002 can be transmitted to the electronic device 3001 via the internet connection 3003 as needed. This reduces the computational burden on the electronic device 3001.

[0360] This embodiment can be appropriately combined with descriptions of other embodiments.

[0361] This embodiment describes a prototype memory chip with arithmetic functions. The memory chip with arithmetic functions was designed based on the semiconductor device 100 described in the above embodiment. In this embodiment, the same reference numerals are used for the components described in the semiconductor device 100, and their descriptions may be omitted.

[0362] Figure 28 shows an external view of the arithmetic memory chip 850. The external dimensions of the fabricated arithmetic memory chip 850 are 4 mm x 4 mm. The arithmetic memory chip 850 is broadly divided into two areas: a region containing multiple memory cells, multiple sense amplifiers, and multiply-accumulate circuits (Memory and SA and PU), and a region where logic circuits and control circuits that control their operation are provided (Control Logic).

[0363] SA corresponds to the global sense amplifier GSA described in the above embodiment. Hereinafter, the global sense amplifier GSA may be abbreviated as "SA" in drawings, etc. PU corresponds to the multiply-accumulate circuit MAC in the multiply-accumulate circuit section 30 described in the above embodiment. Hereinafter, the multiply-accumulate circuit MAC may be abbreviated as "PU" in drawings, etc.

[0364] Figure 29 shows a block diagram of the prototype memory chip 850 with arithmetic functions. A memory cell array MCA, which has memory cells made of OS transistors, is arranged on a sense amplifier SA and a multiply-accumulate operation circuit PU, which are circuits made of Si transistors. The memory cells arranged in the memory cell array MCA are the memory cells 41 described in the above embodiment. Logic circuits and control circuits such as a data sense amplifier section 12, a global sense amplifier drive circuit 13, and a word line side drive circuit 15 are arranged around the sense amplifier SA and the multiply-accumulate operation circuit PU, which are circuits made of Si transistors.

[0365] The memory cell array (MCA) is divided into 64 rows x 1024 bits arrays, with each bit line connected to the sense amplifier (SA) directly below it. The sense amplifier (SA) and the multiply-accumulate (PLP) circuit (PU) are located directly below the memory cell array (MCA). Therefore, the area overhead associated with adding the PLP circuit (PU) to provide arithmetic functionality is small. Furthermore, since the sense amplifiers (SA) can be driven in parallel, high bandwidth can be achieved.

[0366] The memory cell array MCA has seven sub-arrays in the prototype memory chip 850 with arithmetic functions. In the prototype memory chip 850 with arithmetic functions, the seven sub-arrays of the memory cell array MCA may be referred to as Block #0 (MEM) to Block #6 (MEM). In the prototype memory chip 850 with arithmetic functions, the sense amplifier SA has seven blocks corresponding to the seven sub-arrays, which may be referred to as Block #0 (SA) to Block #6 (SA). In the prototype memory chip 850 with arithmetic functions, the multiply-accumulate circuit PU has seven blocks corresponding to the seven sub-arrays, which may be referred to as Block #0 (PU) to Block #6 (PU).

[0367] A more detailed block diagram of the prototype memory chip 850 with arithmetic functions is shown in Figure 30. As an example, Figure 30 shows an input / output circuit 90 that connects the controller 80 to an external circuit, the controller 80 that inputs and outputs control signals EN and data DATA, and the memory chip 850 with arithmetic functions that has 16 banks. Each of the 16 banks has the configuration shown in the block diagram in Figure 29. The controller 80 supplies various control signals EN, such as address signals, word line control signals, sense amplifier control signals, balancing control signals, column selection control signals, read control signals, and write control signals, to the circuits in each bank.

[0368] In Figure 30, a memory cell array MCA having a memory cell 41 is provided above a sense amplifier array SAA and a multiply-accumulate circuit PU, where a plurality of sense amplifiers SA are arranged in an array. The memory cell 41 is connected to the lower-layer sense amplifier SA (not shown) via a bit line BL or an inverting bit line BLB (not shown). The memory cell 41 is connected to a word line-side drive circuit 15 via a word line WL. The sense amplifier SA and the multiply-accumulate circuit PU are connected to a data sense amplifier section 12 via a data bit line DBL. The sense amplifier SA is connected to a global sense amplifier drive circuit 13.

[0369] The sense amplifier array SAA has a configuration in which multiple sense amplifiers SA are arranged in an array. The sense amplifier array SAA is connected to four multiply-accumulate circuits PU, for example, via an inverting bit line BLB. In the seven sub-arrays, by activating one row of word lines WL for each sub-array, multiply-accumulate operations can be performed in parallel within the bank. The multiply-accumulate circuit PU has the configuration described in Figure 10A. Therefore, the multiply-accumulate operation is performed in parallel between the weight data selected by the column selection signal and the input data supplied from the data bit line DBL. The multiply-accumulate circuit can also perform arithmetic processing such as quantization processing and ReLU processing based on the column selection signal. The calculated data can be output to the data sense amplifier unit 12 via the data bit line.

[0370] The multiply-accumulate (MLIT) circuit PU is controlled solely by a column select signal, without using a clock. Since the column select signal is connected to the sense amplifier SA adjacent to the MLIT circuit PU, there are fewer constraints regarding layout and signal delay. By utilizing the column select signal to control the MLIT circuit PU, additional control signals and control logic become unnecessary.

[0371] Figures 31A and 31B illustrate the connection relationships between the data sense amplifier section 12 (shown as DSA in the figures), the global sense amplifier drive circuit 13 (shown as SAD in the figures), and the blocks Block #0(SA) to Block #6(SA) having the sense amplifier SA, and the blocks Block #0(PU) to Block #6(PU) having the multiply-accumulate operation circuit PU in each operating mode. Figures 31A and 31B also illustrate the connection relationships between the word line side drive circuit 15 (shown as WCB in the figures) and the blocks Block #0(MEM) to Block #6(MEM) corresponding to the subarray having memory cells.

[0372] The data sense amplifier DSA is connected to the sense amplifier SA and the multiply-accumulate circuit PU. The value of a setting register inside the control logic allows the DSA to change whether it exchanges data with the sense amplifier SA or the multiply-accumulate circuit PU (in Figures 31A and 31B, solid arrows indicate the connected state and dashed arrows indicate the disconnected state). When the data sense amplifier DSA exchanges data with the sense amplifier SA, it is called the memory access mode, and when it exchanges data with the multiply-accumulate circuit PU, it is called the calculation mode. The memory access mode corresponds to the schematic diagram shown in Figure 31A, and the calculation mode corresponds to the schematic diagram shown in Figure 31B.

[0373] The memory access mode is used when writing weight data to memory cells. Since writing weight data is done only once as initialization, throughput is not an issue. Therefore, writing weight data activates each block #0 (MEM) through #6 (MEM) corresponding to the subarray one by one (activated blocks are shown with hatching in Figure 31A). At this time, the DSA, SAD, and WCB operate only on the blocks corresponding to the active subarrays.

[0374] In calculation mode, weight data is read from Block #0 (MEM) to Block #6 (MEM), corresponding to all subarrays. Therefore, in addition to Blocks #0 (MEM) to Block #6 (MEM), SAD and WCB are all activated, as are Blocks #0 (SA) to Block #6 (SA) and Block #0 (PU) to Block #6 (PU). The data sense amplifier DSA can perform multiply-accumulate operations on all subarray-corresponding blocks Block #0 (MEM) to Block #6 (MEM) by activating all blocks connected to the multiply-accumulate circuit PU.

[0375] Figure 32 is a timing chart illustrating the operation of the prototype memory chip 850 with arithmetic functions. In Figure 32, the operation mode Op. mode switches from the memory access mode P0, which writes weight data to each memory cell, to the arithmetic mode P1, which performs the sum-of-accumulate operation.

[0376] In memory access mode P0, the command is a NOP command, i.e., a command that does not perform calculations. In calculation mode P1, the same commands as in memory access mode can be used. Specifically, these are the ACT command for activation control (ACT), the WRITE command for write control (WRITE), the READ command for read control (READ), and the PC command for precharge control (PC). With this configuration, existing commands can be reused as commands for performing calculations. This avoids the bloat of the control logic that processes according to the commands. The latency of each command is the same as during memory access.

[0377] In calculation mode P1, 1024-bit / block weight data can be read from the memory cell to the sense amplifier SA by specifying the row address (Row ADDR) and issuing an ACT command. The bit line BL of each block (Block #0 to Block #6) becomes the potential of the weight data (W00, W01, W02, W10, W11, W12, W60, W61, W62). The weight data can be loaded into the multiply-accumulate circuit PU via the inverting bit line BLB of the sense amplifier SA.

[0378] Next, in calculation mode P1, the sum-of-accumulate operation is performed by issuing the WRITE command. The WRITE command specifies the row address (Row ADDR) and inputs activation data IP1, such as input data and parameter data, to the data bit line DBL while switching the column address (Col ADDR). If the number of weight data exceeds the length of one word line, the calculation can be continued by activating another word line. By issuing the WRITE command with a specific column address specified, calculations such as quantization and ReLU processing can be performed.

[0379] Next, in calculation mode P1, the calculation result is read by issuing the READ command. The READ command allows you to specify the column address (Col ADDR) and read the calculation result data OP1 by switching the row address (Row ADDR).

[0380] Figure 33A shows the Schmoo plot for Read Time. Figure 33A is a Schmoo plot obtained by changing the voltage supplied to the word line WL (WL Supply Voltage) from 1.0V to 2.0V in 0.1V steps, and changing the Read Time from 2.5ns to 20ns in 2.5ns steps, under room temperature conditions.

[0381] In the Schmoo plot shown in Figure 33A, a Pass is defined as a Pass if the Pass ratio of the arithmetic memory chip 850 is 99.5% or higher, and a Fail if it is lower. The Pass ratio refers to the percentage of memory cells that are able to perform data readout or data writeout out of all memory cells being evaluated.

[0382] Figure 33A shows that stable data readout operation can be achieved when the voltage supplied to the word line WL is 1.9V or higher and the Read Time is 7.5ns or higher.

[0383] Figure 33B shows the Schmoo plot for Write Time. Figure 33B is a Schmoo plot obtained by changing the voltage supplied to the word line WL from 1.0V to 2.0V in 0.1V steps and changing the Write Time from 7.5ns to 25ns in 2.5ns steps under room temperature conditions.

[0384] In the Schmoo plot shown in Figure 33B, a pass ratio of 99.5% or higher for the arithmetic memory chip 850 under room temperature conditions is defined as "Pass," and any other result is defined as "Fail."

[0385] Figure 33B shows that stable data writing operation can be achieved when the voltage supplied to the word line WL is 1.5V or higher and the Write Time is 7.5ns or higher.

[0386] Figure 34A shows a timing chart illustrating the data read time of a memory cell in the prototype memory chip 850 with arithmetic functions. Figure 34B shows a timing chart illustrating the data write time. In Figures 34A and 34B, the multiple states that a memory cell can be in are illustrated as idle state, activation operation, read operation, and precharge operation (PC).

[0387] Read time was defined as the time from turning off the pre-charge signal EQ_ENB and turning on the word line selection signal WL_EN, as shown in Figure 34A, until turning on the SA_EN signal to control the global sensor amplifier. Write time was defined as the time from turning on the column line selection signal CSEL_EN, as shown in Figure 34B, until turning on the pre-charge signal EQ_ENB.

[0388] Figure 35 shows the measurement results of the data retention time of the arithmetic memory chip 850 under conditions of 125°C. The horizontal axis of Figure 35 shows the retention time on a logarithmic scale. The vertical axis shows the pass ratio, which represents the percentage of memory cells that were able to continuously retain data out of all memory cells being evaluated.

[0389] The measurement was performed by ensuring that different data (data 1 and data 0) were stored in adjacent memory cells within a single bit of data. The fabricated memory chip 850 with arithmetic functionality maintained a pass ratio of over 99% even after a retention time of 100 seconds in an environment of 125°C. A retention time of 100 seconds is approximately 1563 times longer than the typical refresh cycle of a DRAM, which is 64 ms. Therefore, the fabricated memory chip 850 with arithmetic functionality enables a reduction in the refresh cycle and thus reduces standby power consumption. It was found that the fabricated memory chip 850 with arithmetic functionality is a storage device capable of high-speed access and long-term data retention.

[0390] Table 1 shows the performance table of the fabricated memory chip 850 with arithmetic functions.

[0391]

[0392] The configurations, structures, or methods shown in this embodiment can be used in appropriate combination with the configurations, structures, or methods shown in other embodiments.

[0393] <Notes Regarding the Description in This Specification, etc.> The above embodiments and descriptions of each component in the embodiments are provided below.

[0394] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0395] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0396] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0397] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0398] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification and can be appropriately rephrased.

[0399] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0400] In this specification, when describing the connection relationships of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, etc.

[0401] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0402] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0403] In this specification, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0404] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0405] In this specification, the channel length in a planar transistor refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap, or in the region where the channel is formed, as seen in a top view of the transistor.

[0406] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0407] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Also, terminals, wiring, etc. can be replaced with "node."

[0408] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship of circuit elements as a physical object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of a circuit element (e.g., a transistor or a switch; however, wiring is not a circuit element) between them. On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected through one or more circuit elements.

[0409] Here, when we define "A and B are indirectly connected," it refers to the following type of connection, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can still be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation).

[0410] The following are specific examples of "indirect connections." First, an example of "A and B being indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of "A and B being indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming the circuit is operating, one transistor between A and B will be ON, conducting, or in a state where current can flow at least once. Note that "A and B are indirectly connected" includes cases where one transistor between A and B is OFF or non-conducting. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be ON, conducting, or in a state where current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0411] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0412] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, if multiple transistors are connected via their sources and drains in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND, then it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." Furthermore, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power source or GND, then it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0413] In this way, an example of "indirect connection" has been shown. As an example, since the provision of "indirect connection" is included in the provision of "electrical connection", when "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0414] Next, a specific example of the case of "direct connection" will be shown. As an example of the case where "A and B are directly connected", there may be a case where A and B are connected without an intervening circuit element. In addition, when A and B are connected to a power supply that supplies a certain potential V or GND or the like without an intervening circuit element, it can be said that "A and B are directly connected", "A and V are directly connected", or "B and V are directly connected". In addition, even when A (or B) is connected to a certain potential V via the source and drain of a transistor, it can be said that "A and B are directly connected". Since A and V or B and V are connected via the source and drain of a transistor, it cannot be said to be a direct connection, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected".

[0415] In this way, an example of "direct connection" has been shown. As an example, since the provision of "direct connection" is included in the provision of "electrical connection", when "A and B are directly connected", it can be said that "A and B are electrically connected".

[0416] 10: Element layer, 11: Functional circuit section, 12: Data sense amplifier section, 13: Global sense amplifier drive circuit, 14: Column line side drive circuit, 15: Word line side drive circuit, 20: Global sense amplifier section, 30: Multiplication and addition operation circuit section, 40: Element layer, 41: Memory cell, 42: Data holding circuit, 43: Transistor, 44: Capacitance element, 45: Switch, 50: Selector, 51: Transistor, 52: Semiconductor layer, 53: Transistor, 54: Semiconductor layer, 100: Semiconductor device

Claims

1. The device comprises a memory cell, a first sense amplifier, a multiply-accumulate circuit, a data holding circuit, and a second sense amplifier, wherein the first sense amplifier, the second sense amplifier, and the multiply-accumulate circuit are provided on a first element layer, the memory cell and the data holding circuit are provided on a second element layer, the second element layer is provided above the first element layer, the memory cell is electrically connected to the first sense amplifier via a first bit line, the first bit line is electrically connected to the multiply-accumulate circuit via the data holding circuit, the second sense amplifier is electrically connected to the first sense amplifier and the multiply-accumulate circuit via a second bit line, the first sense amplifier has the function of amplifying the first data held by the memory cell selected by a word line selection signal, and the function of outputting the amplified first data to the second sense amplifier in accordance with a column selection signal, and the data holding circuit has the function of holding the amplified first data. The semiconductor device has the function of performing a sum-of-products operation on the first data and the second data supplied from the second sense amplifier via the second bit line in accordance with the column selection signal.

2. The semiconductor device according to claim 1, wherein the memory cell has a first transistor, the first transistor has a first semiconductor layer having a channel forming region, and the first semiconductor layer has indium oxide.

3. The semiconductor device according to claim 2, wherein the second element layer has a switch, the switch has the function of dividing the first bit line electrically connected to the memory cell into a plurality of parts, and electrically connecting any one of the divided first bit lines to the first sense amplifier.

4. The semiconductor device according to claim 1, wherein the first bit line has a portion provided between the memory cell and the first sense amplifier, and between the data holding circuit and the sum-accumulate circuit, parallel to a direction perpendicular to the substrate surface on which the first element layer is provided.

5. The semiconductor device according to claim 1, wherein the first element layer has a second transistor, the second transistor has a second semiconductor layer having a channel formation region, and the second semiconductor layer has silicon.

6. The semiconductor device according to claim 1, comprising a column line side drive circuit that outputs the column selection signal, wherein the column line side drive circuit is electrically connected to a column line that supplies the column selection signal, and the column line is alternately connected to the first sense amplifier and the sum-of-accumulate circuit in the direction in which the column line extends.

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