Etching method and method for producing semiconductor device

Abstract

The present disclosure comprises: (a) a step in which, using a gas containing radicalized oxygen, oxidation is carried out on each of a first exposed side surface of an SiGe layer and a second exposed side surface of an Si layer, thereby forming an SiGe oxide film within the first side surface and forming an Si oxide film within the second side surface; and (b) a step in which, using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, the SiGe oxide film is selectively etched while maintaining the temperature of the semiconductor substrate in the range from at least TL (°C) to not more than TH (°C). Using C (%) for the atomic ratio of Ge to Si in the SiGe layer and using P (Pa) for the pressure or partial pressure of hydrogen fluoride in step (b), C (%) < 25%, 50 Pa ≤ P (Pa) ≤ 1000 Pa, TL = 11.3 × LN (P) + 0.23 × C - 97.4, and TH = 13 × LN (P) + C - 102.

Description

Etching method and method for manufacturing semiconductor device

[0001] This invention relates to an etching method and a manufacturing technology for semiconductor devices.

[0002] To continuously improve the functionality and performance of integrated circuit chips, higher transistor integration is always required. To date, this integration has been achieved primarily through miniaturization of transistor elements. In this regard, numerous improvements have been made to transistor structures and the materials that constitute them in order to miniaturize transistor elements while maintaining or improving transistor performance.

[0003] For example, transistor structures are shifting from planar to fin-type structures with three dimensions, and furthermore, it is expected that gate-all-around FETs (GAA) will be developed, in which the channel is composed of a wire-like or sheet-like stacked structure, and the channel is surrounded by a gate electrode.

[0004] In GAA-type FETs, for example, a channel is formed from a layered structure in which silicon layers (Si layers) and silicon-germanium layers (SiGe layers) are alternately stacked. Furthermore, the manufacturing process of GAA-type FETs includes a step in which the silicon-germanium layers are selectively etched.

[0005] For example, Japanese Patent Publication No. 2016-143781 (Patent Document 1) and Japanese Patent Publication No. 2021-150488 (Patent Document 2) describe techniques for selectively etching silicon germanium layers.

[0006] Japanese Patent Publication No. 2019-212872 (Patent Document 3) describes how a silicon oxide film is etched when the temperature of a semiconductor substrate is cooled to -25°C or below.

[0007] Non-patent document 1 describes a technique for self-limiting the etching of a silicon germanium layer using plasma oxidation.

[0008] Japanese Patent Publication No. 2016-143781, Japanese Patent Publication No. 2021-150488, Japanese Patent Publication No. 2019-212872

[0009] J. Li, et. al., "A novel dry selective isotropic atomic layer etching of SiGe for manufacturing vertical nanowire array with diameter less than 20nm", Materials, 13, 771 (2020)

[0010] In the manufacturing process of a GAA-type FET, for example, as shown in Figures 1(a) to 1(d), the following steps are sequentially performed: (a) forming a laminated structure in which Si layers 1 and SiGe layers 2, which are channel materials, are alternately stacked; (b) selective etching of the SiGe layers 2; (c) embedding of inner spacers 3 as insulating films; and (d) etching of excess inner spacers 3.

[0011] The technical significance of selectively etching the SiGe layer 2 to provide the insulating film inner spacer 3 is as follows: In a GAA-type FET, the gate electrode is formed to cover the multilayer structure that constitutes the channel. In this regard, in order to reduce parasitic capacitances such as gate electrode-source capacitance and gate electrode-drain capacitance, the SiGe layer 2 is selectively etched to provide the insulating film inner spacer 3. In other words, the inner spacer 3 is provided to reduce parasitic capacitance in a GAA-type FET. As described above, a process of selectively etching the SiGe layer 2 is carried out in order to provide the inner spacer 3.

[0012] For example, Patent Document 1 describes a technique for selectively etching a SiGe layer. The technique described in Patent Document 1 uses F as the etching gas. ２ and NH ３ This technique involves supplying a mixed gas and controlling its flow rate ratio to selectively etch SiGe relative to Si. However, with this technique, it is difficult to uniformly control the amount of SiGe etched in the upper and lower layers of the laminated structure.

[0013] In this regard, Patent Document 2 describes selective oxidation of the surface of a SiGe layer with oxygen-active species generated by plasma, and then the oxidized SiGe film is treated with HF and NH ３ This document describes a technique for selectively etching the SiGe layer by removing it with a gas containing [a specific substance].

[0014] Since the thickness of the SiGe oxide film formed by plasma oxidation saturates with respect to processing time, the thickness of the SiGe oxide film in the upper and lower layers of the laminated structure remains constant. Furthermore, since SiGe oxide is selectively removed from SiGe by etching, repeating this oxidation and etching process allows for self-limiting and uniform etching of the SiGe layer. However, during the oxidation process, the Si layer is also oxidized to a lesser extent than the SiGe layer, forming a Si oxide film. Therefore, during the etching process, the Si oxide film is also removed, and etching proceeds in the Si layer as well. Consequently, there is room for improvement in the limited etching selectivity ratio between Si and SiGe.

[0015] Similarly, Non-Patent Document 1 describes a technique for self-limiting the etching of a SiGe layer using plasma oxidation. This technique involves oxidizing the Si surface and SiGe surface by plasma oxidation, and then adjusting the mixing ratio appropriately to C ４ F ８ / CF ４ Plasma processing is performed. This technique selectively etches the SiGe layer onto the Si layer by repeatedly performing cycles to remove the SiGe oxide layer from the Si oxide layer.

[0016] In this technology, a hydrocarbon-containing deposit is formed on the surface of the SiGe layer after the SiGe oxide film is removed. This deposit is removed during the subsequent plasma oxidation process. However, on the structural sample, the amount of deposit formation may differ between the upper and lower parts of the layered structure, and it may not be possible to completely remove the deposit. For this reason, even in the technology described in Non-Patent Document 1, uniform etching of the SiGe layer is difficult.

[0017] Therefore, it is desirable to uniformly etch the SiGe layer against the Si layer.

[0018] One embodiment of the etching method is an etching method that etches a laminated structure in which silicon germanium layers and silicon layers are alternately formed on a semiconductor substrate. This etching method comprises (a) a step of oxidizing the exposed first side surface of the silicon germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen, thereby forming a silicon germanium oxide film in the first side surface and a silicon oxide film in the second side surface; and (b) a step of selectively etching the silicon germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) to TH (°C). Here, let C (%) be the atomic ratio of germanium to silicon in the silicon-germanium layer, and let P (Pa) be the pressure or partial pressure of hydrogen fluoride in step (b). Then C (%) < 25%, 50 Pa ≤ P (Pa) ≤ 1000 Pa, TL = 11.3 × LN(P) + 0.23 × C - 97.4, and TH = 13 × LN(P) + C - 10².

[0019] One embodiment of the etching method is an etching method that etches a laminated structure in which silicon germanium layers and silicon layers are alternately formed on a semiconductor substrate. This etching method comprises (a) a step of oxidizing the exposed first side surface of the silicon germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen, thereby forming a silicon germanium oxide film in the first side surface and a silicon oxide film in the second side surface; and (b) a step of selectively etching the silicon germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) to TH (°C). Here, let C (%) be the atomic ratio of germanium to silicon in the silicon-germanium layer, and let P (Pa) be the pressure or partial pressure of hydrogen fluoride in step (b). Then 25% ≤ C (%) < 50%, 50 Pa ≤ P (Pa) ≤ 1000 Pa, TL = 11.6 × LN(P) - 10⁵, and TH = 13 × LN(P) + C - 10⁻².

[0020] One embodiment of a semiconductor device manufacturing method is a method for manufacturing a semiconductor device including a gate-all-around type FET having a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate. This semiconductor device manufacturing method comprises (a) a step of forming a silicon-germanium oxide film in the first side surface and a silicon oxide film in the second side surface by oxidizing the exposed first side surface of the silicon-germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen; and (b) a step of selectively etching the silicon-germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) or higher and TH (°C) or lower. Here, let C (%) be the atomic ratio of germanium to silicon in the silicon-germanium layer, and let P (Pa) be the pressure or partial pressure of hydrogen fluoride in step (b). Then C (%) < 25%, 50 Pa ≤ P (Pa) ≤ 1000 Pa, TL = 11.3 × LN(P) + 0.23 × C - 97.4, and TH = 13 × LN(P) + C - 10².

[0021] One embodiment of a semiconductor device manufacturing method is a method for manufacturing a semiconductor device including a gate-all-around type FET having a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate. This semiconductor device manufacturing method comprises (a) a step of forming a silicon-germanium oxide film in the first side surface and a silicon oxide film in the second side surface by oxidizing the exposed first side surface of the silicon-germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen; and (b) a step of selectively etching the silicon-germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) or higher and TH (°C) or lower. Here, let C (%) be the atomic ratio of germanium to silicon in the silicon-germanium layer, and let P (Pa) be the pressure or partial pressure of hydrogen fluoride in step (b). Then 25% ≤ C (%) < 50%, 50 Pa ≤ P (Pa) ≤ 1000 Pa, TL = 11.6 × LN(P) - 10⁵, and TH = 13 × LN(P) + C - 10⁻².

[0022] According to one embodiment, the SiGe layer can be uniformly etched onto the Si layer.

[0023] Figures (a) to (d) show the formation process of the stacked structure constituting the channel of a GAA-type FET. This is a flowchart explaining the etching method in this disclosure. Figures (a) to (f) are explanatory diagrams showing the main steps for selectively etching the SiGe layer in a Si / SiGe stacked structure. This is a graph showing the relationship between the film thickness of the Si oxide film and SiGe oxide film and the oxidation treatment time when plasma oxidation treatment is performed on the Si layer and SiGe layer. This is a graph showing the relationship between the etching rate of the Si oxide film by HF gas and the temperature of the semiconductor substrate. (a) is a graph showing the relationship between the etching rate and temperature of the SiGe oxide film formed on the surface of a SiGe layer with a Ge concentration of 15%, (b) is a graph showing the relationship between the etching rate and temperature of the SiGe oxide film formed on the surface of a SiGe layer with a Ge concentration of 25%, and (c) is a graph showing the relationship between the etching rate and temperature of the SiGe oxide film formed on the surface of a SiGe layer with a Ge concentration of 50%. Figure 6(a) shows the etching rate of the SiGe oxide film (Ge concentration 15%), and Figure 5 shows the relationship between the etching rate of the Si oxide film and temperature on the same graph. (a) is a graph showing the relationship between the lower limit temperature and the HF gas pressure for SiGe oxide films formed on the surface of SiGe layers with Ge concentrations of 15%, 25%, and 50%, and (b) is a graph showing the relationship between the intercept value (vertical axis intercept value) in the relationship between the lower limit temperature and the HF gas pressure shown in (a) and the Ge concentration. Based on the temperature dependence of the etching rate of the Si oxide film shown in Figure 5, the temperature at which the etching rate becomes 60 nm / min is read at each HF gas pressure, and this graph plots the relationship between this temperature and the HF gas pressure. Figure 8(a) shows the first lower limit temperature and Figure 9 shows the second lower limit temperature plotted on the same graph. (a) is a graph showing the relationship between the temperature at which an etching rate of 0.1 nm / min is obtained (read from Figure 6) and the pressure of the HF gas, and (b) is a graph plotting the relationship between the intercept value in the relationship between the upper limit temperature shown in (a) and the natural logarithm of the HF gas pressure and the Ge concentration.(a) is a graph showing the effective temperature range for a Ge concentration of 25% or 15% as a function of the pressure of HF gas, and (b) is a graph showing the effective temperature range for a Ge concentration of 50% as a function of the pressure of HF gas. It is a diagram showing the configuration of an etching apparatus. It is a graph showing the results of etching a Si layer and a SiGe layer (Ge concentration: 25%) formed on a wafer by the etching method in the embodiment, and is a graph showing the relationship between the etching time and the etching amount. It is a graph showing the results of etching a Si layer and a SiGe layer (Ge concentration: 25%) formed on a wafer by the etching method in the embodiment, and is a graph showing the relationship between the number of processes (process cycles) and the etching amount. (a) is a graph showing the temperature dependence of the etching selectivity between a SiGe layer and a Si layer obtained using SiGe with a Ge concentration of 25%, and (b) is a graph showing the temperature dependence of the etching amount of the SiGe layer obtained using SiGe with a Ge concentration of 25%.

[0024] Hereinafter, the present disclosure will be described based on the drawings. Note that the present disclosure is not limited to the embodiments described below, and various modifications are possible within the scope of its technical idea.

[0025] In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof may be omitted. Also, many changes are possible, such as changing the combination of materials and manufacturing processes with respect to the content disclosed as the embodiment.

[0026] The drawings are not necessarily drawn to scale exactly, and important parts are emphasized and schematically drawn so that the logic is clear. Also, the drawings may be schematically represented compared to the actual aspect for the purpose of making the explanation clearer, but they are merely examples and do not limit the interpretation of the present disclosure.

[0027] <Basic Idea> FIG. 2 is a flowchart showing the process of selectively etching a SiGe layer.

[0028] FIGS. 3(a) to (f) are explanatory diagrams showing the main processes of selectively etching a SiGe layer in a Si / SiGe stacked structure.

[0029] In the following description, the surface referred to as the "exposed surface" is the end face where each layer in which the SiGe layer and the Si layer are alternately arranged is exposed, and is the surface corresponding to the side face in the cross-sectional view.

[0030] In the basic idea, after cooling the semiconductor substrate (S101 in FIG. 2), a step of forming a silicon oxide film 100 and a silicon germanium oxide film 200 on the surface layer of the exposed surface of the Si layer 1 and the SiGe layer 2 laminated on the semiconductor substrate (S102 in FIG. 2, FIGS. 3(b) and 3(d)) is performed.

[0031] Then, after exhausting the oxygen gas used for plasma oxidation (S103 in FIG. 2), a step of removing the formed silicon germanium oxide film 200 (S104 in FIG. 2, FIGS. 3(c) and 3(e)) is performed. Thereafter, a step of exhausting the hydrogen fluoride gas and the reaction products used in the step of removing the silicon germanium oxide film 200 (S105 in FIG. 2) is performed.

[0032] As shown in FIGS. 3(b) to 3(e), S102 and S104 described above are repeatedly performed. Specifically, as shown in FIG. 3(f), it is repeatedly performed until the recession amount of the exposed surface of the SiGe layer 2 in the lateral direction of the paper surface becomes the desired etching amount (S106 in FIG. 2).

[0033] In the basic idea, the etching amount of the SiGe layer 2 is determined by the film thickness of the silicon germanium oxide film 200 formed in S102. Therefore, in order to realize uniform etching of the SiGe layer 2, it is necessary to form a uniform silicon germanium oxide film.

[0034] In the basic idea, in order to oxidize the SiGe layer 2, plasma oxidation treatment using oxygen radicals generated by plasma is used.

[0035] FIG. 4 is a graph showing the relationship between the film thickness of the silicon oxide film 100 and the silicon germanium oxide film 200 and the oxidation treatment time when plasma oxidation treatment is performed on the Si layer 1 and the SiGe layer 2. As shown in FIG. 4, according to the plasma oxidation treatment, the film thickness of the silicon germanium oxide film 200 formed on the SiGe layer 2 tends to saturate with respect to the oxidation treatment time.

[0036] Therefore, by setting the time for performing the plasma oxidation treatment to a sufficiently long time for the thickness of the SiGe oxide film 200 to reach saturation, a SiGe oxide film 200 with a uniform thickness can be formed within the semiconductor substrate and in each stacked SiGe layer 2. In other words, etching based on the basic concept allows for uniform etching of the SiGe layer 2 within the plane of the semiconductor substrate and in each stacked SiGe layer 2.

[0037] In order to ensure etching selectivity between Si and SiGe in the basic concept, it is necessary to remove only the SiGe oxide film 200 in S104 from the Si oxide film 100 formed on the exposed surface of the Si layer 1 and the SiGe oxide film 200 formed on the exposed surface of the SiGe layer 2 in S102.

[0038] In this regard, the inventors have newly discovered that, when etching with HF gas (hydrogen fluoride gas) in S104, by appropriately controlling the temperature of the semiconductor substrate and the pressure of the HF gas, the SiGe oxide film 200 is etched at a higher rate than the Si oxide film 100. The details of this novel finding are described below.

[0039] First, Figure 5 is a graph showing the relationship between the etching rate (ER) of the Si oxide film 100 by HF gas and the temperature of the semiconductor substrate. In Figure 5, the Si oxide film 100 is a thermal oxide film formed by thermal oxidation of the semiconductor substrate (silicon substrate).

[0040] As shown in Figure 5, the Si oxide film 100 is etched by cooling the semiconductor substrate to -25°C or below (see Patent Document 3). It can be seen that the etching rate of the Si oxide film 100 increases as the temperature decreases and as the pressure of the HF gas increases.

[0041] This is understood to be because the lower the temperature and the higher the pressure of the HF gas, the more likely adsorption or aggregation of HF gas onto the Si oxide film is to occur.

[0042] The etching rate of the Si oxide film 100 increases exponentially with temperature, and the slope of the relationship between the logarithm of the etching rate and temperature remains constant regardless of the HF gas pressure. Furthermore, there is a tendency for the etching rate to plateau when it exceeds 40 nm / min.

[0043] Next, we examine the etching rate of the SiGe oxide film 200 by HF gas. The SiGe oxide film 200 is formed by plasma oxidation of SiGe layers 2 (Ge concentrations of 15%, 25%, and 50%), which are formed by epitaxial growth of SiGe on a Si layer 1. The maximum thickness of the SiGe oxide film 200 that can be formed on the surface of the SiGe layer 2 by plasma oxidation is approximately 1.5 nm. Since it is difficult to evaluate the etching rate using this thin film due to the accuracy of film thickness measurement, the SiGe consumption is calculated from the difference in film thickness of the SiGe layer 2 before and after repeating plasma oxidation and etching with HF gas 10 times. Assuming that, similar to the Si oxide film 100, when SiGe is oxidized, a SiGe oxide film 200 with 2.2 times the thickness is formed, and that the SiGe oxide film 200 with a thickness 2.2 times that of the consumed SiGe is etched, the SiGe consumption thickness is converted into the amount of etching of the SiGe oxide film 200.

[0044] Furthermore, the etching time with HF gas is adjusted and evaluated so that the thickness of the SiGe oxide film 200 etched in one HF gas etching is less than or equal to the thickness of the SiGe oxide film 200 formed in one plasma oxidation.

[0045] Figure 6(a) is a graph showing the relationship between the etching rate and temperature of the SiGe oxide film 200 formed on the surface of the SiGe layer 2 with a Ge concentration of 15%. Figure 6(b) is a graph showing the relationship between the etching rate and temperature of the SiGe oxide film 200 formed on the surface of the SiGe layer 2 with a Ge concentration of 25%. Figure 6(c) is a graph showing the relationship between the etching rate and temperature of the SiGe oxide film 200 formed on the surface of the SiGe layer 2 with a Ge concentration of 50%.

[0046] The pressure of the HF gas is set to a pressure value between 50 Pa and 800 Pa. As shown in FIGS. 6(a) to 6(c), the etching rate of the SiGe oxide film 200 has an exponential relationship with temperature. The lower the temperature and the higher the pressure of the HF gas, the higher the etching rate. Also, the higher the Ge concentration, the higher the etching rate.

[0047] FIG. 7 is a graph showing, on the same graph, the relationship between the etching rate of the SiGe oxide film 200 (Ge concentration 15%) shown in FIG. 6(a) and the etching rate of the Si oxide film 100 shown in FIG. 5 and temperature. In FIG. 7, at a temperature above the point (the location marked with a ○ in FIG. 7) where the graphs of the SiGe oxide film 200 and the Si oxide film 100 intersect for the same pressure of the HF gas, the etching rate of the SiGe oxide film 200 is higher than the etching rate of the Si oxide film 100. The temperature at this point can be regarded as the lower limit temperature at which the SiGe oxide film 200 can be preferentially etched over the Si oxide film 100. In this specification, this temperature is defined as the lower limit temperature (T Ｌ１ ).

[0048] FIG. 8(a) is a graph showing the relationship between the lower limit temperature T Ｌ１ and the pressure of the HF gas for the SiGe oxide film 200 formed on the surface of the SiGe layer 2 with Ge concentrations of 15%, 25%, and 50%.

[0049] As shown in FIG. 8(a), the lower limit temperature T Ｌ１ has a relationship proportional to the logarithm of the pressure of the HF gas, and the slope in the relationship between the natural logarithm of the pressure of the HF gas and the lower limit temperature T Ｌ１ is a constant value (11.3) regardless of the Ge concentration.

[0050] FIG. 8(b) is a graph showing the relationship between the intercept value (vertical axis intercept value) in the relationship between the lower limit temperature TL1 shown in FIG. 8(a) and the natural logarithm of the pressure of the HF gas and the Ge concentration.

[0051] As shown in FIG. 8(b), the intercept value T ＣＬ１ has a relationship proportional to the Ge concentration C (%), and is represented by Equation 1 shown below.

[0052] T ＣＬ１= 0.23 × C - 97.4 ... (Equation 1) Therefore, the lower limit temperature T at which the SiGe oxide film 200 is preferentially etched over the Si oxide film 100. Ｌ１ This can be expressed using the natural logarithm LN, the pressure P (Pa) of the HF gas, and the Ge concentration C (%), as shown in Equation 2 below.

[0053] T Ｌ１ = 11.3 × LN(P) + 0.23 × C - 97.4 ... (Equation 2) On the other hand, from a practical standpoint, even if the etching rate of the SiGe oxide film 200 is higher than that of the Si oxide film 100, if the etching rate of the Si oxide film 100 is very high and the Si oxide film 100 is etched in an uncontrollable short time, then selective etching of the SiGe oxide film 200 is practically difficult.

[0054] When selective etching of the SiGe oxide film 200 is performed using the sequence shown in Figure 2, the thickness of the Si oxide film 100 formed by plasma oxidation is approximately 1.5 nm. Therefore, it is necessary that the Si oxide film 100 is not removed within the shortest possible etching time.

[0055] The basic etching process simply involves introducing HF gas, so the minimum time required for gas switching can be considered the shortest etching time. The time required for introducing HF gas depends on the chamber volume, pressure, and flow rate of the HF gas.

[0056] For example, if the internal volume of a 300 mm single-wafer processing chamber is 25 L, the processing pressure of the HF gas is 100 Pa, and the flow rate of the HF gas is 1 L / min, then it takes about 1.5 seconds just to introduce the HF gas into the chamber. In order to avoid completely removing the 1.5 nm Si oxide film 100 within that processing time, the etching rate of the Si oxide film 100 must be 60 nm / min or less.

[0057] Therefore, Figure 9 is a graph plotting the relationship between temperature and HF gas pressure, obtained by reading the temperature at which the etching rate becomes 60 nm / min at each HF gas pressure, based on the temperature dependence of the etching rate of the Si oxide film 100 shown in Figure 5.

[0058] The basic principle is that the temperature during etching with HF gas must be above the temperature shown by the straight line in Figure 9. In this specification, this lower limit temperature is defined as lower limit temperature T. Ｌ２ This is how it is defined.

[0059] The lower limit temperature TL2 is an exponential function of the HF gas pressure and is expressed by Equation 3 shown below.

[0060] T Ｌ２ = 11.6 × LN(P) - 105 ... (Equation 3) Figure 10 shows the lower limit temperature T shown in Figure 8(a). Ｌ１ And the lower limit temperature T shown in Figure 9 Ｌ２ This is a graph plotting the same values ​​on the same graph. As shown in Figure 10, the lower limit temperature T Ｌ２ The lower limit temperature T for a Ge concentration of 25% is Ｌ１ It can be seen that it lies almost on the same line. Therefore, as the lower limit temperature in the basic concept, when the Ge concentration is less than 25%, the lower limit temperature T is expressed in Equation 2. Ｌ１ On the other hand, when the Ge concentration is 25% or higher, the lower limit temperature T expressed in Equation 3 is used. Ｌ２ You can use this.

[0061] Next, we will explain the upper limit temperature at which selective etching of the SiGe oxide film 200 can be achieved based on the basic concept. As shown in Figure 6, the higher the temperature, the lower the etching rate of the SiGe oxide film 200. For example, when applying the basic concept in the process of forming the inner spacer 3 of the GAA type FET shown in Figure 1 (see Figure 1(d)), it is necessary to etch at least 3 nm of the SiGe layer 2, and the SiGe oxide film 200 requires etching of about 6 nm. Since a single-wafer etching apparatus needs to process each sheet in less than one hour, for practical purposes, the etching rate of the SiGe oxide film 200 needs to be 0.1 nm / min or higher.

[0062] Figure 11(a) is a graph showing the relationship between the temperature at which an etching rate of 0.1 nm / min is obtained and the pressure of the HF gas, as read from Figure 6.

[0063] The temperature shown by the straight line in Figure 11(a) is the upper limit temperature T in the basic concept. Ｈ This is defined as follows: Upper temperature TＨ The relationship between the natural logarithm of the HF gas pressure LN and the upper limit temperature T is proportional to the logarithm of the HF gas pressure. Ｈ The slope in relation to is constant regardless of the Ge concentration (13).

[0064] Figure 11(b) shows the upper limit temperature T shown in Figure 11(a). Ｈ The intercept value T in the relationship between the natural logarithm LN of the HF gas pressure and the HF gas pressure. ＣＨ This is a graph plotting the relationship between [the substance] and the Ge concentration.

[0065] As shown in Figure 11(b), the intercept value T ＣＨ This relationship is proportional to the Ge concentration C (%) and is expressed by Equation 4 shown below.

[0066] T ＣＨ = C - 102 ... (Equation 4) Therefore, the upper limit temperature T at which the SiGe oxide film 200 is etched at a sufficient rate is Ｈ This can be expressed using the natural logarithm LN, the pressure P (Pa) of the HF gas, and the Ge concentration C (%), as shown in Equation 5 below.

[0067] T Ｈ = 13 × LN(P) + C-102 ... (Equation 5) From the above, the basic concept relates to an etching method having the following steps.

[0068] The basic concept is an etching method that involves etching a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate, and it comprises the following steps.

[0069] (a) A step of forming a silicon germanium oxide film within the first side surface and a silicon oxide film within the second side surface by oxidizing the first side surface where the silicon germanium layer is exposed and the second side surface where the silicon layer is exposed using a gas containing radicalized oxygen.

[0070] (b) A step of selectively etching a silicon germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in a range of TL (°C) or higher and TH (°C) or lower.

[0071] Here, the characteristic of the basic idea is that, if the atomic ratio of germanium to silicon in the silicon-germanium layer is C (%), then when C (%) < 25%, the characteristic is shown below (A), and when 25% ≤ C (%) < 50%, the characteristic is shown below (B).

[0072] <<Feature A>> Let C (%) be the atomic ratio of germanium to silicon in the silicon-germanium layer, and let P (Pa) be the pressure or partial pressure of hydrogen fluoride in step (b) described above, then C (%) < 25%, 50 Pa ≤ P (Pa) ≤ 1000 Pa, TL = 11.3 × LN(P) + 0.23 × C - 97.4, and TH = 13 × LN(P) + C - 10².

[0073] <<Feature B>> Let C (%) be the atomic ratio of germanium to silicon in the silicon-germanium layer, and let P (Pa) be the pressure or partial pressure of hydrogen fluoride in step (b) described above, then 25% ≤ C (%) < 50%, 50 Pa ≤ P (Pa) ≤ 1000 Pa, TL = 11.6 × LN(P) - 10⁵, and TH = 13 × LN(P) + C - 10⁻².

[0074] In other words, the basic idea is that SiGe is preferred over Si and the temperature at which it is etched with a practical etching rate is the lower limit temperature T according to Equation 2 when the Ge concentration of the SiGe layer 2 is less than 25%. Ｌ１ and the upper limit temperature T according to Equation 5 Ｈ This is within the range. In contrast, when the Ge concentration of the SiGe layer 2 is 25% or more and less than 50%, the lower limit temperature T according to Equation 3 is Ｌ２ and the upper limit temperature T according to Equation 5 Ｈ This is the range. For example, Figure 12(a) shows the effective temperature range for Ge concentrations of 25% and 15% as a function of HF gas pressure, and Figure 12(b) shows the effective temperature range for Ge concentration of 50% as a function of HF gas pressure.

[0075] The following describes embodiments that embody the basic concept described above.

[0076] In this embodiment, the etching step is carried out under conditions where the pressure of the HF gas and the temperature of the semiconductor substrate are within the effective range described above.

[0077] When introducing HF gas, either pure HF gas or a mixture of HF gas and an inert gas such as argon, nitrogen, or helium can be used. When using a mixture of HF gas and an inert gas, the partial pressure of the HF gas is used as P (Pa) in equations 2, 3, and 5.

[0078] <Embodiment> <<Configuration of Etching Apparatus>> Figure 13 is a diagram showing the configuration of the etching apparatus.

[0079] In Figure 13, the processing chamber 8 is composed of a base chamber (vacuum vessel) 11. Inside the base chamber 11 is a wafer stage 10 for placing wafers (semiconductor substrates) 9. Above the processing chamber 8 is a plasma source using the ICP (Inductively Coupled Plasma) discharge method. The plasma source is used for cleaning the inner wall of the chamber with plasma and for generating reactive gases with plasma.

[0080] A cylindrical discharge tube 12, which constitutes the plasma source, is installed above the processing chamber 8. An ICP coil 20 is installed on the outside of the discharge tube 12. A high-frequency power supply 21 for generating plasma is connected to the ICP coil 20 via a matching unit 22. The frequency of the high-frequency power of the high-frequency power supply 21 is in the tens of MHz frequency band, represented by 13.56 MHz. A top plate 25 is installed above the discharge tube 12. A gas dispersion plate 24 and a shower plate 23 are installed below the top plate 25. The processing gas is introduced into the discharge tube 12 via the gas dispersion plate 24 and the shower plate 23. The discharge tube 12 and the high-frequency power supply 21 constitute the plasma source.

[0081] The flow rate of the processing gas is adjusted by a mass flow controller 50 installed for each type of gas. A gas distributor 51 is installed downstream of the mass flow controller 50. The gas distributor 51 independently controls the flow rate and composition of the gas supplied to the vicinity of the center of the discharge tube 12 and the gas supplied to the vicinity of the outer periphery. This allows for detailed control of the spatial distribution of the partial pressure of the processing gas. Note that in Figure 13, Ar and N are shown. ２ HF and O ２ The example shown uses [specific gas] as the processing gas, but other gases may also be used.

[0082] At the bottom of the processing chamber 8, an exhaust mechanism 15 is connected via a vacuum exhaust pipe 16 to reduce the pressure in the processing chamber 8. The exhaust mechanism 15 may, but is not limited to, a turbomolecular pump, a mechanical booster pump, or a dry pump. In addition, a pressure regulating mechanism 14 is installed in the vacuum exhaust pipe 16 connected to the exhaust mechanism 15 to adjust the pressure in the processing chamber 8.

[0083] An IR lamp unit for heating the wafer 9 is installed above the wafer stage 10. The IR lamp unit comprises an IR lamp, a reflector 61 that reflects IR light, and an IR light transmission window 72. Here, the IR lamp is composed of, for example, circular IR lamps 60-1, 60-2, and 60-3.

[0084] The IR lamps emit light primarily in the visible light region to the infrared light region (referred to here as IR light). In this example, three IR lamps 60-1, 60-2, and 60-3 are arranged concentrically, but the arrangement is not limited to this; two circles or four or more circles may be used. Above the IR lamps, a reflector 61 is installed to reflect the IR light downwards (towards the wafer installation direction).

[0085] An IR lamp is connected to an IR lamp power supply 73, and a high-frequency cut filter 74 is installed in between to prevent high-frequency power noise from flowing into the IR lamp power supply 73. In addition, the IR lamp power supply 73 is equipped with a function to independently control the power supplied to IR lamps 60-1, 60-2, and 60-3, so that the radial distribution of the heating amount of the wafer 9 can be adjusted (some wiring is omitted from the illustration).

[0086] A channel 27 is formed in the center of the IR lamp unit. A slit plate 26 with multiple holes is installed in this channel 27 to shield ions and electrons generated in the plasma and allow only neutral gases and neutral radicals to pass through and irradiate the wafer 9.

[0087] The wafer stage 10 has a coolant channel 39 formed inside for cooling the wafer stage 10, and the coolant is circulated and supplied through the channel 39 by a chiller 38. In addition, a plate-shaped electrode plate 30 is embedded in the wafer stage 10 to fix the wafer 9 by electrostatic adsorption, and a DC power supply 31 is connected to it.

[0088] To efficiently cool the wafer 9, helium gas (He), whose flow rate is controlled by a mass flow controller 55, is supplied between the back surface of the wafer 9 and the wafer stage 10. Furthermore, to prevent damage to the back surface of the wafer 9 during heating and cooling while the wafer 9 is adsorbed, the surface of the wafer stage 10 (wafer mounting surface) is coated with a resin such as polyimide. In addition, a thermocouple 70 for measuring the temperature of the wafer stage 10 is installed inside the wafer stage 10, and this thermocouple 70 is connected to a thermocouple thermometer 71.

[0089] <<Etching Method>> The etching method in the embodiment will be explained with reference to Figure 2.

[0090] The sequence shown in Figure 2 is controlled by the control unit 80 of the etching apparatus shown in Figure 13. The control unit 80 is connected to the power supply, mechanism, and controller of the etching apparatus via control lines 81, and controls them to execute in a predetermined sequence.

[0091] In S101, first, the wafer 9 is transported to the processing chamber 8 via a transport port (not shown) provided in the processing chamber 8, and then the wafer 9 is fixed to the wafer stage 10 by electrostatic attraction using power supplied from the DC power supply 31. Inside the wafer stage 10, a coolant flow path 39 is provided, and the stage is cooled by the coolant cooled by the chiller 38. The wafer 9 is cooled by supplying He gas to the back surface of the wafer 9 via the mass flow controller 55. The chiller 38 is set to a temperature such that the wafer temperature is within the temperature range described above, and is set to the same temperature in subsequent processes.

[0092] In step S102, a mixed gas of Ar and oxygen is supplied to the processing chamber 8 via the mass flow controller 50, gas distributor 51, and shower plate 23, and the pressure in the processing chamber 8 is regulated by the pressure regulating mechanism 14 to between 50 Pa and 300 Pa. Simultaneously, the high-frequency power supply 21 is turned on to form a plasma in the discharge region 13 and generate oxygen radicals. At the same time, the wafer 9 is heated by an IR lamp to raise the wafer temperature. It is desirable that the temperature at this time be 100°C or higher. To increase the heating efficiency of the IR lamp, the supply of He gas to the back surface of the wafer 9 is stopped prior to this process. The oxygen radicals generated in the plasma are supplied to the processing chamber 8 via the flow path 27 and slit plate 26 and react with the surface of the wafer 9 heated by the IR lamp. The oxygen radicals react with the surface of the Si layer 1 and the surface of the SiGe layer 2, forming a Si oxide film 100 on the surface of the Si layer 1 and a SiGe oxide film 200 on the surface of the SiGe layer 2. Subsequently, the high-frequency power supply 21 is turned off to stop plasma generation, and the IR lamp is turned off to stop heating the wafer 9.

[0093] In S103, the oxygen gas remaining in the gas phase is evacuated. At the same time, the supply of He gas for wafer cooling to the back surface of wafer 9 is resumed.

[0094] In S104, hydrogen fluoride (HF) is introduced into the processing chamber 8 and the pressure is adjusted to a predetermined level. This etches the SiGe oxide film 200 on the wafer 9, and the etching stops when the underlying SiGe layer 2 is exposed.

[0095] In S105, the gas containing residual hydrogen fluoride and reaction products in the gas phase is evacuated. By repeating steps S102 to S105, the etching amount of the SiGe layer 2 is ultimately controlled to a desired value (S106).

[0096] The etching method according to the embodiment is carried out as described above.

[0097] Figures 14 and 15 are graphs showing the results of etching the Si layer 1 and SiGe layer 2 (Ge concentration 25%) formed on the wafer 9 using the etching method in the embodiment. The results shown in Figures 14 and 15 were obtained under the conditions that the wafer temperature at S101 was -20°C and the HF gas pressure at S105 was 300 Pa.

[0098] Figure 14 shows the amount of etching of Si layer 1 and SiGe layer 2 relative to the processing time with HF gas, with the number of cycles from S102 to S105 being 10 and the processing time in S105 being varied. Figure 14 also shows the amount of etching of Si layer 1 and SiGe layer 2 relative to the number of cycles, with the processing time in S105 being 60 seconds and the number of cycles from S102 to S105 being varied.

[0099] Figure 14 shows that as the processing time with HF gas is extended, the amount of etching of the SiGe layer 2 increases, but it plateaus at 5.5 nm and shows a saturation trend, remaining constant beyond that processing time. This indicates that etching stops when the oxidized SiGe layer 2 is etched by the HF gas and the SiGe layer 2 is exposed. Therefore, it can be seen that the amount of etching of the SiGe layer 2 per cycle depends only on the thickness of the oxidized SiGe layer 2.

[0100] Figure 15 shows that the amount of etching in the SiGe layer 2 increases in proportion to the number of cycles, while the Si layer 1 is hardly etched at all, confirming that the etching method in this embodiment allows for selective etching of the SiGe layer 2.

[0101] Figure 16(a) is a graph showing the temperature dependence of the etching selectivity ratio between the SiGe layer 2 and the Si layer 1, obtained using SiGe with a Ge concentration of 25%.

[0102] Figure 16(b) is a graph showing the temperature dependence of the etching amount of SiGe layer 2 obtained using SiGe with a Ge concentration of 25%.

[0103] The results shown in Figures 16(a) and 16(b) are plotted as a function of wafer temperature, obtained by varying the wafer temperature under the conditions of 10 cycles from S102 to S105, a HF gas pressure of 300 Pa in S105, and a processing time of 60 seconds with HF gas. The dotted lines in the figures correspond to the upper and lower temperature limits. The etching selectivity ratio of SiGe / Si shown in Figure 16(a) is high in the temperature range above the lower temperature limit. Also, the etching amount of the SiGe layer 2 shown in Figure 16(b) decreases as the temperature approaches the upper temperature limit. The reason why the etching selectivity ratio of SiGe / Si shown in Figure 16(a) is low at temperatures above -20°C is that the etching rate of SiGe decreases, resulting in a smaller etching amount.

[0104] The results shown in Figures 16(a) and 16(b) demonstrate that by setting the HF gas processing temperature within the temperature range described in the basic concept, it is possible to provide an etching method for the SiGe layer 2 that combines a high etching selectivity ratio with a practical etching rate.

[0105] In this embodiment, an example is shown in which an IR lamp is used for heating during plasma oxidation in S102. Since the oxidation rate by plasma oxidation is faster at higher wafer temperatures, heating is desirable. However, since the oxidation of the SiGe layer 2 by plasma oxidation is possible even at low temperatures below 0°C, the same temperature as the HF gas processing step in S105, selective etching of the SiGe layer 2 is possible even without using heating with an IR lamp. Furthermore, the heating method is not limited to heating with an IR lamp; for example, a method of heating the wafer stage 10 may also be used.

[0106] In this embodiment, an example is shown in which oxygen radicals generated by an ICP plasma source are used as the method for forming the Si oxide film 100 and the SiGe oxide film 200, but other methods may be used for the radical generation source.

[0107] In this embodiment, the plasma oxidation in S102 and the HF gas treatment in S105 are performed in the same chamber, but each step may be performed in separate chambers. In this embodiment, since the wafer temperature needs to be low, below 0°C, the stage temperature also needs to be low. Therefore, even if heating is performed with an IR lamp, the temperature rise is limited. As a result, there is a limit to the thickness of the oxide film that can be formed in the processing chamber 8, and therefore there is a limit to the thickness of the film that can be etched per cycle. Since the thickness of the oxide film formed by plasma oxidation is expected to increase with higher wafer temperatures, the thickness of the oxide film can be increased by performing plasma oxidation at a higher temperature in a separate chamber, thereby increasing the amount of etching per cycle. This may increase the throughput of the etching process.

[0108] <<Method for Manufacturing a Semiconductor Device>> The etching method in the above-described embodiment is effective when applied to a method for manufacturing a semiconductor device including a gate-all-around type FET having a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate.

[0109] A multilayer structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate constitutes the channel of a GAA-type FET. In the manufacturing process of a GAA-type FET, a gate electrode is formed so as to cover the multilayer structure that constitutes the channel.

[0110] In this regard, in order to reduce parasitic capacitances such as gate electrode-source capacitance and gate electrode-drain capacitance, the manufacturing process of a GAA-type FET includes a step of selectively etching the SiGe layer to form an inner spacer, which is an insulating film, in the region where the SiGe layer has been recessed. Therefore, by using the etching method in the above-described embodiment as the step of selectively etching the SiGe layer included in the manufacturing process of a GAA-type FET, the SiGe layer can be uniformly etched relative to the Si layer. As a result, the performance of semiconductor devices including GAA-type FETs can be improved.

[0111] This disclosure is not limited to the embodiments and includes various modifications.

[0112] For example, the embodiments described in detail are provided to illustrate the present disclosure clearly and are not necessarily limited to those comprising all the configurations described. Furthermore, it is possible to replace some of the configurations in one embodiment with those in another embodiment, and to add configurations from other embodiments to the configuration of one embodiment. It is also possible to add, delete, or replace some of the configurations in an embodiment with those of other embodiments.

[0113] 1 Si layer 2 SiGe layer 3 Inner spacer 8 Processing chamber 9 Wafer 10 Wafer stage 11 Base chamber 12 Discharge tube 13 Discharge area 14 Pressure regulating mechanism 15 Exhaust mechanism 16 Vacuum exhaust piping 20 ICP coil 21 High-frequency power supply 22 Matching machine 23 Shower plate 24 Gas dispersion plate 25 Top plate 26 Slit plate 27 Flow path 30 Electrode plate 31 DC power supply 38 Chiller 39 Flow path 50 Mass flow controller 51 Gas distributor 55 Mass flow controller 60-1 IR lamp 60-2 IR lamp 60-3 IR lamp 61 Reflector 70 Thermocouple 71 Thermocouple thermometer 72 IR light transmission window 73 Power supply for IR lamp 74 High-frequency cut filter 80 Control unit 81 Control line 100 Si oxide film 200 SiGe oxide film

Claims

1. An etching method for etching a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate, comprising: (a) a step of oxidizing the exposed first side surface of the silicon-germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen, thereby forming a silicon-germanium oxide film in the first side surface and a silicon oxide film in the second side surface; (b) a step of selectively etching the silicon-germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) or higher and TH (°C) or lower, wherein the atomic ratio of germanium to silicon in the silicon-germanium layer is C (%), and the pressure or partial pressure of the hydrogen fluoride in step (b) is P (Pa), such that C (%) < 25%, and 50 Pa ≤ P (Pa) ≤ 1000 Pa. An etching method in which TL = 11.3 × LN(P) + 0.23 × C - 97.4 and TH = 13 × LN(P) + C - 102.

2. An etching method for etching a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate, comprising: (a) a step of oxidizing the exposed first side surface of the silicon-germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen, thereby forming a silicon-germanium oxide film in the first side surface and a silicon oxide film in the second side surface; (b) a step of selectively etching the silicon-germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) or higher and TH (°C) or lower, wherein the atomic ratio of germanium to silicon in the silicon-germanium layer is C (%), and the pressure or partial pressure of the hydrogen fluoride in step (b) is P (Pa), such that 25% ≤ C (%) < 50%, and 50 Pa ≤ P (Pa) ≤ 1000 Pa. An etching method in which TL = 11.6 × LN(P) - 10⁵ and TH = 13 × LN(P) + C - 10⁻².

3. The etching method according to claim 1 or 2, wherein step (a) and step (b) are repeated.

4. In the etching method according to claim 1 or 2, step (a) is carried out for an oxidation treatment time that is longer than the time required for the thickness of the silicon germanium oxide film to saturate.

5. In the etching method according to claim 1 or 2, step (a) and step (b) are carried out in the same processing chamber.

6. In the etching method according to claim 5, step (a) is performed by raising the temperature of the semiconductor substrate to a higher temperature than that of step (b).

7. In the etching method according to claim 6, step (a) is performed by using lamp heating to raise the temperature of the semiconductor substrate.

8. In the etching method according to claim 1 or 2, step (a) and step (b) are carried out in different processing chambers.

9. In the etching method according to claim 1 or 2, the stacked structure constitutes the channel of a gate-all-around type FET.

10. A method for manufacturing a semiconductor device including a gate all-around type FET having a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate, comprising: (a) a step of forming a silicon-germanium oxide film in the first side surface and a silicon oxide film in the second side surface by oxidizing the exposed first side surface of the silicon-germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen; (b) a step of selectively etching the silicon-germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) or higher and TH (°C) or lower, wherein the atomic ratio of germanium to silicon in the silicon-germanium layer is C (%), and the pressure or partial pressure of the hydrogen fluoride in step (b) is P (Pa), such that C (%) < 25%, and 50 Pa ≤ P (Pa) ≤ 1000 Pa. A method for manufacturing a semiconductor device, wherein TL = 11.3 × LN(P) + 0.23 × C - 97.4 and TH = 13 × LN(P) + C - 102.

11. A method for manufacturing a semiconductor device including a gate all-around type FET having a laminated structure in which alternating silicon-germanium layers and silicon layers are formed on a semiconductor substrate, comprising: (a) a step of forming a silicon-germanium oxide film in the first side surface and a silicon oxide film in the second side surface by oxidizing the exposed first side surface of the silicon-germanium layer and the exposed second side surface of the silicon layer using a gas containing radicalized oxygen; (b) a step of selectively etching the silicon-germanium oxide film using hydrogen fluoride or a mixed gas of hydrogen fluoride and an inert gas, while maintaining the temperature of the semiconductor substrate in the range of TL (°C) or higher and TH (°C) or lower, wherein the atomic ratio of germanium to silicon in the silicon-germanium layer is C (%), and the pressure or partial pressure of the hydrogen fluoride in step (b) is P (Pa), such that 25% ≤ C (%) < 50%, and 50 Pa ≤ P (Pa) ≤ 1000 Pa. A method for manufacturing a semiconductor device, wherein TL = 11.6 × LN(P) - 10⁵ and TH = 13 × LN(P) + C - 10ⁿ.

12. In the method for manufacturing a semiconductor device according to claim 10 or 11, the stacked structure constitutes the channel of the gate-all-around type FET.

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